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73S8014RN Smart Card Interface Simplifying System IntegrationTM DATA SHEET December 2008 DESCRIPTION The Teridian 73S8014RN is a single smart card (ICC) interface circuit, firmware compatible with 8024-type devices for configurations where only asynchronous cards must be supported. It is derived from the 73S8024RN industrystandard electrical interface. The 73S8014RN has been optimized to match most of the typical Set-Top Box / A/V Conditional Access applications. Optimization essentially involved a smaller pin-count and support for single I/O. The 73S8014RN interfaces with the host processor through the same bus (digital I/Os) as the 73S8024RN, which is compatible with any other 8024-type IC. As a result, the 73S8014RN is a very attractive cost-reduction path from traditional 8024 ICs. The 73S8014RN has been designed to provide full electrical compliance with ISO 7816-3, EMV 4.0 and NDS specifications. Interfacing with the system controller is done through a control bus, composed of digital inputs to control the interface, and one interrupt output to inform the system controller of the card presence and faults. The card clock can be generated by an on-chip oscillator using an external crystal or by connection to an externally supplied clock signal. In addition, the clock divider provides divisor values of divide by 1, 2, 4 and 6 that are compatible with NDS requirements. The 73S8014RN incorporates an ISO 7816-3 activation/deactivation sequencer that controls the card signals. Level-shifters drive the card signals with the selected card voltage (3V or 5V), coming from an internal Low Drop-Out (LDO) voltage regulator. This LDO regulator is powered by a dedicated power supply input VPC. Digital circuitry is powered separately by a digital power supply VDD. With its embedded LDO regulator, the 73S8014RN is a cost-effective solution for any application where a 5V (typically -5% +10%) power supply is available. Emergency card deactivation is initiated upon card extraction or upon any fault detected by the protection circuitry. The fault can be a card over-current, VCC undervoltage or power supply fault (VDD). The card over-current circuitry is a true current detection function, as opposed to VCC voltage drop detection, as usually implemented in non-Teridian 8024 interface ICs. The VDD voltage fault has a threshold voltage that can be adjusted with an external resistor network. It allows automated card deactivation at a customized VDD voltage threshold value. It can be used, for instance, to match the system controller operating voltage range. APPLICATIONS * * Set-Top Box Conditional Access and Pay-per-View General purpose smart card readers ADVANTAGES * * * NDS compliant All NDS frequency divider rates of 4.5, 6.75 and 13.5MHz are supported from a 27MHz clock source Same advantages as the Teridian 73S80xxR family: Card VCC generated by an LDO regulator Very low power dissipation (saves up to 1/2W) Fewer external components are required Better noise performance True card over-current detection Firmware compatibility with all 8024 ICs Small format 20SO package * * * FEATURES * Card Interface: Complies with ISO 7816-3, EMV 4.0 and NDS 73S8014RN device supports 3V / 5V cards up to 65mA ISO 7816-3 Activation / Deactivation sequencer Automated deactivation upon hardware fault (i.e. upon drop on VDD power supply or card overcurrent) The VDD voltage supervisor threshold value (fault) can be externally adjusted Over-current detection 130mA max Card CLK clock frequency up to 20MHz System Controller Interface: 3 Digital inputs control the card activation / deactivation, card reset and card voltage 2 Digital inputs control the card clock frequency 1 Digital output, interrupt to the system controller, reports to the host the card presence and faults Crystal oscillator or host clock, up to 27MHz Regulator Power Supply: 4.75V to 5.5V (EMV 4.0) 4.85V to 5.5V (NDS) Digital Interfacing: 2.7V to 5.5V 6kV ESD protection on the card interface Package: SO 20-pin RoHS compliant (6/6) lead-free package * * * * * * Rev. 1.0 (c) 2008 Teridian Semiconductor Corporation 1 73S8014RN Data Sheet FUNCTIONAL DIAGRAM VDD GND TEST VPC DS_8014RN_014 vdd circuits VCC FAULT VDDF_ADJ INTERNAL POWER SUPPLY VOLTAGE REFERENCE VPD - internal supply VDD FAULT vref bias currents LDO REGULATOR R-C OSC. CMDVCC RSTIN 5V/#V TEST CONTROLLER AND REGISTERS FAULT LOGIC 1.5MHz VCC OFF PRES CKDIV1 CKDIV2 XTALIN XTAL OSC XTALOUT vdd circuits CLOCK RESET BUFFER SC SEQUENCER CLOCK BUFFER RST CLOCK GENERATION CLK I/O IOUC SMART CARD I/O BUFFER vcc circuits 73S8014RN Figure 1: 73S8014RN Block Diagram 2 Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet Table of Contents 1 2 Pinout ................................................................................................................................................................ 5 Electrical Specifications .................................................................................................................................. 8 2.1 Absolute Maximum Ratings ........................................................................................................................ 8 2.2 Recommended Operating Conditions ......................................................................................................... 8 2.3 Package Thermal Parameters .................................................................................................................... 8 2.4 Smart Card Interface Requirements ........................................................................................................... 9 2.5 Characteristics: Digital Signals.................................................................................................................. 11 2.6 DC Characteristics .................................................................................................................................... 12 2.7 Voltage Fault Detection Circuits ................................................................................................................ 12 3 Applications Information ............................................................................................................................... 13 3.1 Example 73S8014RN Schematics ............................................................................................................ 13 3.2 NDS Precautions ....................................................................................................................................... 13 3.3 System Controller Interface....................................................................................................................... 15 3.4 Power Supply and Voltage Supervision .................................................................................................... 15 3.5 Card Power Supply ................................................................................................................................... 16 3.6 On-Chip Oscillator and Card Clock ........................................................................................................... 16 3.7 Activation Sequence ................................................................................................................................. 16 3.8 Deactivation Sequence ............................................................................................................................. 18 3.9 Fault Detection and OFF ........................................................................................................................... 19 3.10 I/O Circuitry and Timing ......................................................................................................................... 19 4 Equivalent Circuits ......................................................................................................................................... 21 5 Mechanical Drawing ....................................................................................................................................... 26 6 Ordering Information ..................................................................................................................................... 27 7 Related Documentation ................................................................................................................................. 27 8 Contact Information ....................................................................................................................................... 27 Revision History .................................................................................................................................................... 28 Rev. 1.0 3 73S8014RN Data Sheet DS_8014RN_014 Figures Figure 1: 73S8014RN Block Diagram ....................................................................................................................... 2 Figure 2: 73S8014RN 20-SOP Pin Out ..................................................................................................................... 5 Figure 3: 73S8014RN - Typical Application Schematic .......................................................................................... 14 Figure 4: Activation Sequence - RSTIN Low When CMDVCC Goes Low ............................................................. 16 Figure 5: Activation Sequence - RSTIN High When CMDVCC Goes Low............................................................. 17 Figure 6: Deactivation Sequence ............................................................................................................................ 18 Figure 7: Timing Diagram - Management of the Interrupt Line OFF ...................................................................... 19 Figure 8: I/O and I/OUC State Diagram................................................................................................................... 20 Figure 9: I/O - I/OUC Delays - Timing Diagram ..................................................................................................... 20 Figure 10: Open Drain type - OFF .......................................................................................................................... 21 Figure 11: Power Input/Output Circuit, VDD, VPC, VCC .............................................................................................. 21 Figure 12: Type 5 - Smart Card CLK Driver Circuit ................................................................................................ 22 Figure 13: Type 6 - Smart Card RST Driver Circuit ................................................................................................ 22 Figure 14: Type 7A - Smart Card IO Interface Circuit ............................................................................................ 23 Figure 15: Type 7B - Smart Card IOUC Interface Circuit ....................................................................................... 23 Figure 16: Type 8 - General Input Circuit ............................................................................................................... 24 Figure 17: Oscillator Circuit ..................................................................................................................................... 24 Figure 18: VDDFLT_ADJ .............................................................................................................................................. 25 Figure 19: Mechanical Drawing 20-Pin SO Package .............................................................................................. 26 Tables Table 1: 73S8014RN 20-Pin SOP Pin Definitions ..................................................................................................... 6 Table 2: Absolute Maximum Device Ratings ............................................................................................................. 8 Table 3: Recommended Operating Conditions ......................................................................................................... 8 Table 4: Package Thermal Parameters ..................................................................................................................... 8 Table 5: DC Smart Card Interface Requirements ..................................................................................................... 9 Table 6: Digital Signals Characteristics ................................................................................................................... 11 Table 7: DC Characteristics ..................................................................................................................................... 12 Table 8: Voltage Fault Detection Circuits ................................................................................................................ 12 Table 9: Order Numbers and Packaging Marks ...................................................................................................... 27 4 Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet 1 Pinout The 73S8014RN is supplied as 20-pin SO package. OFF RSTIN I/OUC VPC CLKDIV2 CMDVCC 5V/#V GND XTALIN XTALOUT 1 2 3 4 5 20 19 18 17 16 CLKDIV1 PRES VCC CLK GND RST I/O VDD VDDF_ADJ TEST 73S8014RN 6 7 8 9 10 15 14 13 12 11 Figure 2: 73S8014RN 20-SOP Pin Out Rev. 1.0 5 73S8014RN Data Sheet DS_8014RN_014 Table 1 provides the 73S8014RN pin names, pin numbers, type, equivalent circuits and descriptions. Table 1: 73S8014RN 20-Pin SOP Pin Definitions Pin Name Card Interface I/O RST CLK 14 15 17 IO O O Figure 14 Figure 13 Figure 12 Card I/O: Data signal to/from card. Includes an 11K pull-up resistor to VCC. Card reset: provides reset (RST) signal to card. Card clock: provides clock signal (CLK) to card. The rate of this clock is determined by the external crystal frequency or frequency of the external clock signal applied on XTALIN and CLKDIV selections. Card Presence switch: active high indicates card is present. Includes a high-impedance pull-down current source. Card power supply - logically controlled by sequencer, output of LDO regulator. Requires an external filter capacitor to the card GND. Card ground. Command VCC (negative assertion): Logic low on this pin causes the LDO regulator to ramp the VCC supply to the card and initiates a card activation sequence, if a card is present. 5 volt / 3 volt card selection: Logic high selects 5 volts for VCC and card interface, logic low selects 3 volt operation. When the part is to be used with a single card voltage, this pin should be tied to either GND or VDD. However, it includes a high impedance pull-up resistor to default this pin high (selection of 5V card) when not connected. This pin shall not be changed when CMDVCC is low. Sets the divide ratio from the XTAL oscillator (or external clock input) to the card clock. These pins include a pull-up resistor for CLKDIV1 and CLKLDIV2 to provide a default rate of divide by two. CLKDIV1 CLKDIV2 CLOCK RATE 0 0 XTALIN/6 0 1 XTALIN/4 1 1 XTALIN/2 1 0 XTALIN Interrupt signal to the processor. Active Low - Multi-function indicating fault conditions and card presence. Open drain output configuration - It includes an internal 20k pull-up to VDD. Reset Input: This signal is the reset command to the card. System controller data I/O to/from the card. Includes an 11K pull-up resistor to VDD. Pin Number Type Equivalent Circuit Description PRES VCC GND 19 18 16 I PSO GND Figure 16 Figure 11 - Host Processor Interface CMDVCC 6 I Figure 16 5V/#V 7 I Figure 16 CLKDIV1 CLKDIV2 20 5 I Figure 16 OFF RSTIN I/OUC 1 2 3 O I IO Figure 10 Figure 16 Figure 15 6 Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet Miscellaneous Inputs and Outputs XTALIN XTALOUT VDDF_ADJ 9 10 12 Figure 17 Figure 17 Figure 18 Crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as external clock input. VDD fault threshold adjustment input: this pin can be used to adjust the VDDF value (that controls deactivation of the card). Must be left open if unused. System interface supply voltage and supply voltage for internal circuitry. LDO regulator power supply source. Test pin. Should be tied to GND. Digital ground. Power Supply and Ground VDD VPC TEST GND 13 4 11 8 GND PSO PSO Figure 11 Figure 11 - - Rev. 1.0 7 73S8014RN Data Sheet DS_8014RN_014 2 Electrical Specifications This section provides the following: Absolute maximum ratings Recommended operating conditions Package thermal parameters Smart card interface requirements Digital signals characteristics DC Characteristics Voltage Fault Detection Circuits 2.1 Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8014RN. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. The smart card interface pins are protected against short circuits to VCC, ground, and each other. Table 2: Absolute Maximum Device Ratings Parameter Supply Voltage VDD Supply Voltage VPC Input Voltage for Digital Inputs Storage Temperature Pin Voltage (except card interface) Pin Voltage (card interface) ESD Tolerance - Card interface pins ESD Tolerance - Other pins Rating -0.5 to 6.0 VDC -0.5 to 6.0 VDC -0.3 to (VDD +0.5) VDC -60 to 150C -0.3 to (VDD +0.5) VDC -0.3 to (VCC + 0.5) VDC +/- 6kV +/- 2kV * Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground. Note: Smart Card pins are protected against shorts between any combinations of Smart Card pins. 2.2 Recommended Operating Conditions Function operation should be restricted to the recommended operating conditions specified in Table 3. Table 3: Recommended Operating Conditions Parameter Supply Voltage VDD Supply Voltage VPC Ambient Operating Temperature Input Voltage for Digital Inputs Rating 2.7 to 5.5 VDC 4.75 to 5.5 VDC -40C to +85C 0V to VDD + 0.3V 2.3 Package Thermal Parameters Table 4: Package Thermal Parameters Parameter 20 SO Rating 50C / W Error! Reference source not found. lists the 73S8014RN Smart Card package thermal parameters. 8 Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet 2.4 Smart Card Interface Requirements Table 5: DC Smart Card Interface Requirements Table 5 lists the 73S8014RN Smart Card interface requirements. Symbol Parameter Condition Min Nom Max Unit Card Power Supply (VCC) Regulator General conditions, -40C < T < 85C, 4.75V < VPC < 5.5V, 2.7V < VDD < 5.5V NDS conditions, 4.85V < VPC < 5.5V Inactive mode Inactive mode, ICC = 1mA Active mode; ICC <65mA; 5V Active mode; ICC <65mA; 5V, NDS condition Active mode; ICC <65mA; 3V Card supply voltage including ripple and noise Active mode; single pulse of 100mA for 2s; 5V, fixed load = 25mA Active mode; single pulse of 100mA for 2s; 3V, fixed load = 25mA Active mode; current pulses of 40nAs with peak |ICC | <200mA, t <400ns; 5V Active mode; current pulses of 40nAs with peak |ICC | <200mA, t <400ns; 5V, NDS condition Active mode; current pulses of 40nAs with peak |ICC | <200mA, t <400ns; 3V VCCrip ICCmax ICCF VSR VSF CFNDS VCC Ripple Card supply output current ICC fault current VCC slew rate, rise VCC slew rate, fall External filter cap (VCC to GND) CF = 1.0F on VCC CF = 1.0F on VCC NDS applications, CF should be ceramic with low ESR (<100m). -0.1 -0.1 4.65 4.75 2.85 4.6 2.76 4.6 0.1 0.4 5.25 5.25 3.15 5.25 3.2 5.25 V V V V V V V V VCC 4.65 5.25 V 2.76 3.15 350 V mV mA mA fRIPPLE = 20K - 200MHz Static load current, VCC>4.6 or 2.7 volts as selected Static load current, VCC>1.62 (1) 65 40 70 0.06 0.075 0.5 0.150 0.150 1.0 130 0.30 0.60 1.5 mA V/s V/s F Rev. 1.0 9 73S8014RN Data Sheet DS_8014RN_014 Symbol Parameter Condition Min Nom Max Unit Interface Requirements - Data Signals: I/O and Host Interfaces: I/OUC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC. Output level, high (I/OUC) VOH Output level, high (I/O) Output level, low (I/OUC) VOL Output level, low (I/O) Input level, high (I/OUC) Input level, high (I/O) Input level, low Input level, low (I/O) Output voltage when outside of session Input leakage Input current, low Short circuit output current Vcc = 5V, 3V IOL = 0 IOL = 1mA VIH = VCC VIL = 0 For output low, shorted to VCC through 33 For output high, shorted to ground through 33 CL = 80pF, 10% to 90%. Output stable for >400ns IOH =0 IOH = -40A IOH =0 IOH = -40A (VCC = 3/5V) IOL=1mA Vcc = 5V Vcc = 3V 0.6 VDD 0.6 VCC -0.3 -0.3 0.9 VDD 0.75 VDD 0.9 VCC 0.75 VCC VDD+0.1 VDD+0.1 VCC+0.1 VCC+0.1 0.3 0.45 0.2 VDD+0.30 VCC+0.30 V V V V V V V V V V V V V A mA mA VIH VIL VINACT ILEAK IIL ISHORTL 0.8 0.8 0.1 0.3 10 0.65 15 ISHORTH tR, tF tIR, tIF RPU FDMAX TFDIO TRDIO CIN Short circuit output current 15 mA Output rise time, fall times Input rise, fall times Internal pull-up resistor Maximum data rate Delay, I/O to I/OUC, I/OUC to I/O, (respectively falling edge to falling edge and rising edge to rising edge) Input capacitance 100 1 8 11 14 1 ns s k MHz Edge from master to slave, measured at 50% 60 100 15 200 ns ns 10 pF 10 Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet Symbol VOH VOL VINACT IRST_LIM ICLK_LIM CLKSR3V CLKSR5V tR, tF Parameter Output level, high Output level, low Output voltage when outside of session Output current limit, RST Output current limit, CLK CLK slew rate CLK slew rate Output rise time, fall time Condition IOH =-200A IOL=200A, VCC = 5V IOL=200A, VCC = 3V IOL = 0 IOL = 1mA Min 0.9 VCC 0 0 Nom Max VCC 0.45 0.2 0.1 0.3 30 70 Unit V V V V V mA mA V/ns V/ns Reset and Clock for Card Interface, RST, CLK < Vcc = 5V CL = 35pF for CLK, 10% to 90% CL = 200pF for RST, 10% to 90% CL =35pF, FCLK 20MHz CL =35pF 0.3 0.5 8 100 45 55 ns ns % Duty cycle for CLK 2.5 Characteristics: Digital Signals Table 6: Digital Signals Characteristics Table 6 lists the 73S8014RN digital signals characteristics. Symbol VIL VIH VOL VOH ROUT |IIL1| |IIL2| Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Pull-up resistor, OFF Input Leakage Current Input Leakage Current Condition Min -0.3 1.8 Nom Max 0.8 VDD + 0.3 0.45 Unit V V V V Digital I/O Except for XTALIN and XTALOUT IOL = 2mA IOH = -1mA VDD - 0.45 16 GND < VIN < VDD GND < VIN < VDD CLKDIV2 only -5 -15 20 24 5 15 k A A Rev. 1.0 11 73S8014RN Data Sheet DS_8014RN_014 Oscillator (XTALIN) I/O Parameters VILXTAL VIHXTAL IILXTAL fMAX Input Low Voltage - XTALIN Input High Voltage - XTALIN Input Current - XTALIN Max freq. Osc or external clock External input duty cycle limit tR/F < 10% fIN, 45% < CLK < 55% 48 GND < VIN < VDD -0.3 0.7 VDD -30 0.3 VDD VDD+0.3 30 27 52 V V A MHz % in 2.6 DC Characteristics Table 7: DC Characteristics Table 7 lists the 73S8014RN DC characteristics. Symbol Parameter Condition 12 MHz XTAL Ext CLK, VDD = 2.7 - 3.6V, VCC Off Min Nom 2.7 1.7 Max 7.0 Unit mA mA Ext CLK, IDD Supply Current VDD = 2.7 - 3.6V, VCC On 2.2 mA Ext CLK, VDD = 4.5 - 5.5V, VCC Off 2.7 mA Ext CLK, VDD = 4.5 - 5.5V, VCC On 3 mA IPC Supply Current VCC on, ICC=0 I/O, AUX1, AUX2=high, Clock not toggling CMDVCC High 450 700 A IPCOFF VPC supply current when VCC = 0 345 650 A 2.7 Voltage Fault Detection Circuits Table 8: Voltage Fault Detection Circuits Table 8 lists the 73S8014RN Voltage Fault Detection Circuits. Symbol VDDF Parameter VDD fault (VDD Voltage supervisor threshold) VCC fault (VCC Voltage supervisor threshold) Condition No external resistor on VDDF_ADJ pin VCC = 5v VCC= 3v Min 2.15 Nom Max 2.4 4.6 2.7 Unit V V V VCCF 12 Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet 3 Applications Information This section provides general usage information for the design and implementation of the 73S8014RN. The documents listed in Related Documentation provide more detailed information. 3.1 Example 73S8014RN Schematics Figure 3 shows a typical application schematic for the implementation of the 73S8014RN. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information. 3.2 NDS Precautions Preliminary testing against the NDS specification has found that the coupled noise level on the I/O signal may approach the maximum NDS limits. Teridian recommends adding capacitor footprints on the CLK, RST and I/O signals for addition of small capacitors to filter system noise if needed. These footprints should be added at or near the smart card connector interface. A typical value of 27pF has been found to reduce the noise to acceptable levels where the noise is an issue. In addition, Teridian recommends the addition of a 0 ohm series resistor in the CLK path. If the CLK output is found to generate too much system noise, a small resistor can be substituted to create a small RC network to slow the CLK edges and reduce the CLK noise to the rest of the system. The amount of the noise being generated from the CLK signal depends on many factors including; board layout and component placement, clock input source, distance between 8014 and the card interface, etc. Lastly, some isolation between the CLK signal should be provided against all other system signals, especially the RST and I/O signals. Rev. 1.0 13 73S8014RN Data Sheet DS_8014RN_014 CLKDIV1_from_uC OFF_interrupt_to_uC RSTIN_from_uC I/OUC_to/from_uC CLKDIV2_from_uC VPC 1 2 3 4 5 6 7 8 9 10 Y1 OFF RSTIN I/OUC VPC CLKDIV2 CMDVCC 5V3V GND XTALIN XTALOUT 73S8014RN CLKDIV1 PRES VCC CLK GND RST I/O VDD VDDF_ADJ TEST 20 19 18 17 16 15 14 13 12 11 VDD R3 Rext2 See note 5 100nF See NOTE 2 C4 10uF C5 VDD See NOTE 1 C6 R1 Rext1 100nF 22pF CMDVCC_from_uC 5V/#V_select_from_uC See NOTE 3 External_clock_from uC - OR 22pF C2 CRYSTAL C3 See NOTE 4 R2 SW-2 SW-1 C8 I/O VPP GND C4 CLK RST VCC 47K NOTES: 1) VDD = 2.7V to 5.5V DC.* 2) VPC = 4.75V(ISO)/4.85V(NDS) to 5.5V DC* VDD 3) Required if external clock from uP is used. R4 4) Required if crystal is used. 1K Y1, C2 and C3 must be removed if external clock is used. Card detection C1 10 9 8 7 6 5 4 3 2 1 NDS, EMV & ISO7816=1uF Low ESR (<100mohms) C1 should be placed near the SC connecter contact 5) R1 and R3 are external resistors that adjust the VDD fault voltage. Can be left open. switch is normally open CLK track should be routed far from RST, I/O, C4 and C8. * Do not begin a NDS card session until VPC > 4.85V and VDD > VTH (VDD fault threshold) Smart Card Connector Figure 3: 73S8014RN - Typical Application Schematic 14 Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet 3.3 System Controller Interface Pin CMDVCC: When asserted low, starts an activation sequence Pin RSTIN: controls the card RST signal (when enabled by the sequencer) Pin 5V/#V: Defines the card VDD voltage (5V when high and 3V when low) Three digital inputs allow direct control of the card interface by the host. The 73S8014RN is controlled as follows: Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card presence only (Low = No card in the reader). When CMDVCC is asserted low (Card activation sequence requested from the host), low level on OFF means a fault has been detected (e.g. card removal during card session, voltage fault, or over-current fault) that automatically initiates a deactivation sequence. 3.4 Power Supply and Voltage Supervision The Teridian 73S8014RN smart card interface ICs incorporate a LDO voltage regulator for VCC. The voltage output is controlled by the digital input 5V/#V of the 73S8014RN. This regulator is able to provide either 3V or 5V card voltage from the power supply applied on the VPC pin. The voltage regulator can provide a current of at least 65mA on VCC for both 3V and 5V that complies with EMV 4.0 and NDS specifications. Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to interface with the system controller. A card deactivation sequence is forced upon fault of any of this voltage supervisor. One voltage supervisor constantly monitors the VDD voltage. It is used to initialize the ISO-7816-3 sequencer at power-on, and to deactivate the card at power-off or upon fault. The voltage threshold of the VDD voltage supervisor is internally set by default to 2.26V nominal. However, it may be desirable, in some applications, to modify this threshold value. The method of adjusting the VDD fault voltage is to use a resistive network of R3 from the VDDF_ADJ pin to VDD supply and R1 from the VDDF_ADJ pin to ground (see application schematics). In order to set the new threshold voltage, the equivalent voltage divider ratio must be determined. This ratio value will be designated Kx. Kx is defined as R1/(R1+R3). Kx is calculated as: Kx = (2.71 / VTH) - 0.595 where VTH is the desired new threshold voltage. To determine the values of R1 and R3, use the following formulas (the parallel resistance of R1 and R3 is selected to be 24000 ohms) R3 = 24000 / Kx R1 = R3*(Kx / (1 - Kx)) Taking the example above, where a VDD fault threshold voltage of 2.6V is desired, solving for Kx gives: Kx = (2.71 / 2.6) - 0.595 = 0.4473. Solving for R3 gives: R3 = 24000 / 0.4473 = 53654. Solving for R1 gives: R1 = 58752 *(0.4473 / (1 - 0.4473)) = 43422. Using standard 1 % resistor values gives R3 = 53.6K and R1 = 43.2K. Using 1% external resistors and a parallel resistance of 24K ohms will result in a +/- 6% tolerance in the value of VDD Fault. The sources of variation due to integrated circuit process variations and mismatches include the internal reference voltage (less than +/- 1%), the internal comparator hysteresis and offset (less than +/- 1.7% for part-to-part, processing and environment), the internal resistor value mismatch and value variations (less than 1.8%), and the external resistor values (1%). If the 2.26V default threshold is used, this pin must be left unconnected. Note: Since the VDD and the VPC power supplies are separate, special care must be taken to insure that the VPC voltage is greater than 4.85V before beginning a card session. In addition, VDD must be greater than the threshold for VDD fault before card activation. Card activation begins on the falling edge of CMDVCC and therefore it must be at VDD when the VDD and VPC supplies power up. When turning off power to the VDD and the VPC power supplies, the card session should be terminated before shutdown or the VPC power supply must remain higher than 4.85V when the VDD fault is detected and the emergency deactivation sequence is completed. Rev. 1.0 15 73S8014RN Data Sheet DS_8014RN_014 3.5 Card Power Supply The card power supply is internally provided by the LDO regulator, and controlled by the digital ISO-7816-3 sequencer. 3.6 On-Chip Oscillator and Card Clock The 73S8014RN devices have an on-chip oscillator that can generate the smart card clock using an external crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the clock signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be left unconnected. The 73S8014RN is capable of generating the 4.5, 6.75 and 13.5MHz NDS clock frequencies using a crystal or external source set at 27MHz. The card clock frequency may be chosen between 4 different division rates, defined by digital inputs CLKDIV 1 and CLKDIV 2, as per the following table: CLKDIV1 0 0 1 1 CLKDIV2 0 1 0 1 CLK 1/6 XTALIN Max XTALIN 27MHz 27MHz 20MHz 27MHz 1/4 XTALIN XTALIN 1/2 XTALIN 3.7 Activation Sequence The 73S8014RN smart card interface ICs have an internal 10ms delay on the application of VDD where VDD > VDDF. No activation is allowed during this 10ms period. The CMDVCC (edge triggered) signal must then be set low to activate the card. In order to initiate activation, the card must be present; there can be no VDD fault. The following steps show the activation sequence and the timing of the card control signals when the system controller sets CMDVCC low while the RSTIN is low: CMDVCC is set low at t0. VCC will rise to the selected level and then the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not valid at t1, the OFF goes low to report a fault to the system controller, and VCC to the card is shut off. Turn I/O to reception mode at t2. CLK is applied to the card at t3. RST is a copy of RSTIN after t3. CMDVCC VCC I/O CLK RSTIN RST - t0 t1 t2 t3 t1 = 0.510 ms (timing by 1.5MHz internal oscillator) t2 = 1.5s, I/O goes to reception state t3 = >0.5s, CLK starts, RST to become the copy of RSTIN Figure 4: Activation Sequence - RSTIN Low When CMDVCC Goes Low 16 Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet The following steps show the activation sequence and the timing of the card control signals when the system controller pulls the CMDVCC low while the RSTIN is high: CMDVCC is set low at t0. VCC will rise to the selected level and then the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not valid at t1, the OFF goes low to report a fault to the system controller, and VCC to the card is shut off. At the fall of RSTIN at t2, CLK is applied to the card RST is a copy of RSTIN after t2. - CMDVCC VCC I/O CLK RSTIN RST t0 t1 t2 t1 = 0.510 ms (timing by 1.5MHz internal oscillator, I/O goes to reception state) t2 = RSTIN goes low and CLK becomes active t3 = > 0.5s, CLK active, RST to become the copy of RSTIN Figure 5: Activation Sequence - RSTIN High When CMDVCC Goes Low Rev. 1.0 17 73S8014RN Data Sheet DS_8014RN_014 3.8 Deactivation Sequence Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of hardware faults. Hardware faults are over-current, VDD fault, VCC fault, and card extraction during the session. The following steps show the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC high or OFF goes low due to a fault or card removal: RST goes low at the end of t1. CLK is set low at the end of t2. I/O goes low at the end of t3. Out of reception mode. VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low. CMDVCC OFF -- OR -- RST CLK I/O VCC t1 t2 t3 t4 t5 t1 = t2 = t3 = t4 = t5 = > 0.5s, timing by 1.5MHz internal Oscillator > 7.5s > 0.5s > 0.5s depends on VCC filter capacitor. For NDS application, CF=1F makes t1 + t2 + t3 + t4 + t5 < 250s Figure 6: Deactivation Sequence 18 Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet 3.9 Fault Detection and OFF There are two different cases that the system controller can monitor the OFF signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. Outside a card session: In this condition, CMDVCC is always high, OFF is low if the card is not present, and high if the card is present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No deactivation is required during this time. During a card session: CMDVCC is always low, and OFF falls low if the card is extracted or if any fault detection is detected. At the same time that OFF is set low, the sequencer starts the deactivation process. Figure 7 shows the timing diagram for the signals CMDVCC, PRES, and OFF during a card session and outside e the card session: OFF is low by card extracted PRES OFF CMDVCC VCC OFF is low by any fault outside card session within card session within card session Figure 7: Timing Diagram - Management of the Interrupt Line OFF 3.10 I/O Circuitry and Timing The state of the I/O pin is low after power on reset and it goes high when the activation sequencer turns on the I/O reception state. See the Activation Sequence section for details on when the I/O reception is enabled. The state of I/OUC is high after power on reset. Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected then both I/O lines return to their neutral state. Note: In certain situations and conditions, the I/O logic can get confused if the host and the card attempt to drive the IOUC and the I/O signal low at the same time. It should be noted that this is an illegal condition as all card communication is initiated by the host with a command/response protocol. The next host command should not be sent until a valid response has been completely received from the card. However, if this condition should occur, the 8014 may set both the IOUC and the I/O as outputs where they are both driven low at the same time. When either side drives their respective signal high, then this mode should be released. However, if there is a series resistance between the host and the 8014, then there may not be enough drive to release this mode. If the series resistance is greater than about 100 ohms, then this may cause this mode to become locked for the duration of the card session. If the host detects this condition (IOUC held low for more than one byte time), the card session must be terminated and restarted. Figure 8 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. The delay between the I/O signals is shown in Figure 9. Rev. 1.0 19 73S8014RN Data Sheet DS_8014RN_014 Neutral State No I/O reception Yes I/O & not I/OUC No Yes No I/OUC & not I/O Yes I/OUC in No I/OUC yes I/O yes I/OICC in No Figure 8: I/O and I/OUC State Diagram I/O I/OUC tI/O_HL Delay from I/O to I/OUC: Delay from I/OUC to I/O: tI/O_LH tI/O_HL = 100ns tI/OUC_HL = 100ns tI/OUC_HL tI/OUC_LH tI/O_LH = 25ns tI/OUC_LH = 25ns Figure 9: I/O - I/OUC Delays - Timing Diagram 20 Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet 4 Equivalent Circuits This section provides illustrations of circuits equivalent to those described in the pinout section. VDD Output Disable 20K Data From circuit PIN ESD STRONG NFET Figure 10: Open Drain type - OFF PIN ESD To Internal circuits Figure 11: Power Input/Output Circuit, VDD, VPC, VCC Rev. 1.0 21 73S8014RN Data Sheet DS_8014RN_014 VCC VERY STRONG PFET ESD From circuit VERY STRONG NFET ESD CLK PIN Figure 12: Type 5 - Smart Card CLK Driver Circuit VCC STRONG PFET ESD From circuit ESD RST PIN STRONG NFET Figure 13: Type 6 - Smart Card RST Driver Circuit 22 Rev. 1.0 DS_8014RN_014 VCC 73S8014RN Data Sheet ESD STRONG PFET 400ns DELAY RL=11K From circuit STRONG NFET IO PIN To circuit CMOS ESD Figure 14: Type 7A - Smart Card IO Interface Circuit VDD ESD STRONG PFET 400ns DELAY RL=11K From circuit STRONG NFET UC PIN To circuit CMOS ESD Figure 15: Type 7B - Smart Card IOUC Interface Circuit Rev. 1.0 23 73S8014RN Data Sheet VDD DS_8014RN_014 Pull-up Disable VERY WEAK PFET ESD To circuit Pull-down Enable TTL PIN VERY WEAK NFET ESD Note: Pins CMDVCC, 5V/#V, CLKDIV1 and CLKDIV2 have the pull-up enabled. Pins RSTIN, CLKIN, PRES have the pull-down enabled. Figure 16: Type 8 - General Input Circuit VDD ENABLEB VERY WEAK FETs ESD STRONG PFET ESD XTALIN STRONG PFET XTALOUT PIN STRONG NFET PIN ESD ESD ENABLE STRONG NFET Figure 17: Oscillator Circuit 24 Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet VDD PIN ESD R = 40k VREF = 1.400v + VDD FAULT DETECTION ESD VDDF_ ADJ PIN R = 60k R = 0.4k (approx.) ESD Figure 18: VDDFLT_ADJ Rev. 1.0 25 73S8014RN Data Sheet DS_8014RN_014 5 Mechanical Drawing + .005(.127) Inches (mm) 0.5050(12.82) - .009(.228) .0125(.318) 0.4065(10.32) 0.2960(7.51) - .004(.101) + .003(.076) 0.5050(12.82) 0.1000 + .004(.101) - .007(.178) (2.54) + .005(.127) - .009(.228) BASE PLANE 0.01(.254) - .0010(.0254) 0- 8 + .0025(.0634) Detail A Detail "A" Figure 19: Mechanical Drawing 20-Pin SO Package 26 0.0082 (.208) .033 (.838) .017(.431) 0.016(.406) + .004(.101) - .003(.076) 0.050(1.27) TYP SEATING PLANE Rev. 1.0 DS_8014RN_014 73S8014RN Data Sheet 6 Ordering Information Table 9 lists the order numbers and packaging marks used to identify 73S8014RN products. Table 9: Order Numbers and Packaging Marks Part Description 73S8014RN 20-pin Lead-Free 73S8014RN 20-pin Lead-Free Tape / Reel Order Number 73S8014RN-IL/F 73S8014RN-ILR/F Packaging Mark 73S8014RN 73S8014RN 7 Related Documentation The following 73S8014RN document is available from Teridian Semiconductor Corporation: 73S8014R/RN/RT 20SO Demo Board User Manual 8 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S8014RN, contact us at: 6440 Oak Canyon Road Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices, go to http://www.teridian.com. Rev. 1.0 27 73S8014RN Data Sheet DS_8014RN_014 Revision History Revision 1.0 Date 12/22/2008 First publication. Description (c) 2008 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company's warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com 28 Rev. 1.0 |
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