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High Supply Voltage 220MHz Unity-Gain Stable Operational Amplifier ISL55001 The ISL55001 is a high speed, low power, low cost monolithic operational amplifier. The ISL55001 is unity-gain stable and features a 300V/s slew rate and 220MHz bandwidth while requiring only 9mA of supply current. The power supply operating range of the ISL55001 is from 15V down to 2.5V. For single-supply operation, the ISL55001 operates from 30V down to 5V. The ISL55001 also features an extremely wide output voltage swing of -12.75V/+13.4V with VS = 15V and RL = 1k. At a gain of +1, the ISL55001 has a -3dB bandwidth of 220MHz with a phase margin of 50. Because of its conventional voltage-feedback topology, the ISL55001 allows the use of reactive or non-linear elements in its feedback network. This versatility combined with low cost and 140mA of output-current drive makes the ISL55001 an ideal choice for price-sensitive applications requiring low power and high speed. The ISL55001 is available in an 8 Ld SO package and specified for operation over the full -40C to +85C temperature range. ISL55001 Features * 220MHz -3dB Bandwidth * Unity-gain Stable * Low Supply Current: 9mA @ VS = 15V * Wide Supply Range: 2.5V to 15V Dual-Supply and 5V to 30V Single-Supply * High Slew Rate: 300V/s * Fast Settling: 75ns to 0.1% for a 10V Step * Wide Output Voltage Swing: -12.75V/+13.6V with VS = 15V, RL = 1k * Low Cost, Enhanced Replacement for the EL2044 * Pb-free (RoHS compliant) Applications * Video Amplifiers * Single-supply Amplifiers * Active Filters/Integrators * High Speed Sample-and-Hold * High Speed Signal Processing * ADC/DAC Buffers * Pulse/RF Amplifiers * Pin Diode Receivers * Log Amplifiers Ordering Information PART NUMBER ISL55001IBZ (Note 2) ISL55001IBZ-T7 (Note 1, 2) PART MARKING 55001 IBZ 55001 IBZ PACKAGE (Pb-free) 8 Ld SO 8 Ld SO 8 Ld SO PKG. DWG. # M8.15E M8.15E M8.15E * Photo Multiplier Amplifiers * Difference Amplifier Pin Configuration ISL55001 (8 LD SO) TOP VIEW NC 1 IN- 2 IN+ 3 VS- 4 + ISL55001IBZ-T13 55001 IBZ (Notes 1, 2) NOTES: 8 NC 7 VS+ 6 OUT 5 NC 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL55001. For more information on MSL please see techbrief TB363. November 3, 2009 FN6200.3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL55001 Absolute Maximum Ratings (TA = +25C) Supply Voltage (VS) . . . . . . . . . Input Voltage (VIN). . . . . . . . . . Differential Input Voltage (dVIN) ESD Rating Human Body Model . . . . . . . . Machine Model . . . . . . . . . . . . . . . . . . . . 16.5V or 33V . . . . . . . . . . . . . . . . . VS . . . . . . . . . . . . . . . . 10V . . . . . . . . . . . . . . . . . 3kV . . . . . . . . . . . . . . . . 250V Thermal Information Continuous Output Current . . . . . . . . . . . . . . . . . . . 60mA Power Dissipation (PD). . . . . . . . . . . . . . . . . . . . see Curves Operating Temperature Range (TA) . . . . . . . -40C to +85C Operating Junction Temperature (TJ) . . . . . . . . . . . . +150C Storage Temperature (TST) . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. DC Electrical Specifications VS = 15V, RL = 1k, TA = +25C, unless otherwise specified. PARAMETER VOS TCVOS IB IOS TC-IOS AVOL PSRR CMRR CMIR VOUT DESCRIPTION Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Offset Current Average Offset Current Drift (Note 4) Open-loop Gain Power Supply Rejection Ratio Common-mode Rejection Ratio Common-mode Input Range Output Voltage Swing VOUT = 10V, RL = 1k VS = 5V to 15V VCM = 10V, VOUT = 0V VS = 15V VO+, RL = 1k VO-, RL = 1k VO+, RL = 150 VO-, RL = 150 ISC IS RIN CIN ROUT PSOR Output Short Circuit Current Supply Current Input Resistance Input Capacitance Output Resistance Power Supply Operating Range AV = +1 AV = +1 Dual supply Single supply NOTE: 4. Measured from TMIN to TMAX. 2.25 4.5 No load 2.0 13.25 -12.6 10.7 -8.8 120 10 75 70 CONDITION MIN TYP 0.06 18 1.72 0.27 0.8 17 90 90 14 13.5 -12.8 11.5 -9.9 145 8.3 2.75 1 50 15 30 9.25 3.5 1.5 MAX 3 UNIT mV V/C A A nA/C kV/V dB dB V V V V V mA mA M pF m V V AC Electrical SpecificationsVS = 15V, AV = +1, RL = 1k, unless otherwise specified. PARAMETER BW DESCRIPTION -3dB Bandwidth (VOUT = 0.4VP-P) AV = +1 AV = -1 AV = +2 AV = +5 GBWP PM SR Gain Bandwidth Product Phase Margin Slew Rate (Note 5) RL = 1k, CL = 5pF RL = 100 250 CONDITION MIN TYP 220 55 53 17 70 55 280 MAX UNIT MHz MHz MHz MHz MHz V/s FN6200.3 November 3, 2009 2 ISL55001 AC Electrical SpecificationsVS = 15V, AV = +1, RL = 1k, unless otherwise specified. (Continued) PARAMETER FPBW tS dG dP eN iN NOTES: 5. Slew rate is measured on rising edge. 6. For VS = 15V, VOUT = 10VP-P, for VS = 5V, VOUT = 5VP-P. Full-power bandwidth is based on slew rate measurement using FPBW = SR/(2*VPEAK). 7. Video performance measured at VS = 15V, AV = +2 with two times normal video level across RL = 150. This corresponds to standard video levels across a back-terminated 75 load. For other values or RL, see "Typical Performance Curves" on page 4. DESCRIPTION Full-power Bandwidth (Note 6) Settling to +0.1% (AV = +1) Differential Gain (Note 7) Differential Phase Input Noise Voltage Input Noise Current VS = 15V VS = 15V, 10V step NTSC/PAL NTSC/PAL 10kHz 10kHz CONDITION MIN TYP 9.5 75 0.01 0.05 12 1.5 MAX UNIT MHz ns % nV/H z pA/H z 3 FN6200.3 November 3, 2009 ISL55001 Typical Performance Curves Vs=+/-15V VS = 15V RL=1K RL = 1k Source Power=-20dBm SOURCE POWER = -20dBm VS = 15V RL = 1k SOURCE POWER = -20dBm FIGURE 1. OPEN-LOOP GAIN vs FREQUENCY FIGURE 2. OPEN-LOOP PHASE vs FREQUENCY VS = 15V CL = 5pF SOURCE POWER = -20dBm RL = 1k RL = 500 VS = 15V CL = 5pF SOURCE POWER = -20dBm RL = 1k RL = 500 RL = 150 RL = 75 RL = -50 RL = 150 RL = 75 RL = 50 FIGURE 3. FREQUENCY RESPONSE FOR VARIOUS RLOAD (AV = +1) FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS RLOAD (AV = +2) CL = 82pF VS = 15V RL = 1k SOURCE POWER = -20dBm CL = 82pF CL = 39pF CL = 39pF CL = 5pF VS = 15V RL = 1k SOURCE POWER = -20dBm CL = 10pF CL = 10pF CL = 5pF FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS CLOAD (AV = +1) FIGURE 6. FREQUENCYRESPONSE FOR VARIOUS CLOAD (AV = +2) 4 FN6200.3 November 3, 2009 ISL55001 Typical Performance Curves 270 180 90 VS = 15V RF = 500 RL= 500 (Continued) 360 VS = 15V 315 RF = 500 RL= 500 270 PHASE () PHASE () AV = +1 0 -90 225 180 135 90 AV = -5 AV = -1 AV = +5 AV = +2 NOTE: FOR AV = +1, RF = 0 100k 1M 10M FREQUENCY (Hz) 100M -180 -270 45 0 100k AV = -2 1M 10M FREQUENCY (Hz) 100M FIGURE 7. PHASE vs FREQUENCY FOR VARIOUS NON-INVERTING GAIN SETTINGS FIGURE 8. PHASE vs FREQUENCY FOR VARIOUS INVERTING GAIN SETTINGS 100 GAIN BANDWIDTH PRODUCT (MHz) RL = 500 350 AV = +2 AV = +2 RF = 500 RF = 500 RL = 500 RL = 500 CL = 5pF CL = 5pF 80 SLEW RATE (V/s) 300 POSITIVE SLEW RATE POSITIVE SLEW RATE 60 250 NEGATIVE NEGATIVE SLEW RATE SLEW RATE 40 200 20 150 0 0 3 6 9 12 15 SUPPLY VOLTAGES (V) 100 0 3 6 9 12 15 SUPPLY VOLTAGES (V) FIGURE 9. GAIN BANDWIDTH PRODUCT vs SUPPLY FIGURE 10. SLEW RATE vs SUPPLY 5 NORMALIZED GAIN (dB) 5 NORMALIZED GAIN (dB) VS = 15V AV = +1 RL = 500 CL = 5pF RF = 500 RF = 250 3 3 VS = 15V AV = +2 RL = 500 CL = 5pF RF = 1k RF = 500 1 RF = 100 1 -1 RF = 0 -1 RF = 250 -3 -3 RF = 100 -5 -5 100k 1M 10M 100M 100k 1M 10M 100M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS RFEEDBACK (AV = +1) FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS RFEEDBACK (AV = +2) 5 FN6200.3 November 3, 2009 ISL55001 Typical Performance Curves 5 NORMALIZED GAIN (dB) VS = 15V AV = +2 R = 500 3 RF = 500 L CL = 5pF 1 CIN = 2.2pF CIN = 0pF -3 CIN = 10pF (Continued) 5 AV = +1 RF = 0 RL = 500 CL = 5pF NORMALIZED GAIN (dB) CIN = 6.8pF CIN = 4.7pF 3 VS = 5V VS = 2.5V 1 -1 -1 VS = 15V VS = 10V -3 -5 100k 1M 10M 100M -5 100k 1M 10M FREQUENCY (Hz) 100M 1G FREQUENCY (Hz) FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS INVERTING INPUT CAPACITANCE (CIN) FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS SUPPLY SETTINGS -10 -20 -30 CMRR (dB) -10 VS = 15V -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 100k 1M FREQUENCY (Hz) 10M 100M VS = 15V NEG_PSRR -40 -50 -60 -70 -80 -90 -100 10k POS_PSRR -100 10k 100k 1M FREQUENCY (Hz) 10M 100M FIGURE 15. COMMON-MODE REJECTION RATIO (CMRR) FIGURE 16. POWER SUPPLY REJECTION RATIO (PSRR) HARMONIC DISTORTION (dBc) -30 HARMONIC DISTORTION (dB) VS = 15V RL = 500 VOUT = 2VP-P THD VS = 15V AV = +2 -40 RF = 500 RL = 500 -50 CL = 5pF FIN = 2MHz -60 -70 THD 2nd HD -80 -90 -100 3rd HD 3rd HD 2nd HD 0 2 4 6 8 10 12 14 16 18 20 22 24 26 OUTPUT VOLTAGE (V) FIGURE 17. HARMONIC DISTORTION vs FREQUENCY (AV = +1) FIGURE 18. HARMONIC DISTORTION vs OUTPUT VOLTAGE(AV = +2) 6 FN6200.3 November 3, 2009 ISL55001 Typical Performance Curves 30 (Continued) 25 OUTPUT VOLTAGE SWING (V) 25 20 RL = 500 CL = 5pF AV = +1 RF = 0 OUTPUT VOLTAGE SWING (VP-P) VS = 15V RL = 500 RL = 500 CL = CL = 5pF5pF AV = +1 AV = +1 AV = +2 AV = +2 RF = 500 RF = 500 20 15 15 10 10 AV = +1 RF = 500 5 0 1M 5 10M 100M 0 0 3 6 9 12 15 FREQUENCY (Hz) SUPPLY VOLTAGES (V) FIGURE 19. OUTPUT SWING vs FREQUENCY FOR VARIOUS GAIN SETTINGS FIGURE 20. OUTPUT SWING vs SUPPLY VOLTAGE FOR VARIOUS GAIN SETTINGS VS = 15V AV = +1 RF = 0 RL = 500 CL = 5pF VOUT = 4V tRISE = 2ns 20% to 80% tRISE = 8.4ns 20% to 80% tFALL = 7.2ns 80% to 20% tFALL = 2.2ns 80% to 20% VS = 15V AV = +1 RF = 0 RL = 500 CL = 5pF VOUT = 400mV FIGURE 21. LARGE SIGNAL RISE AND FALL TIMES FIGURE 22. SMALL SIGNAL RISE AND FALL TIMES JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.8 1.6 POWER DISSIPATION (W) 12.5 TOTAL SUPPLY CURRENT (mA) 10.0 1.4 1.2 1.0 0.8 0.6 0.4 0.2 SO8 JA = +120C/W 1.136W 75 5.0 AV = +1 AV = +1 RF 0 RF == 0 RL == 500 RL 500 CL == 5pF C L 5pF 0 3 6 9 12 15 2.5 0 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) SUPPLY VOLTAGES (V) FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 7 FN6200.3 November 3, 2009 ISL55001 Product Description The ISL55001 is a wide bandwidth, low power, and low offset voltage feedback operational amplifier. This device is internally compensated for closed loop gain of +1 or greater. Connected in voltage follower mode and driving a 500 load, the -3dB bandwidth is around a 220MHz. Driving a 150 load and a gain of 2, the bandwidth is about 90MHz while maintaining a 300V/s slew rate. The ISL55001 is designed to operate with supply voltage from +15V to -15V. That means for single supply application, the supply voltage is from 0V to 30V. For split supplies application, the supply voltage is from 15V. The amplifier has an input common-mode voltage range from 1.5V above the negative supply (VS- pin) to 1.5V below the positive supply (VS+ pin). If the input signal is outside the above specified range, it will cause the output signal to be distorted. The outputs of the ISL55001 can swing from -12.75V to +13.4V for VS = 15V. As the load resistance becomes lower, the output swing is lower. setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Output Drive Capability The ISL55001 does not have internal short circuit protection circuitry. It has a typical short circuit current of 140mA. If the output is shorted indefinitely, the power dissipation could easily overheat the die or the current could eventually compromise metal integrity. Maximum reliability is maintained if the output current never exceeds 60mA. This limit is set by the design of the internal metal interconnect. Note that in transient applications, the part is robust. Short circuit protection can be provided externally with a back match resistor in series with the output placed close as possible to the output pin. In video applications this would be a 75 resistor and will provide adequate short circuit protection to the device. Care should still be taken not to stress the device with a short at the output. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +1, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF can't be very big for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico Farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. For gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF with proper selection of RF and RG (see Figures 15 and 16 for selection). Power Dissipation With the high output drive capability of the ISL55001, it is possible to exceed the +150C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 1: T JMAX - T AMAX PD MAX = ------------------------------------------- JA (EQ. 1) Video Performance For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150, because of the change in output current with DC level. The dG and dP of this device is about 0.01% and 0.05, while driving 150 at a gain of 2. Driving high impedance loads would give a similar or better dG and dP performance. Where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing use Equation 2: n Driving Capacitive Loads and Cables The ISL55001 can drive 47pF loads in parallel with 500 with less than 3dB of peaking at gain of +1 and as much as 100pF at a gain of +2 with under 3db of peaking. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with the output to eliminate most peaking. However, this will reduce the gain slightly. If the gain 8 PD MAX = (V S + - V S - ) x I SMAX + ( VS + i=1 V OUTi - V OUTi ) x -------------------R LOADi (EQ. 2) FN6200.3 November 3, 2009 ISL55001 For sinking use Equation 3: n PD MAX = (V S + - V S - ) x I SMAX + ( VOUTi - VS - ) x i=1 V OUTi -------------------R LOADi (EQ. 3) capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. Printed Circuit Board Layout For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. Where: * VS+ = Positive supply voltage * VS- = Negative supply voltage * ISMAX = Maximum quiescent supply current * VOUT = Average output voltage of the application * RLOAD = Load resistance tied to ground * ILOAD = Load current * n = number of amplifiers (n = 1 for ISL55001) By setting the two PDMAX equations (Equations 1, 2 or 3) equal to each other, we can solve the output current and RLOAD to avoid the device overheat. Application Circuits Sallen-Key Low Pass Filter A common and easy to implement filter taking advantage of the wide bandwidth, low offset and low power demands of the ISL55001. A derivation of the transfer function is provided for convenience (see Figure 25). Power Supply Bypassing Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic Sallen-Key High Pass Filter Again this useful filter benefits from the characteristics of the ISL55001. The transfer function is very similar to the low pass so only the results are presented (see Figure 26). V2 5V C5 C1 1nF R1 V1 1k R2 1k C2 1nF + RB RA 1k 1k C5 1nF V3 5V V+ VVOUT R7 1k 1nF Holp = K wo = Q= (1 - K ) 1 R 1C 1 R 2 C 2 1 R 1C 1 + R 2C 2 R 1C 2 + R 2C 1 R 2C 2 R 1C 1 K 4-K 2 wo = RC 2 Q= 4-K Holp = FIGURE 25. SALLEN-KEY LOW PASS FILTER 9 FN6200.3 November 3, 2009 ISL55001 V2 5V C5 1nF R1 C1 V1 1nF C2 1nF R2 1k 1k + RB RA 1k 1k C5 1nF V3 5V V+ VVOUT R7 1k Holp wo = Q= =K R 1 1 C 1 R 2C 2 1 (1 - K ) R 1C 1 + R 2C 2 R 1C 2 + R 2C 1 R 2C 2 R 1C 1 Equations simplify if we let all components be equal R = C K 4-K 2 wo = RC 2 Q= 4-K Holp = FIGURE 26. SALLEN-KEY HIGH PASS FILTER Differential Output Instrumentation Amplifier The addition of a third amplifier to the conventional three amplifier instrumentation amplifier introduces the benefits of differential signal realization, specifically the advantage of using common-mode rejection to remove e1 A1 + R2 R3 R3 coupled noise and ground potential errors inherent in remote transmission. This configuration also provides enhanced bandwidth, wider output swing and faster slew rate than conventional three amplifier solutions with only the cost of an additional amplifier and few resistors (see Figure 27). A3 + R3 R3 RE R3 R3 + eo e o3 = - ( 1 + 2R 2 R G ) ( e 1 - e 2 ) e o = - 2 ( 1 + 2R 2 R G ) ( e 1 - e 2 ) e o4 = ( 1 + 2R 2 R G ) ( e 1 - e 2 ) RG eo 2f C1, 2 BW = ----------------A Di A Di = - 2 ( 1 + 2R 2 R G ) R2 A4 + R3 R3 eo A2 e2 + FIGURE 27. DIFFERENTIAL OUTPUT INSTRUMENTATION AMPLIFIER 10 FN6200.3 November 3, 2009 ISL55001 Strain Gauge The strain gauge is an ideal application to take advantage of the moderate bandwidth and high accuracy of the ISL55001. The operation of the circuit is very straightforward. As the strain variable component resistor in the balanced bridge is subjected to increasing strain, its resistance changes, resulting in an imbalance in the bridge. A voltage variation from the referenced high accuracy source is generated and translated to the difference amplifier through the buffer stage. This voltage difference as a function of the strain is converted into an output voltage (see Figure 28). +V VARIABLE SUBJECT TO V5 + 0V R15 1k 1k R16 1k 1k RF 1k R17 R18 1k 1k 5V C6 1nF 2 + - V+ VVOUT RL (V1+V2+V3+V4) 1k C12 1nF + V4 - 5V FIGURE 28. STRAIN GAUGE AMPLIFIER For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6200.3 November 3, 2009 ISL55001 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 0.10 A DETAIL "A" 0.22 0.03 B 6.0 0.20 3.90 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45 1.27 0.43 0.076 0.25 M C A B 4 4 SIDE VIEW "B" TOP VIEW 1.75 MAX 1.45 0.1 0.25 0.175 0.075 GAUGE PLANE C SEATING PLANE 0.10 C SIDE VIEW "A 0.63 0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. 6. The pin #1 identifier may be either a mold or mark feature. Reference to JEDEC MS-012. 2. (5.40) 3. 4. TYPICAL RECOMMENDED LAND PATTERN 12 FN6200.3 November 3, 2009 |
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