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| CY62138EV30 MoBL(R) 2-Mbit (256K x 8) MoBL(R) Static RAM Features * Very high speed: 45 ns -- Wide voltage range: 2.20V - 3.60V * Pin-compatible with CY62138CV30 * Ultra-low standby power -- Typical standby current: 1 A -- Maximum standby current: 7 A * Ultra-low active power -- Typical active current: 2 mA @ f = 1 MHz * Easy memory expansion with CE and OE features * Automatic power-down when deselected * CMOS for optimum speed/power * Offered in Pb-free 36-ball BGA package Functional Description[1] The CY62138EV30 is a high-performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption when deselected (CE HIGH). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). Logic Block Diagram Data in Drivers I/O0 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 ROW DECODER SENSE AMPS I/O2 I/O3 I/O4 I/O5 256K x 8 ARRAY CE WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05577 Rev. *A * 198 Champion Court A12 A13 A14 A15 A16 A17 * San Jose, CA 95134-1709 * 408-943-2600 Revised February 14, 2006 [+] Feedback CY62138EV30 MoBL(R) Pin Configuration[2] FBGA Top View A0 I/O4 I/O5 VSS VCC I/O6 I/O7 A9 A1 A2 NC WE NC A3 A4 A5 A6 A7 A8 I/O0 I/O1 Vcc Vss A B C D E F G H NC OE A10 CE A11 A17 A16 A12 A15 A13 I/O2 I/O3 A14 Product Portfolio Power Dissipation Product Min. CY62138EV30LL 2.2 Operating ICC (mA) VCC Range (V) Typ.[3] 3.0 Max. 3.6 Speed (ns) 45 f = 1 MHz Typ.[3] 2 Max. 2.5 15 f = fmax Typ.[3] Max. 20 Standby ISB2 (A) Typ.[3] 1 Max. 7 Notes: 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C. Document #: 38-05577 Rev. *A Page 2 of 9 [+] Feedback CY62138EV30 MoBL(R) Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................... 55C to +125C Supply Voltage to Ground Potential ........................................ -0.3V to VCC(MAX) + 0.3V DC Voltage Applied to Outputs in High-Z State[4,5] ......................... -0.3V to VCC(MAX) + 0.3V DC Input Voltage[4,5] ......................-0.3V to VCC(MAX) + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Product CY62138EV30LL Range Ambient Temperature VCC[6] 2.2V to 3.6V Industrial -40C to +85C Electrical Characteristics Over the Operating Range CY62138EV30-45 Parameter VOH Description Test Conditions VCC = 2.20V VCC = 2.70V Min. 2.0 2.4 0.4 0.4 1.8 2.2 -0.3 -0.3 -1 -1 15 2 1 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +1 20 2.5 7 Typ.[3] Max. Unit V V V V V V V V A A mA mA A Output HIGH Voltage IOH = -0.1 mA IOH = -1.0 mA VOL VIH VIL IIX IOZ ICC Output LOW Voltage IOL = 0.1 mA VCC = 2.20V IOL = 2.1 mA VCC = 2.70V VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current ISB1 Automatic CE Power-down Current -- CMOS Inputs Automatic CE Power-down Current -- CMOS Inputs CE > VCC - 0.2V, VIN > VCC - 0.2V, VIN < 0.2V), f = fMAX (Address and Data Only), f = 0 (OE, and WE), VCC = 3.60V CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V ISB2 1 7 A Capacitance for all packages[7] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max. 10 10 Unit pF pF Notes: 4. VIL(min.) = -2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min.) and 200 s wait time after VCC stabilization. Document #: 38-05577 Rev. *A Page 3 of 9 [+] Feedback CY62138EV30 MoBL(R) Thermal Resistance Parameter JA JC Description Test Conditions BGA 72 8.86 Unit C/W C/W Thermal Resistance Still Air, soldered on a 3 x 4.5 inch, four-layer (Junction to Ambient) printed circuit board Thermal Resistance (Junction to Case) AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC 10% GND Rise Time: 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall time: 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH Parameters R1 R2 RTH VTH 2.50V 16667 15385 8000 1.20 3.0V 1103 1554 645 1.75 Unit V Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR[7] tR[8] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 1V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1 0.8 3 Typ.[3] Max. Unit V A ns ns Data Retention Waveform DATA RETENTION MODE VCC VCC (min.) tCDR VDR > 1.5 V 1.5V tR CE Notes: 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. Document #: 38-05577 Rev. *A Page 4 of 9 [+] Feedback CY62138EV30 MoBL(R) Switching Characteristics (Over the Operating Range)[9] 45 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE [12] Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z [10] [10,11] Min. 45 Max. Unit ns 45 10 45 22 5 18 10 18 0 45 45 35 35 0 0 35 25 0 18 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns OE HIGH to High Z [10] CE HIGH to High Z[10, 11] CE LOW to Power-up CE HIGH to Power-up Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High Z[10, 11] WE HIGH to Low Z[10] Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[13, 14] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes: 9. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high-impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. Document #: 38-05577 Rev. *A Page 5 of 9 [+] Feedback CY62138EV30 MoBL(R) Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB tHZOE tHZCE DATA VALID tRC HIGH IMPEDANCE DATA OUT Write Cycle No. 1 (WE Controlled)[16, 18] tWC ADDRESS tSCE CE tAW WE tSA tPWE tHA OE tSD DATA I/O NOTE 17 tHZOE Notes: 15. Address valid prior to or coincident with CE transition LOW. 16. Data I/O is high impedance if OE = VIH. 17. During this period, the I/Os are in output state and input signals should not be applied. 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state. tHD DATAIN VALID Document #: 38-05577 Rev. *A Page 6 of 9 [+] Feedback CY62138EV30 MoBL(R) Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[16, 18] tWC ADDRESS tSCE CE tSA tAW tPWE WE tHA OE tSD DATA I/O DATAIN VALID tHD Write Cycle No. 3 (WE Controlled, OE LOW)[18] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA tSD tHD DATA I/O NOTE 17 tHZWE DATAIN VALID tLZWE Truth Table CE H L L L WE X H H L OE X L H X High Z Data Out (I/O0-I/O7) High Z Data in (I/O0-I/O7) Inputs/Outputs Mode Deselect/Power-down Read Output Disabled Write Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05577 Rev. *A Page 7 of 9 [+] Feedback CY62138EV30 MoBL(R) Ordering Information Speed (ns) 45 Ordering Code CY62138EV30LL-45BVXI Package Diagram 51-85149 Package Type 36-ball Very Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-free) Operating Range Industrial Package Diagrams TOP VIEW 36-ball VFBGA (6 x 8 x 1 mm) (51-85149) BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(36X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C A B C 8.000.10 8.000.10 0.75 5.25 D E F G H D E 2.625 F G H A B 6.000.10 A 1.875 0.75 3.75 B 6.000.10 0.55 MAX. 0.25 C 0.15(4X) 0.210.05 SEATING PLANE 0.10 C 0.26 MAX. C 51-85149-*C 1.00 MAX MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05577 Rev. *A Page 8 of 9 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62138EV30 MoBL(R) Document History Page Document Title: CY62138EV30 2-Mbit (256K x 8) MoBL(R) Static RAM Document Number: 38-05577 REV. ** *A ECN NO. 237432 427817 Issue Date See ECN See ECN Orig. of Change AJU NXR New data sheet Removed 35 ns Speed Bin Removed "L" version Removed 32-pin TSOPII package from product Offering. Changed ball C3 from DNU to NC. Removed the redundant footnote on DNU. Moved Product Portfolio from Page # 3 to Page #2. Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA to 2 mA at f = 1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax=1/tRC Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values from 2.5 A to 7 A. Changed VCC stabilization time in footnote #7 from 100 s to 200 s Changed the AC test load capacitance from 50pF to 30pF on Page# 4 Changed VDR from 1.5V to 1V on Page# 4. Changed ICCDR from 1 A to 3 A in the Data Retention Characteristics table on Page # 4. Corected tR in Data Retention Characteristics from 100 s to tRC ns Changed tOHA, tLZCE, tLZWE from 6 ns to 10 ns Changed tHZOE, tHZCE, tHZWE from 15 ns to 18 ns Changed tLZOE from 3 ns to 5 ns Changed tSCE and tAW from 40 ns to 35 ns Changed tSD from 20 ns to 25 ns Changed tPWE from 25 ns to 35 ns Updated the Ordering Information table and replaced Package Name column with Package Diagram. Description of Change Document #: 38-05577 Rev. *A Page 9 of 9 [+] Feedback |
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