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Preliminary
merging Memory & Logic Solutions Inc.
Document Title
1M x 16 bit Single Transistor RAM
1Mx16 Single Transistor RAM
EM7164SU16 Series
Revision History
Revision No.
0.0 0.1 0.2
History
Initial Draft 1'st Revision 2'nd Revision DNU pin location changed from E3 to H6. Added Pb-free&Green part. Change tRC/tWC maximum from 40us to 10us.
Draft Date
Jul. 11 , 2005 Nov. 24 , 2005 Feb. 15 , 2006
Remark
Preliminary Preliminary Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Zip Code : 690-717
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1
Preliminary
merging Memory & Logic Solutions Inc.
1M x16 bit Single Transistor RAM
GENERAL DESCRIPTION
1Mx16 Single Transistor RAM
EM7164SU16 Series
The EM7164SU16 is 16,777,216 bits of Single Transistor RAM which uses DRAM type memory cells, but this device has refresh-free operation and extreme low power consumption technology. Furthermore the interface is compatible to a low power Asynchronous type SRAM. The EM7164SU16 is organized as 1,048,576 Words x 16 bit.
FEATURES
- Organization :1M x16 - Power Supply Voltage : 2.7 ~ 3.3V - Separated I/O power(VccQ) & Core power(Vcc) - Three state outputs - Byte read/write control by UB/LB - Support Direct Deep Power Down control by ZZ and Auto TCSR for power saving - Package type : 48-FPBGA 6.0x7.0
PRODUCT FAMILY
Power Dissipation Part Number Operating Temp. Power Supply Speed
(tRC)
Standby
(ISB1, Max.)
Operating
(ICC2, Max.)
EM7164SU16
-25oC to 85oC
2.7V to 3.3V
70ns
80uA
25mA
FUNCTION BLOCK DIAGRAM
/ZZ /CS /UB /LB /WE /OE Self-Refresh CONTROL CONTROL LOGIC
COLUMN SELECT
ROW SELECT
A0~A19
ADDRESS DECODER
Memory Array 1M X 16
DQ0~ DQ15
Din/Dout BUFFER I/O CIRCUIT
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Preliminary
merging Memory & Logic Solutions Inc.
PIN DESCRIPTION ( 48-FBGA-6.00x7.00 )
1 A
LB
1Mx16 Single Transistor RAM
EM7164SU16 Series
2
OE
3
A0
4
A1
5
A2
6
ZZ
B
DQ8
UB
A3
A4
CS
DQ0
C D
DQ9
DQ10
A5
A6
DQ1
DQ2
VSSQ
DQ11
A17
A7
DQ3
VCC
E
VCCQ
DQ12
NC
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
H
DQ15
A19
A12
A13
WE
DQ7
A18
A8
A9
A10
A11
DNU
TOP VIEW (Ball Down)
Name /CS /OE /WE /ZZ
Function Chip select inputs Output enable input Write enable input Low Power Control
Name /LB /UB VCC VCCQ
Function Lower byte (DQ0~7) Upper byte (DQ8~15) Power supply I/O Power supply
DQ0-15 Data In-out A0-19 DNU Address inputs Do Not Use
VSS(Q) Ground NC No connection
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Preliminary
merging Memory & Logic Solutions Inc.
ABSOLUTE MAXIMUM RATINGS 1) Parameter
Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage Temperature Operating Temperature
1Mx16 Single Transistor RAM
EM7164SU16 Series
Symbol
VIN, VOUT VCC, VCCQ PD TSTG TA
Ratings
-0.2 to VCCQ+0.3V -0.22) to 3.6V 1.0 -65 to 150 -25 to 85
Unit
V V W
o
C
oC
1. Stresses greater than those listed above "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Undershoot at power-off : -1.0V in case of pulse width < 20ns
FUNCTIONAL DESCRIPTION
CS H X X L L L L L L L L ZZ H L H H H H H H H H H OE X X X H H L L L X X X WE X X X H H H H H L L L LB X X H L X L H L L H L UB X X H X L H L L H L L DQ0~7 High-Z High-Z High-Z High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In DQ8~15 High-Z High-Z High-Z High-Z High-Z High-Z Data Out Data Out High-Z Data In Data In Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Deep Power Down Stand by Active Active Active Active Active Active Active Active
Note: X means don't care. (Must be low or high state)
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Preliminary
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RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter Supply voltage Ground Input high voltage Input low voltage
1. 2. 3. 4.
1Mx16 Single Transistor RAM
EM7164SU16 Series
Symbol VCC VCCQ VSS, VSSQ VIH VIL
Min 2.7 2.7 0 0.8 * VCCQ -0.23)
Typ 3.0 3.0 0 -
Max 3.3 3.3 0 VCCQ + 0.22) 0.2 * VCCQ
Unit V V V V V
TA= -25 to 85oC, otherwise specified Overshoot: VCC +1.0 V in case of pulse width < 20ns Undershoot: -1.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item Input capacitance Input/Ouput capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 8
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Parameter Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage VOL VOH ISB1 Test Conditions
VIN=VSS to VCCQ , VCC=VCCmax CS=VIH , /ZZ=VIH , OE=VIH or WE=VIL , VIO=VSS to VCCQ , VCC=VCCmax Cycle time=1s, 100% duty, IIO=0mA, CS<0.2V, ZZ=VIH , VIN<0.2V or VIN>VCCQ-0.2V Cycle time = Min, IIO=0mA, 100% duty, CS=VIL, ZZ=VIH, VIN=VIL or VIH IOL = 0.5mA, VCC=VCCmin IOH = -0.5mA, VCC=VCCmin CS,ZZ>VCCQ-0.2V, Other inputs = 0 ~ VCCQ (Typ. condition : VCC=3.0V @ 25oC) (Max. condition : VCC=3.3V @ 85oC)
Min -1 -1 0.8*VCCQ
Typ -
Max 1 1 3 25
0.2*VCCQ
Unit uA uA mA mA V V
-
Standby Current (CMOS)
LL
-
-
80
uA
1. Maximum Icc specifications are tested with VCC = VCCmax.
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Preliminary
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AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.2V to VCCQ-0.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : VCCQ/2 Output Load (See right) : CL = 30pF 1. Including scope and Jig capacitance
1)
1Mx16 Single Transistor RAM
EM7164SU16 Series
Dout
CL1)
AC CHARACTERISTICS (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = -25C to +85oC)
Parameter List
Read Cycle Time Address access time Chip enable to data output Output enable to valid output UB, LB enable to data output Read Chip enable to low-Z output UB, LB enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB, LB disable to high-Z output Output disable to high-Z output Output hold from Address change Write Cycle Time Chip enable to end of write Address setup time Address valid to end of write UB, LB valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z
Symbol
tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW
Speed Min 70 10 10 5 0 0 0 5 70 60 0 60 60 50 0 0 20 0 5 Max 10k 70 70 25 70 15 15 15 10k 15 -
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Preliminary
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TIMING DIAGRAMS
1Mx16 Single Transistor RAM
EM7164SU16 Series
READ CYCLE (1) (Address controlled, CS=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL)
tRC Address tOH Data Out
Previous Data Valid
tAA
Data Valid
READ CYCLE (2) (ZZ=WE=VIH)
tRC Address tAA CS LB, UB OE Data Out
High-Z
tCO tBA tOE tHZ
tOH
tBHZ tOHZ
Data Vaild
tOLZ tLZ tBLZ
NOTES (READ CYCLE) 1. tHZ , tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. Do not Access device with cycle timing shorter than tRC for continuous periods > 40us.
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Preliminary
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
EM7164SU16 Series
WRITE CYCLE (1) (WE controlled, ZZ=OE=VIH)
tWC Address CS LB, UB WE tAS Data In Data Out High-Z tWHZ
Data Undefined
tAW tCW tBW tWP tDW
Data Valid
tWR tDH
tOW
WRITE CYCLE (2) (CS controlled, ZZ=OE=VIH)
tWC Address
tCW
CS LB, UB WE tAS tAW tBW tWP tDW Data In Data Out High-Z
tWR
tDH
Data Valid
8
Preliminary
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
EM7164SU16 Series
WRITE CYCLE (3) (UB, LB controlled, ZZ=OE=VIH)
tWC Address
tCW
CS tAW LB, UB WE tAS tBW tWP tDW Data In Data Out High-Z
tWR
tDH
Data Valid
NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS, low WE and low UB or LB. A write begins at the last transition among low CS and low WE with asserting UB or LB low for single byte operation or simultaneously asserting UB and LB low for word operation. A write ends at the earliest transition among high CS and high WE. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from CS going low to end od write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 5. Do not Access device with cycle timing shorter than tWC for continuous periods > 40us.
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Preliminary
merging Memory & Logic Solutions Inc.
LOW POWER MODES
Deep Power Down Mode Entry/Exit
1Mx16 Single Transistor RAM
EM7164SU16 Series
CS tZZCS ZZ
~~ ~~
tCSZZ tZZP
~ ~
tR
Normal operation
Deep Power Down Entry
Deep Power Down Exit
NOTES ( DEEP POWER DOWN ) During Deep Power Down mode, all referesh related activity are disabled.
Parameter tZZCS tCSZZ tR tZZP
Description ZZ low to CS low CS high to ZZ high Operation Recovery Time ZZ pulse width
Min. 0 0 200 20
Max. -
Units ns ns us ns
Low Power Mode Characteristics
Parameter Deep Power Down Current Symbol IZZ Test Conditions
ZZ < 0.2V, Other inputs = 0 ~ VCCQ (Max. condition : VCC=3.3V @ 85oC)
Min -
Typ -
Max 10
Unit uA
10
Preliminary
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
EM7164SU16 Series
TIMING WAVEFORM OF POWER UP
200us
VCC(Min.)
VCC
CS
Power Up Mode Normal Operation
NOTE . ( POWER UP ) 1. After Vcc reaches Vcc(Min.) , wait 200us with CS high. Then you get into the normal operation.
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Preliminary
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PACKAGE DIMENSION
48 Ball Fine Pitch BGA (0.75mm ball pitch) Top View
B 6 A #A1 B C C 5
1Mx16 Single Transistor RAM
Unit: millimeters
EM7164SU16 Series
Bottom View
B B1 4 3 2 1 0.5 0.5
A1 index Mark
E C1/2 F G H
B/2
Side View
0.26 E2 D
0.25 Typ.
Detail A
A Y
E E1
Min A B B1 C C1 D E E1 E2 Y 5.93 6.93 0.30 1.00 -
Typ 0.75 6.00 3.75 7.00 5.25 0.35 1.04 0.79 0.25 -
Max 6.03 7.03 0.40 1.10 0.08
NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75x0.75) (typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max)
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0.79 Typ.
C
C1 C
D
Preliminary
merging Memory & Logic Solutions Inc.
MEMORY FUNCTION GUIDE
1Mx16 Single Transistor RAM
EM7164SU16 Series
EM X XX X X X XX X X - XX XX
1. EMLSI Memory 2. Device Type 3. Density 4. Option 5. Technology 6. Operating Voltage
1. Memory Component 2. Device Type 6 ---------------------- Low Power SRAM 7 ---------------------- STRAM 3. Density 1 ----------------------- 1M 2 ----------------------- 2M 4 ----------------------- 4M 8 ----------------------- 8M 16 --------------------- 16M 32 --------------------- 32M 64 --------------------- 64M
11. Power 10. Speed
9. Packages 8. Version 7. Organization
7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 8. Version Blank ----------------- Mother die A ----------------------- First version B ----------------------- Second version C ----------------------- Third version D ----------------------- Fourth version E ----------------------- Fifth version 9. Package Blank ---------------------- Package W --------------------- Wafer
4. Function 0 ---------------------- Dual CS 10. Speed 1 ---------------------- Single CS 45 ---------------------- 45ns 2 ---------------------- Multiplexed 55 ---------------------- 55ns 3----------------------- Single CS with /ZZ 70 ---------------------- 70ns 4----------------------- Single CS with /ZZ & Direct DPD 85 ---------------------- 85ns 5 ---------------------- Multiplexed with Sync. mode 90 ---------------------- 90ns 10 --------------------- 100ns 5. Technology 12 --------------------- 120ns Blank ---------------- CMOS F ----------------------- Full CMOS 11. Power S ----------------------- Single Transistor LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free&Green) 6. Operating Voltage L ---------------------- Low Power Blank ---------------- 5V S ---------------------- Standard Power V ----------------------- 3.3V U ----------------------- 3.0V S ----------------------- 2.5V R ----------------------- 2.0V P ----------------------- 1.8V O ----------------------- 1.5V
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