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VirtexTM 2.5 V Field Programmable Gate Arrays
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DS003-1 (v2.5 ) April 2, 2001
Product Specification
Features
* Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz - 66-MHz PCI Compliant - Hot-swappable for Compact PCI Multi-standard SelectIOTM interfaces - 16 high-performance interface standards - Connects directly to ZBTRAM devices Built-in clock-management circuitry - Four dedicated delay-locked loops (DLLs) for advanced clock control - Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets Hierarchical memory system - LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register - Configurable synchronous dual-ported 4k-bit RAMs - Fast interfaces to external high-performance RAMs Flexible architecture that balances speed and density - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Internal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensor diode * Supported by FPGA FoundationTM and Alliance Development Systems - Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager - Wide selection of PC and workstation platforms SRAM-based in-system configuration - Unlimited re-programmability - Four programming modes 0.22 m 5-layer metal process 100% factory tested
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Description
The Virtex FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 m CMOS process. These advances make Virtex FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex family comprises the nine members shown in Table 1. Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
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Table 1: Virtex Field-Programmable Gate Array Family Members Device
XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
System Gates
57,906 108,904 164,674 236,666 322,970 468,252 661,111 888,439 1,124,022
CLB Array
16x24 20x30 24x36 28x42 32x48 40x60 48x72 56x84 64x96
Logic Cells
1,728 2,700 3,888 5,292 6,912 10,800 15,552 21,168 27,648
Maximum Available I/O
180 180 260 284 316 404 512 512 512
Block RAM Bits
32,768 40,960 49,152 57,344 65,536 81,920 98,304 114,688 131,072
Maximum SelectRAM+TM Bits
24,576 38,400 55,296 75,264 98,304 153,600 221,184 301,056 393,216
(c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Virtex Architecture
Virtex devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, versatile routing resources. The abundance of routing resources permits the Virtex family to accommodate even the largest and most complex designs. Virtex FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. In some modes, the FPGA reads its own configuration data from an external PROM (master serial mode). Otherwise, the configuration data is written into the FPGA (SelectMAPTM, slave serial, and JTAG modes). The standard Xilinx FoundationTM and Alliance SeriesTM Development systems deliver complete design support for Virtex, covering every aspect from behavioral and schematic entry, through simulation, automatic design translation and implementation, to the creation, downloading, and readback of a configuration bit stream.
Xilinx thoroughly benchmarked the Virtex family. While performance is design-dependent, many designs operated internally at speeds in excess of 100 MHz and can achieve 200 MHz. Table 2 shows performance data for representative circuits, using worst-case timing parameters. Table 2: Performance for Common Circuit Functions Function Register-to-Register Adder Pipelined Multiplier Address Decoder 16:1 Multiplexer Parity Tree 9 18 36 Chip-to-Chip HSTL Class IV LVTTL,16mA, fast slew 200 MHz 180 MHz 16 64 8x8 16 x 16 16 64 5.0 ns 7.2 ns 5.1 ns 6.0 ns 4.4 ns 6.4 ns 5.4 ns 4.1 ns 5.0 ns 6.9 ns Bits Virtex -6
Higher Performance
Virtex devices provide better performance than previous generations of FPGA. Designs can achieve synchronous system clock rates up to 200 MHz including I/O. Virtex inputs and outputs comply fully with PCI specifications, and interfaces can be implemented that operate at 33 MHz or 66 MHz. Additionally, Virtex supports the hot-swapping requirements of Compact PCI.
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DS003-1 (v2.5 ) April 2, 2001 Product Specification
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VirtexTM 2.5 V Field Programmable Gate Arrays
Virtex Device/Package Combinations and Maximum I/O
Table 3: Virtex Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) Package CS144 TQ144 PQ240 HQ240 BG256 BG352 BG432 BG560 FG256 FG456 FG676 FG680 176 176 176 260 176 284 312 404 444 512 444 512 512 180 180 180 260 180 260 260 316 316 404 316 404 316 404 404 XCV50 94 98 166 XCV100 94 98 166 166 166 166 166 166 166 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
Virtex Ordering Information
Example:
Device Type Speed Grade -4 -5 -6
XCV300 -6 PQ 240 C
Temperature Range C = Commercial (TJ = 0C to +85C) I = Industrial (TJ = -40C to +100C) Number of Pins Package Type BG = Ball Grid Array FG = Fine-pitch Ball Grid Array PQ = Plastic Quad Flat Pack HQ = High Heat Dissipation QFP TQ = Thin Quad Flat Pack CS = Chip-scale Package Figure 1: Virtex Ordering Information
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Revision History
Date 11/98 01/99 02/99 05/99 05/99 07/99 Version 1.0 1.2 1.3 1.4 1.5 1.6 Initial Xilinx release. Updated package drawings and specs. Update of package drawings, updated specifications. Addition of package drawings and specifications. Replaced FG 676 & FG680 package drawings. Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19. Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate. Added IOB Input Switching Characteristics Standard Adjustments. Speed grade update to preliminary status, Power-on specification and Clock-to-Out Minimums additions, "0" hold time listing explanation, quiescent current listing update, and Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE. Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479, 117153, 117154, and 117612. Modified notes for Recommended Operating Conditions (voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43. Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. New TBCKO values; corrected FG680 package connection drawing; new note about status of CCLK pin after configuration. Modified "Pins not listed ..." statement. Speed grade update to Final status. Modified Table 18. * * * * * 04/01 2.5 * * Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices. Corrected Units column in table under IOB Input Switching Characteristics. Added values to table under CLB SelectRAM Switching Characteristics. Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in Table 18. Corrected BG256 Pin Function Diagram. Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL. Converted file to modularized format. See Virtex Data Sheet section. Revision
09/99
1.7
01/00
1.8
01/00
1.9
03/00 05/00 05/00 09/00
2.0 2.1 2.2 2.3
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2.4
Virtex Data Sheet
The Virtex Data Sheet contains the following modules: * * DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
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DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
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DS003-1 (v2.5 ) April 2, 2001 Product Specification
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VirtexTM 2.5 V Field Programmable Gate Arrays
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DS003-2 (v2.8.1) December 9, 2002
Product Specification The output buffer and all of the IOB control signals have independent polarity controls.
Architectural Description
Virtex Array
The Virtex user-programmable gate array, shown in Figure 1, comprises two major configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs). * * CLBs provide the functional elements for constructing logic IOBs provide the interface between the package pins and the CLBs
DLL
IOBs VersaRing
DLL
VersaRing
VersaRing
BRAMs
BRAMs
IOBs
IOBs
CLBs interconnect through a general routing matrix (GRM). The GRM comprises an array of routing switches located at the intersections of horizontal and vertical routing channels. Each CLB nests into a VersaBlockTM that also provides local routing resources to connect the CLB to the GRM. The VersaRingTM I/O interface provides additional routing resources around the periphery of the device. This routing improves I/O routability and facilitates pin locking. The Virtex architecture also includes the following circuits that connect to the GRM. * * * Dedicated block memories of 4096 bits each Clock DLLs for clock-distribution delay compensation and clock domain control 3-State buffers (BUFTs) associated with each CLB that drive dedicated segmentable horizontal routing resources
CLBs
VersaRing DLL IOBs DLL
vao_b.eps
Figure 1: Virtex Architecture Overview All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. Two forms of over-voltage protection are provided, one that permits 5 V compliance, and one that does not. For 5 V compliance, a Zener-like structure connected to ground turns on when the output rises to approximately 6.5 V. When PCI 3.3 V compliance is required, a conventional clamp diode is connected to the output supply voltage, VCCO. Optional pull-up and pull-down resistors and an optional weak-keeper circuit are attached to each pad. Prior to configuration, all pins not involved in configuration are forced into their high-impedance state. The pull-down resistors and the weak-keeper circuits are inactive, but inputs can optionally be pulled up. The activation of pull-up resistors prior to configuration is controlled on a global basis by the configuration mode pins. If the pull-up resistors are not activated, all the pins will float. Consequently, external pull-up or pull-down resistors must be provided on pins required to be at a well-defined logic level prior to configuration. All Virtex IOBs support IEEE 1149.1-compatible boundary scan testing.
Values stored in static memory cells control the configurable logic elements and interconnect resources. These values load into the memory cells on power-up, and can reload if necessary to change the function of the device.
Input/Output Block
The Virtex IOB, Figure 2, features SelectIOTM inputs and outputs that support a wide variety of I/O signalling standards, see Table 1. The three IOB storage elements function either as edge-triggered D-type flip-flops or as level sensitive latches. Each IOB has a clock signal (CLK) shared by the three flip-flops and independent clock enable signals for each flip-flop. In addition to the CLK and CE control signals, the three flip-flops share a Set/Reset (SR). For each flip-flop, this signal can be independently configured as a synchronous Set, a synchronous Reset, an asynchronous Preset, or an asynchronous Clear.
(c) 1999-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-2 (v2.8.1) December 9, 2002 Product Specification
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VirtexTM 2.5 V Field Programmable Gate Arrays
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T TCE
DQ CE Weak Keeper SR
O OCE
DQ CE
PAD OBUFT
SR I IQ Q Programmable Delay IBUF Vref SR SR CLK ICE
ds022_02_091300
D CE
Figure 2: Virtex Input/Output Block (IOB)
Table 1: Supported Select I/O Standards I/O Standard
LVTTL 2 - 24 mA LVCMOS2 PCI, 5 V PCI, 3.3 V GTL GTL+ HSTL Class I HSTL Class III HSTL Class IV SSTL3 Class I &II SSTL2 Class I & II CTT AGP
Input Reference Voltage (VREF)
N/A N/A N/A N/A 0.8 1.0 0.75 0.9 0.9 1.5 1.25 1.5 1.32
Output Source Voltage (VCCO)
3.3 2.5 3.3 3.3 N/A N/A 1.5 1.5 1.5 3.3 2.5 3.3 3.3
Board Termination Voltage (VTT)
N/A N/A N/A N/A 1.2 1.5 0.75 1.5 1.5 1.5 1.25 1.5 N/A
5 V Tolerant
Yes Yes Yes No No No No No No No No No No
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DS003-2 (v2.8.1) December 9, 2002 Product Specification
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VirtexTM 2.5 V Field Programmable Gate Arrays Eight I/O banks result from separating each edge of the FPGA into two banks, as shown in Figure 3. Each bank has multiple VCCO pins, all of which must be connected to the same voltage. This voltage is determined by the output standards in use.
Input Path
A buffer In the Virtex IOB input path routes the input signal either directly to internal logic or through an optional input flip-flop. An optional delay element at the D-input of this flip-flop eliminates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the FPGA, and when used, assures that the pad-to-pad hold time is zero. Each input buffer can be configured to conform to any of the low-voltage signalling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can used in close proximity to each other. See I/O Banking, page 3. There are optional pull-up and pull-down resistors at each user I/O input for use after configuration. Their value is in the range 50 k - 100 k.
Bank 0
Bank 7
Bank 1
Bank 2
GCLK3 GCLK2
Virtex Device
Bank 6
GCLK1 GCLK0 Bank 5 Bank 4
Output Path
The output path includes a 3-state output buffer that drives the output signal onto the pad. The output signal can be routed to the buffer directly from the internal logic or through an optional IOB output flip-flop. The 3-state control of the output can also be routed directly from the internal logic or through a flip-flip that provides synchronous enable and disable. Each output driver can be individually programmed for a wide range of low-voltage signalling standards. Each output buffer can source up to 24 mA and sink up to 48mA. Drive strength and slew rate controls minimize bus transients. In most signalling standards, the output High voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in close proximity to each other. See I/O Banking, page 3. An optional weak-keeper circuit is connected to each output. When selected, the circuit monitors the voltage on the pad and weakly drives the pin High or Low to match the input signal. If the pin is connected to a multiple-source signal, the weak keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way eliminates bus chatter. Because the weak-keeper circuit uses the IOB input buffer to monitor the input level, an appropriate VREF voltage must be provided if the signalling standard requires one. The provision of this voltage must comply with the I/O banking rules. Figure 3:
X8778_b
Virtex I/O Banks
Within a bank, output standards can be mixed only if they use the same VCCO. Compatible standards are shown in Table 2. GTL and GTL+ appear under all voltages because their open-drain outputs do not depend on VCCO. Table 2: Compatible Output Standards VCCO 3.3 V 2.5 V 1.5 V Compatible Standards PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL, GTL+ SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+ HSTL I, HSTL III, HSTL IV, GTL, GTL+
Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are automatically configured as inputs for the VREF voltage. Approximately one in six of the I/O pins in the bank assume this role. The VREF pins within a bank are interconnected internally and consequently only one VREF voltage can be used within each bank. All VREF pins in the bank, however, must be connected to the external voltage source for correct operation. Within a bank, inputs that require VREF can be mixed with those that do not. However, only one VREF voltage can be used within a bank. Input buffers that use VREF are not 5 V tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V tolerant. The VCCO and VREF pins for each bank appear in the device Pinout tables and diagrams. The diagrams also show the bank affiliation of each I/O. Within a given package, the number of VREF and VCCO pins can vary depending on the size of device. In larger devices,
I/O Banking
Some of the I/O standards described above require VCCO and/or VREF voltages. These voltages externally and connected to device pins that serve groups of IOBs, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank.
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Bank 3
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VirtexTM 2.5 V Field Programmable Gate Arrays more I/O pins convert to VREF pins. Since these are always a superset of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device if necessary. All the VREF pins for the largest device anticipated must be connected to the VREF voltage, and not used for I/O. In smaller devices, some VCCO pins used in larger devices do not connect within the package. These unconnected pins can be left unconnected externally, or can be connected to the VCCO voltage to permit migration to a larger device if necessary. In TQ144 and PQ/HQ240 packages, all VCCO pins are bonded together internally, and consequently the same VCCO voltage must be connected to all of them. In the CS144 package, bank pairs that share a side are interconnected internally, permitting four choices for VCCO. In both cases, the VREF pins remain internally connected as eight banks, and can be used as described previously.
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of five or six inputs. Consequently, when estimating the number of system gates provided by a given device, each CLB counts as 4.5 LCs.
Look-Up Tables
Virtex function generators are implemented as 4-input look-up tables (LUTs). In addition to operating as a function generator, each LUT can provide a 16 x 1-bit synchronous RAM. Furthermore, the two LUTs within a slice can be combined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, or a 16x1-bit dual-port synchronous RAM. The Virtex LUT can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. This mode can also be used to store data in applications such as Digital Signal Processing.
Storage Elements
The storage elements in the Virtex slice can be configured either as edge-triggered D-type flip-flops or as level-sensitive latches. The D inputs can be driven either by the function generators within the slice or directly from slice inputs, bypassing the function generators. In addition to Clock and Clock Enable signals, each Slice has synchronous set and reset signals (SR and BY). SR forces a storage element into the initialization state specified for it in the configuration. BY forces it into the opposite state. Alternatively, these signals can be configured to operate asynchronously. All of the control signals are independently invertible, and are shared by the two flip-flops within the slice.
Configurable Logic Block
The basic building block of the Virtex CLB is the logic cell (LC). An LC includes a 4-input function generator, carry logic, and a storage element. The output from the function generator in each LC drives both the CLB output and the D input of the flip-flop. Each Virtex CLB contains four LCs, organized in two similar slices, as shown in Figure 4. Figure 5 shows a more detailed view of a single slice. In addition to the four basic LCs, the Virtex CLB contains logic that combines function generators to provide functions
COUT
COUT
G4 G3 G2 G1 RC LUT Carry & Control SP DQ EC
YB Y YQ
G4 G3 G2 G1 RC LUT Carry & Control SP DQ EC
YB Y YQ
BY
BY XB X
XB F4 F3 LUT F2 F1 RC Slice 0 Carry & Control SP DQ EC X XQ
F4 F3 F2 F1 LUT Carry & Control SP DQ EC
XQ
BX
RC Slice 1
BX
slice_b.eps CIN CIN
Figure 4: 2-Slice Virtex CLB
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VirtexTM 2.5 V Field Programmable Gate Arrays
COUT
YB CY G4 G3 G2 G1 I3 I2 I1 I0 O INIT DQ EC Y
LUT
WE DI
YQ
0 1 BY
REV XB
F5IN
F6
CY
F5
F5 X
CK WE A4 BX F4 F3 F2 F1 I3 I2 I1 I0
WSO WSH
BY DG BX DI
INIT DQ EC
XQ
WE
DI O REV
LUT
0 1 SR CLK CE
CIN viewslc4.eps
Figure 5: Detailed View of VIrtex Slice
Additional Logic
The F5 multiplexer in each slice combines the function generator outputs. This combination provides either a function generator that can implement any 5-input function, a 4:1 multiplexer, or selected functions of up to nine inputs. Similarly, the F6 multiplexer combines the outputs of all four function generators in the CLB by selecting one of the F5-multiplexer outputs. This permits the implementation of any 6-input function, an 8:1 multiplexer, or selected functions of up to 19 inputs. Each CLB has four direct feedthrough paths, one per LC. These paths provide extra data input lines or additional local routing that does not consume logic resources.
Block SelectRAM
Virtex FPGAs incorporate several large block SelectRAM memories. These complement the distributed LUT SelectRAMs that provide shallow RAM structures implemented in CLBs. Block SelectRAM memory blocks are organized in columns. All Virtex devices contain two such columns, one along each vertical edge. These columns extend the full height of the chip. Each memory block is four CLBs high, and consequently, a Virtex device 64 CLBs high contains 16 memory blocks per column, and a total of 32 blocks. Table 3 shows the amount of block SelectRAM memory that is available in each Virtex device. Table 3: Virtex Block SelectRAM Amounts
Device XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 # of Blocks 8 10 12 14 16 20 24 28 32 Total Block SelectRAM Bits 32,768 40,960 49,152 57,344 65,536 81,920 98,304 114,688 131,072
Arithmetic Logic
Dedicated carry logic provides fast arithmetic carry capability for high-speed arithmetic functions. The Virtex CLB supports two separate carry chains, one per Slice. The height of the carry chains is two bits per CLB. The arithmetic logic includes an XOR gate that allows a 1-bit full adder to be implemented within an LC. In addition, a dedicated AND gate improves the efficiency of multiplier implementation. The dedicated carry path can also be used to cascade function generators for implementing wide logic functions.
BUFTs
Each Virtex CLB contains two 3-state drivers (BUFTs) that can drive on-chip busses. See Dedicated Routing, page 7. Each Virtex BUFT has an independent 3-state control pin and an independent input pin.
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VirtexTM 2.5 V Field Programmable Gate Arrays Each block SelectRAM cell, as illustrated in Figure 6, is a fully synchronous dual-ported 4096-bit RAM with independent control signals for each port. The data widths of the two ports can be configured independently, providing built-in bus-width conversion.
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Table 4: Block SelectRAM Port Aspect Ratios Width 1 2 Depth 4096 2048 1024 512 256 ADDR Bus ADDR<11:0> ADDR<10:0> ADDR<9:0> ADDR<8:0> ADDR<7:0> Data Bus DATA<0> DATA<1:0> DATA<3:0> DATA<7:0> DATA<15:0>
RAMB4_S#_S#
WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0]
4 8
DOA[#:0]
16
WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0]
The Virtex block SelectRAM also includes dedicated routing to provide an efficient interface with both CLBs and other block SelectRAMs. Refer to XAPP130 for block SelectRAM timing waveforms.
DOB[#:0]
Programmable Routing Matrix
It is the longest delay path that limits the speed of any worst-case design. Consequently, the Virtex routing architecture and its place-and-route software were defined in a single optimization process. This joint optimization minimizes long-path delays, and consequently, yields the best system performance. The joint optimization also reduces design compilation times because the architecture is software-friendly. Design cycles are correspondingly reduced due to shorter design iteration times.
xcv_ds_006
Figure 6: Dual-Port Block SelectRAM Table 4 shows the depth and width aspect ratios for the block SelectRAM.
To Adjacent GRM
To Adjacent GRM
GRM
To Adjacent GRM
To Adjacent GRM Direct Connection To Adjacent CLB
X8794b
CLB
Direct Connection To Adjacent CLB
Figure 7: Virtex Local Routing
Local Routing
The VersaBlock provides local routing resources, as shown in Figure 7, providing the following three types of connections. * Interconnections among the LUTs, flip-flops, and GRM
*
*
Internal CLB feedback paths that provide high-speed connections to LUTs within the same CLB, chaining them together with minimal routing delay Direct paths that provide high-speed connections between horizontally adjacent CLBs, eliminating the delay of the GRM.
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DS003-2 (v2.8.1) December 9, 2002 Product Specification
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VirtexTM 2.5 V Field Programmable Gate Arrays * 12 Longlines are buffered, bidirectional wires that distribute signals across the device quickly and efficiently. Vertical Longlines span the full height of the device, and horizontal ones span the full width of the device.
General Purpose Routing
Most Virtex signals are routed on the general purpose routing, and consequently, the majority of interconnect resources are associated with this level of the routing hierarchy. The general routing resources are located in horizontal and vertical routing channels associated with the rows and columns CLBs. The general-purpose routing resources are listed below. * Adjacent to each CLB is a General Routing Matrix (GRM). The GRM is the switch matrix through which horizontal and vertical routing resources connect, and is also the means by which the CLB gains access to the general purpose routing. 24 single-length lines route GRM signals to adjacent GRMs in each of the four directions. 12 buffered Hex lines route GRM signals to another GRMs six-blocks away in each one of the four directions. Organized in a staggered pattern, Hex lines can be driven only at their endpoints. Hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). One third of the Hex lines are bidirectional, while the remaining ones are uni-directional.
I/O Routing
Virtex devices have additional routing resources around their periphery that form an interface between the CLB array and the IOBs. This additional routing, called the VersaRing, facilitates pin-swapping and pin-locking, such that logic redesigns can adapt to existing PCB layouts. Time-to-market is reduced, since PCBs and other system components can be manufactured while the logic design is still in progress.
* *
Dedicated Routing
Some classes of signal require dedicated routing resources to maximize performance. In the Virtex architecture, dedicated routing resources are provided for two classes of signal. * Horizontal routing resources are provided for on-chip 3-state busses. Four partitionable bus lines are provided per CLB row, permitting multiple busses within a row, as shown in Figure 8. Two dedicated nets per CLB propagate carry signals vertically to the adjacent CLB.
Tri-State Lines
*
CLB
CLB
CLB
CLB
buft_c.eps
Figure 8: BUFT Connections to Dedicated Horizontal Bus Lines
Global Routing
Global Routing resources distribute clocks and other signals with very high fanout throughout the device. Virtex devices include two tiers of global routing resources referred to as primary global and secondary local clock routing resources. * The primary global routing resources are four dedicated global nets with dedicated input pins that are designed to distribute high-fanout clock signals with minimal skew. Each global clock net can drive all CLB, IOB, and block RAM clock pins. The primary global nets can only be driven by global buffers. There are four global buffers, one for each global net.
*
The secondary local clock routing resources consist of 24 backbone lines, 12 across the top of the chip and 12 across bottom. From these lines, up to 12 unique signals per column can be distributed via the 12 longlines in the column. These secondary resources are more flexible than the primary resources since they are not restricted to routing only to clock pins.
Clock Distribution
Virtex provides high-speed, low-skew clock distribution through the primary global routing resources described above. A typical clock distribution net is shown in Figure 9. Four global buffers are provided, two at the top center of the device and two at the bottom center. These drive the four primary global nets that in turn drive any clock pin.
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VirtexTM 2.5 V Field Programmable Gate Arrays Four dedicated clock pads are provided, one adjacent to each of the global buffers. The input to the global buffer is
GCLKPAD3 Global Clock Rows GCLKBUF3
R
selected either from these pads or from signals in the general purpose routing.
GCLKPAD2 GCLKBUF2 Global Clock Column
Global Clock Spine
GCLKBUF1 GCLKPAD1
GCLKBUF0 GCLKPAD0
gclkbu_2.eps
Figure 9: Global Clock Distribution Network
Delay-Locked Loop (DLL)
Associated with each global clock input buffer is a fully digital Delay-Locked Loop (DLL) that can eliminate skew between the clock input pad and internal clock-input pins throughout the device. Each DLL can drive two global clock networks.The DLL monitors the input clock and the distributed clock, and automatically adjusts a clock delay element. Clock edges reach internal flip-flops one to four clock periods after they arrive at the input. This closed-loop system effectively eliminates clock-distribution delay by ensuring that clock edges arrive at internal flip-flops in synchronism with clock edges arriving at the input. In addition to eliminating clock-distribution delay, the DLL provides advanced control of multiple clock domains. The DLL provides four quadrature phases of the source clock, can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16. The DLL also operates as a clock mirror. By driving the output from a DLL off-chip and then back on again, the DLL can be used to de-skew a board level clock among multiple Virtex devices. In order to guarantee that the system clock is operating correctly prior to the FPGA starting up after configuration, the DLL can delay the completion of the configuration process until after it has achieved lock. See DLL Timing Parameters, page 21 of Module 3, for frequency range information.
Boundary Scan
Virtex devices support all the mandatory boundary-scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS, IDCODE, USERCODE, and HIGHZ instructions. The TAP also supports two internal scan chains and configuration/readback of the device.The TAP uses dedicated package pins that always operate using LVTTL. For TDO to operate using LVTTL, the VCCO for Bank 2 should be 3.3 V. Otherwise, TDO switches rail-to-rail between ground and VCCO. Boundary-scan operation is independent of individual IOB configurations, and unaffected by package type. All IOBs, including un-bonded ones, are treated as independent 3-state bidirectional pins in a single scan chain. Retention of the bidirectional test capability after configuration facilitates the testing of external interconnections, provided the user design or application is turned off. Table 5 lists the boundary-scan instructions supported in Virtex FPGAs. Internal signals can be captured during EXTEST by connecting them to un-bonded or unused IOBs. They can also be connected to the unused outputs of IOBs defined as unidirectional input pins. Before the device is configured, all instructions except USER1 and USER2 are available. After configuration, all instructions are available. During configuration, it is recommended that those operations using the boundary-scan register (SAMPLE/PRELOAD, INTEST, EXTEST) not be performed.
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VirtexTM 2.5 V Field Programmable Gate Arrays The FPGA supports up to two additional internal scan chains that can be specified using the BSCAN macro. The macro provides two user pins (SEL1 and SEL2) which are decodes of the USER1 and USER2 instructions respectively. For these instructions, two corresponding pins (TDO1 and TDO2) allow user scan data to be shifted out of TDO. Likewise, there are individual clock pins (DRCK1 and DRCK2) for each user register. There is a common input pin (TDI) and shared output pins that represent the state of the TAP controller (RESET, SHIFT, and UPDATE).
In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA, and also to read back the configuration data. Figure 10 is a diagram of the Virtex Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes.
Instruction Set
The Virtex Series boundary scan instruction set also includes instructions to configure the device and read back configuration data (CFG_IN, CFG_OUT, and JSTART). The complete instruction set is coded as shown in Table 5.
Bit Sequence
The order within each IOB is: In, Out, 3-State. The input-only pins contribute only the In bit to the boundary scan I/O data register, while the output-only pins contributes all three bits. From a cavity-up view of the chip (as shown in EPIC), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Figure 11. BSDL (Boundary Scan Description Language) files for Virtex Series devices are available on the Xilinx web site in the File Download area.
Data Registers
The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out, and 3-State Control. Non-IOB pins have appropriate partial bit population if input-only or output-only. Each EXTEST CAPTURED-OR state captures all In, Out, and 3-state pins. The other standard data register is the single flip-flop BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device.
IOB.T
DATA IN 0 1 0 IOB IOB IOB IOB IOB D Q D sd Q 1
LE
IOB
IOB
1 0
sd D Q D Q
IOB
IOB LE
IOB
IOB IOB.I 1 0 1 sd D Q D Q
IOB
IOB
IOB
IOB
0
IOB
IOB
LE 1 IOB.Q IOB.T 0
IOB
BYPASS REGISTER INSTRUCTION REGISTER
IOB
TDI
M TDO U X
0 1 0 D Q D sd Q 1
LE
1 0 D Q D
sd Q
LE
1 IOB.I 0
DATAOUT SHIFT/ CLOCK DATA CAPTURE REGISTER
UPDATE
EXTEST
X9016
Figure 10: Virtex Series Boundary Scan Logic
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Identification Registers
Bit 0 ( TDO end) Bit 1 Bit 2 Right half of Top-edge IOBs (Right-to-Left) GCLK2 GCLK3 Left half of Top-edge IOBs (Right-to-Left) Left-edge IOBs (Top-to-Bottom) M1 M0 M2 Left half of Bottom-edge IOBs (Left-to-Right) GCLK1 GCLK0 Right half of Bottom-edge IOBs (Left-to-Right) DONE PROG Right-edge IOBs (Bottom -to-Top) (TDI end) CCLK
990602001
The IDCODE register is supported. By using the IDCODE, the device connected to the JTAG port can be determined. The IDCODE register has the following binary format: vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the family code (03h for Virtex family) a = the number of CLB rows (ranges from 010h for XCV50 to 040h for XCV1000) c = the company code (49h for Xilinx) The USERCODE register is supported. By using the USERCODE, a user-programmable identification code can be loaded and shifted out for examination. The identification code is embedded in the bitstream during bitstream generation and is valid only after configuration. Table 6: IDCODEs Assigned to Virtex FPGAs FPGA IDCODE v0610093h v0614093h v0618093h v061C093h v0620093h v0628093h v0630093h v0638093h v0640093h
Figure 11: Boundary Scan Bit Sequence
Table 5: Boundary Scan Instructions
Boundary-Scan Command EXTEST SAMPLE/PRELOAD Binary Code(4:0) 00000 00001 Description Enables boundary-scan EXTEST operation Enables boundary-scan SAMPLE/PRELOAD operation Access user-defined register 1 Access user-defined register 2 Access the configuration bus for read operations. Access the configuration bus for write operations. Enables boundary-scan INTEST operation Enables shifting out USER code Enables shifting out of ID Code 3-states output pins while enabling the Bypass Register Clock the start-up sequence when StartupClk is TCK Enables BYPASS Xilinx reserved instructions
XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
USER 1 USER 2 CFG_OUT CFG_IN INTEST USERCODE IDCODE HIGHZ
00010 00011 00100 00101 00111 01000 01001 01010
Including Boundary Scan in a Design
Since the boundary scan pins are dedicated, no special element needs to be added to the design unless an internal data register (USER1 or USER2) is desired. If an internal data register is used, insert the boundary scan symbol and connect the necessary pins as appropriate.
Development System
Virtex FPGAs are supported by the Xilinx Foundation and Alliance CAE tools. The basic methodology for Virtex design consists of three interrelated steps: design entry, implementation, and verification. Industry-standard tools are used for design entry and simulation (for example, Synopsys FPGA Express), while Xilinx provides proprietary architecture-specific tools for implementation. The Xilinx development system is integrated under the Xilinx Design Manager (XDMTM) software, providing designers
JSTART
01100
BYPASS RESERVED
11111 All other codes
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VirtexTM 2.5 V Field Programmable Gate Arrays design, thus allowing the most convenient entry method to be used for each portion of the design.
with a common user interface regardless of their choice of entry and verification tools. The XDM software simplifies the selection of implementation options with pull-down menus and on-line help. Application programs ranging from schematic capture to Placement and Routing (PAR) can be accessed through the XDM software. The program command sequence is generated prior to execution, and stored for documentation. Several advanced software features facilitate Virtex design. RPMs, for example, are schematic-based macros with relative location constraints to guide their placement. They help ensure optimal implementation of common functions. For HDL design entry, the Xilinx FPGA Foundation development system provides interfaces to the following synthesis design environments. * * * Synopsys (FPGA Compiler, FPGA Express) Exemplar (Spectrum) Synplicity (Synplify)
Design Implementation
The place-and-route tools (PAR) automatically provide the implementation flow described in this section. The partitioner takes the EDIF net list for the design and maps the logic into the architectural resources of the FPGA (CLBs and IOBs, for example). The placer then determines the best locations for these blocks based on their interconnections and the desired performance. Finally, the router interconnects the blocks. The PAR algorithms support fully automatic implementation of most designs. For demanding applications, however, the user can exercise various degrees of control over the process. User partitioning, placement, and routing information is optionally specified during the design-entry process. The implementation of highly structured designs can benefit greatly from basic floor planning. The implementation software incorporates Timing Wizard(R) timing-driven placement and routing. Designers specify timing requirements along entire paths during design entry. The timing path analysis routines in PAR then recognize these user-specified requirements and accommodate them. Timing requirements are entered on a schematic in a form directly relating to the system requirements, such as the targeted clock frequency, or the maximum allowable delay between two registers. In this way, the overall performance of the system along entire signal paths is automatically tailored to user-generated specifications. Specific timing information for individual nets is unnecessary.
For schematic design entry, the Xilinx FPGA Foundation and alliance development system provides interfaces to the following schematic-capture design environments. * * Mentor Graphics V8 (Design Architect, QuickSim II) Viewlogic Systems (Viewdraw)
Third-party vendors support many other environments. A standard interface-file specification, Electronic Design Interchange Format (EDIF), simplifies file transfers into and out of the development system. Virtex FPGAs supported by a unified library of standard functions. This library contains over 400 primitives and macros, ranging from 2-input AND gates to 16-bit accumulators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, I/O functions, latches, Boolean functions, multiplexers, shift registers, and barrel shifters. The "soft macro" portion of the library contains detailed descriptions of common logic functions, but does not contain any partitioning or placement information. The performance of these macros depends, therefore, on the partitioning and placement obtained during implementation. RPMs, on the other hand, do contain predetermined partitioning and placement information that permits optimal implementation of these functions. Users can create their own library of soft macros or RPMs based on the macros and primitives in the standard library. The design environment supports hierarchical design entry, with high-level schematics that comprise major functional blocks, while lower-level schematics define the logic in these blocks. These hierarchical design elements are automatically combined by the implementation tools. Different design entry tools can be combined within a hierarchical
Design Verification
In addition to conventional software simulation, FPGA users can use in-circuit debugging techniques. Because Xilinx devices are infinitely reprogrammable, designs can be verified in real time without the need for extensive sets of software simulation vectors. The development system supports both software simulation and in-circuit debugging techniques. For simulation, the system extracts the post-layout timing information from the design database, and back-annotates this information into the net list for use by the simulator. Alternatively, the user can verify timing-critical portions of the design using the TRACE(R) static timing analyzer. For in-circuit debugging, the development system includes a download and readback cable. This cable connects the FPGA in the target system to a PC or workstation. After downloading the design into the FPGA, the designer can single-step the logic, readback the contents of the flip-flops, and so observe the internal logic state. Simple modifications can be downloaded into the system in a matter of minutes.
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Configuration
Virtex devices are configured by loading configuration data into the internal configuration memory. Some of the pins used for this are dedicated configuration pins, while others can be re-used as general purpose inputs and outputs once configuration is complete. The following are dedicated pins: * * * * * Mode pins (M2, M1, M0) Configuration clock pin (CCLK) PROGRAM pin DONE pin Boundary-scan pins (TDI, TDO, TMS, TCK)
After Virtex devices are configured, unused IOBs function as 3-state OBUFTs with weak pull downs. For a more detailed description than that given below, see the XAPP138, Virtex Configuration and Readback.
Configuration Modes
Virtex supports the following four configuration modes. * * * * Slave-serial mode Master-serial mode SelectMAP mode Boundary-scan mode
Depending on the configuration mode chosen, CCLK can be an output generated by the FPGA, or it can be generated externally and provided to the FPGA as an input. The PROGRAM pin must be pulled High prior to reconfiguration. Note that some configuration pins can act as outputs. For correct operation, these pins can require a VCCO of 3.3 V to permit LVTTL operation. All the pins affected are in banks 2 or 3. The configuration pins needed for SelectMap (CS, Write) are located in bank 1. Table 7: Configuration Codes Configuration Mode Master-serial mode Boundary-scan mode SelectMAP mode Slave-serial mode Master-serial mode Boundary-scan mode SelectMAP mode Slave-serial mode M2 0 1 1 1 1 0 0 0 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 CCLK Direction Out N/A In In Out N/A In In
The Configuration mode pins (M2, M1, M0) select among these configuration modes with the option in each case of having the IOB pins either pulled up or left floating prior to configuration. The selection codes are listed in Table 7. Configuration through the boundary-scan port is always available, independent of the mode selection. Selecting the boundary-scan mode simply turns off the other modes. The three mode pins have internal pull-up resistors, and default to a logic High if left unconnected. However, it is recommended to drive the configuration mode pins externally.
Data Width 1 1 8 1 1 1 8 1
Serial Dout Yes No No Yes Yes No No Yes
Configuration Pull-ups No No No No Yes Yes Yes Yes
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other source of serial configuration data. The serial bitstream must be setup at the DIN input pin a short time before each rising edge of an externally generated CCLK. For more information on serial PROMs, see the PROM data sheet at: http://www.xilinx.com/bvdocs/publications/ds026.pdf. Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular FPGA has been configured, the data for the next device is routed to the DOUT pin. The data on the DOUT pin changes on the rising edge of CCLK. The change of DOUT on the rising edge of CCLK differs from previous families, but does not cause a problem for
mixed configuration chains. This change was made to improve serial configuration rates for Virtex-only chains. Figure 12 shows a full master/slave system. A Virtex device in slave-serial mode should be connected as shown in the third device from the left. Slave-serial mode is selected by applying <111> or <011> to the mode pins (M2, M1, M0). A weak pull-up on the mode pins makes slave-serial the default mode if the pins are left unconnected. However, it is recommended to drive the configuration mode pins externally. Figure 13 shows slave-serial mode programming switching characteristics. Table 8 provides more detail about the characteristics shown in Figure 13. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
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VirtexTM 2.5 V Field Programmable Gate Arrays
Table 8: Master/Slave Serial Mode Programming Switching Description DIN setup/hold, slave mode DIN setup/hold, master mode DOUT CCLK High time Low time Maximum Frequency Frequency Tolerance, master mode with respect to nominal Figure References 1/2 1/2 3 4 5 Symbol TDCC/TCCD TDSCK/TCKDS TCCO TCCH TCCL FCC Values 5.0 / 0 5.0 / 0 12.0 5.0 5.0 66 +45% -30% Units ns, min ns, min ns, max ns, min ns, min MHz, max
3.3V
V CC
M0 M1 M2 DOUT
4.7 K
M0 M1 M2 DIN CCLK DOUT
VIRTEX
MASTER SERIAL
CCLK Optional Pull-up Resistor on Done DIN
XC1701L
CLK DATA CE INIT RESET/OE CEO
VIRTEX, XC4000XL,
SLAVE
PROGRAM DONE INIT
1
PROGRAM DONE
(Low Reset Option Used)
PROGRAM
Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor of 330 should be added to the common DONE line.
xcv_12_091499
Figure 12: Master/Slave Serial Mode Circuit Diagram
DIN 1 TDCC CCLK 4 TCCH 3 TCCO DOUT (Output)
X5379_a
2 TCCD
5 TCCL
Figure 13: Slave-Serial Mode Programming Switching Characteristics
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Master-Serial Mode
In master-serial mode, the CCLK output of the FPGA drives a Xilinx Serial PROM that feeds bit-serial data to the DIN input. The FPGA accepts this data on each rising CCLK edge. After the FPGA has been loaded, the data for the next device in a daisy-chain is presented on the DOUT pin after the rising CCLK edge. The interface is identical to slave-serial except that an internal oscillator is used to generate the configuration clock (CCLK). A wide range of frequencies can be selected for CCLK which always starts at a slow default frequency. Configuration bits then switch CCLK to a higher frequency for the remainder of the configuration. Switching to a lower frequency is prohibited. The CCLK frequency is set using the ConfigRate option in the bitstream generation software. The maximum CCLK frequency that can be selected is 60 MHz. When selecting a CCLK frequency, ensure that the serial PROM and any
daisy-chained FPGAs are fast enough to support the clock rate. On power-up, the CCLK frequency is 2.5 MHz. This frequency is used until the ConfigRate bits have been loaded when the frequency changes to the selected ConfigRate. Unless a different frequency is specified in the design, the default ConfigRate is 4 MHz. Figure 12 shows a full master/slave system. In this system, the left-most device operates in master-serial mode. The remaining devices operate in slave-serial mode. The SPROM RESET pin is driven by INIT, and the CE input is driven by DONE. There is the potential for contention on the DONE pin, depending on the start-up sequence options chosen. Figure 14 shows the timing of master-serial configuration. Master-serial mode is selected by a <000> or <100> on the mode pins (M2, M1, M0). Table 8 shows the timing information for Figure 14.
CCLK (Output) TCKDS 2 1 TDSCK Serial Data In
Serial DOUT (Output)
DS022_44_071201
Figure 14: Master-Serial Mode Programming Switching Characteristics At power-up, VCC must rise from 1.0 V to VCC min in less than 50 ms, otherwise delay configuration by pulling PROGRAM Low until VCC is valid. The sequence of operations necessary to configure a Virtex FPGA serially appears in Figure 15. In the SelectMAP mode, multiple Virtex devices can be chained in parallel. DATA pins (D7:D0), CCLK, WRITE, BUSY, PROGRAM, DONE, and INIT can be connected in parallel between all the FPGAs. Note that the data is organized with the MSB of each byte on pin DO and the LSB of each byte on D7. The CS pins are kept separate, insuring that each FPGA can be selected individually. WRITE should be Low before loading the first bitstream and returned High after the last device has been programmed. Use CS to select the appropriate FPGA for loading the bitstream and sending the configuration data. at the end of the bitstream, deselect the loaded device and select the next target FPGA by setting its CS pin High. A free-running oscillator or other externally generated signal can be used for CCLK. The BUSY signal can be ignored for frequencies below 50 MHz. For details about frequencies above 50 MHz, see XAPP138, Virtex Configuration and Readback. Once all the devices have been programmed, the DONE pin goes High.
SelectMAP Mode
The SelectMAP mode is the fastest configuration option. Byte-wide data is written into the FPGA with a BUSY flag controlling the flow of data. An external data source provides a byte stream, CCLK, a Chip Select (CS) signal and a Write signal (WRITE). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes Low. Data can also be read using the SelectMAP mode. If WRITE is not asserted, configuration data is read out of the FPGA as part of a readback operation.
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Apply Power FPGA starts to clear configuration memory. Set PROGRAM = High FPGA makes a final clearing pass and releases INIT when finished.
Release INIT
If used to delay configuration
INIT?
Low
High
Load a Configuration Bit Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error.
End of Bitstream? Yes
No
If no CRC errors found, FPGA enters start-up phase causing DONE to go High.
Configuration Completed
ds003_154_111799
Figure 15: Serial Configuration Flowchart After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be retained to permit high-speed 8-bit readback. Retention of the SelectMAP port is selectable on a design-by-design basis when the bitstream is generated. If retention is selected, PROHIBIT constraints are required to prevent the SelectMAP-port pins from being used as user I/O. Table 9: SelectMAP Write Timing Characteristics Description D0-7 Setup/Hold CS Setup/Hold CCLK WRITE Setup/Hold BUSY Propagation Delay Maximum Frequency Maximum Frequency with no handshake 1/2 3/4 5/6 7 Symbol TSMDCC/TSMCCD TSMCSCC/TSMCCCS TSMCCW/TSMWCC TSMCKBY FCC FCCNH 5.0 / 1.7 7.0 / 1.7 7.0 / 1.7 12.0 66 50 Units ns, min ns, min ns, min ns, max MHz, max MHz, max Multiple Virtex FPGAs can be configured using the SelectMAP mode, and be made to start-up simultaneously. To configure multiple devices in this way, wire the individual CCLK, Data, WRITE, and BUSY pins of all the devices in parallel. The individual devices are loaded separately by asserting the CS pin of each device in turn and writing the appropriate data. See Table 9 for SelectMAP Write Timing Characteristics.
.
Write
Write operations send packets of configuration data into the FPGA. The sequence of operations for a multi-cycle write operation is shown below. Note that a configuration packet can be split into many such sequences. The packet does not have to complete within one assertion of CS, illustrated in Figure 16.
1. Assert WRITE and CS Low. Note that when CS is asserted on successive CCLKs, WRITE must remain either asserted or de-asserted. Otherwise an abort will be initiated, as described below. 2. Drive data onto D[7:0]. Note that to avoid contention, the data source should not be enabled while CS is Low and WRITE is High. Similarly, while WRITE is High, no more that one CS should be asserted.
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VirtexTM 2.5 V Field Programmable Gate Arrays 3. At the rising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High (from a previous write), the data is not accepted. Acceptance will instead occur on the first clock after BUSY goes Low, and the data must be held until this has happened. 4. Repeat steps 2 and 3 until all the data has been sent. 5. De-assert CS and WRITE.
R
A flowchart for the write operation appears in Figure 17. Note that if CCLK is slower than fCCNH, the FPGA never asserts BUSY. In this case, the above handshake is unnecessary, and data can simply be entered into the FPGA every CCLK cycle.
CCLK CS WRITE
3 5 1 2 4 6
DATA[0:7]
7
BUSY Write Write No Write Write
ds003_16_071902
Figure 16: Write Operations
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Apply Power FPGA starts to clear configuration memory.
PROGRAM from Low to High
No
FPGA makes a final clearing pass and releases INIT when finished.
Yes Release INIT If used to delay configuration
INIT?
Low
High Set WRITE = Low
Enter Data Source Sequence A
Set CS = Low
On first FPGA
Apply Configuration Byte Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error.
Busy?
High
Low No
End of Data? If no errors, first FPGAs enter start-up phase releasing DONE. Yes Set CS = High
On first FPGA
If no errors, later FPGAs enter start-up phase releasing DONE.
Repeat Sequence A
For any other FPGAs
Disable Data Source
Set WRITE = High When all DONE pins are released, DONE goes High and start-up sequences complete.
Configuration Completed
ds003_17_090602
Figure 17: SelectMAP Flowchart for Write Operation
Abort
During a given assertion of CS, the user cannot switch from a write to a read, or vice-versa. This action causes the current packet command to be aborted. The device will remain BUSY until the aborted operation has completed. Following an abort, data is assumed to be unaligned to word bound-
aries, and the FPGA requires a new synchronization word prior to accepting any new packets. To initiate an abort during a write operation, de-assert WRITE. At the rising edge of CCLK, an abort is initiated, as shown in Figure 18.
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The end of the memory-clearing phase is signalled by INIT going High, and the completion of the entire process is signalled by DONE going High.
CCLK CS WRITE
VCC
The power-up timing of configuration signals is shown in Figure 19. The corresponding timing characteristics are listed in Table 10.
TPOR
DATA[0:7]
PROGRAM
BUSY
INIT
TPI
Abort
X8797_c
TICCK
CCLK OUTPUT or INPUT
Figure 18: SelectMAP Write Abort Waveforms
M0, M1, M2 (Required)
VALID
Boundary-Scan Mode
In the boundary-scan mode, configuration is done through the IEEE 1149.1 Test Access Port. Note that the PROGRAM pin must be pulled High prior to reconfiguration. A Low on the PROGRAM pin resets the TAP controller and no JTAG operations can be performed. Configuration through the TAP uses the CFG_IN instruction. This instruction allows data input on TDI to be converted into data packets for the internal configuration bus. The following steps are required to configure the FPGA through the boundary-scan port (when using TCK as a start-up clock). 1. Load the CFG_IN instruction into the boundary-scan instruction register (IR) 2. Enter the Shift-DR (SDR) state 3. Shift a configuration bitstream into TDI 4. Return to Run-Test-Idle (RTI) 5. Load the JSTART instruction into IR 6. Enter the SDR state 7. Clock TCK through the startup sequence 8. Return to RTI Configuration and readback via the TAP is always available. The boundary-scan mode is selected by a <101> or 001> on the mode pins (M2, M1, M0). For details on TAP characteristics, refer to XAPP139. Table 10: Power-up Timing Characteristics Description Power-on Reset Program Latency CCLK (output) Delay Symbol TPOR TPL TICCK TPROGRAM Value 2.0 100.0 0.5 4.0 Program Pulse Width 300
98122302
Figure 19: Power-Up Timing Configuration Signals
Units ms, max
s, max s, min s, max
ns, min
Delaying Configuration
INIT can be held Low using an open-drain driver. An open-drain is required since INIT is a bidirectional open-drain pin that is held Low by the FPGA while the configuration memory is being cleared. Extending the time that the pin is Low causes the configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded.
Start-Up Sequence
The default Start-up sequence is that one CCLK cycle after DONE goes High, the global 3-state signal (GTS) is released. This permits device outputs to turn on as necessary. One CCLK cycle later, the Global Set/Reset (GSR) and Global Write Enable (GWE) signals are released. This permits the internal storage elements to begin changing state in response to the logic and the user clock. The relative timing of these events can be changed. In addition, the GTS, GSR, and GWE events can be made dependent on the DONE pins of multiple devices all going High, forcing the devices to start in synchronism. The sequence can also be paused at any stage until lock has been achieved on any or all DLLs.
Configuration Sequence
The configuration of Virtex devices is a three-phase process. First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is activated by a start-up process. Configuration is automatically initiated on power-up unless it is delayed by the user, as described below. The configuration process can also be initiated by asserting PROGRAM.
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VirtexTM 2.5 V Field Programmable Gate Arrays
Data Stream Format
Virtex devices are configured by sequentially loading frames of data. Table 11 lists the total number of bits required to configure each device. For more detailed information, see application note XAPP151 "Virtex Configuration Architecture Advanced Users Guide". Table 11: Virtex Bit-Stream Lengths Device XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 # of Configuration Bits 559,200 781,216 1,040,096 1,335,840 1,751,808 2,546,048 3,607,968 4,715,616 6,127,744
Readback
The configuration data stored in the Virtex configuration memory can be readback for verification. Along with the configuration data it is possible to readback the contents all flip-flops/latches, LUTRAMs, and block RAMs. This capability is used for real-time debugging. For more detailed information, see Application Note XAPP138: Virtex FPGA Series Configuration and Readback, available online at www.xilinx.com.
Revision History
Date 11/98 01/99 02/99 05/99 05/99 07/99 Version 1.0 1.2 1.3 1.4 1.5 1.6 Initial Xilinx release. Updated package drawings and specs. Update of package drawings, updated specifications. Addition of package drawings and specifications. Replaced FG 676 & FG680 package drawings. Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19. Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate. Added IOB Input Switching Characteristics Standard Adjustments. Speed grade update to preliminary status, Power-on specification and Clock-to-Out Minimums additions, "0" hold time listing explanation, quiescent current listing update, and Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE. Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479, 117153, 117154, and 117612. Modified notes for Recommended Operating Conditions (voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43. Revision
09/99
1.7
01/00
1.8
DS003-2 (v2.8.1) December 9, 2002 Product Specification
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Date 01/00
Version 1.9
Revision Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. New TBCKO values; corrected FG680 package connection drawing; new note about status of CCLK pin after configuration. Modified "Pins not listed ..." statement. Speed grade update to Final status. Modified Table 18. * * * * * Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices. Corrected Units column in table under IOB Input Switching Characteristics. Added values to table under CLB SelectRAM Switching Characteristics. Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in Table 18. Corrected BG256 Pin Function Diagram. Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL. Updated SelectMAP Write Timing Characteristics values in Table 9. Converted file to modularized format. See the Virtex Data Sheet section. Made minor edits to text under Configuration. Made minor edit to Figure 16 and Figure 18. Added clarifications in the Configuration, Boundary-Scan Mode, and Block SelectRAM sections. Revised Figure 17. Added clarification in the Boundary Scan section. Corrected number of buffered Hex lines listed in General Purpose Routing section.
03/00 05/00 05/00 09/00
2.0 2.1 2.2 2.3
10/00
2.4
04/01
2.5
* * * * * * * *
07/19/01 07/19/02 09/10/02 12/09/02
2.6 2.7 2.8 2.8.1
Virtex Data Sheet
The Virtex Data Sheet contains the following modules: * * DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
* *
DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
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DS003-3 (v3.2) September 10, 2002
Production Product Specification
Virtex Electrical Characteristics
Definition of Terms
Electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance: These speed files are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary: These speed files are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production: These speed files are released once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. Contact the factory for design considerations requiring more detailed information. Table 1 correlates the current status of each Virtex device with a corresponding speed file designation. Table 1: Virtex Device Speed Grade Designations Speed Grade Designations Device
XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
Advance
Preliminary
Production
-6, -5, -4 -6, -5, -4 -6, -5, -4 -6, -5, -4 -6, -5, -4 -6, -5, -4 -6, -5, -4 -6, -5, -4 -6, -5, -4
All specifications are subject to change without notice.
(c) 1999-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Virtex DC Characteristics
Absolute Maximum Ratings
Symbol VCCINT VCCO VREF VIN VTS VCC TSTG TJ Voltage applied to 3-state output Longest Supply Voltage Rise Time from 1V-2.375V Storage temperature (ambient) Junction temperature(4) Plastic Packages Description(1) Supply voltage relative to GND (2) Supply voltage relative to GND (2) Input Reference Voltage Input voltage relative to GND (3) Using VREF Internal threshold -0.5 to 3.0 -0.5 to 4.0 -0.5 to 3.6 -0.5 to 3.6 -0.5 to 5.5 -0.5 to 5.5 50 -65 to +150 +125 Units V V V V V V ms C C
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability. 2. Power supplies can turn on in any order. 3. For protracted periods (e.g., longer than a day), VIN should not exceed VCCO by more than 3.6 V. 4. For soldering guidelines and thermal considerations, see the "Device Packaging" infomation on www.xilinx.com.
Recommended Operating Conditions
Symbol VCCINT (1) Description Input Supply voltage relative to GND, TJ = 0 C to +85C Input Supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TJ = 0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C Input signal transition time Commercial Industrial Commercial Industrial Min 2.5 - 5% 2.5 - 5% 1.4 1.4 Max 2.5 + 5% 2.5 + 5% 3.6 3.6 250 Units V V V V ns
VCCO (4) TIN
Notes: 1. Correct operation is guaranteed with a minimum VCCINT of 2.375 V (Nominal VCCINT -5%). Below the minimum value, all delay parameters increase by 3% for each 50-mV reduction in VCCINT below the specified range. 2. At junction temperatures above those listed as Operating Conditions, delay parameters do increase. Please refer to the TRCE report. 3. Input and output measurement threshold is ~50% of VCC. 4. Min and Max values for VCCO are I/O Standard dependant.
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VirtexTM 2.5 V Field Programmable Gate Arrays
DC Characteristics Over Recommended Operating Conditions
Symbol VDRINT VDRIO ICCINTQ Description Data Retention VCCINT Voltage (below which configuration data can be lost) Data Retention VCCO Voltage (below which configuration data can be lost) Quiescent VCCINT supply current (1,3) Device All All XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 ICCOQ Quiescent VCCO supply current (1) XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 IREF IL CIN IRPU IRPD VREF current per VREF pin Input or output leakage current Input capacitance (sample tested)
BGA, PQ, HQ, packages
Min 2.0 1.2
Max
Units V V
50 50 50 75 75 75 100 100 100 2 2 2 2 2 2 2 2 2 20 -10 +10 8
Note (2) Note (2)
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A pF mA mA
All All All All
Pad pull-up (when selected) @ Vin = 0 V, VCCO = 3.3 V (sample tested) Pad pull-down (when selected) @ Vin = 3.6 V (sample tested)
0.25 0.15
Notes: 1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating. 2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. 3. Multiply ICCINTQ limit by two for industrial grade.
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Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal power supply voltage of the device (1) from 0 V. The current is highest at the fastest suggested ramp rate (0 V to nominal voltage in 2 ms) and is lowest at the slowest allowed ramp rate (0 V to nominal voltage in 50 ms). For more details on power supply requirements, see Application Note XAPP158 on www.xilinx.com. Product Virtex Family, Commercial Grade Virtex Family, Industrial Grade Description (2) Minimum required current supply Minimum required current supply Current Requirement (1,3) 500 mA 2A
Notes: 1. Ramp rate used for this specification is from 0 - 2.7 VDC. Peak current occurs on or near the internal power-on reset threshold of 1.0V and lasts for less than 3 ms. 2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above. 3. Larger currents can result if ramp rates are forced to be faster.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed output currents over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO for each standard with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Input/Output Standard LVTTL (1) LVCMOS2 PCI, 3.3 V PCI, 5.0 V GTL GTL+ HSTL I (3) HSTL III HSTL IV SSTL3 I SSTL3 II SSTL2 I SSTL2 II CTT AGP VIL V, min - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 V, max 0.8 .7 44% VCCINT 0.8 VREF - 0.05 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.2 VREF - 0.2 VREF - 0.2 VREF - 0.2 VREF - 0.2 VREF - 0.2 V, min 2.0 1.7 60% VCCINT 2.0 VREF + 0.05 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VIH V, max 5.5 5.5 VCCO + 0.5 5.5 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 VOL V, Max 0.4 0.4 10% VCCO 0.55 0.4 0.6 0.4 0.4 0.4 VREF - 0.6 VREF - 0.8 VREF - 0.61 VREF - 0.80 VREF - 0.4 10% VCCO VOH V, Min 2.4 1.9 90% VCCO 2.4 n/a n/a VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VREF + 0.6 VREF + 0.8 VREF + 0.61 VREF + 0.80 VREF + 0.4 90% VCCO IOL mA 24 12
Note 2 Note 2
IOH mA -24 -12
Note 2 Note 2
40 36 8 24 48 8 16 7.6 15.2 8
Note 2
n/a n/a -8 -8 -8 -8 -16 -7.6 -15.2 -8
Note 2
Notes: 1. VOL and VOH for lower drive currents are sample tested. 2. Tested according to the relevant specifications. 3. DC input and output levels for HSTL18 (HSTL I/O standard with VCCO of 1.8 V) are provided in an HSTL white paper on www.xilinx.com.
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VirtexTM 2.5 V Field Programmable Gate Arrays
Virtex Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Virtex devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values shown in , page 6. Speed Grade Description
Propagation Delays
Device
Symbol
Min
-6
-5
-4
Units
Pad to I output, no delay Pad to I output, with delay
All XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
TIOPI TIOPID
0.39 0.8 0.8 0.8 0.8 0.8 0.9 0.9 1.1 1.1
0.8 1.5 1.5 1.5 1.5 1.5 1.8 1.8 2.1 2.1 1.6 3.7 3.7 3.9 4.0 4.0 4.1 4.2 4.4 4.5
0.9 1.7 1.7 1.7 1.7 1.7 2.0 2.0 2.4 2.4 1.8 4.2 4.2 4.3 4.4 4.4 4.6 4.7 4.9 5.1
1.0 1.9 1.9 1.9 1.9 1.9 2.3 2.3 2.7 2.7 2.0 4.8 4.8 4.9 5.1 5.1 5.3 5.4 5.6 5.8
ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
Pad to output IQ via transparent latch, no delay Pad to output IQ via transparent latch, with delay
All XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
TIOPLI TIOPLID
0.8 1.9 1.9 2.0 2.0 2.0 2.1 2.1 2.2 2.3
Sequential Delays
Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low Clock CLK to output IQ
All TCH TCL TIOCKIQ 0.8 0.8 0.2 1.5 1.5 0.7 1.7 1.7 0.7 2.0 2.0 0.8 ns, min ns, min ns, max
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Speed Grade Description Device Symbol Min -6 -5 -4 Units
Setup and Hold Times with respect to Clock CLK at IOB input register (1)
Setup Time / Hold Time
Pad, no delay Pad, with delay
All XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
TIOPICK/TIOICKP TIOPICKD/TIOICKPD
0.8 / 0 1.9 / 0 1.9 / 0 1.9 / 0 2.0 / 0 2.0 / 0 2.1 / 0 2.1 / 0 2.2 / 0 2.3 / 0
1.6 / 0 3.7 / 0 3.7 / 0 3.8 / 0 3.9 / 0 3.9 / 0 4.1 / 0 4.2 / 0 4.4 / 0 4.5 / 0 0.8 / 0
1.8 / 0 4.1 / 0 4.1 / 0 4.3 / 0 4.4 / 0 4.4 / 0 4.6 / 0 4.7 / 0 4.9 / 0 5.0 / 0 0.9 / 0
2.0 / 0 4.7 / 0 4.7 / 0 4.9 / 0 5.0 / 0 5.0 / 0 5.3 / 0 5.4 / 0 5.6 / 0 5.8 / 0 1.0 / 0
ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, max
ICE input
Set/Reset Delays
All
TIOICECK/TIOCKICE TIOSRCKI TIOSRIQ TGSRQ
0.37/ 0
SR input (IFF, synchronous) SR input to IQ (asynchronous) GSR to output IQ
All All All
0.49 0.70 4.9
1.0 1.4 9.7
1.1 1.6 10.9
1.3 1.8 12.5
ns, max ns, max ns, max
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
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IOB Input Switching Characteristics Standard Adjustments
Speed Grade Description
Data Input Delay Adjustments
Symbol TILVTTL TILVCMOS2 TIPCI33_3 TIPCI33_5 TIPCI66_3 TIGTL TIGTLP TIHSTL TISSTL2 TISSTL3 TICTT TIAGP
Standard (1) LVTTL LVCMOS2 PCI, 33 MHz, 3.3 V PCI, 33 MHz, 5.0 V PCI, 66 MHz, 3.3 V GTL GTL+ HSTL SSTL2 SSTL3 CTT AGP
Min 0 -0.02 -0.05 0.13 -0.05 0.10 0.06 0.02 -0.04 -0.02 0.01 -0.03
-6 0 -0.04 -0.11 0.25 -0.11 0.20 0.11 0.03 -0.08 -0.04 0.02 -0.06
-5 0 -0.04 -0.12 0.28 -0.12 0.23 0.12 0.03 -0.09 -0.05 0.02 -0.07
-4 0 -0.05 -0.14 0.33 -0.14 0.26 0.14 0.04 -0.10 -0.06 0.02 -0.08
Units ns ns ns ns ns ns ns ns ns ns ns ns
Standard-specific data input delay adjustments
Notes: 1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 9. Speed Grade Description
Propagation Delays
Symbol
Min
-6
-5
-4
Units
O input to Pad O input to Pad via transparent latch
3-State Delays
TIOOP TIOOLP TIOTHZ TIOTON TIOTLPHZ TIOTLPON TGTS
1.2 1.4
2.9 3.4
3.2 3.7
3.5 4.0
ns, max ns, max
T input to Pad high-impedance (1) T input to valid data on Pad T input to Pad high-impedance via transparent latch (1) T input to valid data on Pad via transparent latch GTS to Pad high impedance (1)
Sequential Delays
1.0 1.4 1.2 1.6 2.5
2.0 3.1 2.4 3.5 4.9
2.2 3.3 2.6 3.8 5.5
2.4 3.7 3.0 4.2 6.3
ns, max ns, max ns, max ns, max ns, max
Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low TCH TCL 0.8 0.8 1.5 1.5 1.7 1.7 2.0 2.0 ns, min ns, min
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Speed Grade Description Clock CLK to Pad delay with OBUFT enabled (non-3-state) Clock CLK to Pad high-impedance (synchronous) (1) Clock CLK to valid data on Pad delay, plus enable delay for OBUFT
Setup and Hold Times before/after Clock CLK (2)
Symbol TIOCKP TIOCKHZ TIOCKON
Min 1.0 1.1 1.5
-6 2.9 2.3 3.4
-5 3.2 2.5 3.7
-4 3.5 2.9 4.1
Units ns, max ns, max ns, max
Setup Time / Hold Time
O input OCE input SR input (OFF) 3-State Setup Times, T input 3-State Setup Times, TCE input 3-State Setup Times, SR input (TFF)
Set/Reset Delays
TIOOCK/TIOCKO TIOOCECK/TIOCKOCE TIOSRCKO/TIOCKOSR TIOTCK/TIOCKT TIOTCECK/TIOCKTCE TIOSRCKT/TIOCKTSR TIOSRP TIOSRHZ TIOSRON TIOGSRQ
0.51 / 0 0.37 / 0 0.52 / 0 0.34 / 0 0.41 / 0 0.49 / 0
1.1 / 0 0.8 / 0 1.1 / 0 0.7 / 0 0.9 / 0 1.0 / 0
1.2 / 0 0.9 / 0 1.2 / 0 0.8 / 0 0.9 / 0 1.1 / 0
1.3 / 0 1.0 / 0 1.4 / 0 0.9 / 0 1.1 / 0 1.3 / 0
ns, min ns, min ns, min ns, min ns, min ns, min
SR input to Pad (asynchronous) SR input to Pad high-impedance (asynchronous) (1) SR input to valid data on Pad (asynchronous) GSR to Pad
1.6 1.6 2.0 4.9
3.8 3.1 4.2 9.7
4.1 3.4 4.6 10.9
4.6 3.9 5.1 12.5
ns, max ns, max ns, max ns, max
Notes: 1. 3-state turn-off delays should not be adjusted. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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VirtexTM 2.5 V Field Programmable Gate Arrays
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Speed Grade Description
Output Delay Adjustments
Symbol
Standard (1)
Min
-6
-5
-4
Unit s
Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl)
TOLVTTL_S2 TOLVTTL_S4 TOLVTTL_S6 TOLVTTL_S8 TOLVTTL_S12 TOLVTTL_S16 TOLVTTL_S24 TOLVTTL_F2 TOLVTTL_F4 TOLVTTL_F6 TOLVTTL_F8 TOLVTTL_F12 TOLVTTL_F16 TOLVTTL_F24 TOLVCMOS2 TOPCI33_3 TOPCI33_5 TOPCI66_3 TOGTL TOGTLP TOHSTL_I TOHSTL_III TOHSTL_IV TOSSTL2_I TOSSLT2_II TOSSTL3_I TOSSTL3_II TOCTT TOAGP
LVTTL, Slow, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVTTL, Fast, 2mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS2 PCI, 33 MHz, 3.3 V PCI, 33 MHz, 5.0 V PCI, 66 MHz, 3.3 V GTL GTL+ HSTL I HSTL III HSTL IV SSTL2 I SSTL2 II SSTL3 I SSTL3 II CTT AGP
4.2 2.5 1.8 1.2 1.0 0.9 0.8 1.9 0.7 0.2 0.1 0 -0.10 -0.10 0.10 0.50 0.40 0.10 0.6 0.7 0.10 -0.10 -0.20 -0.10 -0.20 -0.20 -0.30 0 0
14.7 7.5 4.8 3.0 1.9 1.7 1.3 13.1 5.3 3.1 1.0 0 -0.05 -0.20 0.10 2.3 2.8 -0.40 0.50 0.8 -0.50 -0.9 -1.0 -0.50 -0.9 -0.50 -1.0 -0.6 -0.9
15.8 8.0 5.1 3.3 2.1 1.9 1.4 14.0 5.7 3.3 1.1 0 -0.05 -0.21 0.11 2.5 3.0 -0.42 0.54 0.9 -0.53 -0.9 -1.0 -0.53 -0.9 -0.53 -1.0 -0.6 -0.9
17.0 8.6 5.6 3.5 2.2 2.0 1.6 15.1 6.1 3.6 1.2 0 -0.05 -0.23 0.12 2.7 3.3 -0.46 0.6 1.0 -0.5 -1.0 -1.1 -0.5 -1.0 -0.5 -1.1 -0.6 -1.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see Table 2 and Table 3.
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Calculation of Tioop as a Function of Capacitance
Tioop is the propagation delay from the O Input of the IOB to the pad. The values for Tioop were based on the standard capacitive load (Csl) for each I/O standard as listed in Table 2. Table 2: Constants for Calculating Tioop Standard
LVTTL Fast Slew Rate, 2mA drive LVTTL Fast Slew Rate, 4mA drive LVTTL Fast Slew Rate, 6mA drive LVTTL Fast Slew Rate, 8mA drive LVTTL Fast Slew Rate, 12mA drive LVTTL Fast Slew Rate, 16mA drive LVTTL Fast Slew Rate, 24mA drive LVTTL Slow Slew Rate, 2mA drive LVTTL Slow Slew Rate, 4mA drive LVTTL Slow Slew Rate, 6mA drive LVTTL Slow Slew Rate, 8mA drive LVTTL Slow Slew Rate, 12mA drive LVTTL Slow Slew Rate, 16mA drive LVTTL Slow Slew Rate, 24mA drive LVCMOS2 PCI 33MHz 5V PCI 33MHZ 3.3 V PCI 66 MHz 3.3 V GTL GTL+ HSTL Class I HSTL Class III HSTL Class IV SSTL2 Class I SSTL2 Class II SSTL3 Class I SSTL3 Class II CTT AGP
For other capacitive loads, use the formulas below to calculate the corresponding Tioop. Tioop = Tioop + Topadjust + (Cload - Csl) * fl Where: Topadjust is reported above in the Output Delay Adjustment section. Cload is the capacitive load for the design. fl (ns/pF)
0.41 0.20 0.13 0.079 0.044 0.043 0.033 0.41 0.20 0.100 0.086 0.058 0.050 0.048 0.041 0.050 0.050 0.033 0.014 0.017 0.022 0.016 0.014 0.028 0.016 0.029 0.016 0.035 0.037 AGP GTL GTL+ HSTL Class I HSTL Class III HSTL Class IV SSTL3 I & II SSTL2 I & II CTT VREF -0.2 VREF -0.2 VREF -0.5 VREF -0.5 VREF -0.5 VREF -1.0 VREF -0.75 VREF -0.2 VREF - (0.2xVCCO) VREF +0.2 VREF +0.2 VREF +0.5 VREF +0.5 VREF +0.5 VREF +1.0 VREF +0.75 VREF +0.2 VREF + (0.2xVCCO) VREF VREF VREF VREF VREF VREF VREF VREF VREF 0.80 1.0 0.75 0.90 0.90 1.5 1.25 1.5 Per AGP Spec
Csl (pF)
35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 50 10 10 0 0 20 20 20 30 30 30 30 20 10
Table 3: Delay Measurement Methodology Standard
LVTTL LVCMOS2 PCI33_5 PCI33_3 PCI66_3
VL (1)
0 0
VH (1)
3 2.5 Per PCI Spec Per PCI Spec Per PCI Spec
Meas. Point
1.4 1.125
VREF Typ (2)
-
Notes: 1. Input waveform switches between VLand VH. 2. Measurements are made at VREF (Typ), Maximum, and Minimum. Worst-case values are reported. 3. I/O parameter measurements are made with the capacitance values shown in Table 2. See Application Note XAPP133 on www.xilinx.com for appropriate terminations. 4. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it.
Notes: 1. I/O parameter measurements are made with the capacitance values shown above. See Application Note XAPP133 on www.xilinx.com for appropriate terminations. 2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it.
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VirtexTM 2.5 V Field Programmable Gate Arrays
Clock Distribution Guidelines
Speed Grade Description Global Clock Skew (1) Global Clock Skew between IOB Flip-flops XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 TGSKEWIOB 0.10 0.12 0.12 0.13 0.14 0.13 0.14 0.16 0.20 0.12 0.13 0.13 0.14 0.16 0.13 0.15 0.17 0.23 0.14 0.15 0.15 0.16 0.18 0.14 0.17 0.20 0.25 ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max Device Symbol -6 -5 -4 Units
Notes: 1. These clock-skew delays are provided for guidance only. They reflect the delays encountered in a typical design under worst-case conditions. Precise values for a particular design are provided by the timing analyzer.
Clock Distribution Switching Characteristics
Speed Grade Description GCLK IOB and Buffer Global Clock PAD to output. Global Clock Buffer I input to O output TGPIO TGIO 0.33 0.34 0.7 0.7 0.8 0.8 0.9 0.9 ns, max ns, max Symbol Min -6 -5 -4 Units
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I/O Standard Global Clock Input Adjustments
Speed Grade Description Data Input Delay Adjustments Standard-specific global clock input delay adjustments TGPLVTTL TGPLVCMOS
2
Symbol
Standard (1)
Min
-6
-5
-4
Units
LVTTL LVCMOS2 PCI, 33 MHz, 3.3 V PCI, 33 MHz, 5.0 V PCI, 66 MHz, 3.3 V GTL GTL+ HSTL SSTL2 SSTL3 CTT AGP
0 -0.02 -0.05 0.13 -0.05 0.7 0.7 0.7 0.6 0.6 0.7 0.6
0 -0.04 -0.11 0.25 -0.11 0.8 0.8 0.7 0.52 0.6 0.7 0.54
0 -0.04 -0.12 0.28 -0.12 0.9 0.8 0.7 0.51 0.55 0.7 0.53
0 -0.05 -0.14 0.33 -0.14 0.9 0.8 0.7 0.50 0.54 0.7 0.52
ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
TGPPCI33_3 TGPPCI33_5 TGPPCI66_3 TGPGTL TGPGTLP TGPHSTL TGPSSTL2 TGPSSTL3 TGPCTT TGPAGP
Notes: 1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
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VirtexTM 2.5 V Field Programmable Gate Arrays
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise values are provided by the timing analyzer. Speed Grade Description Combinatorial Delays 4-input function: F/G inputs to X/Y outputs 5-input function: F/G inputs to F5 output 5-input function: F/G inputs to X output 6-input function: F/G inputs to Y output via F6 MUX 6-input function: F5IN input to Y output Incremental delay routing through transparent latch to XQ/YQ outputs BY input to YB output Sequential Delays FF Clock CLK to XQ/YQ outputs Latch Clock CLK to XQ/YQ outputs Setup and Hold Times before/after Clock CLK (1) 4-input function: F/G Inputs 5-input function: F/G inputs 6-input function: F5IN input 6-input function: F/G inputs via F6 MUX BX/BY inputs CE input SR/BY inputs (synchronous) Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low Set/Reset Minimum Pulse Width, SR/BY inputs Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) Delay from GSR to XQ/YQ outputs Toggle Frequency (MHz) (for export control) TRPW TRQ TIOGSRQ FTOG (MHz) 1.3 0.54 4.9 625 2.5 1.1 9.7 333 2.8 1.3 10.9 294 3.3 1.4 12.5 250 ns, min ns, max ns, max MHz TCH TCL 0.8 0.8 1.5 1.5 1.7 1.7 2.0 2.0 ns, min ns, min TICK/TCKI TIF5CK/TCKIF5 TF5INCK/TCKF5IN TIF6CK/TCKIF6 TDICK/TCKDI TCECK/TCKCE TRCKTCKR TCKO TCKLO 0.54 0.6 1.1 1.2 1.2 1.4 1.4 1.6 ns, max ns, max TILO TIF5 TIF5X TIF6Y TF5INY TIFNCTL TBYYB 0.29 0.32 0.36 0.44 0.17 0.31 0.27 0.6 0.7 0.8 0.9 0.32 0.7 0.53 0.7 0.8 0.8 1.0 0.36 0.7 0.6 0.8 0.9 1.0 1.2 0.42 0.8 0.7 ns, max ns, max ns, max ns, max ns, max ns, max ns, max Symbol Min -6 -5 -4 Units
Setup Time / Hold Time 0.6 / 0 0.7 / 0 0.46 / 0 0.8 / 0 0.30 / 0 0.37 / 0 0.33 / 0 1.2 / 0 1.3 / 0 1.0 / 0 1.5 / 0 0.6 / 0 0.8 / 0 0.7 / 0 1.4 / 0 1.5 / 0 1.1 / 0 1.7 / 0 0.7 / 0 0.9 / 0 0.8 / 0 1.5 / 0 1.7 / 0 1.2 / 0 1.9 / 0 0.8 / 0 1.0 / 0 0.9 / 0 ns, min ns, min ns, min ns, min ns, min ns, min ns, min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Speed Grade Description Combinatorial Delays F operand inputs to X via XOR F operand input to XB output F operand input to Y via XOR F operand input to YB output F operand input to COUT output G operand inputs to Y via XOR G operand input to YB output G operand input to COUT output BX initialization input to COUT CIN input to X output via XOR CIN input to XB CIN input to Y via XOR CIN input to YB CIN input to COUT output Multiplier Operation F1/2 operand inputs to XB output via AND F1/2 operand inputs to YB output via AND F1/2 operand inputs to COUT output via AND G1/2 operand inputs to YB output via AND G1/2 operand inputs to COUT output via AND Setup and Hold Times before/after Clock CIN input to FFX CIN input to FFY CLK (1) TCCKX/TCKCX TCCKY/TCKCY TFANDXB TFANDYB TFANDCY TGANDYB TGANDCY 0.18 0.40 0.22 0.25 0.07 0.36 0.8 0.43 0.50 0.13 0.40 0.9 0.48 0.6 0.15 0.46 1.1 0.6 0.7 0.17 ns, max ns, max ns, max ns, max ns, max TOPX TOPXB TOPY TOPYB TOPCYF TOPGY TOPGYB TOPCYG TBXCY TCINX TCINXB TCINY TCINYB TBYP 0.37 0.54 0.8 0.8 0.6 0.46 0.8 0.7 0.41 0.21 0.02 0.23 0.23 0.05 0.8 1.1 1.5 1.5 1.2 1.0 1.6 1.3 0.9 0.41 0.04 0.46 0.45 0.09 0.9 1.3 1.7 1.7 1.3 1.1 1.8 1.4 1.0 0.46 0.05 0.52 0.51 0.10 1.0 1.4 2.0 2.0 1.5 1.2 2.1 1.6 1.1 0.53 0.06 0.6 0.6 0.11 ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max Symbol Min -6 -5 -4 Units
Setup Time / Hold Time 0.50 / 0 0.53 / 0 1.0 / 0 1.1 / 0 1.2 / 0 1.2 / 0 1.3 / 0 1.4 / 0 ns, min ns, min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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VirtexTM 2.5 V Field Programmable Gate Arrays
CLB SelectRAM Switching Characteristics
Speed Grade Description Sequential Delays Clock CLK to X/Y outputs (WE active) 16 x 1 mode Clock CLK to X/Y outputs (WE active) 32 x 1 mode Shift-Register Mode Clock CLK to X/Y outputs Setup and Hold Times before/after Clock CLK (1) F/G address inputs BX/BY data inputs (DIN) CE input (WE) Shift-Register Mode BX/BY data inputs (DIN) CE input (WS) Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low Minimum clock period to meet address write cycle time Shift-Register Mode Minimum Pulse Width, High Minimum Pulse Width, Low TSRPH TSRPL 1.2 1.2 2.4 2.4 2.7 2.7 3.1 3.1 ns, min ns, min TWPH TWPL TWC 1.2 1.2 2.4 2.4 2.4 4.8 2.7 2.7 5.4 3.1 3.1 6.2 ns, min ns, min ns, min TSHDICK TSHCECK 0.34 0.38 0.7 0.8 0.8 0.9 0.9 1.0 ns, min ns, min TAS/TAH TDS/TDH TWS/TWH TREG 1.2 3.7 4.1 4.7 ns, max TSHCKO16 TSHCKO32 1.2 1.2 2.3 2.7 2.6 3.1 3.0 3.5 ns, max ns, max Symbol Min -6 -5 -4 Units
Setup Time / Hold Time 0.25 / 0 0.34 / 0 0.38 / 0 0.5 / 0 0.7 / 0 0.8 / 0 0.6 / 0 0.8 / 0 0.9 / 0 0.7 / 0 0.9 / 0 1.0 / 0 ns, min ns, min ns, min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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Block RAM Switching Characteristics
Speed Grade Description Sequential Delays Clock CLK to DOUT output Setup and Hold Times before/after Clock CLK (1) ADDR inputs DIN inputs EN input RST input WEN input Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low CLKA -> CLKB setup time for different ports TBPWH TBPWL TBCCS 0.8 0.8 1.5 1.5 3.0 1.7 1.7 3.5 2.0 2.0 4.0 ns, min ns, min ns, min TBACK/TBCKA TBDCK/TBCKD TBECK/TBCKE TBRCK/TBCKR TBWCK/TBCKW TBCKO 1.7 3.4 3.8 4.3 ns, max Symbol Min -6 -5 -4 Units
Setup Time / Hold Time 0.6 / 0 0.6 / 0 1.3 / 0 1.3 / 0 1.2 / 0 1.2 / 0 1.2 / 0 2.6 / 0 2.5 / 0 2.3 / 0 1.3 / 0 1.3 / 0 3.0 / 0 2.7 / 0 2.6 / 0 1.5 / 0 1.5 / 0 3.4 / 0 3.2 / 0 3.0 / 0 ns, min ns, min ns, min ns, min ns, min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
TBUF Switching Characteristics
Speed Grade Description Combinatorial Delays IN input to OUT output TRI input to OUT output high-impedance TRI input to valid data on OUT output TIO TOFF TON 0 0.05 0.05 0 0.09 0.09 0 0.10 0.10 0 0.11 0.11 ns, max ns, max ns, max Symbol Min -6 -5 -4 Units
JTAG Test Access Port Switching Characteristics
Speed Grade Description TMS and TDI Setup times before TCK TMS and TDI Hold times after TCK Output delay from clock TCK to output TDO Maximum TCK clock frequency Symbol TTAPTCK TTCKTAP TTCKTDO FTCK -6 4.0 2.0 11.0 33 -5 4.0 2.0 11.0 33 -4 4.0 2.0 11.0 33 Units ns, min ns, min ns, max MHz, max
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DS003-3 (v3.2) September 10, 2002 Production Product Specification
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VirtexTM 2.5 V Field Programmable Gate Arrays
Virtex Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Speed Grade Description LVTTL Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, with DLL. For data output with different standards, adjust delays with the values shown in Output Delay Adjustments. Symbol TICKOFDLL Device XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 -6 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 -5 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 -4 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 Units ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values. For other I/O standards and different loads, see Table 2 and Table 3. 3. DLL output jitter is already included in the timing calculation.
Global Clock Input-to-Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Speed Grade Description LVTTL Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, without DLL. For data output with different standards, adjust delays with the values shown in Input and Output Delay Adjustments. For I/O standards requiring VREF, such as GTL, GTL+, SSTL, HSTL, CTT, and AGO, an additional 600 ps must be added. Symbol TICKOF Device XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 Min 1.5 1.5 1.5 1.5 1.5 1.5 1.6 1.6 1.7 -6 4.6 4.6 4.7 4.7 4.7 4.8 4.9 4.9 5.0 -5 5.1 5.1 5.2 5.2 5.2 5.3 5.4 5.5 5.6 -4 5.7 5.7 5.8 5.8 5.9 6.0 6.0 6.2 6.3 Units ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values. For other I/O standards and different loads, see Table 2 and Table 3.
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Minimum Clock-to-Out for Virtex Devices
With DLL I/O Standard *LVTTL_S2 *LVTTL_S4 *LVTTL_S6 *LVTTL_S8 *LVTTL_S12 *LVTTL_S16 *LVTTL_S24 *LVTTL_F2 *LVTTL_F4 *LVTTL_F6 *LVTTL_F8 *LVTTL_F12 *LVTTL_F16 *LVTTL_F24 LVCMOS2 PCI33_3 PCI33_5 PCI66_3 GTL GTL+ HSTL I HSTL III HSTL IV SSTL2 I SSTL2 II SSTL3 I SSTL3 II CTT AGP All Devices 5.2 3.5 2.8 2.2 2.0 1.9 1.8 2.9 1.7 1.2 1.1 1.0 0.9 0.9 1.1 1.5 1.4 1.1 1.6 1.7 1.1 0.9 0.8 0.9 0.8 0.8 0.7 1.0 1.0 V50 6.0 4.3 3.6 3.1 2.9 2.8 2.6 3.8 2.6 2.0 1.9 1.8 1.7 1.7 1.9 2.4 2.2 1.9 2.5 2.5 1.9 1.7 1.6 1.7 1.6 1.6 1.5 1.8 1.8 V100 6.0 4.3 3.6 3.1 2.9 2.8 2.6 3.8 2.6 2.0 1.9 1.8 1.8 1.7 1.9 2.4 2.2 1.9 2.5 2.5 1.9 1.7 1.6 1.7 1.6 1.7 1.5 1.8 1.8 V150 6.0 4.3 3.6 3.1 2.9 2.8 2.7 3.8 2.6 2.0 1.9 1.8 1.8 1.7 1.9 2.4 2.3 2.0 2.5 2.6 1.9 1.8 1.6 1.7 1.6 1.7 1.6 1.8 1.9 V200 6.0 4.3 3.6 3.1 2.9 2.8 2.7 3.8 2.6 2.1 1.9 1.8 1.8 1.8 2.0 2.4 2.3 2.0 2.5 2.6 1.9 1.8 1.7 1.7 1.6 1.7 1.6 1.9 1.9 Without DLL V300 6.1 4.4 3.7 3.1 2.9 2.8 2.7 3.8 2.6 2.1 2.0 1.9 1.8 1.8 2.0 2.4 2.3 2.0 2.5 2.6 2.0 1.8 1.7 1.8 1.7 1.7 1.6 1.9 1.9 V400 6.1 4.4 3.7 3.1 2.9 2.8 2.7 3.8 2.6 2.1 2.0 1.9 1.8 1.8 2.0 2.4 2.3 2.0 2.5 2.6 2.0 1.8 1.7 1.8 1.7 1.7 1.6 1.9 1.9 V600 6.1 4.4 3.7 3.2 3.0 2.9 2.7 3.9 2.7 2.1 2.0 1.9 1.8 1.8 2.0 2.5 2.3 2.0 2.6 2.6 2.0 1.8 1.7 1.8 1.7 1.7 1.6 1.9 1.9 V800 6.1 4.4 3.7 3.2 3.0 2.9 2.7 3.9 2.7 2.1 2.0 1.9 1.9 1.8 2.0 2.5 2.3 2.1 2.6 2.6 2.0 1.8 1.7 1.8 1.7 1.8 1.6 1.9 1.9 V1000 6.1 4.4 3.7 3.2 3.0 2.9 2.8 3.9 2.7 2.2 2.0 1.9 1.9 1.9 2.1 2.5 2.4 2.1 2.6 2.7 2.0 1.9 1.8 1.8 1.7 1.8 1.7 2.0 2.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
*S = Slow Slew Rate, F = Fast Slew Rate Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Input and output timing is measured at 1.4 V for LVTTL. For other I/O standards, see Table 3. In all cases, an 8 pF external capacitive load is used.
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VirtexTM 2.5 V Field Programmable Gate Arrays
Virtex Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVTTL Standard, with DLL
Speed Grade Description Symbol Device Min -6 -5 -4 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in Input Delay Adjustments. No Delay Global Clock and IFF, with DLL XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
IFF = Input Flip-Flop or Latch Notes: 1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 2. DLL output jitter is already included in the timing calculation. 3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
TPSDLL/TPHDLL
XCV50
0.40 / -0.4 0.40 /-0.4 0.40 /-0.4 0.40 /-0.4 0.40 /-0.4 0.40 /-0.4 0.40 /-0.4 0.40 /-0.4 0.40 /-0.4
1.7 /-0.4 1.7 /-0.4 1.7 /-0.4 1.7 /-0.4 1.7 /-0.4 1.7 /-0.4 1.7 /-0.4 1.7 /-0.4 1.7 /-0.4
1.8 /-0.4 1.9 /-0.4 1.9 /-0.4 1.9 /-0.4 1.9 /-0.4 1.9 /-0.4 1.9 /-0.4 1.9 /-0.4 1.9 /-0.4
2.1 /-0.4 2.1 /-0.4 2.1 /-0.4 2.1 /-0.4 2.1 /-0.4 2.1 /-0.4 2.1 /-0.4 2.1 /-0.4 2.1 /-0.4
ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min
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Global Clock Set-Up and Hold for LVTTL Standard, without DLL
Speed Grade Description Symbol Device Min -6 -5 -4 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. (2) For data input with different standards, adjust the setup time delay by the values shown in Input Delay Adjustments. Full Delay Global Clock and IFF, without DLL TPSFD/TPHFD XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
IFF = Input Flip-Flop or Latch Notes: Notes: 1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
0.6 / 0 0.6 / 0 0.6 / 0 0.7 / 0 0.7 / 0 0.7 / 0 0.7 / 0 0.7 / 0 0.7 / 0
2.3 / 0 2.3 / 0 2.4 / 0 2.5 / 0 2.5 / 0 2.6 / 0 2.6 / 0 2.7 / 0 2.8 / 0
2.6 / 0 2.6 / 0 2.7 / 0 2.8 / 0 2.8 / 0 2.9 / 0 2.9 / 0 3.1 / 0 3.1 / 0
2.9 / 0 3.0 / 0 3.1 / 0 3.2 / 0 3.2 / 0 3.3 / 0 3.3 / 0 3.5 / 0 3.6 / 0
ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min
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VirtexTM 2.5 V Field Programmable Gate Arrays
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating conditions. Speed Grade -6 Description Input Clock Frequency (CLKDLLHF) Input Clock Frequency (CLKDLL) Input Clock Pulse Width (CLKDLLHF) Input Clock Pulse Width (CLKDLL) Symbol FCLKINHF FCLKINLF TDLLPWHF TDLLPWLF Min 60 25 2.0 2.5 Max 200 100 Min 60 25 2.4 3.0 -5 Max 180 90 Min 60 25 2.4 3.0 -4 Max 180 90 Units MHz MHz ns ns
Notes: 1. All specifications correspond to Commercial Operating Temperatures (0C to + 85C).
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. CLKDLLHF Description Input Clock Period Tolerance Input Clock Jitter Tolerance (Cycle to Cycle) Time Required for DLL to Acquire Lock Symbol TIPTOL TIJITCC TLOCK > 60 MHz 50 - 60 MHz 40 - 50 MHz 30 - 40 MHz 25 - 30 MHz Output Jitter (cycle-to-cycle) for any DLL Clock Output (1) Phase Offset between CLKIN and CLKO (2) TOJITCC TPHIO TPHOO TPHIOM TPHOOM FCLKIN Min Max 1.0 150 20 60 100 140 160 200 CLKDLL Min Max 1.0 300 20 25 50 90 120 60 100 140 160 200 Units ns ps s s s s s ps ps ps ps ps
Phase Offset between Clock Outputs on the DLL (3) Maximum Phase Difference between CLKIN and CLKO (4) Maximum Phase Difference between Clock Outputs on the DLL (5)
Notes: 1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter. 2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO, excluding Output Jitter and input clock jitter. 3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL outputs, excluding Output Jitter and input clock jitter. 4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO, or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter). 5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter). 6. All specifications correspond to Commercial Operating Temperatures (0C to +85C).
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Period Tolerance: the allowed input clock period change in nanoseconds.
TCLKIN
TCLKIN + TIPTOL _
Output Jitter: the difference between an ideal reference clock edge and the actual design.
Phase Offset and Maximum Phase Difference
Ideal Period Actual Period
+ Jitter
+/- Jitter + Maximum Phase Difference + Phase Offset ds003_20c_110399
Figure 1: Frequency Tolerance and Clock Jitter
Revision History
Date 11/98 01/99 02/99 05/99 05/99 07/99 Version 1.0 1.2 1.3 1.4 1.5 1.6 Initial Xilinx release. Updated package drawings and specs. Update of package drawings, updated specifications. Addition of package drawings and specifications. Replaced FG 676 & FG680 package drawings. Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19. Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate. Added IOB Input Switching Characteristics Standard Adjustments. Speed grade update to preliminary status, Power-on specification and Clock-to-Out Minimums additions, "0" hold time listing explanation, quiescent current listing update, and Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE. Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479, 117153, 117154, and 117612. Modified notes for Recommended Operating Conditions (voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43. Revision
09/99
1.7
01/00
1.8
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VirtexTM 2.5 V Field Programmable Gate Arrays
Date 01/00
Version 1.9
Revision Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. New TBCKO values; corrected FG680 package connection drawing; new note about status of CCLK pin after configuration. Modified "Pins not listed ..." statement. Speed grade update to Final status. Modified Table 18. * * * * * Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices. Corrected Units column in table under IOB Input Switching Characteristics. Added values to table under CLB SelectRAM Switching Characteristics. Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in Table 18. Corrected BG256 Pin Function Diagram. Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL. Converted file to modularized format. See the Virtex Data Sheet section. Clarified TIOCKP and TIOCKON IOB Output Switching Characteristics descriptors. Under Absolute Maximum Ratings, changed (TSOL) to 220 C . Removed TSOL parameter and added footnote to Absolute Maximum Ratings table. Updated the speed grade designations used in data sheets, and added Table 1, which shows the current speed grade designation for each device. Added footnote to DC Input and Output Levels table. Removed mention of MIL-M-38510/605 specification. Added link to xapp158 from the Power-On Power Supply Requirements section. Added Clock CLK to IOB Input Switching Characteristics and IOB Output Switching Characteristics.
03/00 05/00 05/00 09/00
2.0 2.1 2.2 2.3
10/00
2.4
04/02/01 04/19/01 07/19/01 07/26/01 10/29/01 02/01/02 07/19/02 09/10/02
2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2
* * * * * * * * * *
Virtex Data Sheet
The Virtex Data Sheet contains the following modules: * * DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
* *
DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
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Virtex Pin Definitions
Table 1: Special Purpose Pins Pin Name
GCK0, GCK1, GCK2, GCK3 M0, M1, M2 CCLK
Dedicated Pin
Yes Yes Yes
Direction
Input Input Input or Output Input Bidirectional Bidirectional (Open-drain) Output
Description
Clock input pins that connect to Global Clock Buffers. These pins become user inputs when not needed for clocks. Mode pins are used to specify the configuration mode. The configuration Clock I/O pin: it is an input for SelectMAP and slave-serial modes, and output in master-serial mode. After configuration, it is input only, logic level = Don't Care. Initiates a configuration sequence when asserted Low. Indicates that configuration loading is complete, and that the start-up sequence is in progress. The output can be open drain. When Low, indicates that the configuration memory is being cleared. The pin becomes a user I/O after configuration. In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. In bit-serial modes, DOUT provides header information to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration.
PROGRAM DONE INIT BUSY/ DOUT
Yes Yes No No
D0/DIN, D1, D2, D3, D4, D5, D6, D7 WRITE CS TDI, TDO, TMS, TCK DXN, DXP VCCINT VCCO VREF GND
No
Input or Output
In SelectMAP mode, D0 - D7 are configuration data pins. These pins become user I/Os after configuration unless the SelectMAP port is retained. In bit-serial modes, DIN is the single data input. This pin becomes a user I/O after configuration.
No No Yes Yes Yes Yes No Yes
Input Input Mixed N/A Input Input Input Input
In SelectMAP mode, the active-low Write Enable signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. In SelectMAP mode, the active-low Chip Select signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. Boundary-scan Test-Access-Port pins, as defined in IEEE 1149.1. Temperature-sensing diode pins. (Anode: DXP, cathode: DXN) Power-supply pins for the internal core logic. Power-supply pins for the output drivers (subject to banking rules) Input threshold voltage pins. Become user I/Os when an external threshold voltage is not needed (subject to banking rules). Ground
(c) 1999-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Virtex Pinout Information
Pinout Tables
See www.xilinx.com for updates or additional pinout information. For convenience, Table 2, Table 3 and Table 4 list the locations of special-purpose and power-supply pins. Pins not listed are either user I/Os or not connected, depending on the device/package combination. See the Pinout Diagrams starting on page 17 for any pins not listed for a particular part/package combination. Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) Pin Name GCK0 GCK1 GCK2 GCK3 M0 M1 M2 CCLK PROGRAM DONE INIT BUSY/DOUT D0/DIN D1 D2 D3 D4 D5 D6 D7 WRITE CS TDI TDO TMS TCK VCCINT All All All All All All All All All All All All All All All All All All All All All All All All All All All Device K7 M7 A7 A6 M1 L2 N2 B13 L12 M12 L13 C11 C12 E10 E12 F11 H12 J13 J11 K10 C10 D10 A11 A12 B1 C3 A9, B6, C5, G3, G12, M5, M9, N6 CS144 90 93 19 16 110 112 108 38 72 74 71 39 40 45 47 51 59 63 65 70 32 33 34 36 143 2 10, 15, 25, 57, 84, 94, 99, 126 TQ144 92 89 210 213 60 58 62 179 122 120 123 178 177 167 163 156 145 138 134 124 185 184 183 181 2 239 16, 32, 43, 77, 88, 104, 137, 148, 164, 198, 214, 225 PQ/HQ240
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Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued) Pin Name VCCO All Device CS144 Banks 0 and 1: A2, A13, D7 Banks 2 and 3: B12, G11, M13 Banks 4 and 5: N1, N7, N13 Banks 6 and 7: B2, G2, M2 VREF, Bank 0 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 1 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 2 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 D11, F10 ... + D13 N/A N/A N/A N/A 42, 50 ... + 44 N/A N/A N/A N/A 157, 171 ... + 168 ... + 175 ... + 154 ... + 169 ... + 161 XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 A10, B8 ... + D9 N/A N/A N/A N/A 22, 30 ... + 28 N/A N/A N/A N/A 191, 205 ... + 194 ... + 187 ... + 208 ... + 193 ... + 201 XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 C4, D6 ... + B4 N/A N/A N/A N/A 5, 13 ... + 7 N/A N/A N/A N/A 218, 232 ... + 229 ... + 236 ... + 215 ... + 230 ... + 222 TQ144 No I/O Banks in this package: 1, 17, 37, 55, 73, 92, 109, 128 PQ/HQ240 No I/O Banks in this package: 15, 30, 44, 61, 76, 90, 105, 121, 136, 150, 165, 180, 197, 212, 226, 240
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VirtexTM 2.5 V Field Programmable Gate Arrays Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued) Pin Name VREF, Bank 3 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 4 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 5 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 L4, L6 ... + N4 N/A N/A N/A N/A 96, 104 ... + 102 N/A N/A N/A N/A 70, 84 ... + 73 ... + 66 ... + 87 ... + 72 ... + 80 XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 L8, L10 ... + N10 N/A N/A N/A N/A 79, 87 ... + 81 N/A N/A N/A N/A 97, 111 ... + 108 ... + 115 ... + 94 ... + 109 ... + 101 Device XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 CS144 H11, K12 ... + J10 N/A N/A N/A N/A TQ144 60, 68 ... + 66 N/A N/A N/A N/A PQ/HQ240 130, 144 ... + 133 ... + 126 ... + 147 ... + 132 ... + 140
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Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued) Pin Name VREF, Bank 6 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 7 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. GND All A1, B9, B11, C7, D5, E4, E11, F1, G10, J1, J12, L3, L5, L7, L9, N12 9, 18, 26, 35, 46, 54, 64, 75, 83, 91, 100, 111, 120, 129, 136, 144, 1, 8, 14, 22, 29, 37, 45, 51, 59, 69, 75, 83, 91, 98, 106, 112, 119, 129, 135, 143, 151, 158, 166, 172, 182, 190, 196, 204, 211, 219, 227, 233 XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 D4, E1 ... + D2 N/A N/A N/A N/A 133, 140 ... + 138 N/A N/A N/A N/A 9, 23 ... + 12 ... + 5 ... + 26 ... + 11 ... + 19 Device XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 CS144 H2, K1 ... + J3 N/A N/A N/A N/A TQ144 116, 123 ... + 118 N/A N/A N/A N/A PQ/HQ240 36, 50 ... + 47 ... + 54 ... + 33 ... + 48 ... + 40
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Table 3: Virtex Pinout Tables (BGA) Pin Name GCK0 GCK1 GCK2 GCK3 M0 M1 M2 CCLK PROGRAM DONE INIT BUSY/DOUT D0/DIN D1 D2 D3 D4 D5 D6 D7 WRITE CS TDI TDO TMS TCK DXN DXP Device All All All All All All All All All All All All All All All All All All All All All All All All All All All All BG256 Y11 Y10 A10 B10 Y1 U3 W2 B19 Y20 W19 U18 D18 C19 E20 G19 J19 M19 P19 T20 V19 A19 B18 C17 A20 D3 A1 W3 V4 BG352 AE13 AF14 B14 D14 AD24 AB23 AC23 C3 AC4 AD3 AD2 E4 D3 G1 J3 M3 R3 U4 V3 AC3 D5 C4 B3 D4 D23 C24 AD23 AE24 BG432 AL16 AK16 A16 D17 AH28 AH29 AJ28 D4 AH3 AH4 AJ2 D3 C2 K4 K2 P4 V4 AB1 AB3 AG4 B4 D5 B3 C4 D29 D28 AH27 AK29 BG560 AL17 AJ17 D17 A17 AJ29 AK30 AN32 C4 AM1 AJ5 AH5 D4 E4 K3 L4 P3 W4 AB5 AC4 AJ4 D6 A2 D5 E6 B33 E29 AK29 AJ28
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Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name VCCINT
Notes: * Superset includes all pins, including the ones in bold type. Subset excludes pins in bold type. * In BG352, for XCV300 all the VCCINT pins in the superset must be connected. For XCV150/200, VCCINT pins in the subset must be connected, and pins in bold type can be left unconnected (these unconnected pins cannot be used as user I/O.) * In BG432, for XCV400/600/800 all VCCINT pins in the superset must be connected. For XCV300, VCCINT pins in the subset must be connected, and pins in bold type can be left unconnected (these unconnected pins cannot be used as user I/O.) * In BG560, for XCV800/1000 all VCCINT pins in the superset must be connected. For XCV400/600, VCCINT pins in the subset must be connected, and pins in bold type can be left unconnected (these unconnected pins cannot be used as user I/O.)
Device XCV50/100
BG256 C10, D6, D15, F4, F17, L3, L18, R4, R17, U6, U15, V10 Same as above
BG352 N/A
BG432 N/A
BG560 N/A
XCV150/200/300
A20, C14, D10, J24, K4, P2, P25, V24, W2, AC10, AE14, AE19, B16, D12, L1, L25, R23, T1, AF11, AF16
A10, A17, B23, C14, C19, K3, K29, N2, N29, T1, T29, W2, W31, AB2, AB30, AJ10, AJ16, AK13, AK19, AK22, B26, C7, F1, F30, AE29, AF1, AH8, AH24 Same as above
N/A
XCV400/600/800/1000
N/A
N/A
A21, B14, B18, B28, C24, E9, E12, F2, H30, J1, K32, N1, N33, U5, U30, Y2, Y31, AD2, AD32, AG3, AG31, AK8, AK11, AK17, AK20, AL14, AL27, AN25, B12, C22, M3, N29, AB2, AB32, AJ13, AL22
VCCO, Bank 0 VCCO, Bank 1 VCCO, Bank 2 VCCO, Bank 3 VCCO, Bank 4 VCCO, Bank 5
All All All All All All
D7, D8 D13, D14 G17, H17 N17, P17 U13, U14 U7, U8
A17, B25, D19 A10, D7, D13 B2, H4, K1 P4, U1, Y4 AC8, AE2, AF10 AC14, AC20, AF17 U26, W23, AE25
A21, C29, D21 A1, A11, D11 C3, L1, L4 AA1, AA4, AJ3 AH11, AL1, AL11 AH21, AJ29, AL21 AA28, AA31, AL31
A22, A26, A30, B19, B32 A10, A16, B13, C3, E5 B2, D1, H1, M1, R2 V1, AA2, AD1, AK1, AL2 AM2, AM15, AN4, AN8, AN12 AL31, AM21, AN18, AN24, AN30 W32, AB33, AF33, AK33, AM32
VCCO, Bank 6
All
N4, P4
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VirtexTM 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name VCCO, Bank 7 VREF, Bank 0 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 1 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Device All XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 XCV1000 XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 XCV1000 VREF, Bank 2 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 XCV1000 BG256 G4, H4 A8, B4 ... + A4 ... + A2 N/A N/A N/A N/A A17, B12 ... + B15 ... + B17 N/A N/A N/A N/A C20, J18 ... + F19 ... + G18 N/A N/A N/A N/A BG352 G23, K26, N23 N/A A16,C19, C21 ... + D21 N/A N/A N/A N/A N/A B6, C9, C12 ... + D6 N/A N/A N/A N/A N/A E2, H2, M4 ... + D2 N/A N/A N/A N/A E2, G3, J2, N1 ... + R3 ... + H1 ... + M3 N/A G5, H4, L5, P4, R1 ... + K5 ... + N5 ... + B3 N/A A13, B7, C6, C10 ... + B15 ... + D10 ... + B12 N/A N/A N/A A6, D7, D11, D16, E15 ... + D10 ... + D13 ... + E7 N/A N/A N/A BG432 A31, L28, L31 N/A N/A B19, D22, D24, D26 ... + C18 ... + C24 ... + B21 N/A N/A N/A BG560 C32, D33, K33, N32, T33 N/A N/A N/A A19, D20, D26, E23, E27 ... + E24 ... + E21 ... + D29 N/A N/A
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Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name VREF, Bank 3 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 4 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Device XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 XCV1000 XCV50 XCV100/150 XCV200/300 XCV400 BG256 M18, V20 ... + R19 ... + P18 N/A N/A N/A N/A V12, Y18 ... + W15 ... + V14 N/A BG352 N/A R4, V4, Y3 ... + AC2 N/A N/A N/A N/A N/A AC12, AE5, AE8, ... + AE4 N/A BG432 N/A N/A V2, AB4, AD4, AF3 ... + U2 ... + AC3 ... + Y3 N/A N/A N/A AJ7, AL4, AL8, AL13 ... + AK15 BG560 N/A N/A N/A V4, W5, AD3, AE5, AK2 ... + AF1 ... + AA4 ... + AH4 N/A N/A N/A AL7, AL10, AL16, AM4, AM14 ... + AL9 ... + AK13 ... + AN3 N/A N/A N/A AJ18, AJ25, AL20, AL24, AL29 ... + AM26 ... + AN23 ... + AK28 N/A N/A N/A V29, Y32, AD31, AE29, AK32 ... + AE31 ... + AA30 ... + AH30
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XCV600 XCV800 XCV1000
N/A N/A N/A V9, Y3 ... + W6 ... + V7 N/A
N/A N/A N/A N/A AC15, AC18, AD20 ... + AE23 N/A
... + AK8 ... + AJ12 N/A N/A N/A AJ18, AJ25, AK23, AK27 ... + AJ17
VREF, Bank 5 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O.
XCV50 XCV100/150 XCV200/300 XCV400
XCV600 XCV800 XCV1000
N/A N/A N/A M2, R3 ... + T1 ... + T3 N/A N/A N/A N/A
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N/A N/A N/A N/A R24, Y26, AA25, ... + AD26 N/A N/A N/A N/A
... + AL24 ... + AH19 N/A N/A N/A V28, AB28, AE30, AF28 ... + U28 ... + AC28 ... + Y30 N/A
VREF, Bank 6 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O.
XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 XCV1000
DS003-4 (v2.8) July 19, 2002 Production Product Specification
VirtexTM 2.5 V Field Programmable Gate Arrays Table 3: Virtex Pinout Tables (BGA) (Continued) Pin Name VREF, Bank 7 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Device XCV50 XCV100/150 XCV200/300 BG256 G3, H1 ... + D1 ... + B2 BG352 N/A D26, G26, L26 ... + E24 F28, F31, J30, N30 XCV400 XCV600 XCV800 XCV1000 GND All N/A N/A N/A N/A C3, C18, D4, D5, D9, D10, D11, D12, D16, D17, E4, E17, J4, J17, K4, K17, L4, L17, M4, M17, T4, T17, U4, U5, U9, U10, U11, U12, U16, U17, V3, V18 N/A N/A N/A N/A A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1, AF2, AF5, AF8, AF13, AF19, AF22, AF25, AF26 ... + R31 ... + J28 ... + M28 N/A A2, A3, A7, A9, A14, A18, A23, A25, A29, A30, B1, B2, B30, B31, C1, C31, D16, G1, G31, J1, J31, P1, P31, T4, T28, V1, V31, AC1, AC31, AE1, AE31, AH16, AJ1, AJ31, AK1, AK2, AK30, AK31, AL2, AL3, AL7, AL9 AL14, AL18 AL23, AL25, AL29, AL30 E31, G31, K31, P31, T31 ... + H32 ... + L33 ... + D31 A1, A7, A12, A14, A18, A20, A24, A29, A32, A33, B1, B6, B9, B15, B23, B27, B31, C2, E1, F32, G2, G33, J32, K1, L2, M33, P1, P33, R32, T1, V33, W2, Y1, Y33, AB1, AC32, AD33, AE2, AG1, AG32, AH2, AJ33, AL32, AM3, AM7, AM11, AM19, AM25, AM28, AM33, AN1, AN2, AN5, AN10, AN14, AN16, AN20, AN22, AN27, AN33 N/A N/A BG432 N/A N/A BG560 N/A N/A
R
GND (1)
All
J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12 N/A
N/A
N/A
No Connect
All
N/A
N/A
C31, AC2, AK4, AL3
Notes: 1. 16 extra balls (grounded) at package center.
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VirtexTM 2.5 V Field Programmable Gate Arrays
Table 4: Virtex Pinout Tables (Fine-Pitch BGA) Pin Name GCK0 GCK1 GCK2 GCK3 M0 M1 M2 CCLK PROGRAM DONE INIT BUSY/DOUT D0/DIN D1 D2 D3 D4 D5 D6 D7 WRITE CS TDI TDO TMS TCK DXN DXP Device All All All All All All All All All All All All All All All All All All All All All All All All All All All All FG256 N8 R8 C9 B8 N3 P2 R3 D15 P15 R14 N15 C15 D14 E16 F15 G16 J16 M16 N16 N14 C13 B13 A15 B14 D3 C4 R4 P4 FG456 W12 Y11 A11 C11 AB2 U5 Y4 B22 W20 Y19 V19 C21 D20 H22 H20 K20 N22 R21 T22 Y21 A20 C19 B20 A21 D3 C4 Y5 V6 FG676 AA14 AB13 C13 E13 AD4 W7 AB6 D24 AA22 AB21 Y21 E23 F22 K24 K22 M22 R24 U23 V24 AB23 C22 E21 D22 C23 F5 E6 AB7 Y8 FG680 AW19 AU22 D21 A20 AT37 AU38 AT35 E4 AT5 AU5 AU2 E3 C2 P4 P3 R1 AD3 AG2 AH1 AR4 B4 D5 B3 C4 E36 C36 AV37 AU35
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Module 4 of 4 11
VirtexTM 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name VCCINT Device All FG256 C3, C14, D4, D13, E5, E12, M5, M12, N4, N13, P3, P14 FG456 E5, E18, F6, F17, G7, G8, G9, G14, G15, G16, H7, H16, J7, J16, P7, P16, R7, R16, T7, T8, T9, T14, T15, T16, U6, U17, V5, V18 FG676 G7, G20, H8, H19, J9, J10, J11, J16, J17, J18, K9, K18, L9, L18, T9, T18, U9, U18, V9, V10, V11, V16, V17, V18, W8, W19, Y7, Y20 FG680 AD5, AD35, AE5, AE35, AL5, AL35, AM5, AM35, AR8, AR9, AR15, AR16, AR24, AR25, AR31, AR32, E8, E9, E15, E16, E24, E25, E31, E32, H5, H35, J5, J35, R5, R35, T5, T35 E26, E27, E29, E30, E33, E34 E6, E7, E10, E11, E13, E14 F5, G5, K5, L5, N5, P5 AF5, AG5, AN5, AK5, AJ5, AP5 AR6, AR7, AR10, AR11, AR13, AR14 AR26, AR27, AR29, AR30, AR33, AR34 AF35, AG35, AJ35, AK35, AN35, AP35 F35, G35, K35, L35, N35, P35 N/A N/A N/A
R
VCCO, Bank 0 VCCO, Bank 1 VCCO, Bank 2 VCCO, Bank 3 VCCO, Bank 4
All All All All All
E8, F8 E9, F9 H11, H12 J11, J12 L9. M9
F7, F8, F9, F10 G10, G11 F13, F14, F15, F16, G12, G13 G17, H17, J17, K16, K17, L16 M16, N16, N17, P17, R17, T17 T12, T13, U13, U14, U15, U16, T10, T11, U7, U8, U9, U10 M7, N6, N7, P6, R6, T6 G6, H6, J6, K6, K7, L7 N/A A9, C6, E8 ... + B4 N/A N/A N/A N/A
H9, H10, H11, H12, J12, J13 H15, H16, H17, H18, J14, J15 J19, K19, L19, M18, M19, N18 P18, R18, R19, T19, U19, V19 V14, V15, W15, W16, W17, W18 V12, V13, W9,W10, W11, W12 P9, R8, R9, T8, U8, V8 J8, K8, L8, M8, M9, N9 N/A N/A N/A A12, C11, D6, E8, G10 ... + B7 ... + B10 N/A
VCCO, Bank 5
All
L8, M8
VCCO, Bank 6
All
J5, J6
VCCO, Bank 7 VREF, Bank 0 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O.
All XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 XCV1000
H5, H6 B4, B7 ... + C6 ... + A3 N/A N/A N/A N/A
A33, B28, B30, C23, C24, D33 ... + A26 ... + D34
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VirtexTM 2.5 V Field Programmable Gate Arrays
Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name VREF, Bank 1 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 2 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 3 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Device XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 XCV1000 XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 XCV1000 XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 XCV1000 FG256 B9, C11 ... + E11 ... + A14 N/A N/A N/A N/A F13, H13 ... + F14 ... + E13 N/A N/A N/A N/A K16, L14 ... + L13 ... + M13 N/A N/A N/A N/A FG456 N/A A18, B13, E14 ... + A19 N/A N/A N/A N/A N/A F21, H18, K21 ... + D22 N/A N/A N/A N/A N/A N21, R19, U21 ... + U20 N/A N/A N/A N/A FG676 N/A N/A N/A A14, C20, C21, D15, G16 ... + B19 ... + A17 N/A N/A N/A N/A F24, H23, K20, M23, M26 ... + G26 ... + K25 N/A N/A N/A N/A R23, R25, U21, W22, W23 ... + W26 ... + U25 N/A FG680 N/A N/A N/A N/A B6, B8, B18, D11, D13, D17 ... + B14 ... + B5 N/A N/A N/A N/A G1, H4, J1, L2, V5, W3 ... + N1 ... + D2 N/A N/A N/A N/A AC1, AJ2, AK3, AL4, AR1, Y1 ... + AF3 ... + AP4
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Module 4 of 4 13
VirtexTM 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name VREF, Bank 4 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Device XCV50 XCV100/150 XCV200/300 XCV400 FG256 P9, T12 ... + T11 ... + R13 N/A FG456 N/A AA13, AB16, AB19 ... + AB20 N/A FG676 N/A N/A N/A AC15, AD18, AD21, AD22, AF15 ... + AF20 FG680 N/A N/A N/A N/A
R
XCV600
N/A
N/A
AT19, AU7, AU17, AV8, AV10, AW11 ... + AV14 ... + AU6 N/A N/A N/A N/A AT27, AU29, AU31, AV35, AW21, AW23 ... + AT25 ... + AV36 N/A N/A N/A N/A AB35, AD37, AH39, AK39, AM39, AN36 ... + AE39 ... + AT39
XCV800 XCV1000 VREF, Bank 5 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 6 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. XCV50 XCV100/150 XCV200/300 XCV400 XCV600
N/A N/A T4, P8 ... + R5 ... + T2 N/A N/A
N/A N/A N/A W8, Y10, AA5 ... + Y6 N/A N/A
... + AF17 N/A N/A N/A N/A AA10, AB8, AB12, AC7, AF12 ... + AF8
XCV800 XCV1000 XCV50 XCV100/150 XCV200/300 XCV400 XCV600
N/A N/A J3, N1 ... + M1 ... + N2 N/A N/A
N/A N/A N/A N2, R4, T3 ... + Y1 N/A N/A
... + AE10 N/A N/A N/A N/A AB3, R1, R4, U6, V5 ... + Y1
XCV800 XCV1000
N/A N/A
N/A N/A
... + U2 N/A
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VirtexTM 2.5 V Field Programmable Gate Arrays
Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name VREF, Bank 7 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. GND Device XCV50 XCV100/150 XCV200/300 XCV400 XCV600 XCV800 XCV1000 All FG256 C1, H3 ... + D1 ... + B1 N/A N/A N/A N/A A1, A16, B2, B15, F6, F7, F10, F11, G6, G7, G8, G9, G10, G11, H7, H8, H9, H10, J7, J8, J9, J10, K6, K7, K8, K9, K10, K11, L6, L7, L10, L11, R2, R15, T1, T16 FG456 N/A E2, H4, K3 ... + D2 N/A N/A N/A N/A A1, A22, B2, B21, C3, C20, J9, J10, J11, J12, J13, J14, K9, K10, K11, K12, K13, K14, L9, L10, L11, L12, L13, L14, M9, M10, M11, M12, M13, M14, N9, N10, N11, N12, N13, N14, P9, P10, P11, P12, P13, P14, Y3, Y20, AA2, AA21, AB1, AB22 FG676 N/A N/A N/A F4, G4, K6, M2, M5 ... + H1 ... + K1 N/A A1, A26, B2, B9, B14, B18, B25, C3, C24, D4, D23, E5, E22, J2, J25, K10, K11, K12, K13, K14, K15, K16, K17, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, M17, N2, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, P25, R10, R11, R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16, U17, V2, V25, AB5, AB22, AC4, AC23, AD3, AD24, AE2, AE9, AE13, AE18, AE25, AF1, AF26 FG680 N/A N/A N/A N/A E38, G38, L36, N36, U36, U38 ... + N38 ... + F36 A1, A2, A3, A37, A38, A39, AA5, AA35, AH4, AH5, AH35, AH36, AR5, AR12, AR19, AR20, AR21, AR28, AR35, AT4, AT12, AT20, AT28, AT36, AU1, AU3, AU20, AU37, AU39, AV1, AV2, AV38, AV39, AW1, AW2, AW3, AW37, AW38, AW39, B1, B2, B38, B39, C1, C3, C20, C37, C39, D4, D12, D20, D28, D36, E5, E12, E19, E20, E21, E28, E35, M4, M5, M35, M36, W5, W35, Y3, Y4, Y5, Y35, Y36, Y37
DS003-4 (v2.8) July 19, 2002 Production Product Specification
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Module 4 of 4 15
VirtexTM 2.5 V Field Programmable Gate Arrays Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued) Pin Name No Connect (No-connect pins are listed incrementally. All pins listed for both the required device and all larger devices listed in the same package are no connects.) Device XCV800 FG256 N/A FG456 N/A FG676 A2, A3, A15, A25, B1, B6, B11, B16, B21, B24, B26, C1, C2, C25, C26, F2, F6, F21, F25, L2, L25, N25, P2, T2, T25, AA2, AA6, AA21, AA25, AD1, AD2, AD25, AE1, AE3, AE6, AE11, AE14, AE16, AE21, AE24, AE26, AF2, AF24, AF25 same as above ... + A9, A10, A13, A16, A24, AC1, AC25, AE12, AE15, AF3, AF10, AF11, AF13, AF14, AF16, AF18, AF23, B4, B12, B13, B15, B17, D1, D25, H26, J1, K26, L1, M1, M25, N1, N26, P1, P26, R2, R26, T1, T26, U26, V1 N/A N/A FG680 N/A
R
XCV600 XCV400
N/A N/A
N/A N/A
N/A N/A
XCV300 XCV200
N/A N/A
D4, D19, W4, W19 ... + A2, A6, A12, B11, B16, C2, D1, D18, E17, E19, G2, G22, L2, L19, M2, M21, R3, R20, U3, U18, Y22, AA1, AA3, AA11, AA16, AB7, AB12, AB21, ... + A13, A14, C8, C9, E13, F11, H21, J1, J4, K2, K18, K19, M17, N1, P1, P5, P22, R22, W13, W15, AA9, AA10, AB8, AB14
N/A N/A
XCV150
N/A
N/A
N/A
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VirtexTM 2.5 V Field Programmable Gate Arrays
Pinout Diagrams
The following diagrams, CS144 Pin Function Diagram, page 17 through FG680 Pin Function Diagram, page 27, illustrate the locations of special-purpose pins on Virtex FPGAs. Table 5 lists the symbols used in these diagrams. The diagrams also show I/O-bank boundaries. Table 5: Pinout Diagram Symbols Symbol V v O R r G O, 1, 2, 3 General I/O Device-dependent general I/O, n/c on smaller devices VCCINT Device-dependent VCCINT, n/c on smaller devices VCCO VREF Device-dependent VREF, remains I/O on smaller devices Ground Global Clocks Pin Function Table 5: Pinout Diagram Symbols (Continued) Symbol , , , , , , , , , B D P I K W S T + - n DOUT/BUSY DONE PROGRAM INIT CCLK WRITE CS Boundary-scan Test Access Port Temperature diode, anode Temperature diode, cathode No connect M0, M1, M2 D0/DIN, D1, D2, D3, D4, D5, D6, D7 Pin Function
CS144 Pin Function Diagram
Bank 0 A B C D E F G H J K L M N Bank 1
Bank 7
1 2 3 4 5 6 7 8 9 10 11 12 13
GO 3 2 V R T T O A T O r V RGGO K B T R V G W B C r RGRO r S R r D R G G E G CS144 R F O V (Top view) G O V G R H R G r r G J R O R K GRGRGR GR P I L O V 1 V DO M O r V O r GO N
Bank 2
Bank 6
Bank 3
Figure 1: CS144 Pin Function Diagram
DS003-4 (v2.8) July 19, 2002 Production Product Specification
1 2 3 4 5 6 7 8 9 10 11 12 13
Bank 5 Bank 4
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VirtexTM 2.5 V Field Programmable Gate Arrays
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TQ144 Pin Function Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
O T R r G V R V 3 O G 2 R V G r R W S T G T
G T R r GR GO V R G r R G O Bank 7 Bank 6
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
Bank 0 Bank 5
TQ144
(Top view)
Bank 1
Bank 4
Bank 2
Bank 3
O K B R r G R G O V R G r R I P
R r G V R V 1 O G O R V G r R G D O
108
107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
Module 4 of 4 18
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 2: TQ144 Pin Function Diagram
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VirtexTM 2.5 V Field Programmable Gate Arrays
PQ240/HQ240 Pin Function Diagram
239 237 235 233 231 229 227 225 223 221 219 217 215 213 211 209 207 205 203 201 199 197 195 193 191 189 187 185 183 181
TG r GVG r 3GRr O r Rr WTT Or R r Or RVO2 r GVG r GSG
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
T r G R r r G O V r G R r G O V r R G r V O G r r R G r G
G
Bank 0
Bank 1
O B G
K r R r
179 177 175 173 171 169 167 165 163 161 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121
Bank 7
Bank 2
PQ240/HQ240
(Top view) Pins are shown staggered for readability
Bank 6
Bank 3
Bank 5
Bank 4
r G O V r G R r G O V r R G r V O G r r R G r I P O
r R r Or RVOOr GVG r GD OG r GVG r 1GR r Or Rr G
DS003-4 (v2.8) July 19, 2002 Production Product Specification
61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119
Figure 3: PQ240/HQ240 Pin Function Diagram
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VirtexTM 2.5 V Field Programmable Gate Arrays
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BG256 Pin Function Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A B C D E F G H J K L M N P R T U V W Y T r R r r r R G T R V R r G - R r R G G V O O G G G G O O V G G + G V R OOG Bank 0 2 3 V G G R GOO Bank 1 r V G
BG256
Bank 7 G G G G Bank 6 G G G G G G G G G G G G Bank 3 Bank 2
(Top View)
G
V r
Bank 5 OOG r R
G V 1
G O
Bank 4 GOO Rr
V r
G
R r T G G V O O G G G G O O V G G
S G B r R V R r I G R
WT K R r r R D P
A B C D E F G H J K L M N P R T U V W Y
Module 4 of 4 20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
DS003_18_100300
Figure 4: BG256 Pin Function Diagram
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VirtexTM 2.5 V Field Programmable Gate Arrays
BG352 Pin Function Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF GG GO r GR GR O V G V V O GV G r I GO GG G T K S TW B O V R O R R RO P D rR G R r O G R O V R V O G 2 V 3 R V O G R O V R r G Bank 1 Bank 0 Bank 2 Bank 7
BG352
(Top View)
Bank 3
Bank 6
Bank 4 O R G V O V R O G O V 1 R
Bank 5 V O R V G O R G
T O O V O - r
T r V R V +
G O V V R O G
G G R G R G O R G O G R G r G G
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
DS003-4 (v2.8) July 19, 2002 Production Product Specification
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
DS003_19_100600
Figure 5: BG352 Pin Function Diagram
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BG432 Pin Function Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL O G G V G r G O R G V G O G G V G G O G G R R V r R V V I G G G T O B R V r r r r R P O G W T K O G O R R D R S R G R V G V R r O O r R G V r 2 G V 3 G r R V O r O R G V r R G V R Bank 1 Bank 0 Bank 2 Bank 7
BG432
(Top View)
Bank 3
Bank 6
Bank 4 R G V r R G V O O r V R G r G V 1 O r R G r V
Bank 5 O O V R G V r R G - R
T R r O r G r R O R r R
G O T V V V V O + G
G G V R R r V R G G
O G G R G G O G r G V O G G G G O
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DS003_21_100300
Figure 6: BG432 Pin Function Diagram
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VirtexTM 2.5 V Field Programmable Gate Arrays
BG560 Pin Function Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN G G O G O V G O V G R G O G G O r G O P G S O G V G G O G V O V n V G G R O O G RGO r GG OK BTWR r R OT r V Bank 1 R R r Bank 2 R V r R V R R r Bank 3 R R V Bank 4 r I D n V V n R r R GRGG r OGOG G V V O r G V G R O R 3 2 G V R O G R V r O V G G V Rr Bank 0 O R G R V Bank 7
BG560
(Top View)
Bank 6
Bank 5 O V r V R G O R G 1 V O R O G V R G O V G r R O R G V r V G + r G
G r T V R R - R
O V V r r O
G n r R R R R R V R r V O
G O O G r G V O G O R V G V G R G O
G T O G O r G V G O G G O G O G O G G
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN
DS003-4 (v2.8) July 19, 2002 Production Product Specification
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
DS003_22_100300
Figure 7: BG560 Pin Function Diagram
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Module 4 of 4 23
VirtexTM 2.5 V Field Programmable Gate Arrays
R
FG256 Pin Function Diagram
Bank 0
Bank 1
A B C Bank 7 D E F G H J K L M Bank 6 N P R T
G r r T G A r GRR 3 RS T G B R V T r 2 R W V B C r T V V K D V OO r V r E GGOOGGR r F GGGGGG G R OOGGGGOOR H R O O G G G G O O J GGGGGGR K GGOOGG r R L r V OO V r M R r V O V I N V + RRV P P G - r 1 r DG R G r R r R G T
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Bank 2
Bank 3
Bank 5
Bank 4
FG256
(Top view)
Figure 8: FG256 Pin Function Diagram
Module 4 of 4 24
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R
VirtexTM 2.5 V Field Programmable Gate Arrays
FG456 Pin Function Diagram
Bank 0
Bank 1
Bank 7
Bank 6
A B C D E F G H J K L M N P R T U V W Y AA AB
G R 2 R r WT G A G r R T G K B G T R 3 SGB C r T n n r D RV R R V E V OOOO OOOO V R F O V V V OOOO V V V O G VOR H R O V O V GGGGGG V O J R OO GGGGGG OO R K O GGGGGG O L O GGGGGG O M R OO GGGGGG OO R N O V GGGGGG V O P VOR R R O V R O V V V OOOO V V V O T V OOOOOOOO V r R U V + V I V n R O n P W r G - r R 1 DG Y G R R G AA G R R r G AB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Bank 2
Bank 3
Notes: Packages FG456 and FG676 are layout compatible.
DS003-4 (v2.8) July 19, 2002 Production Product Specification
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Bank 5 Bank 4
FG456
(Top view)
Figure 9: FG456 Pin Function Diagram
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Module 4 of 4 25
VirtexTM 2.5 V Field Programmable Gate Arrays
R
FG676 Pin Function Diagram
Bank 0
Bank 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16
17 18
19 20 21
22 23 24
W T G T G B R R R n G K R
Bank 7
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
G n n r r R r
n G n n G n R G n n r G
n G
G R R R
G T R
n R T n R R R
r V
R V O O O O O O O O
G O V V V O O O O V V V
r R O V G G G G G G G G V
n R O V G G G G G G G G V
R O O G G G G G G G G O
2 3 O G G G G G G G G O
R G O G G G G G G G G O
n R O O G G G G G G G G O
n R O V G G G G G G G G V
r O V G G G G G G G G V
G O V V V O O O O V V V
r V O O O O O O O O
R V R
n R S n R
25 26
G n n n r G r n R n G R n r G n G n A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

Bank 2

Bank 6
n G G n nG nGnn Gn n R
VOOOOOOOOVRR r V+V I
-R R G r R 0 R1 r nGn R R n Rr n D RR Gn r Pn G G RGn nG nn n G

Bank 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16
17 18
19 20 21
22 23 24
Bank 5
Bank 4
FG676
(Top view)
fg676a
Figure 10: FG676 Pin Function Diagram
Notes: Packages FG456 and FG676 are layout compatible.
Module 4 of 4 26
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DS003-4 (v2.8) July 19, 2002 Production Product Specification
25 26
R
VirtexTM 2.5 V Field Programmable Gate Arrays
FG680 Pin Function Diagram
Bank 1
Bank 0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
G G
38
G G R R
Bank 2
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG
G G G R R
GG GTW GT rG BK R R
r S G O O V V O O
R O
O
R V
V
O
R O
G G
R O
r O
V
V
R
R
G
3 G G G
2 G

R
R V
V
r O
O
R G G
O
R O
V
V
R R O
r O
G O O V V O O
T G T r R
39
G G G A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP Bank 6 AR AT AU AV AW
1
2
3
4
5
6
7
8
9
Bank 7
V
GG rO O
GG ORr O V V RR G GGG G
V
R RG RGGG G R V V rO O R R r
FG680
(Top Bank 2
View)
Bank 7
AH AJ AK AL AM AN Bank 3 AP AR AT AU AV AW
GG
R R I
R V V O O G O O V V O O G
G R
R

r R R R
O O V V O O GOOVVOOGOOVVGGGVVOOGOOVVOO rRRG1RR
GPGRGrRG G GD
G r +GG
GGRRrR r GG GGGR0RRGGG
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Bank 4
Bank 5
Note: AA3, AA4, and AB2 are in Bank 2
Note: AA37 is in Bank 7
Figure 11: FG680 Pin Function Diagram
DS003-4 (v2.8) July 19, 2002 Production Product Specification
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39
fg680_12a
1
2
3
4
5
6
7
8
9
Module 4 of 4 27
VirtexTM 2.5 V Field Programmable Gate Arrays
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Revision History
Date 11/98 01/99 02/99 05/99 05/99 07/99 Version 1.0 1.2 1.3 1.4 1.5 1.6 Initial Xilinx release. Updated package drawings and specs. Update of package drawings, updated specifications. Addition of package drawings and specifications. Replaced FG 676 & FG680 package drawings. Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19. Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate. Added IOB Input Switching Characteristics Standard Adjustments. Speed grade update to preliminary status, Power-on specification and Clock-to-Out Minimums additions, "0" hold time listing explanation, quiescent current listing update, and Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE. Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479, 117153, 117154, and 117612. Modified notes for Recommended Operating Conditions (voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43. Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. New TBCKO values; corrected FG680 package connection drawing; new note about status of CCLK pin after configuration. Modified "Pins not listed ..." statement. Speed grade update to Final status. Modified Table 18. * * * * * * * * * * * Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices. Corrected Units column in table under IOB Input Switching Characteristics. Added values to table under CLB SelectRAM Switching Characteristics. Corrected pinout info for devices in the BG256, BG432, and BG560 pkgs in Table 18. Corrected BG256 Pin Function Diagram. Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL. Converted file to modularized format. See section Virtex Data Sheet, below. Corrected pinout information for FG676 device in Table 4. (Added AB22 pin.) Clarified VCCINT pinout information and added AE19 pin for BG352 devices in Table 3. Changed pinouts listed for BG352 XCV400 devices in banks 0 thru 7. Changed pinouts listed for GND in TQ144 devices (see Table 2). Revision
09/99
1.7
01/00
1.8
01/00
1.9
03/00 05/00 05/00 09/00
2.0 2.1 2.2 2.3
10/00 04/02/01 04/19/01 07/19/01 07/19/02
2.4 2.5 2.6 2.7 2.8
Virtex Data Sheet
The Virtex Data Sheet contains the following modules: * * DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
* *
DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
Module 4 of 4 28
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DS003-4 (v2.8) July 19, 2002 Production Product Specification

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