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| SD1731 (TH562) RF POWER BIPOLAR TRANSISTORS HF SSB APPLICATIONS FEATURES SUMMARY OPTIMIZED FOR SSB Figure 1. Package 30 MHz 50 VOLTS EFFICIENCY 40% COMMON EMITTER GOLD METALLIZATION POUT = 220 W PEP WITH 13 dB GAIN DESCRIPTION The SD1731 is a 50 V epitaxial silicon NPN planar transistor designed primarily for SSB communications. This device utilizes emitter ballasting for improved ruggedness and reliability. .500 4L FL (M174) epoxy sealed Figure 2. Pin Connection bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 1. Collector 2. Emitter 3. Base 4. Emitter Table 1. Order Codes Order Codes Marking SD1731 Package M174 Packaging PLASTIC TRAYS SD1731 (TH562) REV. 2 June 2004 1/9 SD1731 (TH562) Table 2. Absolute Maximum Ratings (Tcase = 25C) Symbol VCBO VCEO VEBO IC PDISS TJ TSTG Parameter Collector-Base Voltage Collector-Emitter Voltage Emitter-Base Voltage Device Current Power Dissipation (Theatsink 25C) Junction Temperature Storage Temperature Value 110 55 4.0 20 233 +200 - 65 to +150 Unit V V V A W C C Table 3. Thermal Data Symbol RTH(j-c) RTH(c-s) Parameter Junction-Case Thermal Resistance Case-Heatsink Thermal Resistance Value 0.55 0.2 Unit ELECTRICAL SPECIFICATIONS Table 4. Static (Tcase = 25C) Symbol BVCBO BVCEO BVEBO ICEO ICES hFE Test Conditions IC = 200 mA; IE = 0 mA IC = 200 mA; IB = 0 mA IE = 20 mA; IC = 0 mA VCE = 30 V; IE = 0 mA VCE = 55 V; IE = 0 mA VCE = 6 V; IC = 10 A Table 5. Dynamic (Theatsink = 25C) Symbol bs O POUT GP(1) let o ro P e du ct (s) so Ob - te le Min. 110 55 4.0 -- -- 15 ro P Value Typ. -- -- -- -- -- -- uc d Max. -- -- -- 5 10 80 s) t( C/W C/W Unit V V V mA mA -- Value Test Conditions Min. 220 13 -- 40 -- Typ. -- -- -- -- 330 Max. -- -- -30 -- -- W dB dBc % pF Unit f = 30 MHz; VCE = 50 V; ICQ = 150 mA POUT = 220 W PEP; VCE = 50 V; ICQ = 150 mA POUT = 220 W PEP; VCE = 50 V; ICQ = 150 mA POUT = 220 W PEP; VCE = 50 V; ICQ = 150 mA f = 1 MHz; VCB = 50 V IMD(1) c(1) COB Note: 1. f1 = 30.00 MHz, f2 = 30.001 MHz 2/9 SD1731 (TH562) TYPICAL PERFORMANCE Figure 3. Power Output PEP vs Power Input Figure 4. Collector Efficiency vs Power Output PEP Figure 5. Intermodulation Distortion vs Power Output PEP bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 3/9 SD1731 (TH562) Figure 6. Power Gain vs Power Output PEP Figure 7. Collector Base Capacitance vs Collector Emitter Voltage bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 4/9 SD1731 (TH562) TEST CIRCUIT Figure 8. Test Circuit Table 6. Test Circuit C1 C2 C3 C4 C5 C6 2 x 10nF Chips Arco 426 + 220pF + 330pF Chips Arco 4615 + 2.2nF + 2 x 1nF LCC + 4.7nF + 560pf Chps C7, C8, C9, C10, C11 L1 L2, L3 L4 O L5 bs let o Pr e du o Arco 4213 + 330pF Chip 10nF Chip (s) ct so Ob - te le ro P uc d s) t( 3 x 10nF Chips 1nF + 10nF + 100nF + 4.7F, 63V + 100F, 63V 3 Turns of 1.2mm Unenameled Wire Diameter, 7.1mm, Length 13mm 8 Turns of 0.55mm Enameled Wire on Ferrite Core Phillips 4C6 97170 (9 x 6 x 3) 10 Turns of 1.2mm Enameled Wire, Diameter 8.1mm, Length 20mm 7 Turns of 1.2mm Enameled Wire on Ferrite Core Phillips 4C6 97180 6:3.5 Impedance Transformer on toriod Phillips 4C6 97180 Twisted Pair 4:1 Transformer, 4 Turns Made with 1.0mm Enameled on toriod Phillips 4C6 97180 Feedback Transformer Primary: 2 Turns of 1mm Enameled Wire Secondary: 8 Turns of 1mm Enameled Wire Twisted Pair 4:1 Transformer, 4 Turns of bifilar Twisted 1.2mm Wires on Ferrite Core Phillips 4C6 97200 T1 T2 T3 T4 5/9 SD1731 (TH562) Figure 9. Mounting Circuit BIAS CIRCUIT Figure 10. Bias Circuit bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 6/9 SD1731 (TH562) PACKAGE MECHANICAL Table 7. M174 Mechanical Data Symbol A B C D E F G H I J K L 24.64 12.57 0.08 2.29 4.06 6.22 18.28 3.18 24.89 12.83 0.18 2.79 4.45 7.11 26.67 0.970 0.495 0.003 0.090 0.160 millimeters Min 5.59 3.18 6.48 18.54 0.245 0.720 0.125 0.980 0.505 0.007 Typ Max 5.84 Min 0.220 0.125 0.255 0.730 inches Typ Max 0.230 Figure 11. M174 Package Dimensions bs O let o Pr e du o (s) ct so Ob - eP let od r uc s) t( 0.175 0.280 1.050 0.110 Note: Drawing is not to scale. 7/9 SD1731 (TH562) REVISION HISTORY Table 8. Revision History Date July-1995 8-June-2004 Revision 1 2 First Issue Stylesheet update. No content change. Description of Changes bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 8/9 SD1731 (TH562) bs O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 9/9 |
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