Part Number Hot Search : 
78005 310ALTM1 FQA7N80C OP113 FQA7N80C 5400J 21A090I A2016
Product Description
Full Text Search
 

To Download PJDLLLC05 Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 PJDLLLC05
Low Capacitance TVS Diode Array
This diode array is configured to protect up to two high speed data transmission lines, used in Low Voltage Differential Signal (LVDS) ports. Acting as a line terminator, minimizes overshoot and undershoot conditions due to bus impedance, as well as protect against over-voltage events as electrostatic discharges. The line-line concept minimizes the problems to customers to re-route PCB lines, simplifying the design.
SOT563 Package
6 5
4
1
2
SPECIFICATION FEATURES
Maximum Capacitance of 1.2pF at 0Vdc 1MHz Line-to-Ground Maximum Leakage Current of 1.0A @ VRWM Industry Standard SMT Package SOT563 IEC61000-4-2 Full Compliance; 15kV Air, 8kV Contact* 100% Tin Matte finish (LEAD-FREE PRODUCT)
6
3
Line1
Gnd
5
Line2
4
APPLICATIONS
USB 2.0 and Firewire Port Protection HDMI Version 1.3 DVI
1
2
3
Line1 Gnd Line2
Note: pins 1and 6 (Line1), pins 3 and 4 ( Line2) and pins 2 and 5 (Gnd) must be connected externally, as the drawing attached below.
MARKING : 05
I/O Data line + Ground I/O Data line -
1
6
2
5
3
4
Line-line concept ease the PCB design, directly placing the device over the data lines, opening only the contact points. VREF is fixed by the operating voltage, referenced to the ground.
MAXIMUM RATINGS Tj = 25C Unless otherwise noted
Rating Peak Pulse Power (8/20s Waveform) Peak Pulse Current (8/20s Waveform) Operating Junction Temperature Range Storage Temperature Range Soldering Temperature, t max = 10s Symbol P PPM I PP TJ Tstg TL Value 50 6 -55 to +125 -55 to +150 260 Units W A C C C
7/23/2009
Page 1
www.panjit.com
PJDLLLC05
ELECTRICAL CHARACTERISTICS
Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20s) Clamping Voltage (8/20s) Clamping Voltage (8/20s) Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Vc Cj I BR = 1mA VR = 5V I pp = 1 A I pp = 2 A I pp = 5 A
0 Vdc Bias f = 1MHz Between I/O pins and GND 0 Vdc Bias f = 1MHz Between I/O pins
Tj = 25C unless otherwise noted
Conditions Min Typical Max 5 6.2 1.0 10 12 15 1.0 1.0 Units V V A V V V pF pF
7/23/2009
Page.2
www.panjit.com
PJDLLLC05
PACKAGE DIMENSIONS - SOT563
APPLICATION EXAMPLE (USB2.0 port)
4 and 3 pins connected together through the same Data line
D+
D+
2 and 5 pins connected together To Ground
D6 and 1 pins connected together through the same Data line
D-
7/23/2009
Page.3
www.panjit.com


▲Up To Search▲   

 
Price & Availability of PJDLLLC05

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X