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| R 8 8 Platform Flash XL High-Density Configuration and Storage Device Product Specification DS617 (v3.0.1) January 07, 2010 Features * * * * * * * * * * * In-System Programmable Flash Memory Optimized for Virtex(R)-5 or Virtex-6 FPGA Configuration High-Performance FPGA Bitstream Transfer up to 800 Mb/s (50 MHz x 16-bits), Ideal for PCI Express(R) Endpoint Applications MultiBoot Bitstream, Design Revision Storage FPGA Configuration Synchronization (READY_WAIT) Handshake Signal ISE(R) Software Support for In-System Programming via Xilinx(R) JTAG Cables Standard NOR-Flash Interface for Access to Code or Data Storage Operation over Full Industrial Temperature Range (-40C to +85C) Common Flash Interface (CFI) Low-Power Advanced CMOS NOR-Flash Process Endurance of 10,000 Program/Erase Cycles Per Block Power Supplies * Memory Organization 128-Mb Main Array Capacity 16-bit Data Bus Multiple 8-Mb Bank Architecture for Dual Erase/Program and Read Operation 127 Regular 1-Mb Main Blocks 4 Small 256-Kb Parameter Blocks Power-On in Synchronous Burst Read Mode Asynchronous Random Access Mode Accelerated Asynchronous Page Read Mode Default Block Protection at Power-Up Hardware Write Protection (when VPP = VSS) Unique Device Number (64-bits) One-Time-Programmable (OTP) Registers * Synchronous/Asynchronous Read Modes * Protection * Security Industry-Standard Core Power Supply Voltage (VDD) = 1.8V 3.3V or 2.5V I/O (VDDQ) Power Supply Voltage * Small-Footprint (10 mm x 13 mm) FT64 Packaging Description A reliable compact high-performance configuration bitstream storage and delivery solution is essential for the high-density FPGAs. Platform Flash XL is the industry's highest performing configuration and storage device and is specially optimized for high-performance FPGA configuration. Platform Flash XL integrates 128 Mb of in-system programmable flash storage and performance features for configuration within a small-footprint FT64 package (Figure 5). Power-on burst read mode and dedicated I/O power supply enable Platform Flash XL to mate seamlessly with the native SelectMAP configuration interface. A wide, 16-bit data bus delivers the FPGA configuration bitstream at speeds up to 800 Mb/s without wait states. See UG438, Platform Flash XL Configuration and Storage Device User Guide, for system-level usage and performance considerations. Platform Flash XL is supported for use with Virtex-5 or Virtex-6 FPGAs only. Use with older Virtex families, Spartan(R) families, or AES encrypted bitstreams is not supported. Platform Flash XL is a non-volatile flash storage solution, optimized for FPGA configuration. The device provides a READY_WAIT signal that synchronizes the start of the FPGA configuration process, improving both system reliability and simplifying board design. Platform Flash XL can download an XC5VLX330 bitstream (79,704,832 bits) in less than 100 ms, making the configuration performance of Platform Flash XL ideal for PCI Express endpoints and other high-performance applications. Platform Flash XL is a single-chip configuration solution with additional system-level capabilities. A standard NOR flash interface (Figure 2) and support for common flash interface (CFI) queries provide industry-standard access to the device memory space. The Platform Flash XL's 128 Mb capacity can typically hold one or more FPGA bitstreams. Any memory space not used for bitstream storage can be used to hold general purpose data or embedded processor code. (c) 2007-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 1 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 1 Platform Flash XL READY_WAIT Clock up to 50 MHz(1) FPGA Design (.bit) File Wide (16-bit) Datapath Up to 800 Mb/s SelectMAP (x16) Port Configuration Synchronization Handshake FPGA DS617_01_102709 Notes: 1. System considerations can lower the configuration clock frequency below the maximum clock frequency for the device. To determine the maximum configuration clock frequency, check the minimum clock period (TKHKH) for the chosen I/O voltage range (VDDQ), the clock Highto-output valid time (TKHQV), and the FPGA SelectMAP setup time. Figure 1: Platform Flash XL Delivers Reliable, High-Performance FPGA Configuration Platform Flash XL support is integrated with the Xilinx design and debug tool suite.The iMPACT application, included with the ISE software, supports indirect, in-system programming of Platform Flash XL via the IEEE Standard 1149.1 (JTAG) port on the FPGA for prototype programming (Figure 3). X-Ref Target - Figure 2 Platform Flash XL Code User Data Design (.bit) File, Rev. 1 Design (.bit) File, Rev. 0 Control Address FPGA User Design Data/Commands DS617_02_081209 Figure 2: Standard NOR Flash Interface for User Access to Memory X-Ref Target - Figure 3 Single Cable Connector for Direct FPGA Configuration/Debug and Indirect Platform Flash XL Programming IEEE 1149.1 (JTAG) Port Xilinx JTAG Cable Connector FPGA For Programming Platform Flash XL Platform Flash XL Standard NOR Flash Interface FPGA Design (.bit) File Control Address Data/Commands BPI Flash Configuration Port Indirect, In-System Programming Engine For Programming Platform Flash XL DS617_03_081209 Figure 3: Indirect Programming Solution for Platform Flash XL DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 2 R Platform Flash XL High-Density Configuration and Storage Device Flash Memory Architecture Overview Platform Flash XL is a 128-Mb (8 Mb x 16) non-volatile flash memory. The device is in-system programmable with a 1.8V core (VDD) power supply. A separate I/O (VDDQ) power supply enables I/O operation at 3.3V or 2.5V. An optional 9V VPP power supply can accelerate factory programming. A common flash interface (CFI) provides access to device memory (Figure 3, page 3). Moreover, Platform Flash XL supports multiple read modes. A 23-bit address bus provides random read access to each 16-bit word. Four words occupy each page for accelerated page mode reads. The device powers-up in a synchronous burst read mode capable of sequential read rates up to 54 MHz. Platform Flash XL has a multiple-bank architecture. An array of 131 individually erasable blocks are divided into 16, 8-Mb banks. Fifteen main banks contain uniform blocks of 64 Kwords, and one parameter bank contains seven main blocks of 64 Kwords, plus four parameter blocks of 16 Kwords. Note: The device is electronically erasable at the block level and programmable on a word-by-word basis. be suspended to read data at any memory location except for the one being programmed, and then resumed. Program and erase commands are written to the command interface of the memory. An internal program/erase controller takes care of the timing necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the status register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array. At power-up, the device is configured for synchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 54 MHz. The synchronous burst read operation can be suspended and resumed. When the bus is inactive during asynchronous read operations, the device automatically switches to an automatic standby mode. In this condition the power consumption is reduced to the standby value, and the outputs are still driven. Platform Flash XL features an instant, individual blocklocking scheme, allowing any block to be locked or unlocked with no latency, and enabling instant code and data protection. All blocks have three levels of protection. Blocks can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase: when VPP = VPPLK all blocks are protected against program or erase. All blocks are locked at power-up. The device features a separate region of 17 programmable registers whose values can be protected against further programming changes. Sixteen of these registers are each 128-bits in size, with the 17th register subdivided into two 64bit registers. One of the 64-bit registers contains a factory preprogrammed, unique device number, permanently protected against modification. The second 64-bit register is user-programmable. All bits within these registers (except for the permanentlyprotected unique number register) are one-timeprogrammable (OTP) -- each bit can be programmed only once from a one-value to a zero-value. Two protection lock registers can be programmed to lock any of the 17 protectable registers against further changes. One protection lock register contains bits that determine the protection state of the two special 64-bit registers. The bit corresponding to the unique device number register is preprogrammed to ensure the unique device number register is permanently protected against modification. The second protection lock register contains OTP bits that correspond the protection state each of the remaining 16 registers. Platform Flash XL is available in a 10 x 13 mm, 1.0 mm-pitch FT64 package and supplied with all the bits erased (set to '1'). The multiple-bank architecture allows dual operations -- read operations can occur on one bank while a program or erase operation occurs in a different bank. However, only one bank at a time is allowed to be in program or erase mode. Burst reads are allowed to cross bank boundaries. Table 1 summarizes the bank architecture, and the memory map is shown in Figure 4, page 5. The parameter blocks are located at the top of the memory address space in Platform Flash XL. Table 1: Bank Architecture Number Parameter Bank Bank 1 Bank 2 Bank 3 Bank Size 8 Mbits 8 Mbits 8 Mbits 8 Mbits Parameter Blocks 4 blocks of 16 Kwords - - - Main Blocks 7 blocks of 64 Kwords 8 blocks of 64 Kwords 8 blocks of 64 Kwords 8 blocks of 64 Kwords Bank 14 Bank 15 Each block can be erased separately. Erase operations can be suspended in order to perform a program or read operation in any other block and then resumed. Program operations can DS617 (v3.0.1) January 07, 2010 Product Specification ... 8 Mbits 8 Mbits ... ... - - 8 blocks of 64 Kwords 8 blocks of 64 Kwords ... www.xilinx.com 3 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 4 Address 7FFFFFh 7FC000h 7F3FFFh 16 Kword 4 Parameter Blocks 16 Kword 64 Kword 7 Main Blocks 64 Kword 64 Kword 8 Main Blocks 64 Kword 64 Kword 8 Main Blocks 64 Kword 64 Kword 8 Main Blocks 64 Kword Parameter Bank 7F0000h 7EFFFFh 7E0000h 78FFFFh 780000h 77FFFFh 770000h Bank 1 70FFFFh 700000h 6FFFFFh 6F0000h Bank 2 68FFFFh 680000h 67FFFFh 670000h Bank 3 60FFFFh 600000h 07FFFFh 070000h 64 Kword 8 Main Blocks 64 Kword DS167_04_053008 Bank 15 00FFFFh 000000h Figure 4: Platform Flash XL Memory Map (Address Lines A22 - A0) DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 4 R Platform Flash XL High-Density Configuration and Storage Device Pinout and Signal Descriptions See Figure 5 and Table 2 for a logic diagram and brief overview of the signals connected to this device. Table 2: Signal Names Signal Name A22-A0 DQ15-DQ0 E G W RP WP K L READY_WAIT VDD VDDQ VPP VSS VSSQ NC Notes: 1. Typically, VPP is tied to the VDDQ supply on a board. See the VPP Program Supply Voltage section for alternate options. X-Ref Target - Figure 5 VDD VDDQ VPP Function Address Inputs Data Input/Outputs, Command Inputs Chip Enable Output Enable Write Enable Reset Write Protect Clock Latch Enable Ready/Wait Supply Voltage Supply Voltage for Input/Output Buffers Optional(1) Supply Voltage for Fast Program and Erase Ground Ground Input/output Supply Not Connected Internally Direction Inputs I/O Input Input Input Input Input Input Input I/O - - L K RP WP E G READY_WAIT A22-A0 W 23 16 DQ15-DQ0 Platform Flash XL - VSS VSSQ DS617_05_053008 - - - Figure 5: Logic Diagram Address Inputs (A22-A0) The Address inputs select the words in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. deselected, the outputs are high impedance, and the power consumption is reduced to the standby level. Output Enable (G) The Output Enable input controls data outputs during the Bus Read operation of the memory. Before the start of the first address latching sequence (FALS), the Output Enable input must be held Low before the clock starts toggling. Data Inputs/Outputs (DQ15-DQ0) The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. Write Enable (W) The Write Enable input controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable, whichever occurs first. Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VIL and Reset is at VIH, the device is in active mode. When Chip Enable is at VIH, the memory is DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 5 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 6 1 A B C D E F G H 2 3 4 5 6 7 8 A0 A5 A7 VPP A12 VDD A17 A21 A1 VSS A8 E A13 NC A18 READY_WAIT A2 A6 A9 A11 A14 NC A19 A20 A3 A4 A10 RP NC NC A15 A16 DQ8 DQ1 DQ9 DQ3 DQ4 NC DQ15 NC K DQ0 DQ10 DQ11 DQ12 NC NC G A22 WP DQ2 VDDQ DQ5 DQ6 DQ14 W L NC VDD VSSQ DQ13 VSS DQ7 NC DS617_10_110807 Notes: 1. See the FT64/FTG64 package specifications at http://www.xilinx.com/support/documentation/package_specifications.htm. Figure 6: FT64 Package Connections (Top View through Package) Write Protect (WP) Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled, and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled, and the Locked-Down blocks can be locked or unlocked. Reset (RP) The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance, and the current consumption is reduced to the Reset supply current IDD2. After Reset all blocks are in the Locked state, and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters the synchronous read mode and the FALS is executed. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 6 R Platform Flash XL High-Density Configuration and Storage Device the READY_WAIT signal to a valid input High). The device waits until the READY_WAIT input becomes a valid input High before permitting a synchronous read or accepting a command. Connecting the READY_WAIT to the FPGA INIT_B pin in a wired-and circuit creates a handshake coordinating the initiation of the device synchronous read with the start of the FPGA configuration sequence. When READY_WAIT is an input/open-drain ready signal, the system can drive READY_WAIT to VIL to reinitiate a synchronous read operation. A valid address must be provided to the device for a reinitiated synchronous read operation. Optionally, READY_WAIT can be configured as an output signaling a wait condition during a synchronous read operation. The wait condition indicates a clock cycle during which the output data is not valid. When configured as an output wait signal, READY_WAIT is high impedance when Chip Enable is at VIH or Output Enable is at VIH. Only when configured as a wait signal, READY_WAIT can be configured to be active during the wait cycle or one clock cycle in advance, and the READY_WAIT polarity can be configured. Latch Enable (L) Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and inhibited when Latch Enable is at VIH. The Latch Enable (L) signal must be held at VIH during the power-up phase, during the FALS restart phase and through the entire FALS. In asynchronous mode, the address is latched on L going High. or addresses are sent continuously if L is held Low. During Write operations, L can be tied Low (VIL) to allow the addresses to flow through. Table 3: Latch Enable Logic Levels in Synchronous and Asynchronous Modes Operation Bus Read Bus Write Address Latch Standby Reset FALS Power-up Notes: 1. See waveforms in the "DC and AC Parameters" section for details. Asynchronous X X or toggling Toggling X VIH VIH VIH Synchronous VIH X or toggling Toggling X VIH VIH VIH VDD Supply Voltage VDD provides the power supply to the internal core of the memory device and is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently of VDD. Clock (K) The Clock input synchronizes the memory to the FPGA during synchronous read operations. The address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous read and in write operations. VPP Program Supply Voltage VPP is either a control input or a power supply pin, selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ), VPP is seen as a control input. In this case a voltage lower than VPPLK gives absolute protection against program or erase, while VPP in the VPP1 range enables these functions. VPP is only sampled at the beginning of a program or erase -- a change in its value after the operation starts does not have any effect, and all program or erase operations continue. If VPP is in the range of VPPH, the signal acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed. Ready/Wait (READY_WAIT) Caution! The READY_WAIT requires an external pull-up resistor to VDDQ. The external pull-up resistor must be sufficiently strong to ensure a clean, Low-to-High transition within less than one microsecond (TRWRT) when the READY_WAIT pin is released to a high-impedance state. READY_WAIT can perform one of two functions. By default, READY_WAIT is an input/open-drain ready signal coordinating the initiation of the device's synchronous read operation with the start of an FPGA configuration sequence. Optionally, READY_WAIT can be dynamically configured as an output wait signal, indicating a wait condition during a synchronous read operation. Upon a power-on reset (POR) or RP-pin reset event, the device drives READY_WAIT to VIL until the device is ready to initiate a synchronous read or receive a command. When the device reaches an internal ready state from a reset condition, READY_WAIT is released to a high-impedance state (an external pull-up resistor to VDDQ is required to externally pull VSS Ground VSS Ground is the reference for the core supply and must be connected to the system ground. VSSQ Ground VSSQ Ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS. Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1 F ceramic capacitor close to the pin (highfrequency, inherently low-inductance capacitors should be placed DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 7 R Platform Flash XL High-Density Configuration and Storage Device as close as possible to the package). The PCB track widths should be sufficient to carry the required VPP program and erase currents. FPGA Configuration Overview Platform Flash XL enables the rich set of FPGA configuration features without additional glue logic. The device delivers the FPGA bitstream at power-on through a 16-bit data bus at data rates up to 800 Mb/s. The FPGA can also be configured from one of many design/revision bitstreams stored in the device. These revision bitstreams are accessed through the FPGA's MultiBoot addressing and fallback features available in specific system configurations with Platform Flash XL. For detailed descriptions of the FPGA configuration features and configuration procedure, refer to the respective FPGA configuration user guide. At a high level, the general procedure for FPGA configuration from Platform Flash XL is as follows: 1. A system event, such as power-up, initiates the FPGA configuration process. The FPGA drives its INIT_B pin Low while it clears its configuration memory. The Platform Flash XL drives its READY_WAIT pin Low during its reset period. 2. When ready, the FPGA and Platform Flash XL release their respective INIT_B and READY_WAIT pins. An external resistor pulls the connected INIT_B-READY_WAIT signal from Low to High, synchronizing the start of the FPGA configuration process. 3. At the start of the configuration process, the FPGA samples its mode pins to determine its configuration mode. For Master BPI-Up mode, the FPGA outputs an address to read from the flash. For Slave SelectMAP mode, onboard resistors set the initial flash read address. 4. The Platform Flash XL latches the initial address from the FPGA or from onboard resistor settings into its internal address counter and the Platform Flash XL outputs the first 16-bit word. 5. The bitstream is synchronously transferred from the Platform Flash XL to the FPGA. During each successive FPGA CCLK period, the Platform Flash XL increments its internal address counter and outputs the next 16-bit word of the bitstream for the FPGA to consume. 6. At the end of the configuration process, the FPGA starts operation of the loaded bitstream and either drives DONE High or releases DONE to High, indicating the completion of the configuration procedure. Platform Flash XL can configure the FPGA in Slave SelectMAP (x16) (recommended for maximum performance), Master SelectMAP (x16), or Master BPI-Up (x16) configuration mode. See Table 4 for a summary of attributes for different configuration modes and memories. Table 4: Overview of FPGA Configuration from Platform Flash XL and Standard BPI Flash Platform Flash XL High-Performance Configuration Mode FPGA Configuration Mode Guaranteed Bitstream Transfer Bandwidth at Best Clock Setting Virtex-5 FPGA Support Virtex-6 FPGA Support ISE Software Programming Support MultiBoot Capable Notes: 1. 2. 3. 4. The 800 Mb/s rate is achieved using a Virtex-5 FPGA with an external 50 MHz configuration clock source. Specific speed grades of the Virtex-6 FPGA or system-level considerations can limit the configuration performance to less than 800 Mb/s. Bandwidth is based on an example Virtex-5 FPGA considering FMCCKTOL and BitGen ConfigRate = 31 MHz (nominal frequency). Bandwidth is based on an example Virtex-5 FPGA considering FMCCKTOL and BitGen ConfigRate = 17 MHz (nominal frequency), bpi_page_size = 4, and bpi_1st_read_cycle = 4. First word access time = 110 ns; Page word access time = 25 ns. See XAPP973, Indirect Programming of BPI PROMs with Virtex-5 FPGAs. Standard BPI Flash Compatibility Mode Master BPI-Up mode (x16 data bus width) 248 Mb/s(2) Third-Party Standard BPI Flash (110-ns Access Time) Master BPI-Up mode (x16 data bus width) 78 Mb/s(3) Slave SelectMAP mode (x16 data bus width) 800 Mb/s(1) For limited setups(4) DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 8 R Platform Flash XL High-Density Configuration and Storage Device Configuration User Guide for details of the Slave SelectMAP mode. Note: The FPGA fallback feature is disabled in the Slave SelectMAP mode. Slave SelectMAP Configuration Mode Platform Flash XL achieves maximum configuration performance when the FPGA is in Slave SelectMAP configuration mode. In the Slave SelectMAP mode, a stable, external clock source can drive the synchronous bitstream transfer from the device to the FPGA up to the maximum burst read frequency (TCLK). See the SelectMAP Configuration Interface section in the respective FPGA See UG438, Platform Flash XL Configuration and Storage Device User Guide, for guidance and examples of FPGAs connected to a Platform Flash XL for Slave SelectMAP configuration mode. Alternate Configuration Modes Platform Flash XL is optimized for the Slave SelectMAP configuration mode. Alternatively, Platform Flash XL can configure an FPGA via the Master SelectMAP or Master BPI-Up mode--albeit with compromises in configuration speed. See the respective FPGA configuration user guide for details regarding the Master SelectMAP mode or Master BPI-Up mode. See UG438, Platform Flash XL Configuration and Storage Device User Guide, for additional information on using the Platform Flash XL with the FPGA in Master SelectMAP or Master BPI-Up mode. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 9 R Platform Flash XL High-Density Configuration and Storage Device Programming Overview Programming solutions satisfying the requirements for each product phase are available for Platform Flash XL. ISE software provides integrated programming support for the FPGA design engineer in the prototyping environment. Third-party programming support is also available for the demands of the manufacturing environments. connections. iMPACT supports reading and writing of only the main memory array. iMPACT does not support reading or writing of special data registers, for example, electronic signature codes, protection registers, or OTP registers. Production Programming Solutions For the requirements of manufacturing environments, multiple solutions exist for programming Platform Flash XL. Programming support is available for the common production programming platforms. Note: Check with the third-party vendor for the availability of Platform Flash XL programming support. iMPACT Programming Solution for Prototype FPGA Designs Xilinx ISE software has integral support for in-system programming enabling rapid develop-program-and-test cycles for prototype FPGA designs. The software can compile the FPGA design into a configuration bitstream and program the bitstream into a Platform Flash XL in-system via a Xilinx JTAG cable (Figure 7). The iMPACT software tool within the ISE software suite formats the FPGA user design bitstream into a flash memory image file and programs the device via a Xilinx JTAG cable connection to the JTAG port of the FPGA. For the programming process, the iMPACT software first downloads a pre-built bitstream containing an in-system programming engine into the FPGA. Then, the iMPACT software indirectly programs the FPGA user design bitstream into a Platform Flash XL via the downloaded in-system programming engine in the FPGA. Note: For iMPACT software indirect in-system programming support, a specific set of connections is required between the FPGA and Platform Flash XL. See UG438, Platform Flash XL Configuration and Storage Device User Guide, for recommended X-Ref Target - Figure 7 Device Programmers Device programmers can gang program a high volume of Platform Flash XL in an minimum of time. Third-party device programmer vendors, such as BPM Microsystems, support programming of Platform Flash XL. See http://www.xilinx.com/support/programr/dev_sup.htm for a sample list of third-party programmer vendors supporting Platform Flash XL. Device programmers require the array data in the form of a standard PROM formatted data file, such as MCS. The FPGA .bit file is not a valid data input format for thirdparty device programmers. See the Platform Flash XL Configuration and Storage Device User Guide for instructions on preparing a programming file. ISE Foundation Software Compile Design Board FPGA Platform Flash XL Control Design (.bit) File Xilinx JTAG Cable for programming prototype designs iMPACT Software Format File Program File IEEE 1149.1 (JTAG) Port Indirect, In-System, Programming Engine Address Data/Commands FPGA Design (.bit) File DS617_08_081309 Figure 7: Integrated FPGA Design and In-System Programming Solution for Platform Flash XL DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 10 R Platform Flash XL High-Density Configuration and Storage Device Bus Operations There are six standard bus operations that control the device: Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset (Table 5). Address Latch Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. Addresses are latched on the rising edge of Latch Enable. Bus Read Bus Read operations are used to output the contents of the Memory Array, Electronic Signature, Status Register and Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see "Command Interface," page 14). Output Disable The outputs are held at high impedance when Output Enable is at VIH. Standby Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at VIH. Power consumption is reduced to the standby level IDD3, and the outputs are set to high impedance independently from Output Enable or Write Enable. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished with the program or erase operation. Bus Write Bus Write operations write commands to the memory or latch Input Data to be programmed. A Bus Write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can be latched prior to the write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch Enable signal can also be held at VIL by the system, but then the system must guarantee that the address lines remain stable for at least TWHAX. Note: Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations. Table 5: Bus Operations(1) Operation Bus Read Bus Write Address Latch Output Disable Standby Reset FALS Notes: 1. 2. 3. 4. 5. 6. 7. Reset During Reset mode, the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. Power consumption is reduced to the Reset level independently from Chip Enable, Output Enable or Write Enable. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid. E VIL VIL VIL VIL VIH X VIL G VIL VIH X VIH X X VIL W VIH VIL VIH VIH X X VIH L VIL(4) VIL (4) RP VIH VIH VIH VIH VIH VIL (6) READY_WAIT(2,3) CR4 = 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z VIL (7) CR4 = 0 - - - Hi-Z Hi-Z - - DQ15-DQ0 Data output Data input Data output or Hi-Z(5) Hi-Z Hi-Z Hi-Z Data output VIL X X X VIH VIH Hi-Z X = Don't care. If READY_WAIT is configured as an output wait signal (CR4 = 0), then the CR10 Configuration Register bit defines the signal polarity. READY_WAIT is configured using the CR4 Configuration Register bit. L can be tied to VIH if the valid address was previously latched. Depends on G. The Configuration Register reverts to its default value after a Low logic level (VIL) is detected on the RP pin. READY_WAIT pin used as an output. READY_WAIT goes Low TPLRWL after RP goes Low. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 11 R Platform Flash XL High-Density Configuration and Storage Device Command Interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the program and erase commands. The Program/Erase Controller provides a Status Register whose output can be read at any time to monitor the progress or the result of the operation. The Command Interface is set to synchronous read mode when power is first applied, when exiting from Reset, or whenever VDD falls below its power-down threshold. Command sequences must be followed exactly -- any invalid combination of commands are ignored. Table 6 provides a summary of the Command Interface codes. Table 6: Command Codes Hex Code 01h 03h 10h 20h 2Fh 40h 50h 60h 70h 80h 90h 98h B0h BCh C0h CBh D0h E8h FFh Block Lock Confirm Set Configuration Register Confirm Alternative Program Setup Block Erase Setup Block Lock-Down Confirm Program Setup Clear Status Register Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup Read Status Register Buffer Enhanced Factory Program Setup Read Electronic Signature Read CFI Query Program/Erase Suspend Blank Check Setup Protection Register Program Blank Check Confirm Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm, Buffer Program or Buffer Enhanced Factory Program Confirm Buffer Program Read Array A Read Array command can be issued to any bank while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank returns to Read Array mode but the program or erase operation continues; however the data output from the bank is not guaranteed until the program or erase operation finishes. The read modes of other banks are not affected. Read Status Register Command The device contains a Status Register used to monitor program or erase operations. The Read Status Register command is used to read the contents of the Status Register for the addressed bank. One Bus Write cycle is required to issue the Read Status Register command. After a bank is in Read Status Register mode, subsequent read operations output the contents of the Status Register. The Status Register data is latched on the falling edge of Chip Enable or Output Enable. Either Chip Enable or Output Enable must be toggled to update the Status Register data. The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Status Register. A Read Array command is required to return the bank to Read Array mode. See Table 11, page 23 for the description of the Status Register Bits. Command Read Electronic Signature Command The Read Electronic Signature command is used to read the Manufacturer and Device Codes, Lock Status of the addressed bank, Protection Register, and Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. After a bank is in Read Electronic Signature mode, subsequent read operations in the same bank output the Manufacturer Code, Device Code, Lock Status of the addressed bank, Protection Register, or Configuration Register (see Table 10, page 22). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during Protection Register Program operations. Dual operations between the Parameter bank and the Electronic Signature location are not allowed (see Table 17, page 36 for details). If a Read Electronic Signature command is issued to a bank executing a program or erase operation, the bank enters Read Array Command The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command. After a bank is in Read Array mode, subsequent read operations output data from the memory array. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 12 R Platform Flash XL High-Density Configuration and Storage Device If the block is protected, then the erase operation aborts, data in the block is not changed, and the Status Register outputs the error. Two Bus Write cycles are required to issue the command. * * The first bus cycle sets up the Block Erase command. The second latches the block address and starts the Program/Erase Controller. into Read Electronic Signature mode. Subsequent Bus Read cycles output Electronic Signature data, and the Program/Erase controller continues to program or erase in the background. The Read Electronic Signature command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Electronic Signature. A Read Array command is required to return the bank to Read Array mode. Read CFI Query Command The Read CFI Query command is used to read data from the Common Flash Interface (CFI). One Bus Write cycle is required to issue the Read CFI Query command. After a bank is in Read CFI Query mode, subsequent Bus Read operations in the same bank read from the Common Flash Interface. The Read CFI Query command can be issued at any time, even during program or erase operations. If a Read CFI Query command is issued to a bank executing a program or erase operation, the bank enters into Read CFI Query mode. Subsequent Bus Read cycles output CFI data, and the Program/Erase controller continues to program or erase in the background. The Read CFI Query command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read from the CFI. A Read Array command is required to return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI memory space are not allowed (see Table 17, page 36 for details). See "Appendix B: Common Flash Interface," page 65, Table 36, page 65, through Table 45, page 70, Table 38, Table 38 for details on the information contained in the Common Flash Interface memory area. If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5 are set and the command is aborted. After the command is issued, the bank enters Read Status Register mode, and any read operation within the addressed bank outputs the contents of the Status Register. A Read Array command is required to return the bank to Read Array mode. During Block Erase operations, the bank containing the block being erased only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and Program/Erase Suspend command; all other commands are ignored. The Block Erase operation aborts if Reset (RP) goes to VIL. As data integrity cannot be guaranteed when the Block Erase operation is aborted, the block must be erased again. Refer to "Dual Operations and Multiple Bank Architecture," page 35 for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 21, page 44. See Figure 41, page 75, for a suggested flowchart for using the Block Erase command. Blank Check Command The Blank Check command is used to check whether a Block is completely erased. Only one block at a time can be checked. To use the Blank Check command, VPP must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the command and no error is shown in the Status Register. Two bus cycles are required to issue the Blank Check command: * * The first bus cycle writes the Blank Check command (BCh) to any address in the block to be checked. The second bus cycle writes the Blank Check Confirm command (CBh) to any address in the block to be checked and starts the Blank Check operation. Clear Status Register Command The Clear Status Register command can be used to reset (set to `0') all error bits (SR1, 3, 4 and 5) in the Status Register. One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the read mode of the bank. The error bits in the Status Register do not automatically return to `0' when a new command is issued. The error bits in the Status Register should be cleared before attempting a new program or erase command. Block Erase Command The Block Erase command is used to erase a block. It sets all the bits within the selected block to `1'. All previous data in the block is lost. DS617 (v3.0.1) January 07, 2010 Product Specification If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are set to '1', and the command aborts. After the command is issued, the addressed bank automatically enters the Status Register mode and further reads within the bank output the Status Register contents. www.xilinx.com 13 R Platform Flash XL High-Density Configuration and Storage Device The only operation permitted during Blank Check is Read Status Register. Dual Operations are not supported while a Blank Check operation is in progress. Blank Check operations cannot be suspended and are not allowed while the device is in Program/Erase Suspend. The SR7 Status Register bit indicates the status of the Blank Check operation in progress: * * SR7 = '0' indicates that the Blank Check operation is still ongoing. SR7 = '1' indicates that the operation is complete. Buffer Program Command The Buffer Program Command makes use of the device's 32-word Write Buffer to speed up programming. Up to 32 words can be loaded into the Write Buffer. The Buffer Program command dramatically reduces in-system programming time compared to the standard non-buffered Program command. Four successive steps are required to issue the Buffer Program command: 1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. After the first Bus Write cycle, read operations in the bank output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = 1). If the buffer is not available (SR7 = 0), the Buffer Program command must be re-issued to update the Status Register contents. 2. The second Bus Write cycle sets up the number of words to be programmed. Value n is written to the same block address, where n + 1 is the number of words to be programmed. 3. A total of n + 1 Bus Write cycles are used to load the address and data for each word into the Write Buffer. Addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. Optimum performance is obtained when the start address corresponds to a 32-word boundary. 4. The final Bus Write cycle confirms the Buffer Program command and starts the program operation. All the addresses used in the Buffer Program operation must lie within the same block. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles sets an error in the Status Register and aborts the operation without affecting the data in the memory array. If the block being programmed is protected, an error is set in the Status Register, and the operation aborts without affecting the data in the memory array. During Buffer Program operations, the bank being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and Program/Erase Suspend command; all other commands are ignored. Refer to "Dual Operations and Multiple Bank Architecture," page 35 for detailed information about simultaneous operations allowed in banks not being programmed. See Figure 39, page 73, for a suggested flowchart on using the Buffer Program command. The SR5 Status Register bit goes High (SR5 = '1') to indicate that the Blank Check operation has failed. At the end of the operation the bank remains in the Read Status Register mode until another command is written to the Command Interface. See Figure 38, page 72, for a suggested flowchart for using the Blank Check command. Typical Blank Check times are given in Table 21, page 44. Program Command The program command is used to program a single word to the memory array. If the block being programmed is protected, then the Program operation aborts, data in the block is not changed, and the Status Register outputs the error. Two Bus Write cycles are required to issue the Program Command. * * The first bus cycle sets up the Program command. The second latches the address and data to be programmed and starts the Program/Erase Controller. After the programming starts, read operations in the bank being programmed output the Status Register content. During a Program operation, the bank containing the word being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and Program/Erase Suspend command; all other commands are ignored. A Read Array command is required to return the bank to Read Array mode. Refer to "Dual Operations and Multiple Bank Architecture," page 35 for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 21, page 44. The Program operation aborts if Reset (RP) goes to VIL. As data integrity cannot be guaranteed when the Program operation is aborted, the word must be reprogrammed. See Figure 37, page 71, for the flowchart for using the Program command. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 14 R Platform Flash XL High-Density Configuration and Storage Device Buffer is full (32 words). To program less than 32 words, the remaining words should be programmed with FFFFh. Four successive steps are required to issue and execute the Program and Verify Phase of the command. 1. One Bus Write operation is used to latch the Start Address and the first word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next word. 2. Each subsequent word to be programmed is latched with a new Bus Write operation. The address must remain the Start Address as the P/E.C. increments the address location.If any address not in the same block as the Start Address is given, the Program and Verify Phase terminates. Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next word. 3. After the Write Buffer is full, the data is programmed sequentially to the memory array. After the program operation, the device automatically verifies the data and reprograms if necessary. The Program and Verify phase can be repeated without re-issuing the command to program an additional 32word locations as long as the address remains in the same block. 4. Finally, after all words, or the entire block are programmed, one Bus Write operation must be written to any address outside the block containing the Start Address to terminate Program and Verify Phase. Status Register bit SR0 must be checked to determine whether the program operation is finished. The Status Register can be checked for errors at any time but must be checked after the entire block is programmed. Buffer Enhanced Factory Program Command The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. The command is used to program one or more Write Buffer(s) of 32 words to a block. After the device enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. If the block being programmed is protected, then the Program operation aborts, data in the block is not changed, and the Status Register outputs the error. The use of the Buffer Enhanced Factory Program command requires certain operating conditions: * * * * * * VPP must be set to VPPH. VDD must be within operating range. Ambient temperature TA must be 30C 10C. The targeted block must be unlocked. The start address must be aligned with the start of a 32- word buffer boundary. The address must remain the Start Address throughout programming. Dual operations are not supported during the Buffer Enhanced Factory Program operation, and the command cannot be suspended. The Buffer Enhanced Factory Program Command consists of three phases: Setup, Program and Verify, and Exit (refer to Table 8, page 21 for detail information). Setup Phase The Buffer Enhanced Factory Program command requires two Bus Write cycles to initiate the command: * * The first Bus Write cycle sets up the Buffer Enhanced Factory Program command. The second Bus Write cycle confirms the command. Exit Phase Status Register P/E.C. bit SR7 is set to `1' when the device exits the Buffer Enhanced Factory Program operation and returns to Read Status Register mode. A full Status Register check should be done to ensure that the block is successfully programmed. See "Status Register," page 23 for more details. For optimum performance, the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded, the internal algorithm continues to work properly, but some degradation in performance is possible. Typical program times are given in Table 21, page 44. See Figure 45, page 79, for a suggested flowchart on using the Buffer Enhanced Factory Program command. After the confirm command is issued, read operations output the contents of the Status Register. Caution! The read Status Register command must not be issued as it is interpreted as data to program. The Status Register Program/Erase Controller (P/E.C). Bit SR7 should be read to check that the P/E.C. is ready to proceed to the next phase. If an error is detected, SR4 goes High (set to `1') and the Buffer Enhanced Factory Program operation is terminated. See "Status Register," page 23 for details on the error. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. The command can be addressed to any bank. Program and Verify Phase The Program and Verify Phase requires 32 cycles to program the 32 words to the Write Buffer. Data is stored sequentially, starting at the first address of the Write Buffer until the Write DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 15 R Platform Flash XL High-Density Configuration and Storage Device The Program/Erase Resume command is required to restart the suspended operation. One Bus Write cycle is required to issue the Program/Erase Suspend command. After the Program/Erase Controller pauses, bits SR7, SR6 and/or SR2 of the Status Register are set to `1'. The following commands are accepted during Program/Erase Suspend: * * * * * Program/Erase Resume Read Array (data from erase-suspended block or program-suspended word is not valid) Read Status Register Read Electronic Signature Read CFI Query Program/Erase Resume Command The Program/Erase Resume command is used to restart the program or erase operation suspended by the Program/Erase Suspend command. One Bus Write cycle is required to issue the command and can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank is in Read Status Register, Read Electronic Signature or Read CFI Query mode, the bank remains in that mode and outputs the corresponding data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the program operation is complete. See Figure 40, page 74, and Figure 42, page 76, for flowcharts for using the Program/Erase Resume command. Additionally, if the suspended operation is a Block Erase, then the following commands are also accepted: * * * * * * * Clear Status Register Program (except in erase-suspended block) Buffer Program (except in erase suspended blocks) Block Lock Block Lock-Down Block Unlock Set Configuration Register Protection Register Program Command The Protection Register Program command is used to program the user one-time-programmable (OTP) segments of the Protection Register and the two Protection Register Locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits (Figure 8, page 22). The segments are programmed one word at a time. When shipped, all bits in the segment are set to `1'. The user can only program the bits to `0'. Two Bus Write cycles are required to issue the Protection Register Program command: * * The first bus cycle sets up the Protection Register Program command. The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller. During an erase suspend, the block being erased can be protected by issuing Block Lock or Block Lock-Down commands. When the Program/Erase Resume command is issued, the operation completes. It is possible to accumulate multiple suspend operations. For example, suspend an erase operation, start a program operation, suspend the program operation, then read the array. If a Program command is issued during a Block Erase Suspend, the erase operation cannot be resumed until the program operation is complete. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank is in Read Status Register, Read Electronic Signature or Read CFI Query mode, the bank remains in that mode and outputs the corresponding data. Refer to "Dual Operations and Multiple Bank Architecture," page 35 for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/erase is aborted if Reset (RP) goes to VIL. See Figure 40, page 74, and Figure 42, page 76, for flowcharts for using the Program/Erase Suspend command. Read operations to the bank being programmed output the Status Register content after the program operation starts. Attempting to program a previously protected Protection Register results in a Status Register error. The Protection Register Program cannot be suspended. Dual operations between the Parameter Bank and the Protection Register memory space are not allowed (see Table 17, page 36, for details). The two Protection Register Locks are used to protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 8, page 22, and Table 10, page 22, for details on the Lock bits. See Figure 44, page 78, for a flowchart for using the Protection Register Program command. Set Configuration Register Command The Set Configuration Register command is used to write a new value to the Configuration Register. Two Bus Write cycles are required to issue the Set Configuration Register command: DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 16 R Platform Flash XL High-Density Configuration and Storage Device * The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content. The second cycle writes the Configuration Register data and the confirm command. Block Unlock Command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command: * * The first bus cycle sets up the Block Unlock command. The second Bus Write cycle latches the block address and unlocks the block. * The Configuration Register data must be written as an address during the bus write cycles, that is A0 = CR0, A1 = CR1, ..., A15 = CR15. Addresses A16-A22 are ignored. Read operations output the array content after the Set Configuration Register command is issued. The Read Electronic Signature command is required to read the updated contents of the Configuration Register. Block Lock Command The Block Lock command is used to lock a block and prevent program or erase operations from changing the contents. All blocks are locked after power-up or reset. Two Bus Write cycles are required to issue the Block Lock command: * * The first bus cycle sets up the Block Lock command. The second Bus Write cycle latches the block address and locks the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 18, page 38 shows the protection status after issuing a Block Unlock command. Refer to the "Block Locking," page 37 for a detailed explanation and Figure 43, page 77, for a flowchart for using the Block Unlock command. Block Lock-Down Command The Block Lock-Down command is used to lock down a locked or unlocked block. A locked-down block cannot be programmed or erased. The lock status of a locked-down block cannot be changed when WP is Low (at VIL). When WP is High (at VIH), the LockDown function is disabled, and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block LockDown command: * * The first bus cycle sets up the Block Lock-Down command. The second Bus Write cycle latches the block address and locks-down the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 18, page 38 shows the Lock Status after issuing a Block Lock command. After being set, the Block Lock bits remain set even after a hardware reset or power-down/power-up. They are cleared by a Block Unlock command. Refer to "Block Locking," page 37 for a detailed explanation. See Figure 43, page 77, for a flowchart for using the Lock command. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the Locked (and not LockedDown) state when the device is reset on power-down. Table 18 shows the Lock Status after issuing a Block LockDown command. Refer to "Block Locking", for a detailed explanation and Figure 43, for a flowchart for using the Lock-Down command. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 17 R Platform Flash XL High-Density Configuration and Storage Device Table 7: Standard Commands(1) Cycles Bus Operations First Cycle Op. Write Write Write Write Write Write Write Write n+4 Write Write Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Lock Block Unlock Block Lock-Down Notes: 1. X = Don't Care, WA = Word Address in targeted bank, RD =Read Data, SRD =Status Register Data, ESD = Electronic Signature Data, QD =Query Data, BA =Block Address, BKA = Bank Address, PD = Program Data, PA = Program address, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration Register Data. Must be same bank as in the first cycle. The signature addresses are listed in Table 9, page 21. Any address within the bank can be used. n+1 is the number of words to be programmed. Commands Second Cycle Data FFh 70h 90h 98h 50h Add. BKA BKA BKA BKA X BKA or BKA or BA(3) WA(3) Op. Read Read Read Read - Write Write Write Write Write - - Write Write Write Write Write Add. WA BKA(2) BKA(2) BKA(2) - BA WA BA PA2 X - - PRA CRD BA BA BA Data RD SRD ESD QD - D0h PD n PD2 D0h - - PRD 03h 01h D0h 2FH Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase Program Buffer Program(4) 1+ 1+ 1+ 1+ 1 2 2 20h 40h or 10h E8h PD1 PDn+1 B0h D0h C0h 60h 60h 60h 60h BA PA1 PAn+1 X X PRA CRD BKA or BA(3) BKA or BKA or BA(3) BA(3) 1 1 2 2 2 2 2 Write Write Write Write Write Write Write 2. 3. 4. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 18 R Platform Flash XL High-Density Configuration and Storage Device Table 8: Factory Commands Command Phase Cycles Bus Write Operations(1) First Add. BA BKA or WA(2) WA1 NOT BA1(4) Second Add. BA WA1 WA1 - Third Add. - - Data BCh 80h Data CBh D0h Data - - ... ... ... Final - 1 Add. - - Final Add. - - Data - - Data - - Blank Check Setup Buffer Enhanced Factory Program Program/ Verify(3) Exit Notes: 1. 2. 3. 4. 2 2 32 1 PD1 X PD2 - WA1 - PD3 - ... ... WA1 - PD31 - WA1 - PD32 - WA = Word Address in targeted bank, BKA = Bank Address, PD =Program Data, BA = Block Address, X = Don't Care. Any address within the bank can be used. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same block. WA1 is the Start Address, NOT BA1 = Not Block Address of WA1. Table 9: Electronic Signature Codes Code Manufacturer Code Device Code Locked Block Protection Unlocked Locked and Locked-Down Unlocked and Locked-Down Configuration Register Protection Register PR0 Lock Factory Default OTP Area Permanently Locked Bank Address + 005 Bank Address + 080 0000 Bank Address + 081 Bank Address + 084 Bank Address + 085 Bank Address + 088 Bank Address + 089 Bank Address + 08A Bank Address + 109 Unique Device Number OTP Area PRLD(1) OTP Area Block Address + 002 0003 0002 CR(1) 0002 Address (h) Bank Address + 000 Bank Address + 001 Data (h) 0049 506B 0001 0000 Protection Register PR0 Protection Register PR1 through PR16 Lock Protection Registers PR1-PR16 Notes: 1. 2. CR = Configuration Register, PRLD = Protection Register Lock Data. The iMPACT software does not support reading of the electronic signature codes. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 19 R Platform Flash XL High-Density Configuration and Storage Device Table 10: Protection Register Locks Lock Number Lock 1 Address 80h Bits bit 0 bit 1 bits 2 to 15 bit 0 bit 1 bit 2 Description Preprogrammed to protect Unique Device Number, address 81h to 84h in PR0 Protects 64 bits of OTP segment, address 85h to 88h in PR0 Reserved Protects 128 bits of OTP segment PR1 Protects 128 bits of OTP segment PR2 Protects 128 bits of OTP segment PR3 - Protects 128 bits of OTP segment PR14 Protects 128 bits of OTP segment PR15 Protects 128 bits of OTP segment PR16 Lock 2 89h - bit 13 bit 14 bit 15 X-Ref Target - Figure 8 109h PR16 User Programmable OTP 102h 91h PR1 User Programmable OTP Protection Register Lock 8Ah 89h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 88h 85h 84h PR0 User Programmable OTP Unique Device Number 81h 80h Protection Register Lock 10 DS617_41_101508 Notes: 1. The iMPACT software does not support reading or writing of the protection register locks, OTP fields, or unique device number. Figure 8: Protection Register Memory Map DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 20 R Platform Flash XL High-Density Configuration and Storage Device Status Register The Status Register provides information on the current or previous program or erase operations. A Read Status Register command is issued to read the contents of the Status Register, refer to "Read Status Register Command," page 14 for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single asynchronous or synchronous reads. Bus Read operations from any address within the bank always read the Status Register during program and erase operations if no Read Array command is issued. Table 11: Status Register Bits Bit SR7 The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors and are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1', the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 11. Name P/E.C. Status Type Status Logic Level(1) '1' '0' '1' '0' '1' '0' '1' '0' '1' '0' '1' '0' '1' '0' '1' Ready Busy Erase suspended Definition SR6 Erase Suspend Status Erase/Blank Check Status Program Status Status Erase In progress or completed Erase/blank check error Erase/blank check success Program error Program success VPP invalid, abort VPP OK Program suspended Program In progress or completed Program/erase on protected block, abort No operation to protected block SR7 = `1' SR7 = `0' SR7 = `1' Not allowed Program or erase operation in a bank other than the addressed bank No program or erase operation in the device Program or erase operation in addressed bank Not allowed The device is NOT ready for the next Buffer loading or is going to exit the BEFP mode The device has exited the BEFP mode The device is ready for the next Buffer loading SR5 Error SR4 Error SR3 VPP Status Program Suspend Status Block Protection Status Error SR2 Status SR1 Error Bank Write Status Status '0' SR7 = `0' SR7 = `1' SR0 '1' Multiple Word Program Status (Buffer Enhanced Factory Program mode) Status '0' SR7 = `0' SR7 = `1' SR7 = `0' Notes: 1. Logic level '1' is High, '0' is Low. Program/Erase Controller Status Bit (SR7) The Program/Erase Controller Status bit indicates whether DS617 (v3.0.1) January 07, 2010 Product Specification the Program/Erase Controller is active or inactive in any bank. When this bit is Low (set to `0'), the Program/Erase www.xilinx.com 21 R Platform Flash XL High-Density Configuration and Storage Device Attempting to program a '1' to an already programmed bit while VPP = VPPH also sets the Program Status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0'), and the attempt is not shown. After set High, the Program Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program command is issued; otherwise, the new command appears to fail. Controller is active; when the bit is High (set to `1'), the controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status bit is Low immediately after a Program/Erase Suspend command was issued until the controller pauses. After the Program/Erase Controller pauses the bit is High. Erase Suspend Status Bit (SR6) The Erase Suspend Status bit indicates that an erase operation is suspended. When this bit is High (set to `1'), a Program/Erase Suspend command was issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued; therefore, the memory can still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued, the Erase Suspend Status bit returns Low. VPP Status Bit (SR3) The VPP Status bit is used to identify an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage. When the VPP Status bit is High (set to `1'), the VPP pin has a voltage below the VPP Lockout Voltage (VPPLK). the memory is protected and program and erase operations cannot be performed. After set High, the VPP Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued; otherwise, the new command appears to fail. Erase/Blank Check Status Bit (SR5) The Erase/Blank Check Status bit is used to identify if an error occurred during a Block Erase operation. When this bit is High (set to `1'), the Program/Erase Controller applied the maximum number of pulses to the block and still failed to verify that it erased correctly. The Erase/Blank Check Status bit should be read after the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). The Erase/Blank Check Status bit is also used to indicate whether an error occurred during the Blank Check operation. If the data at one or more locations in the block where the Blank Check command was issued is different from FFFFh, SR5 is set to '1'. After set High, the Erase/Blank Check Status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is issued; otherwise, the new command appears to fail. Program Suspend Status Bit (SR2) The Program Suspend Status bit indicates that a program operation is suspended. This bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Suspend Status bit is High (set to `1'), a Program/Erase Suspend command was issued, and the memory is waiting for a Program/Erase Resume command. SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued; therefore, the memory can still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued, the Program Suspend Status bit returns Low. Program Status Bit (SR4) The Program Status bit is used to identify if there is an error during a program operation. This bit should be read after the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is High (set to `1'), the Program/Erase Controller applied the maximum number of pulses to the word and still failed to verify that it programmed correctly. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 22 R Platform Flash XL High-Density Configuration and Storage Device Program bit shows if the device is ready to accept a new word to be programmed to the memory array. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to `0'). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to `0'), the addressed bank is executing a program or erase operation. When the Program/Erase Controller Status bit is Low (set to `0') and the Bank Write Status bit is High (set to `1'), a program or erase operation is being executed in a bank other than the one being addressed. In Buffer Enhanced Factory Program mode, if Multiple Word Program Status bit is Low (set to `0'), the device is ready for the next word; if the Multiple Word Program Status bit is High (set to `1') the device is not ready for the next word. For further details on how to use the Status Register, see the Flowcharts and Pseudocodes provided in "Appendix C: Flowcharts and Pseudocodes," page 71. Block Protection Status Bit (SR1) The Block Protection Status bit is used to identify if a Program or Block Erase operation tried to modify the contents of a locked or locked-down block. When this bit is High (set to `1'), a program or erase operation was attempted on a locked or locked-down block. After set High, the Block Protection Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued; otherwise, the new command appears to fail. Bank Write/Multiple Word Program Status Bit (SR0) The Bank Write Status bit indicates whether the addressed bank is busy performing a write or is ready to accept a new write command (a program or erase command). In Buffer Enhanced Factory Program mode, the Multiple Word DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 23 R Platform Flash XL High-Density Configuration and Storage Device Configuration Register The Configuration Register is used to configure the type of bus access that the memory performs. Refer to "Read Modes," page 34 for details on read operations. The Configuration Register is set through the Command Interface using the Set Configuration Register command. After a reset or power-up, the device is configured for Synchronous Read (CR15 = 0). The Configuration Register bits (Table 12, page 26) specify the selection of the burst length, burst type, burst X latency, and read operation. Refer to Figure 9, page 28 and Figure 10, page 30 for examples of synchronous burst configurations. Table 12: Configuration Register Bits Bits CR15 CR14 Description Read mode Value 0 1 Description Synchronous Read (default) Asynchronous Read 2 clock latency(1) 3 clock latency 4 clock latency 5 clock latency 6 clock latency 7 clock latency (default) Reserved 0 010 011 100 CR13-CR11 Clock Latency 101 110 111 Other configurations reserved 0 CR10 Wait Polarity 1 CR9 Data output configuration Wait Configuration 1 0 CR7 Burst Type 1 0 CR6 CR5 CR4 CR3(2) Valid Clock Edge 1 Reserved Device_ready 1 0 Wrap burst 1 001 CR2-CR0(2) 010 Burst Length 011 111 Notes: 1. 2. The combination X-Latency = 2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported. CR3 (wrap/no wrap) bit has no effect when CR2-CR0 (burst length) bits are set to continuous burst mode. Platform Flash XL wraps to the first memory address after the device outputs the data from the last memory address. READY_WAIT with Wait function (CR4 = 0) is active Low READY_WAIT with Wait function (CR4 = 0) is active High (default) Data held for 1 clock cycle (default) Data held for 2 clock cycles(1) Wait active during wait state Wait active 1 clock cycle before wait state (default) Reserved Sequential (default) Falling clock edge Rising clock edge (default) - READY_WAIT signal has the Wait function READY_WAIT signal has the Ready function (default) Wrap No wrap (default) 4 words 8 words 16 words Continuous (default) 0 1 0 CR8 0 0 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 24 R Platform Flash XL High-Density Configuration and Storage Device where: tK is the clock period tQVK_CPU is the data setup time required by the system CPU tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to `1' for two clock cycles (Figure 9, page 28). Read Mode Select Bit (CR15) The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read operations. When this bit is set to `1', read operations are asynchronous; when set to `0', read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up, the Read Select bit is set to `0' for synchronous access. Wait Configuration Bit (CR8) The Wait Configuration bit is used to control the timing of the READY_WAIT signal when configured as an output with the Wait function (in Synchronous Burst Read mode). When READY_WAIT is asserted, data is not valid; when READY_WAIT is deasserted, data is valid. When the Wait Configuration bit is Low (reset to `0'), the READY_WAIT signal (configured as an output with the Wait function) is asserted during the WAIT state. When the Wait Configuration bit is High (set to `1'), the READY_WAIT output pin is asserted one data cycle before the WAIT state. X-Latency Bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available (Figure 9). For correct operation the X-Latency bits can only assume the values listed in Table 12, page 26. Table 13 shows how to set the X-Latency parameter, taking into account the speed class of the device and the frequency used to read the flash memory in synchronous mode. Table 13: X-latency Settings FMAX 30 MHz 40 MHz 54 MHz TKmin 33 ns 25 ns 19 ns X-Latency min 3 4 5 Burst Type Bit (CR7) The Burst Type bit determines the sequence of addresses read during Synchronous Burst Read operations. This bit is High (set to `1') as the memory outputs from sequential addresses only. See Table 14, page 29, for the sequence of addresses output from a given starting address in sequential mode. Wait Polarity Bit (CR10) The Wait Polarity bit is used to set the polarity of the READY_WAIT signal used in Synchronous Burst Read mode (with CR4 = 0). During this mode, the READY_WAIT signal indicates whether the data output is valid or a WAIT state must be inserted. When the Wait Polarity bit is at '0', the READY_WAIT signal is active Low. When this bit is set to '1', the READY_WAIT signal is active High. The CR10 Configuration Register bit becomes "don't care" if CR4 is set to `1', in which case the READY_WAIT pin behaves like a READY pin (default value). Valid Clock Edge Bit (CR6) The Valid Clock Edge bit (CR6) is used to configure the active edge of the Clock (K) during synchronous read operations. When this bit is Low (set to `0'), the falling edge of the Clock is the active edge; when High (set to `1'), the rising edge of the Clock is the active edge. READY_WAIT Bit (CR4) The READY_WAIT Configuration Register bit is a userconfigurable bit. The default value is `1', where the READY_WAIT signal is configured as an input with the Ready function (CR4 = '1'). This particular configuration allows the use of the READY_WAIT signal for handshaking during the configuration sequence and during a Reset (RP) pulse as the device holds the pin Low until the entire internal configuration of the device finishes. With CR4 = 1, the external pin can also be used by the end user to retrigger the first address latching sequence (FALS), simply by applying a High, a Low, and then a High pulse on the READY_WAIT pin. See "First Address Latching Sequence," page 41. When CR4 = '0', the READY_WAIT signal assumes the standard WAIT functionality. Data Output Configuration Bit (CR9) The Data Output Configuration bit is used to configure the output to remain valid for either one or two clock cycles during synchronous mode. When this bit is `0', the output data is valid for one clock cycle; when the bit is `1', the output data is valid for two clock cycles. The Data Output Configuration must be configured using the following condition: tK > tKQV + tQVK_CPU DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 25 R Platform Flash XL High-Density Configuration and Storage Device In continuous burst mode, or 4, 8 or 16 words no-wrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is shifted by 1, 2 or 3 positions from the four-word boundary, WAIT is asserted for 1, 2 or 3 clock cycles, respectively, when the burst sequence crosses the first 16-word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT is asserted only once during a continuous burst access. See also Table 14, page 29. CR14 and CR5 are reserved for future use. Wrap Burst Bit (CR3) The Wrap Burst bit (CR3) is used to select between wrap and no wrap. Synchronous burst reads can be confined inside the 4, 8 or 16-word boundary (wrap) or overcome the boundary (no wrap). When this bit is Low (set to `0'), the burst read wraps. When it is High (set to `1'), the burst read does not wrap. Burst Length Bits (CR2-CR0) The Burst Length bits are used to set the number of words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. These bits can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In continuous burst mode, the burst sequence can cross bank boundaries. X-Ref Target - Figure 9 X-latency 1st cycle 2nd cycle 3rd cycle 4th cycle K E L A22-A0 TDELAY VALID ADDRESS TAVK_CPU TACC TQVK_CPU TKQV VALID DATA VALID DATA DS617_42_032508 TK TQVK_CPU DQ15-DQ0 Figure 9: X-Latency and Data Output Configuration Example DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 26 R Platform Flash XL High-Density Configuration and Storage Device Table 14: Burst Type Definition Mode Start Address 0 1 2 3 Sequence 4 Words 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8 Words 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 ... 16 Words 0-1-2-3-4-5-6-7-8-9-10-1112-13-14-15 1-2-3-4-5-6-7-8-9-10-1112-13-14-15-0 2-3-4-5-6-7-8-9-10-11-1213-14-15-0-1 3-4-5-6-7-8-9-10-11-1213-14-15-0-1-2 Continuous Burst 0-1-2-3-4-5-6... 1-2-3-4-5-6-7-...15-WAIT16-17-18... 2-3-4-5-6-7...15-WAITWAIT-16-17-18... 3-4-5-6-7...15-WAIT-WAITWAIT-16-17-18... Wrap 7 7-4-5-6 7-0-1-2-3-4-5-6 ... 7-8-9-10-11-12-13-14-150-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15WAIT-WAIT-WAIT-16-17.. 12 13 14 15 0 1 0-1-2-3 1-2-3-4 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 0-1-2-3-4-5-6-7-8-9-10-1112-13-14-15 1-2-3-4-5-6-7-8-9-10-1112-13-14-15-WAIT-16 2-3-4-5-6-7-8-9-10-11-1213-14-15-WAIT-WAIT-1617 3-4-5-6-7-8-9-10-11-1213-14-15-WAIT-WAITWAIT-16-17-18 - 12-13-14-15-16-17-18... 13-14-15-WAIT-16-17-18... 14-15-WAIT-WAIT-16-1718.... 15-WAIT-WAIT-WAIT-1617-18... 2 2-3-4-5 2-3-4-5-6-7-8-9... 3 3-4-5-6 3-4-5-6-7-8-9-10 ... No-Wrap 7 7-8-9-10 7-8-9-10-11-12-13-14 ... 7-8-9-10-11-12-13-14-15WAIT-WAIT-WAIT-16-1718-19-20-21-22 Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst) 12 12-13-14-15 12-13-14-15-16-17-18-19 13-14-15-WAIT-16-17-1819-20 14-15-WAIT-WAIT-16-1718-19-20-21 15-WAIT-WAIT-WAIT-1617-18-19-20-21-22 12-13-14-15-16-17-18-1920-21-22-23-24-25-26-27 13-14-15-WAIT-16-17-1819-20-21-22-23-24-25-2627-28 14-15-WAIT-WAIT-1617-18-19-20-21-22-2324-25-26-27-28-29 15-WAIT-WAIT-WAIT-1617-18-19-20-21-22-23-2425-26-27-28-29-30 13 13-14-15-WAIT-16 14 14-15-WAIT-WAIT-16-17 15 15-WAIT-WAIT-WAIT-1617-18 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 27 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 10 E K L A22-A0 VALID ADDRESS DQ15-DQ0 VALID DATA VALID DATA NOT VALID VALID DATA Wait CR8 = `0' CR10 = `0' Wait CR8 = `1' CR10 = `0' Wait CR8 = `0' CR10 = `1' Wait CR8 = `1' CR10 = `1' DS617_43_032508 Figure 10: Wait Application Example (CR4 = `0') DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 28 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 11 First Address Latching Sequence VDD/VDDQ TVHRWZ READY_WAIT TRWRT Latency cycles (default = 7) G L TRWHKL TAVKH3 1 2 3 TKH3AX 4 K A22-A0 Address not Valid Address TKHQV DQ15-DQ0 Notes: 1. 2. 3. FFFFh (Sync + Dummy cycle) D0 D1 D2 D3 D4 D5 DS617_44_053008 W is tied High. Address is latched on the third rising edge of K when G and E are Low, and L and READY_WAIT are High. READY_WAIT requires an external pull-up resistor to VDDQ sufficiently strong to ensure a clean Low-to-High transition within less than TRWRT when the READY_WAIT pin is released to a high-impedance state. Figure 11: Power-Up X-Ref Target - Figure 12 VDD/VDDQ TVHRWZ TRWRT READY_WAIT G L TAVRWH TRWHAX K1 2 3 4 K A22-A0 DQ15-DQ0 Valid Address TKHQV FFFFh Latency Cycles (default = 7) D0 D1 D2 D3 D4 D5 D6 D7 D8 DS617_45_101508 Notes: 1. 2. 3. It is recommended to use the shown timings in the case of a free-running clock. W is tied High. K1 is the first clock edge from which both the READY_WAIT and the Output Enable signals are asserted (READY_WAIT at VIH and G at VIL). Figure 12: Power-Up (Free-Running Clock) DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 29 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 13 READY_WAIT TRWLRWH G L, W K High TRWHKL 1 TAVKH3 2 3 4 TKH3AX Valid Address TKHQV Latency Cycles (default = 7) A22-A0 DQ15-DQ0 Dk Dn FFFFh FFFFh D0 D1 D2 D3 D4 D5 DATA VALID DS617_46_100608 DATA VALID Notes: 1. 2. Dk and Dn indicate the Data valid after k and n clock cycles, respectively. This figure applies when READY_WAIT (CR4) is configured with the Ready function. Figure 13: READY_WAIT Pulse (Clock is not Free Running) X-Ref Target - Figure 14 TPLPH RP READY_WAIT TPHRWZ TRWRT TPLRWL Low G L, W High TAVRWH TRWHAX K1 2 3 4 K A22-A0 Valid Address TKHQV DQ15-DQ0 FFFFh FFFFh Latency Cycles (default = 7) D0 D1 D2 D3 D4 D5 D6 D7 D8 DS617_47_102308 Notes: 1. 2. 3. 4. W is tied High. It is recommended to use the shown timings when the system has a free-running clock. K1 is the first clock edge from which both the READY_WAIT and the Output Enable signals are asserted (READY_WAIT at VIH and G at VIL). READY_WAIT requires an external pull-up resistor to VDDQ sufficiently strong to ensure a clean Low-to-High transition within less than TRWRT when the READY_WAIT pin is released to a high-impedance state. Figure 14: READY_WAIT Pulse (Free-Running Clock) DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 30 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 15 TPLPH RP TPLRWL TPHRWZ TRWRT READY_WAIT G High L, W K A22-A0 Valid Address Latency Default Cycles Address not Valid TKHQV DQ15-DQ0 FFFFh D0 D1 D2 D3 D4 D5 Valid Data DS617_48_101508 Figure 15: RP Pulse (Clock is not Free Running) X-Ref Target - Figure 16 RP READY_WAIT TPLPH TRWRT TPHRWZ TPLRWL G L, W K A22-A0 DQ15-DQ0 Low High TAVRWH K1 2 3 4 TRWHAX Valid Address TKHQV FFFFh FFFFh D0 D1 D2 D3 D4 D5 D6 D7 D8 Latency Cycles (default = 7) DS617_49_101608 Notes: 1. 2. It is recommended to use the shown timings in the case of a free-running clock. K1 is the first clock edge from which both the READY_WAIT and the Output Enable signals are asserted (READY_WAIT at VIH and G at VIL). Figure 16: RP Pulse (Free Running Clock) DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 31 R Platform Flash XL High-Density Configuration and Storage Device Read Modes Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is also synchronous. The read mode and format of the data output are determined by the Configuration Register (see "Program/Erase Controller Status Bit (SR7)," page 23). All banks support both asynchronous and synchronous read operations. In Synchronous Burst Read mode, the flow of the data output depends on parameters configured in the Configuration Register. A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration Register. The number of words to be output during a Synchronous Burst Read operation can be configured as 4 words, 8 words, 16 words or continuous (Burst Length bits CR2CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Wrap Burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 word boundary (Wrap) or overcome the boundary (No Wrap). The READY_WAIT signal configured for the Wait function (CR4 = `0') can be asserted to indicate to the system that an output delay occurs. This delay depends on the starting address of the burst sequence and on the burst configuration. READY_WAIT (with CR4 = `0') is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16-word burst. The signal is only de-asserted when output data is valid or when G is at VIH. In Continuous Burst Read mode, a WAIT state occurs when crossing the first 16-word boundary. If the starting address is aligned to the Burst Length (4, 8 or 16 words), the wrapped configuration has no impact on the output sequence. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 29, page 52: Synchronous Read ac characteristics, and Figure 27, page 51: Synchronous Burst Read ac waveforms, CR4 = 0, for details. Asynchronous Read Mode In Asynchronous Read operations, the clock signal is `don't care'. Depending on the last command issued, the device outputs the memory array data corresponding to the latched address, the status register value, common flash interface value, or electronic signature. Note: The Read Mode Select bit (CR15) in the Configuration Register must be set to '1' for asynchronous read mode operations. Asynchronous Read operations can be performed in two different ways: Asynchronous Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. In Asynchronous Read mode a page of data is internally read and stored in a Page Buffer. A page has a size of 4 words and is addressed by address inputs A0 and A1. The first read operation within the page has a longer access time (tAVQV, Random Access Time), subsequent reads within the same page have much shorter access times (tAVQV1, Page Access Time). If the page changes then the normal, longer timings apply again. The device features an Automatic Standby mode. During Asynchronous Read operations, after a bus inactivity of 150 ns, the device automatically switches to the Automatic Standby mode. In this mode, the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, when the READY_WAIT signal is configured for the Wait function (CR4 = `0'), it is always deasserted. See Table 28, page 50, Figure 25, page 48, and Figure 26, page 49, for details. Synchronous Burst Read Suspend A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. The operation can be suspended during the initial access latency time (before data is output) or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when Chip Enable (E) is Low and the current address is latched (on a Latch Enable rising edge, or on a valid clock edge). Synchronous Burst Read Mode In Synchronous Burst Read mode, the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI, and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 32 R Platform Flash XL High-Density Configuration and Storage Device Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status, or Protection Register. When the addressed bank is in Read CFI, Read Status Register, or Read Electronic Signature mode, the READY_WAIT signal (if configured for the Wait function with CR4 = `0') is asserted during X-latency, the WAIT state and at the end of a 4, 8 and 16-word burst. The signal is only deasserted when output data is valid. See Table 29, page 52 and Figure 27, page 51, for details. The Clock signal is then halted at VIH or at VIL, and Output Enable (G) goes High. When Output Enable goes Low again and the Clock signal restarts, the Synchronous Burst Read operation is resumed at its previous location. When READY_WAIT (with CR4 = `0') is gated by E, it reverts to high impedance when G goes High. See Table 29, page 52, and Figure 30, page 54 for details. Single Synchronous Read Mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that the memory outputs the same data to the end of the operation. Dual Operations and Multiple Bank Architecture The Multiple Bank Architecture of Platform Flash XL gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual Operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. This feature allows read operations with zero latency in one bank while programming or erasing in another bank. Note: Only one bank at a time is allowed to be in program or erase mode. Suspend mode, one in programming mode, and other banks in read mode. Bus Read operations are allowed in other banks between setup and confirm cycles of program or erase operations. By using a combination of these features, read operations are always possible in Platform Flash XL. Table 15 and Table 16, page 35 show which dual operations are possible in other banks and in the same bank. Dual operations between the Parameter Bank and either of the CFI, OTP, or Electronic Signature memory spaces are not allowed. Table 17, page 36 shows which dual operations are allowed or not between the CFI, OTP, Electronic Signature locations and the memory array. If a read operation is required in a bank which is programming or erasing, the program or erase operation can be suspended. Also if the suspended operation is erase, then a program command can be issued to another block so that the device can have one block in Erase Table 15: Dual Operations Allowed in Another Bank Commands Allowed in Another Bank Status of Bank Read Array Read Status Register Read CFI Query Read Electronic Signature Program, Buffer Program Block Erase Program/ Erase Suspend Program/ Erase Resume Idle Programming Erasing Program Suspended Erase Suspended - - - - - - - - - - - Table 16: Dual Operations Allowed in Same Bank Commands Allowed in Same Bank Status of Bank Read Array Read Status Register Read CFI Query Read Electronic Signature Program, Buffer Program Block Erase Program/ Erase Suspend Program/ Erase Resume Idle Programming Erasing -(1) -(1) - - - - - - DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 33 R Platform Flash XL High-Density Configuration and Storage Device Table 16: Dual Operations Allowed in Same Bank (Cont'd) Commands Allowed in Same Bank Status of Bank Read Array Read Status Register Read CFI Query Read Electronic Signature Program, Buffer Program - Block Erase - - Program/ Erase Suspend - - Program/ Erase Resume Program Suspended Erase Suspended Notes: 1. 2. 3. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed. The Read Array command is accepted but the data output is not guaranteed in the Block that is being erased or the word being programmed. Not allowed in the Block being erased or in the word being programmed. Table 17: Dual Operation Limitations Commands Allowed Current Status Read CFI / OTP / Electronic Signature - Read Parameter Blocks - - Read Main Blocks Located in Parameter Bank - - In Different Bank Only Not Located in Parameter Bank Programming / Erasing Parameter Blocks Programming / Erasing Main Blocks Not Located in Parameter Bank Programming OTP Located in Parameter Bank - - - - DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 34 R Platform Flash XL High-Density Configuration and Storage Device Block Locking Platform Flash XL features an instant, individual block-locking scheme, allowing any block to be locked or unlocked with no latency. This locking scheme has three levels of protection: * * * Lock/Unlock - this first level allows software only control of block locking. Lock-Down - this second level requires hardware interaction before locking can be changed. VPP = VPPLK - this third level offers a complete hardware protection against program and erase on all blocks. Locked-Down State Blocks that are Locked-Down (state (0,1,x)) are protected from program and erase operations (similar to locked blocks) but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by issuing the Lock-Down command. Locked-down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the Write Protect (WP) input pin. When WP = 0 (VIL), blocks in the LockDown state (0,1,x) are protected from program, erase and protection status changes. When WP = 1 (VIH), the Lock-Down function is disabled (1,1,x), and locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command to erase and programme. When the Lock-Down function is disabled (WP = 1), blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. When WP = 0. Blocks previously locked-down return to the Lock-Down state (0,1,x), regardless of any changes made while WP = 1. Device reset or power-down resets all blocks, including those in Locked-Down, to the Locked state. The protection status of each block can be set to Locked, Unlocked, and Locked-Down. Table 18, page 38, defines all of the possible protection states (WP, DQ1, DQ0), and Figure 43, page 77, shows a flowchart for the locking operations. Reading a Block's Lock Status The lock status of every block can be read during the Read Electronic Signature mode of the device (see "Read Electronic Signature Command," page 14). Subsequent reads at the address specified in Table 9, page 21 output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. DQ0 is automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. DQ1 cannot be cleared by software, only by a hardware reset or power-down. Locking Operations during Erase Suspend Changes to block lock status can be performed during a suspended erase by using standard locking command sequences to unlock, lock or lock-down a block. This capability is useful in the case when another block needs to be updated while an erase operation is in progress. Three steps are needed to change block locking during an erase operation: 1. An Erase Suspend command is issued. 2. The Status Register is checked until it indicates that the erase operation is suspended. 3. The desired Lock command sequence is issued to a block (lock status changes). After completing any desired lock, read, or program operations, the erase operation is resumed with the Erase Resume command. If a block is locked or locked-down during a suspended erase of the same block, the locking status bits are changed immediately. But when the erase is resumed, the erase operation completes. Locking operations cannot be performed during a program suspend. Block Lock States Locked State The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any program or erase operations attempted on a locked block returns an error in the Status Register. The status of a locked block can be changed to Unlocked or Locked-Down using the appropriate software commands. An unlocked block can be Locked by issuing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)) can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 35 R Platform Flash XL High-Density Configuration and Storage Device Table 18: Lock Status Current Protection Status(1) (WP, DQ1, DQ0) Current State 1,0,0 1,0,1(2) 1,1,0 1,1,1 0,0,0 0,0,1(2) 0,1,1 Notes: 1. 2. 3. The lock status is defined by the write protect pin and by DQ1 (`1' for a locked-down block) and DQ0 (`1' for a locked block) as read in the Read Electronic Signature command with DQ1 = VIH and DQ0 = VIL. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110. Next Protection Status(1) (WP, DQ1, DQ0) After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 Program/Erase Allowed After Block Lock Command 1,0,1 After Block LockDown Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1 After WP Transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0(3) - 1,0,1 1,1,1 - 1,1,1 0,0,1 - - 0,0,1 0,1,1 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 36 R Platform Flash XL High-Density Configuration and Storage Device Power-On Reset To ensure a correct power-up sequence of Platform Flash XL, the VDD ramp time, TVDDPOR, must not be shorter than 200 s or longer than 50 ms during power-up (see Figure 18, page 40). These timing limits correspond to the ramp rate values for which the power-up current is in the range where the VDD ramp time is formally characterized or tested. The device requires that the VDD power supply monotonically rises to the nominal operating voltage within the specified VDD rise time. If the power supply cannot meet this requirement, then the device might not perform poweron reset properly. During the POR sequence or a reset pulse (RP), the READY_WAIT pin is held Low by the device. After the required supply voltages (VDD and VDDQ) have reached X-Ref Target - Figure 17 their respective POR thresholds, the READY_WAIT pin is released after a minimum time of tRWL, to give the power supplies an additional margin for them to stabilize before initiating the configuration. For systems using a slow-rising power supply, an additional power-monitoring circuit can be used to delay the release of the READY_WAIT pin. If the power drops below the power-down threshold (VDDPD), the device is reset and the READY_WAIT pin is held Low again until the POR threshold is reached (see Figure 18 for an illustration). The power-up sequences with and without free-running clock are represented in Figure 11, page 31 and Figure 17. VDD/VDDQ TVHRWZ READY_WAIT TRWRT G L TAVKH3 TKH3AX 2 3 4 Latency Cycles (default = 7) K A22-A0 DQ15-DQ0 Notes: 1. W is tied High. 1 Address not Valid Valid Address TKHQV FFFFh (Sync + Dummy Cycle) D0 D1 D2 D3 D4 D5 DS617_13_053008 Figure 17: Power-Up Sequence (System with Free-Running Clock) DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 37 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 18 TVDDPOR(MAX) TVDDPOR(MIN) VDD Ram p Recommended Operating Voltage Range am p VDDPOR VDDPD 200 s Delay FPGA Configuration(1) 50 R ms TVHRWZ TVHRWZ TRST Time DS617_14_101608 Notes: 1. 2. A slow-ramping VDD power supply can still be below the minimum operating voltage when the READY_WAIT pin is released. In this case, the configuration sequence must be delayed until both VDD and VDDQ have reached their recommended operating conditions. For FPGA configuration via Master-BPI mode, the supplies VDD and VDDQ must reach their respective recommended operating conditions before the start of the FPGA configuration procedure. Figure 18: VDD Behavior During the Power-Up Sequence or Brownout DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 38 R Platform Flash XL High-Density Configuration and Storage Device First Address Latching Sequence The first address latching sequence (FALS) is one of the key features of Platform Flash XL. This particular sequence, shown in Figure 19, page 41 and Figure 21, page 43, allows the device to latch the first address soon after VIH is detected on the READY_WAIT pin. FALS requires four clock cycles. The device internally latches the address from which the system must start to read on the third detected positive edge of the clock after READY_WAIT goes High. In the case of a system with a free-running clock, FALS takes place in the same way, but it is strongly recommended (see Note 3) to use the timings represented in Figure 12, page 31, Figure 14, page 32, Figure 16, page 33 and Figure 17, page 39. To start the sequence, the following conditions must be met at the same time: * L must be tied High. X-Ref Target - Figure 19 * * RP must be tied High. G must be held Low (see Note 2). FALS is always reset when READY_WAIT is asserted Low, and CR4 is set to 1. The major advantage of this feature is that it allows the system to start reading data from any available main memory address in the device. If the system cannot guarantee any of the timings, the data output from the device is not guaranteed. Notes: 1. 2. If VDDQ drops, the output is no longer guaranteed, and it is necessary to reset the device by performing an external reset. Only on power-on-reset, FALS is initiated by READY_WAIT rising (Low-to-High) edge or G falling (High-to-Low) edge, whichever occurs last. After POR, FALS is initiated only by a READY_WAIT rising edge. Due to the internal threshold of the READY_WAIT signal, the system might not exactly determine which of the clock edges are the right ones to perform the sequence in the right way. 3. VDD/VDDQ READY_WAIT G High First Address Latching Sequence RP E L Low TRWHKH K TRWHKL 1 2 3 4 TAVKH3 First Address TKH3AX A22-A0 Address not Valid DQ15-DQ0 FFFFh (Sync + Dummy Cycle) DS617_15_102308 Notes: 1. W is tied High. Figure 19: First Address Latching Sequence (FALS) Clock is not Free Running and G is Held Low DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 39 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 20 VDD/VDDQ READY_WAIT G High First Address Latching Sequence RP E L Low TGLKH K TGLKL 1 2 3 4 TAVKH3 First Address TKH3AX A22-A0 Address not Valid DQ15-DQ0 Notes: 1. FFFFh (Sync + Dummy Cycle) DS617_52_102308 Only on power-on-reset, FALS is initiated by READY_WAIT rising (Low-to-High) edge or G falling (High-to-Low) edge, whichever occurs last. After POR, FALS is initiated only by a READY_WAIT rising edge. Figure 20: First Address Latching Sequence (FALS) Clock is not Free Running and G Transitions High-to-Low after READY_WAIT Goes High Table 19: FALS Sequence Timings When the Clock Is Not Free Running Voltage Range Symbol TAVKH3 TKH3AX TRWHKL TRWHKH TGLKL TGLKH Parameter Address setup on third positive edge of clock Address hold on third positive edge of clock Clock Low after READY_WAIT High Clock High after READY_WAIT High Clock Low after G Low Clock High after G Low Min Min Min Min Min Min VDDQ = 2.3V to 2.7V 9 9 600 600 600 600 VDDQ = 3.0V to 3.6V 9 9 600 600 600 600 Unit ns ns ns ns ns ns DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 40 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 21 VDD/VDDQ READY_WAIT TGLRWH TRWHAX G High RP E Low L K TAVRWH 1 2 3 4 A22-A0 First Address DQ15-DQ0 FFFFh (Sync + Dummy Cycle) DS617_16_081309 Figure 21: First Address Latching Sequence (FALS): Clock is Free Running Table 20: FALS Sequence Timings with Free-Running Clock Voltage Range Symbol TAVRWH TGLRWH TRWHAX Notes: 1. 4tK = Fourth rising edge of clock (K) after READY_WAIT goes High. Parameter Address Valid before READY_WAIT High Output Enable Low before READY_WAIT High Address Hold time after READY_WAIT High Min Min Min VDDQ = 2.3V to 2.7V 200 200 4tK + 200(1) VDDQ = 3.0V to 3.6V 200 200 4tK + 200(1) Unit s s s DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 41 R Platform Flash XL High-Density Configuration and Storage Device Program and Erase Times and Endurance Cycles Table 21 lists both program and erase times plus the number of program/erase cycles per block. Exact erase times can vary depending on the memory array condition. The best case is when all the bits in the block are at `0' (pre-programmed). The worst case is when all the bits in the block are at `1' (not preprogrammed). Usually, the system overhead is negligible with respect to the erase time. The maximum number of program/erase cycles depends on the VPP voltage supply used. Table 21: Program/Erase Times and Endurance Cycles(1,2) Parameter Erase Condition Parameter Block (16 Kword) Preprogrammed Main Block (64 Kword) Not Preprogrammed Word Program Single Word Buffer Program Buffer (32 words) (Buffer Program) Main Block (64 Kword) Program Erase Main Blocks Parameter Blocks Parameter Block (16 Kword) Main Block (64 Kword) Word Program Single Word Buffer Enhanced Factory Program(4) Buffer Program Buffer (32 words) Buffer Enhanced Factory Program Buffer Program Main Block (64 Buffer Enhanced Kwords) Factory Program Buffer Program Bank (8 Mbits) Buffer Enhanced Factory Program Main Blocks Parameter Blocks Main Blocks Parameter Blocks Min - - - - - - - - - 10,000 10,000 - - - - - - - - - - - - - - Typ 0.4 1.2 1.5 12 12 384 768 5 5 - - 0.4 1 10 2.5 80 80 160 160 1.28 1.28 - - 16 4 Program(3) Suspend Latency Program/Erase Cycles (per Block) Erase Typical after 10k P/E Cycles 1 3 - - - - - - - - - - - - - - - - - - - - - - - Max 2.5 4 4 180 180 - - 10 25 - - 2.5 4 170 - - - - - - - 1000 2500 - - Unit s s s s s s ms s s cycles cycles s s s s s s ms ms s s cycles cycles ms ms VPP = VPPH VPP = VDDQ Program(3) Program/Erase Cycles (per Block) Blank Check Notes: 1. 2. 3. 4. TA = -25C to 85 C; VDD = 1.7V to 2V; VDDQ = 2.3V to 2.7V or 3.0V to 3.6V. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). Excludes the time needed to execute the command sequence. This is an average value on the entire device. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 42 R Platform Flash XL High-Density Configuration and Storage Device Maximum Rating Stressing the device above the rating listed in Table 22 might cause permanent damage to the device. These are stress ratings only, and proper operation of the device at these or any other conditions above those indicated in this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods can affect device reliability. Table 22: Absolute Maximum Ratings Symbol TA TBIAS TJ TSTG VIO VDD VDDQ VPP IO TVPPH Ambient operating temperature Temperature under bias Junction temperature Storage temperature Input or output voltage Supply voltage Input/output supply voltage Program voltage Output short circuit current Time for VPP at VPPH Parameter Value Min -40 -40 - -65 -0.5 -0.2 -0.2 -0.2 - - Max 85 85 125 125 4.2 2.5 3.8 10 100 100 Unit C C C C V V V V mA hours DC and AC Parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the measurement conditions summarized in Table 23. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 23: Operating and AC Measurement Conditions Parameter VDD supply voltage VDDQ supply voltage VPP supply voltage (Factory environment) VPP supply voltage (Application environment) Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing reference voltages - 0 to VDDQ VDDQ/2 Min 1.7 3.0 2.3 8.5 -0.4 -40 30 Max 2.0 3.6 2.7 9.5 VDDQ+0.4 85 Units V V V V V C pF 5 ns V V DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 43 R Platform Flash XL High-Density Configuration and Storage Device Table 24: Quality and Reliability Characteristics Symbol TDR NPE VESD Notes: 1. Program/erase cycles when VPP = VDDQ. See Table 21, page 44 for program/erase cycles when VPP = VPPH. Description Data retention Program/erase cycles (Endurance) Electrostatic Discharge (ESD) Min 20 10,000(1) 2,000 Max - - - Units Years Cycles Volts X-Ref Target - Figure 22 VDDQ VDDQ 2 0V DS617_17_032708 Figure 22: AC Measurement I/O Waveform X-Ref Target - Figure 23 VDDQ VDD VDDQ 22 k Device Under Test 22 k 0.1 F 0.1 F CL (1) DS617_18_101608 Notes: 1. CL includes JIG capacitance. Figure 23: AC Measurement Load Circuit X-Ref Target - Figure 24 VDDQ VDD VDDQ 4.7 k Device Under Test READY_WAIT 0.1 F 0.1 F CL(1) DS617_19_101608 Notes: 1. CL includes JIG capacitance. Figure 24: Connecting the READY_WAIT Pin when Using the Device DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 44 R Platform Flash XL High-Density Configuration and Storage Device Table 25: Capacitance(1) Symbol CIN COUT Notes: 1. Sampled only, not 100% tested. Parameter Input capacitance Output capacitance Test condition VIN = 0V VOUT = 0V Min 6 8 Max 8 12 Unit pF pF Table 26: DC Characteristics: Currents Symbol ILI ILO Parameter Input leakage current Output leakage current Supply current asynchronous read (F = 5 MHz) Test Condition 0V = VIN = VDDQ 0V = VOUT = VDDQ E = VIL, G = VIH 4 word Typ - - 14 13 15 17 21 16 19 22 23 25 25 25 8 10 8 10 24 Max 1 1 16 17 19 21 26 19 23 26 28 75 75 75 20 25 20 25 41 Unit A A mA mA mA mA mA mA mA mA mA A A A mA mA mA mA mA Supply current synchronous read (F = 40 MHz) IDD1 8 word 16 word Continuous 4 word Supply current synchronous read (F = 54 MHz) 8 word 16 word Continuous IDD2 IDD3 IDD4 Supply current (reset) Supply current (standby) Supply current (automatic standby) Supply current (program) RP = VSS 0.2V E = VDDQ 0.2V K=VSS E = VIL, G = VIH VPP = VPPH VPP = VDDQ VPP = VPPH VPP = VDDQ Program/Erase in one Bank, Asynchronous Read in another Bank IDD5(1) Supply current (erase) IDD6(1),(2) Supply current (dual operations) Program/Erase in one Bank, Synchronous Read (Continuous f = 54 MHz) in another Bank E = VDDQ 0.2V K=VSS VPP = VPPH VPP = VDDQ VPP = VPPH VPP = VDDQ VPP = VDDQ VPP = VDDQ 33 53 mA IDD7(1) Supply current program/erase suspended (standby) VPP supply current (program) 25 2 0.2 2 0.2 0.2 0.2 75 5 5 5 5 5 5 A mA A mA A A A IPP1(1) VPP supply current (erase) IPP2 IPP3 Notes: 1. 2. Sampled only, not 100% tested. VDD dual operation current is the sum of read and program or erase currents. (1) VPP supply current (read) VPP supply current (standby) DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 45 R Platform Flash XL High-Density Configuration and Storage Device Table 27: DC Characteristics: Voltages Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VDDPD VDDPOR VDQPOR X-Ref Target - Figure 25 Parameter Input Low voltage Input High voltage Output Low voltage Output High voltage VPP program voltage-logic VPP program voltage factory Program or erase lockout VDD power-down threshold VDD power-on reset threshold VDDQ power-on reset threshold Test condition - - IOL = 100 A IOH = -100 A Program, Erase Program, Erase - - - - Min 0 VDDQ -0.4 - VDDQ -0.1 VDDQ -0.4 8.5 - - - - Typ - - - - - 9.0 - - - - Max 0.4 VDDQ + 0.4 0.1 - VDDQ +0.4 9.5 0.4 1.5 1.6 1.6 Unit V V V V V V V V V V TAVAV A22-A0 TAVLH VALID TLHAX TAVQV TAXQX VALID L(2) TLLLH TLLQV TELLH E TELQV TELQX TEHQZ TEHQX G TGLQV TGLQX TGHQX TGHQZ VALID TGLTV TELTV TGHTZ TEHTZ DQ15-DQ0 Hi-Z READY_WAIT(1) Notes: 1. 2. Hi-Z DS617_20_101608 Write Enable, W, is High, READY_WAIT is active Low. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported. Figure 25: Asynchronous Random Access Read AC Waveforms, CR4 = 0 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 46 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 26 A22-A3 TAVAV VALID ADDRESS A2-A0 L VALID ADDRESS TAVLH TLHAX VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. TLLLH TLLQV TELLH E TELQV TELQX G TGLTV TELTV READY_WAIT(1) Hi-Z TGLQV TGLQX TAVQV1 VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA DQ15-DQ0 Valid Address Latch Outputs Enabled Valid Data Standby DS617_21_053008 Notes: 1. 2. READY_WAIT is active Low. Write Enable (W) is High. Figure 26: Asynchronous Page Read AC Waveforms, CR4 = 0 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 47 R Platform Flash XL High-Density Configuration and Storage Device Table 28: Asynchronous Read AC Characteristics Voltage Range Symbol Alt TAVAV TAVQV TAVQV1 TAXQX(1) TELTV TELQV(2) TCE TLZ TOH THZ TOE TOLZ TOH TDF TAVADVH TELADVH TADVHAX TADVLADVH TADVLQV TRC TACC TPAGE TOH Parameter Address valid to next address valid Address valid to output valid (random) Address valid to output valid (page) Address transition to output transition Chip enable Low to wait valid Chip enable Low to output valid Chip enable Low to output transition Chip enable High to wait Hi-Z Chip enable High to output transition Chip enable High to output Hi-Z Output enable Low to output valid Output enable Low to output transition Output enable Low to wait valid Output enable High to output transition Output enable High to output Hi-Z Output enable High to wait Hi-Z Address valid to latch enable High Chip enable Low to latch enable High Latch enable High to address transition Latch enable pulse width Latch enable Low to output valid (random) Min Max Max Min Max Max Min Max Min Max Max Min Max Min Max Max Min Min Min Min Max VDDQ = 2.3V to 2.7V 85 85 30 0 17 85 0 17 0 17 25 0 17 0 17 17 10 10 9 10 85 VDDQ = 3.0V to 3.6V 85 85 30 0 17 85 0 17 0 17 25 0 17 0 17 17 10 10 9 10 85 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Read Timings TELQX(1) TEHTZ TEHQX(1) TEHQZ(1) TGLQV(2) TGLQX(1) TGLTV TGHQX(1) TGHQZ(1) TGHTZ TAVLH TELLH TLHAX TLLLH TLLQV Notes: 1. 2. Sampled only, not 100% tested. G may be delayed by up to TELQV - TGLQV after the falling edge of E without increasing tELQV. DS617 (v3.0.1) January 07, 2010 Product Specification Latch Timings www.xilinx.com 48 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 27 DQ15-DQ0 Hi-Z A22-A0 VALID ADDRESS TAVLH TLLLH VALID VALID VALID NOT VALID VALID L TLLKH TAVKH TKHQV Note 1 TEHQX TKHQX TEHQZ K(4) TELKH TKHAX TEHEL E TGHQX TGLQX TGHQZ G High TGLTV W TELTV TKHTV Note 2 Address Latch X Latency Valid Data Flow TKHTX Note 2 Note 2 Boundary Crossing Valid Data Standby DS617_22_053008 TEHTZ READY_WAIT Hi-Z Notes: 1. 2. 3. 4. 5. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register. The READY_WAIT signal can be configured to be active during wait state or one cycle before. READY_WAIT signal is active Low. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one. The minimum system clock period is TKHQV plus the FPGA data setup time. Figure 27: Synchronous Burst Read AC Waveforms, CR4 = 0 X-Ref Target - Figure 28 TKHKL TKHKH TF TR TKLKH DS617_25_032708 Figure 28: Clock Input AC Waveform DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 49 R Platform Flash XL High-Density Configuration and Storage Device Table 29: Synchronous Read AC Characteristics(1,2) Voltage Range Symbol TAVKH TELKH Alt TAVCLKH TELCLKH Parameter Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Low to Wait Valid Chip Enable pulse width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z Min Min Max Min Max Min Max VDDQ = 2.3V to 2.7V 9 9 17 20 17 10 16 VDDQ = 3.0V to 3.6V 9 9 17 20 17 10 16 Units ns ns ns ns ns ns ns Synchronous Read Timings TELTV(3) TEHEL TEHTZ(3) TKHAX TKHQV(4) TKHTV(3) TKHQX TKHTX(3) TLLKH TCLKHAX TCLKHQV TCLKHQX Clock High to Address Transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output Transition Clock High to WAIT Transition Clock Period (f = 54 MHz)(4) Clock High to Clock Low Clock Low to Clock High Min Min Min Min 2 9 19 6 2 9 19 6 ns ns ns ns TADVLCLKH Latch Enable Low to Clock High TCLK Clock Specifications TKHKH(4) TKHKL TKLKH TF TR Clock Fall or Rise Time Max 2 2 ns Notes: 1. 2. 3. 4. Sampled only, not 100% tested. For other timings, refer to Table 28, page 50. Parameter applies when READY_WAIT is configured (CR4) with the output WAIT function. The minimum system clock period is TKHQV + FPGA data-to-CCLK setup time. See the FPGA data sheet for FPGA setup time. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 50 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 29 A22-A0 VALID ADDRESS TAVKH L TLLKH K(2) TELKH TELQV TKHQV E TGLQV TGLQX G High TELQX TGHTZ W DQ15-DQ0 Hi-Z VALID TGLTV TKHTV READY_WAIT(1,2) Hi-Z DS617_23_101608 Notes: 1. 2. 3. The READY_WAIT signal is configured to be active during wait state. READY_WAIT signal is active Low. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one. The number of clock pulses in the dashed area depends on the latency (default latency = 7). The first clock that occurs while L is Low, latches the address. Figure 29: Single Synchronous Read AC Waveforms, CR4 = 0 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 51 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 30 DQ15-DQ0 A22-A0 Hi-Z VALID VALID VALID VALID VALID ADDRESS TAVLH TLLLH L TLLKH TAVKH TKHQV Note 1 TELKH TKHAX Note 3 TEHEL TEHQX TEHQZ K(4) E TGLQX TGLQV TGHQZ TGHQX G TGLTV TELTV TGHTZ TEHTZ READY_WAIT(2,5) W Notes: 1. 2. 3. 4. 5. Hi-Z High DS617_24_053008 The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. The READY_ WAIT signal is configured to be active during wait state. READY_ WAIT signal is active Low. The CLOCK signal can be held High or Low. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one. From the moment data is valid, soon after G becomes asserted, the READY_WAIT signal reverts its previous level. Figure 30: Synchronous Burst Read Suspend AC Waveforms, CR4 = 0 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 52 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 31 PROGRAM OR ERASE TAVAV A22-A0 TAVLH BANK ADDRESS TLHAX TLLLH VALID ADDRESS TAVWH TWHAX TWHAV VALID ADDRESS L TELLH TWHLL E TELWL TWHEH G TGHWL TWHWL TWHGL W TWLWH TDVWH TWHDX COMMAND CMD or DATA TWHWPL TWPHWH TQVWPL STATUS REGISTER TWHEL TELQV DQ15-DQ0 WP TWHVPL TVPHWH TQVVPL VPP TELKV K SET-UP COMMAND CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING DS617_26_053008 Figure 31: Write AC Waveforms, Write Enable Controlled DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 53 R Platform Flash XL High-Density Configuration and Storage Device Table 30: Write AC Characteristics, Write Enable Controlled(1) Symbol TAVAV TAVLH TAVWH(2) TDVWH TELLH TELWL TELQV TELKV TGHWL TLHAX TLLLH TWHAV(2) TWHAX(2) TWHDX TWHEH TWHEL(3) TWHGL TWHLL(3) TWHWL TWLWH TQVVPL TQVWPL TVPHWH TWHVPL TWHWPL TWPHWH Alt Parameter Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Protection Timings TWC Address Valid to Next Address Valid Address Valid to Latch Enable High Address Valid to Write Enable High TDS Data Valid to Write Enable High Chip Enable Low to Latch Enable High TCS Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Chip Enable Low to Clock Valid Output Enable High to Write Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Address Valid TAH Write Enable High to Address Transition TDH Write Enable High to Input Transition TCH Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low Write Enable High to Latch Enable Low TWPH Write Enable High to Write Enable Low TWP Write Enable Low to Write Enable High Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low TVPS VPP High to Write Enable High Write Enable High to VPP Low Write Enable High to Write Protect Low Write Protect High to Write Enable High Voltage Range VDDQ = VDDQ = 2.3V to 2.7V 3.0V to 3.6V 85 85 10 10 50 50 50 50 10 10 0 0 85 85 9 9 17 17 9 9 10 10 0 0 0 0 0 0 0 0 25 25 0 0 25 25 25 25 50 50 0 0 0 0 200 200 200 200 200 200 200 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. 2. 3. Sampled only, not 100% tested. Meaningful only if L is always kept Low. TWHEL and TWHLL have this value when reading in the targeted bank or when reading following a Set Configuration Register command. System designers should take this timing into account and can insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register are issued, TWHEL and TWHLL are 0 ns. DS617 (v3.0.1) January 07, 2010 Product Specification Write Enable Controlled Timings www.xilinx.com 54 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 32 PROGRAM OR ERASE TAVAV A22-A0 TAVLH TLLLH L TELLH W TWLEL G TGHEL E TELEH TDVEH DQ15-DQ0 COMMAND TEHDX CMD or DATA TEHWPL TWPHEH WP TEHVPL TVPHEH VPP TELKV K SET-UP COMMAND CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING TQVVPL TQVWPL STATUS REGISTER TWHEL TELQV TEHEL TEHGL TEHWH BANK ADDRESS TLHAX VALID ADDRESS TAVEH TEHAX VALID ADDRESS DS17_27_053008 Figure 32: Write AC Waveforms, Chip Enable Controlled DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 55 R Platform Flash XL High-Density Configuration and Storage Device Table 31: Write AC Characteristics, Chip Enable Controlled(1) Symbol TAVAV TAVEH TAVLH TDVEH TEHAX TEHDX TEHEL TEHGL TEHWH TELKV TELEH TELLH TELQV TGHEL TLHAX TLLLH TWHEL(2) TWLEL TEHVPL TEHWPL TQVVPL TQVWPL TVPHEH TWPHEH Alt TWC Parameter Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Protection Timings Address Valid to Next Address Valid Address Valid to Chip Enable High Address Valid to Latch Enable High TDS Data Valid to Chip Enable High TAH Chip Enable High to Address Transition TDH Chip Enable High to Input Transition TCPH Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low TCH Chip Enable High to Write Enable High Chip Enable Low to Clock Valid TCP Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Output Enable High to Chip Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Chip Enable Low TCS Write Enable Low to Chip Enable Low Chip Enable High to VPP Low Chip Enable High to Write Protect Low Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low TVPS VPP High to Chip Enable High Write Protect High to Chip Enable High Voltage Range VDDQ = VDDQ = 2.3V to 2.7V 3.0V to 3.6V 85 85 50 50 10 10 50 50 0 0 0 0 25 25 0 0 0 0 9 9 50 50 10 10 85 85 17 17 9 9 10 10 25 25 0 0 200 200 200 200 0 0 0 0 200 200 200 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. 2. Sampled only, not 100% tested. TWHEL has this value when reading in the targeted bank or when reading following a Set Configuration Register command. System designers should take this timing into account and can insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register are issued, TWHEL is 0 ns. X-Ref Target - Figure 33 Chip Enable Controlled Timings W,E,G,L T T PHEL T PHGL T PHLL PHWL TPLWL T PLEL T PLGL T PLLL RP T VDHPH TPLPH VDD , VDDQ Power-Up Reset DS617_50_090108 Figure 33: Reset and Power-Up AC Waveforms DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 56 R Platform Flash XL High-Density Configuration and Storage Device Table 32: Reset and Power-Up AC Characteristics Symbol TPLWL TPLEL TPLGL TPLLL TPHWL TPHEL TPHGL TPHLL TPLPH(1),(2) TVDHPH Notes: 1. 2. A device reset is possible but not guaranteed if TPLPH < 50 ns. Sampled only, not 100% tested. Parameter Reset Low to: Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low Reset High to: Write Enable Low Chip Enable Low Output Enable Low Latch Enable Low RP Pulse Width Supply Voltages High to Reset High Test Condition During Program During Erase Other Conditions Min 60 60 60 Unit s s s - 60 s - - 50 0 ns s X-Ref Target - Figure 34 High W, G, L E Low VDD, VDDQ TVDHPT TPLPH RP TRWRT TRWL TPHRWZ TRWLRWH READY_WAIT TPLRWL Power-Up Reset TRWRT TRWRT READY_WAIT (pulse) DS617_29_090108 Notes: 1. READY_WAIT requires an external pull-up resistor to VDDQ sufficiently strong to ensure a clean Low-to-High transition within less than TRWRT when the READY_WAIT pin is released to a high-impedance state. Figure 34: READY_WAIT AC Waveform DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 57 R Platform Flash XL High-Density Configuration and Storage Device Table 33: Power-Up Timing Characteristics Symbol TRWL(1) TRWLRWH TRWRT(2) TPHRWZ TPLRWL TRST TVDDPOR TVDQHPOR TVHRWZ Notes: 1. 2. Depends on the VDD/VDDQ operating conditions. READY_WAIT requires an external pull-up resistor to VDDQ sufficiently strong to ensure a clean Low-to-High transition within less than TRWRT when the READY_WAIT pin is released to a high-impedance state. Parameter READY_WAIT Low driven from the device READY_WAIT pulse driven from the system READY_WAIT rise time Time from RP High to when device releases READY_WAIT to highimpedance state Reset Low to READY_WAIT Low Time required to trigger a device reset when VDD drops below the maximum VDDPD threshold VDD ramp rate VDDQ ramp rate Time from VDD/VDDQ POR thresholds to when device releases READY_WAIT to high-impedance state VDDQ = 2.3V to 2.7V Min 60 50 - - - 5 0.2 0.2 5 VDDQ = 3.0V to 3.6V Min 60 50 - - - 5 0.2 0.2 5 Unit s ns s s ns ms ms ms ms Max - - 1 200 50 15 50 50 15 Max - - 1 200 50 15 50 50 15 Ordering Information X-Ref Target - Figure 35 Example: XCF128X FTG64 C Device Type Package Type FT64 = 64-ball, Fine-Pitch Thin Ball Grid Array FTG64 = 64-ball, Fine-Pitch Thin Ball Grid Array, Pb-free Notes: 1. See the FT64/FTG64 package specifications at http://www.xilinx.com/support/documentation/package_specifications.htm. DS617_11_050808 Operating Range C = Industrial (TA = -40C to +85C) Figure 35: Ordering Information Valid Ordering Combinations Table 34: Valid Ordering Combinations XCF128XFTG64C XCF128XFT64C DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 58 R Platform Flash XL High-Density Configuration and Storage Device Marking Information X-Ref Target - Figure 36 Device Type Xilinx Logo XCF128XFTG64C XXX Fab Code Country of Origin and Traceability Code XXXXX XX XXX XX YWW Lot Codes Date Code (Year/Work-Week) FT64 Ball A1 Figure 36: Marking Information DS617_12_0509508 Appendix A: Block Address Tables Table 35: Boot Block Addresses Bank(1) # 0 1 2 3 4 Size (Kword) 16 16 16 16 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF 7D0000-7DFFFF 7C0000-7CFFFF 7B0000-7BFFFF 7A0000-7AFFFF 790000-79FFFF 780000-78FFFF 770000-77FFFF 760000-76FFFF 750000-75FFFF 740000-74FFFF 730000-73FFFF 720000-72FFFF 710000-71FFFF 700000-70FFFF Parameter Bank 5 6 7 8 9 10 11 12 13 Bank 1 14 15 16 17 18 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 59 R Platform Flash XL High-Density Configuration and Storage Device Table 35: Boot Block Addresses (Cont'd) Bank(1) # 19 20 21 Size (Kword) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 6F0000-6FFFFF 6E0000-6EFFFF 6D0000-6DFFFF 6C0000-6CFFFF 6B0000-6BFFFF 6A0000-6AFFFF 690000-69FFFF 680000-68FFFF 670000-67FFFF 660000-66FFFF 650000-65FFFF 640000-64FFFF 630000-63FFFF 620000-62FFFF 610000-61FFFF 600000-60FFFF 5F0000-5FFFFF 5E0000-5EFFFF 5D0000-5DFFFF 5C0000-5CFFFF 5B0000-5BFFFF 5A0000-5AFFFF 590000-59FFFF 580000-58FFFF 570000-57FFFF 560000-56FFFF 550000-55FFFF 540000-54FFFF 530000-53FFFF 520000-52FFFF 510000-51FFFF 500000-50FFFF 4F0000-4FFFFF 4E0000-4EFFFF 4D0000-4DFFFF 4C0000-4CFFFF 4B0000-4BFFFF 4A0000-4AFFFF 490000-49FFFF 480000-48FFFF Bank 2 22 23 24 25 26 27 28 29 Bank 3 30 31 32 33 34 35 36 37 Bank 4 38 39 40 41 42 43 44 45 Bank 5 46 47 48 49 50 51 52 53 Bank 6 54 55 56 57 58 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 60 R Platform Flash XL High-Density Configuration and Storage Device Table 35: Boot Block Addresses (Cont'd) Bank(1) # 59 60 61 Size (Kword) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 470000-47FFFF 460000-46FFFF 450000-45FFFF 440000-44FFFF 430000-43FFFF 420000-42FFFF 410000-41FFFF 400000-40FFFF 3F0000-3FFFFF 3E0000-3EFFFF 3D0000-3DFFFF 3C0000-3CFFFF 3B0000-3BFFFF 3A0000-3AFFFF 390000-39FFFF 380000-38FFFF 370000-37FFFF 360000-36FFFF 350000-35FFFF 340000-34FFFF 330000-33FFFF 320000-32FFFF 310000-31FFFF 300000-30FFFF 2F0000-2FFFFF 2E0000-2EFFFF 2D0000-2DFFFF 2C0000-2CFFFF 2B0000-2BFFFF 2A0000-2AFFFF 290000-29FFFF 280000-28FFFF 270000-27FFFF 260000-26FFFF 250000-25FFFF 240000-24FFFF 230000-23FFFF 220000-22FFFF 210000-21FFFF 200000-20FFFF Bank 7 62 63 64 65 66 67 68 69 Bank 8 70 71 72 73 74 75 76 77 Bank 9 78 79 80 81 82 83 84 85 Bank 10 86 87 88 89 90 91 92 93 Bank 11 94 95 96 97 98 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 61 R Platform Flash XL High-Density Configuration and Storage Device Table 35: Boot Block Addresses (Cont'd) Bank(1) # 99 100 101 Size (Kword) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 1F0000-1FFFFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF 180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 100000-10FFFF 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 000000-00FFFF Bank 12 102 103 104 105 106 107 108 109 Bank 13 110 111 112 113 114 115 116 117 Bank 14 118 119 120 121 122 123 124 125 Bank 15 126 127 128 129 130 Notes: 1. There are two Bank Regions: Bank Region 1 contains all the banks made up of main blocks only; Bank Region 2 contains the banks made up of the parameter and main blocks (Parameter Bank). DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 62 R Platform Flash XL High-Density Configuration and Storage Device Appendix B: Common Flash Interface The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from flash memory devices. This interface allows system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling software to upgrade itself when necessary. When the Read CFI Query Command is issued, the device enters CFI Query mode and the data structure is read from Table 36: Query Structure Overview Offset 000h 010h 01Bh 027h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table the memory. Table 36, through and Table 45, page 70 show the addresses used to retrieve the data. The Query data is always presented on the lowest order data outputs (DQ7-DQ0), the other outputs (DQ15-DQ8) are set to `0'. The CFI data structure also contains a security area where a unique 64-bit security number is written (Figure 8, page 22). The security number cannot be changed and can only be accessed in Read mode. Read Array command is used to return to Read mode. Subsection Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Lock Protection Register Unique device Number and User Programmable OTP 080h Notes: 1. Security Code Area The flash memory displays the CFI data structure when CFI Query command is issued. This table lists the main sub-sections detailed in Table 38, page 66, and Table 41, page 68. Query data is always presented on the lowest order data outputs. Table 37: CFI Query Identification String Offset 000h 001h 002h-00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah Manufacturer code Device code Reserved Query Unique ASCII String "QRY" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 40, page 67) Alternate Vendor Command Set and Control Interface ID Code second vendor (specified algorithm supported) Address for Alternate Algorithm extended Query table Description Value 0049h 506Bh Reserved 0051h ("Q") 0052h ("R") 0059h ("Y") 0001h 0000h Offset = P = 000Ah 0001h 0000h 0000h Value = A = 0000h 0000h DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 63 R Platform Flash XL High-Density Configuration and Storage Device Table 38: CFI Query System Interface Information Offset 01Bh Data 0017h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical time-out per single byte/word program = 2n s Typical time-out for Buffer Program = 2n s 2n ms Value 1.7V 01Ch 0020h 2V 01Dh 0085h 8.5V 01Eh 01Fh 020h 021h 022h 023h 024h 025h 026h 0095h 0004h 0009h 000Ah 0000h 0004h 0004h 0002h 0000h 9.5V 16 s 512 s 1s - 256 s 8192 s 4s - Typical time-out per individual block erase = Typical time-out for full chip erase = 2n ms 2n Maximum time-out for word program = times typical times typical 2n times typical Maximum time-out for Buffer Program = 2n 2n Maximum time-out per individual block erase = Maximum time-out for chip erase = times typical Table 39: Device Geometry Definition Offset 027h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh 02Fh 030h 031h 032h 033h 034h 035h 038h Data 0018h 0001h 0001h 0006h 0000h 0002h 007Eh 0000h 0000h 0002h 0003h 0000h 0080h 0000h Reserved Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase Block Regions Erase Block Region 1 Information Number of identical-size erase blocks = 007Eh + 1 Erase Block Region 1 Information Block size in Region 1 = 0200h x 256 byte Erase Block Region 2 Information Number of identical-size erase blocks = 0003h + 1 Erase Block Region 2 Information Block size in Region 2 = 0080h x 256 byte Reserved for future erase block region information Value 16 Mbytes x16 Sync. 64 bytes 2 127 128 Kbyte 4 32 Kbyte - DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 64 R Platform Flash XL High-Density Configuration and Storage Device Table 40: Primary Algorithm-Specific Extended Query Table Offset (P)h = 10Ah (P+3)h = 10Dh (P+4)h = 10Eh Data 0050h 0052h 0049h 0031h 0033h Description Primary Algorithm extended Query table unique ASCII string "PRI" Value "P" R" "I" "1" "3" Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte: bit 0 Chip Erase supported (1 = Yes, 0 = No) bit 1 Erase Suspend supported (1 = Yes, 0 = No) bit 2 Program Suspend supported (1 = Yes, 0 = No) bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No) bit 4 Queued Erase supported (1 = Yes, 0 = No) \ bit 5 Instant individual block locking supported (1 = Yes, 0 = No) bit 6 Protection bits supported (1 = Yes, 0 = No) bit 7 Page mode read supported (1 = Yes, 0 = No) bit 8 Synchronous read supported (1 = Yes, 0 = No) bit 9 Simultaneous operation supported (1 = Yes, 0 = No) bit 10 to 31 Reserved; undefined bits are `0'. If bit 31 is `1' then another 31 bit field of optional features follows at the end of the bit-30 field. Supported Functions after Suspend Read Array, Read Status Register and CFI Query: bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are `0' Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented: bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2; Reserved for future use undefined bits are `0' VDD Logic Supply Optimum Program/Erase voltage (highest performance): bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Optimum Program/Erase voltage: bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV (P+5)h = 10Fh (P+7)h = 111h 00E6h 0003h 0000h (P+8)h = 112h 0000h No Yes Yes No No Yes Yes Yes Yes Yes (P+9)h = 113h 0001h Yes (P+A)h = 114h (P+B)h = 115h 0003h 0000h Yes Yes (P+C)h = 116h 0018h 1.8V (P+D)h = 117h 0090h 9V DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 65 R Platform Flash XL High-Density Configuration and Storage Device Table 41: Protection Register Information Offset (P+E)h = 118h (P+F)h = 119h (P+10)h = 11Ah (P+ 11)h = 11Bh (P+12)h = 11Ch (P+13)h = 11Dh (P+14)h = 11Eh (P+15)h = 11Fh (P+16)h = 120h (P+17)h = 121h (P+18)h = 122h (P+19)h = 123h (P+1A)h = 124h (P+1B)h = 125h (P+1C)h = 126h Data 0002h 0080h 0000h 0003h 0003h 0089h 0000h 0000h 0000h 0000h 0000h 0000h 0010h 0000h 0004h Description Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Protection Register 1: Protection Description: Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address Bits 16-23 2n bytes in factory pre-programmed region Bits 24-31 2n bytes in user programmable region Value 2 80h 00h 8 bytes 8 bytes 89h 00h Protection Register 2: Protection Description: Bits 0-31 protection register address Bits 32-39 n number of factory programmed regions (lower byte) Bits 40-47 n number of factory programmed regions (upper byte) Bits 48-55 2n bytes in factory programmable region Bits 56-63 n number of user programmable regions (lower byte) Bits 64-71 n number of user programmable regions (upper byte) Bits 72-79 2n bytes in user programmable region 00h 00h 0 0 0 16 0 16 Table 42: Burst Read Information Offset Data Description Page-mode read capability bits 0-7 n' such that 2n HEX value represents the number of read-page bytes. See offset 0028h for device word width to determine page-mode data output width. Number of synchronous mode read configuration fields that follow. Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 0028h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4 Value (P+1D)h = 127h 0003h 8 bytes (P+1E)h = 128h 0004h 4 (P+1F)h = 129h 0001h 4 (P+20)h = 12Ah (P-21)h = 12Bh (P+22)h = 12Ch 0002h 0003h 0007h 8 16 Cont. Table 43: Bank and Erase Block Region Information(1,2) Offset (P+23)h = 12Dh Notes: 1. 2. The variable P is a pointer which is defined at CFI offset 015h. Bank Regions. There are two Bank Regions, see Table 35, page 61. Data 02h Description Number of Bank Regions within the device DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 66 R Platform Flash XL High-Density Configuration and Storage Device Table 44: Bank and Erase Block Region 1 Information(1,2) Offset (P+24)h = 12Eh (P+25)h = 12Fh (P+26)h = 130h Data 0Fh 00h 11h Description Number of identical banks within Bank Region 1 Number of program or erase operations allowed in Bank Region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in Bank Region 1 n = number of erase block regions with contiguous same-sized erase blocks. Symmetrically blocked banks have one blocking region(2). Bank Region 1 Erase Block Type 1 Information: Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 1 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 1 (Erase Block Type 1): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 1 (Erase Block Type 2) Minimum block erase cycles x 1000 (P+27)h = 131h 00h (P+28)h = 132h 00h (P+29)h = 133h (P+2A)h = 134h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h (P+2E)h = 138h (P+2F)h = 139h 01h 07h 00h 00h 02h 64h 00h (P+30)h = 13Ah 01h (P+31)h = 13Bh 03h - - Bank Regions 1 (Erase Block Type 2): Bits per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" Bits 5-7: reserved Bank Region 1 (Erase Block Type 2): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Notes: 1. 2. The variable P is a pointer which is defined at CFI offset 015h. Bank Regions. There are two Bank Regions, see Table 35, page 61. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 67 R Platform Flash XL High-Density Configuration and Storage Device Table 45: Bank and Erase Block Region 2 Information(1,2) Offset (P+32)h = 13Ch (P+33)h = 13Dh (P+34)h = 13Eh Data 01h 00h 11h Description Number of identical banks within Bank Region 2 Number of program or erase operations allowed in Bank Region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in Bank Region 2 n = number of erase block regions with contiguous same-sized erase blocks. Symmetrically blocked banks have one blocking region.(2) Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 2 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 1): Bits per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" Bits 5-7: reserved Bank Region 2 (Erase Block Type 1):Page mode and Synchronous mode capabilities (defined in Table 42, page 68) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 2 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 2): Bits per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" Bits 5-7: reserved Bank Region 2 (Erase Block Type 2): Page mode and Synchronous mode capabilities (defined in Table 42, page 68) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Feature Space definitions Reserved (P+35)h = 13Fh 00h (P+36)h = 140h 00h (P+37)h = 141h (P+38)h = 142h (P+39)h = 143h (P+3A)h = 144h (P+3B)h = 145h (P+3C)h = 146h (P+3D)h = 147h (P+3E)h = 148h 02h 06h 00h 00h 02h 64h 00h 01h (P+3F)h = 149h 03h (P+40)h = 14Ah (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh (P+44)h = 14Eh (P+45)h = 14Fh (P+46)h = 150h 03h 00h 80h 00h 64h 00h 01h (P+47)h = 151h 03h (P+48)h = 152h (P+49)h = 153h Notes: 1. 2. - - The variable P is a pointer which is defined at CFI offset 015h. Bank Regions. There are two Bank Regions, see Table 35, page 61. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 68 R Platform Flash XL High-Density Configuration and Storage Device Appendix C: Flowcharts and Pseudocodes X-Ref Target - Figure 37 Start program_command (addressToProgram, dataToProgram) {: Write 40h or 10h(3) writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram); "see note (3)"; /* E or G must be toggled*/ NO } YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End } DS617_31_101608 Write Address & Data Read Status Register(3) SR7 = 1 while (status_register.SR7== 0) ; NO VPP Invalid Error(1,2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error(1,2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error(1,2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; Notes: 1. 2. 3. 4. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. Any address within the bank can equally be used. To read the memory in Asynchronous mode, the CR15 Configuration Register bit must be written to 1. Figure 37: Program Flowchart and Pseudocode DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 69 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 38 Start blank_check_command (blockToCheck) { Write Block Address & BCh writeToFlash (blockToCheck, 0xBC); Write Block Address & CBh writeToFlash (blockToCheck, 0xCB); /* Memory enters read status state after the Blank Check Command */ Read Status Register(1) do { status_register = readFlash (blockToCheck); /* see note (1) */ /* E or G must be toggled */ } while (status_register.SR7==0); SR7 = 1 YES SR4 = 1 SR5 = 1 NO YES Command Sequence Error(2) if (status_register.SR4==1) && (status_register.SR5==1) /* command sequence error */ error_handler () ; SR5 = 0 NO Blank Check Error(2) if (status_register.SR5==1) /* Blank Check error */ error_handler () ; End } DS617_32_101608 Notes: 1. 2. 3. Any address within the bank can equally be used. If an error is found, the Status Register must be cleared before further Program/Erase operations. To read the memory in Asynchronous mode, the CR15 Configuration Register bit must be written to 1. Figure 38: Blank Check Flowchart and Pseudocode DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 70 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 39 Start Buffer Program E8h Command, Start Address Read Status Register Buffer_Program_command (Start_Address, n, buffer_Program[] ) /* buffer_Program [] is an array structure used to store the address and data to be programmed to the Flash memory (the address must be within the segment Start Address and Start Address+n) */ { do {writeToFlash (Start_Address, 0xE8) ; status_register=readFlash (Start_Address); SR7 = 1 YES Write n(1), Start Address NO } while (status_register.SR7==0); writeToFlash (Start_Address, n); Write Buffer Data, Start Address writeToFlash (buffer_Program[0].address, buffer_Program[0].data); /*buffer_Program[0].address is the start address*/ X=0 x = 0; X=n YES while (x { writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data); x++; X=X+1 } Program Buffer to Flash Confirm D0h writeToFlash (Start_Address, 0xD0); Read Status Register do {status_register=readFlash (Start_Address); SR7 = 1 YES Full Status Register Check(3) NO } while (status_register.SR7==0); full_status_register_check(); } End DS617_33_101608 Notes: 1. 2. 3. 4. n + 1 is the number of data being programmed. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to buffer_Program[].address Routine for Error Check by reading SR3, SR4 and SR1. To read the memory in Asynchronous mode, the CR15 Configuration Register bit must be written to 1. Figure 39: Buffer Program Flowchart and Pseudocode DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 71 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 40 Start Write B0h program_suspend_command () { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ Read Status Register SR7 = 1 YES SR2 = 1 NO } while (status_register.SR7== 0) ; NO Program Complete if Write FFh (status_register.SR2==0) { /*program completed */ writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ YES Write FFh Read Data } else { writeToFlash (bank_address, 0xFF) ; Read data from another address read_data ( ); /*read data from another address*/ Write D0h writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ Write 70h(1) } Program Continues with Bank in Read Status Register Mode } writeToFlash (bank_address, 0x70) ; /*read status register to check if program has completed */ DS617_34_101608 Notes: 1. 2. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command. To read the memory in Asynchronous mode, the CR15 Configuration Register bit must be written to 1. Figure 40: Program Suspend & Resume Flowchart and Pseudocode DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 72 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 41 Start Write 20h(2) erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; /*see note (2) */ writeToFlash (blockToErase, 0xD0) ; /* Memory enters read status state after the Erase Command */ Write Block Address & D0h Read Status Register(2) do { status_register=readFlash (blockToErase) ; /* see note (2) */ /* E or G must be toggled*/ SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } DS617_35_101608 NO VPP Invalid Error(1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; YES Command Sequence Error(1) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO Erase Error(1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; NO Erase to Protected Block Error(1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; Notes: 1. 2. 3. If an error is found, the Status Register must be cleared before further Program/Erase operations. Any address within the bank can equally be used. To read the memory in Asynchronous mode, the CR15 Configuration Register bit must be written to 1. Figure 41: Block Erase Flowchart and Pseudocode DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 73 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 42 Start Write B0h erase_suspend_command () { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ Write 70h Read Status Register do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ SR7 = 1 YES SR6 = 1 YES Write FFh NO } while (status_register.SR7== 0) ; NO Erase Complete if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ Read data from another block, Program, Set Configuration Register or Block Protect/Unprotect/Lock } else { writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ } } DS617_36_101608 Write D0h Write FFh Erase Continues Read Data Notes: 1. 2. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command. To read the memory in Asynchronous mode, the CR15 Configuration Register bit must be written to 1. Figure 42: Erase Suspend & Resume Flowchart and Pseudocode DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 74 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 43 Start Write 60h(1) locking_operation_command (address, lock_operation) { writeToFlash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (address, 0x90) ; /*see note (1) */ Write 01h, D0h or 2Fh Write 90h(1) Read Block Lock States if Locking change confirmed? YES Write FFh(1) } End NO (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/ writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ /*see note (1) */ DS617_37_101608 Notes: 1. 2. Any address within the bank can equally be used. To read the memory in Asynchronous mode, the CR15 Configuration Register bit must be written to 1. Figure 43: Locking Operation Flowchart and Pseudocode DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 75 R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 44 Start Write C0h(3) protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (3) */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram) ; /* see note (3) */ /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; Write Address & Data Read Status Register(3) SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End NO VPP Invalid Error(1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error(1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error(1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; } DS617_38_101608 Notes: 1. 2. 3. 4. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. Any address within the bank can equally be used. To read the memory in Asynchronous mode, the CR15 Configuration Register bit must be written to 1. Figure 44: Protection Register Program Flowchart and Pseudocode X-Ref Target - Figure 45 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 76 R Platform Flash XL High-Density Configuration and Storage Device Start Write 80h to Address WA1 SETUP PHASE Buffer_Enhanced_Factory_Program_Command (start_address, DataFlow[]) { writeToFlash (start_address, 0x80) ; Write D0h to Address WA1 writeToFlash (start_address, 0xD0) ; do { do { status_register = readFlash (start_address); Read Status Register NO SR7 = 0 YES NO SR4 = 1 Initialize count X=0 Write PDX Address WA1 PROGRAM AND VERIFY PHASE if (status_register.SR4==1) { /*error*/ if (status_register.SR3==1) error_handler ( ) ;/*VPP error */ if (status_register.SR1==1) error_handler ( ) ;/* Locked Block */ } while (status_register.SR7==1) x=0; /* initialize count */ do { writeToFlash (start_address, DataFlow[x]); Read Status Register SR3 and SR1for errors Exit Increment Count X=X+1 x++; NO X = 32 YES Read Status Register }while (x<32) do { status_register = readFlash (start_address); NO SR0 = 0 YES }while (status_register.SR0==1) NO Last data? YES Write FFFFh to Address = NOT WA1 } while (not last data) writeToFlash (another_block_address, FFFFh) EXIT PHASE Read Status Register do { status_register = readFlash (start_address) NO SR7 = 1 YES Full Status Register Check }while (status_register.SR7==0) full_status_register_check(); End } DS617_39_101608 Notes: 1. To read the memory in Asynchronous mode, the CR15 Configuration Register bit must be written to 1. Figure 45: Buffer Enhanced Factory Program Flowchart and Pseudocode DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 77 R Platform Flash XL High-Density Configuration and Storage Device Appendix D: Command Interface State Tables Table 46: Command Interface States - Modify Table, Next State(1) Command Input Buffer Program, Program/ Erase Suspend (B0h) Clear Status Register (5) (50h) Erase Confirm P/E Resume, Block Unlock Confirm, BEFP Confirm(3)(4) (D0h) Read Status Register (70h) Blank Check confirm (CBh) Buffer Program (3)(4) (E8h) Read Electronic Signature, Read CFI Query Blank Check Setup (BCh) Program Setup(3)(4 ) (10/40h) Block Erase, Setup(3)(4) (20h) Read Array(2) (FFh) BEFP Setup (80h) Current CI State Ready Ready Program Setup BP Setup Erase Setup BEFP Setup Blank Check setup Ready (unlock block) OTP Busy Ready Lock/CR Setup Setup OTP Busy IS in OTP busy Setup Busy IS in Program Busy Suspend IS in PS Setup Buffer Load 1 Buffer Load 2 Confirm Buffer Program Busy IS in BP Busy BP Suspend BP Busy PS IS in PS Program Busy OTP Busy Ready (Lock Error) Ready (Lock Error) IS in OTP Busy OTP busy IS in OTP Busy OTP Busy Program Busy OTP Busy IS in Program Busy Program Busy IS in Program Busy Program Busy Program Busy Prog. Susp. Program Busy Program PS IS in Program Suspend PS Program Busy Program Suspend Program Suspend Buffer Program Load 1 (give word count load (N-1)) if N=0 go to Buffer Program Confirm. Else (N. 0) go to Buffer Program Load 2 (data load) Buffer Program Confirm when count =0;Else Buffer Program Load 2(7) Ready (error) IS in BP Busy BP Busy BP Busy IS in BP Busy Buffer Program Busy BP Suspen d IS in BP Susp end BP Busy Ready (error) BP Buffer Program Susp. Busy Suspend IS in BP Suspend BP Suspend BP busy Buffer Program Suspend IS in BP Suspend Buffer Program Suspend DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 78 R Platform Flash XL High-Density Configuration and Storage Device Table 46: Command Interface States - Modify Table, Next State(1) (Cont'd) Command Input Buffer Program, Program/ Erase Suspend (B0h) Clear Status Register (5) (50h) Erase Confirm P/E Resume, Block Unlock Confirm, BEFP Confirm(3)(4) (D0h) Read Status Register (70h) Blank Check confirm (CBh) Buffer Program (3)(4) (E8h) Read Electronic Signature, Read CFI Query Blank Check Setup (BCh) Program Setup(3)(4 ) (10/40h) Block Erase, Setup(3)(4) (20h) Read Array(2) (FFh) Erase Busy BEFP Setup (80h) Current CI State Setup Ready (error) Busy IS in Erase Busy Suspend IS in ES Erase Suspend Program in ES BP in ES IS in Erase Suspend IS in Erase Busy Erase Busy IS in Erase Busy Erase Busy Erase Suspend Erase Busy Ready (error) Erase Busy Erase Erase Busy Erase Busy ES Erase Suspend Erase Suspend Setup Program Busy in Erase Suspend Program Busy in ES IS in Program Busy in ES Program Busy in ES IS in Program Busy in ES PS in ES Program Busy in Erase Suspend Busy Program Busy in ES Program in Erase Suspend IS in Program busy in ES Suspend PS in ES Suspend PS in ES in ES IS in PS in ES Setup Buffer Load 1 Buffer Load 2 Confirm BP Busy in ES IS in PS in ES PS in ES Program busy in Erase Suspend IS in Program Program Suspend in Erase Suspend Program Suspend in Erase Suspend Program Busy in ES Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N. 0) go to Buffer Program Load 2 Buffer Program Load 2 in Erase Suspend (data load) Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program will fail at this point if any block address is different from the first address) Erase Suspend (sequence error) IS in BP Busy in ES BP busy in ES IS in BP busy in ES BP Busy in ES BP Busy in ES Erase Suspend (sequence error) BP Susp. in ES Buffer Program Busy in ES Buffer Program in Erase Suspend Busy IS in BP busy in ES Buffer Program Busy in Erase Suspend DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 79 R Platform Flash XL High-Density Configuration and Storage Device Table 46: Command Interface States - Modify Table, Next State(1) (Cont'd) Command Input Buffer Program, Program/ Erase Suspend (B0h) Clear Status Register (5) (50h) Erase Confirm P/E Resume, Block Unlock Confirm, BEFP Confirm(3)(4) (D0h) Read Status Register (70h) Blank Check confirm (CBh) Buffer Program (3)(4) (E8h) Read Electronic Signature, Read CFI Query Blank Check Setup (BCh) Program Setup(3)(4 ) (10/40h) Block Erase, Setup(3)(4) (20h) Read Array(2) (FFh) BEFP Setup (80h) Current CI State BP Busy in Erase Suspend BP IS in BP Buffer Suspend Suspend Suspend Program in ES in ES in Erase Suspend (Cont'd) IS in BP Suspend in ES BP Suspe nd in ES IS in BP Suspend in Erase Suspend BP Suspend in ES Buffer Program Suspend in Erase Suspend BP Suspend in Erase Suspend Blank Check busy Setup Blank Check Busy Blank Check busy Ready (error) Ready (error) IS in Blank Check busy Blank Check busy IS in Blank Check busy Blank Check busy Lock/CR Setup in Erase Suspend Buffer EFP Notes: 1. 2. 3. 4. 5. 6. 7. Erase Suspend (Lock Error) Erase Suspend Erase Suspend (Lock Error) Setup Busy Ready (error) BEFP Busy(6) BEFP Busy Ready (error) CI = Command Interface: CR = Configuration register: BEFP = Buffer Enhanced Factory program: P/E C = Program/Erase controller: IS = Illegal State: BP = Buffer Program: ES = Erase Suspend. At power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. The two cycle command should be issued to the same bank address. If the P/E C is active, both cycles are ignored. The Clear Status Register command clears the SR error bits except when the P/E C. is busy or suspended. BEFP is allowed only when Status Register bit SR0 is reset to '0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data. Buffer Program will fail at this point if any block address is different from the first address. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 80 R Platform Flash XL High-Density Configuration and Storage Device Table 47: Command Interface States - Modify Table, Next Output State(1,2) Command Input Erase Confirm P/E Resume, Block Unlock Confirm, BEFP Confirm(4)(5) (D0h) Read Electronic Signature, Read CFI Query (90h, 98h) Program/ Erase Suspend (B0h) Blank Check Setup (BCh) Clear Status Register (50h) Buffer Program (E8h) Read Status Register (70h) Blank Check confirm (CBh) Program Setup(4)(5) (10/40h) Read Array(3) (FFh) BEFP Setup (80h) Block Erase, Setup(4)(5) (20h) Current CI State Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Blank Check setup Lock/CR Setup Lock/CR Setup in Erase Suspend Status Register DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 81 R Platform Flash XL High-Density Configuration and Storage Device Table 47: Command Interface States - Modify Table, Next Output State(1,2) (Cont'd) Command Input Erase Confirm P/E Resume, Block Unlock Confirm, BEFP Confirm(4)(5) (D0h) Read Electronic Signature, Read CFI Query (90h, 98h) Program/ Erase Suspend (B0h) Blank Check Setup (BCh) Clear Status Register (50h) Buffer Program (E8h) Read Status Register (70h) Blank Check confirm (CBh) Program Setup(4)(5) (10/40h) Read Array(3) (FFh) BEFP Setup (80h) Block Erase, Setup(4)(5) (20h) Current CI State OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Blank Check busy Illegal State Notes: 1. Status Register Output Unchanged Status Register Array Status Register Output Unchanged Electronic Signature/ CFI Output Unchanged 2. 3. 4. 5. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank output state. CI = Command Interface: CR = Configuration Register: BEFP = Buffer Enhanced Factory Program: P/E. C. = Program/Erase Controller. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. The two cycle command should be issued to the same bank address. If the P/E.C. is active, both cycles are ignored. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 82 R Platform Flash XL High-Density Configuration and Storage Device Table 48: Command Interface States - Lock Table, Next State(1) Command Input Current CI State Lock/CR Setup(2) (60h) Lock/CR Setup OTP Setup(2) (C0h) OTP Setup Block Lock Confirm (01h) Block Lock-Down Confirm (2Fh) Set CR Confirm (03h) Ready Block Address (WA0)(3) (XXXXh) Illegal Command(4) P/E C Operation Completed(5) - Ready Lock/CR Setup Ready (Lock error) Setup Ready OTP Busy x Ready (Lock error) - - Ready IS Ready - Ready IS Ready - - OTP Busy IS in OTP busy Setup Busy IS in OTP Busy OTP Busy OTP Busy Program Busy IS in Program Busy Program Busy Program Busy Program IS in Program busy Suspend IS in PS Setup Buffer Load 1 Buffer Load 2 Confirm IS in PS Program Suspend Program Suspend Buffer Program Load 1 (give word count load (N-1) Buffer Program Load 2(6) Exit see note (6) Buffer Program Confirm when count =0; Else Buffer Program Load 2(9) Ready (error) IS in BP Busy Buffer Program Busy Buffer Program Busy IS in BP Suspend Buffer Program Suspend Buffer Program Suspend Ready (error) IS in Erase Busy Erase Busy Lock/CR Setup in ES Erase Busy - - - Ready IS Ready Buffer Program Busy IS in Buffer Program busy Suspend IS in BP Suspend Setup Busy IS in Erase busy Suspend IS in ES Setup Busy - - Ready IS ready Erase IS in ES Erase Suspend Erase Suspend Program Busy in Erase Suspend - - ES IS in ES - IS in Program busy in ES Program Busy in Erase Suspend Program Busy in Erase Suspend Program in Erase Suspend IS in Program busy in ES Suspend IS in PS in ES IS in PS in ES Program Suspend in Erase Suspend Program Suspend in Erase Suspend DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 83 R Platform Flash XL High-Density Configuration and Storage Device Table 48: Command Interface States - Lock Table, Next State(1) (Cont'd) Command Input Current CI State Lock/CR Setup(2) (60h) Setup Buffer Load 1 Buffer Load 2 Buffer Program in Erase Suspend Confirm Busy IS in BP busy in ES Suspend IS in BP Suspend in ES Setup Blank Check Blank Check busy IS in Blank Check busy Erase Suspend (Lock error) IS in BP suspend in ES IS in BP busy in ES OTP Setup(2) (C0h) Block Lock Confirm (01h) Block Lock-Down Confirm (2Fh) Set CR Confirm (03h) Block Address (WA0)(3) (XXXXh) Illegal Command(4) P/E C Operation Completed(5) Buffer Program Load 1 in Erase Suspend (give word count load (N-1)) Buffer Program Load 2 in Erase Suspend(7) Exit see note (7) - Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend(9) Erase Suspend (sequence error) Buffer Program Busy in Erase Suspend BP busy in ES Buffer Program Suspend in Erase Suspend ES IS in ES Buffer Program Suspend in Erase Suspend Ready (error) Blank Check busy Erase Suspend Ready (error) BEFP Busy(8) Exit BEFP Busy(8) Erase Suspend (Lock error) - - Ready - - - Lock/CR Setup in ES Setup BEFP Busy Notes: 1. 2. 3. 4. 5. 6. 7. 8. CI = Command Interface: CR = Configuration register: BEFP = Buffer Enhanced Factory program: P/E C = Program/Erase controller: IS = Illegal State: BP = Buffer program: ES = Erase suspend: WA0 = Address in a block different from first BEFP address. If the P/E C is active, both cycle are ignored. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. Illegal commands are those not defined in the command set. -: not available. In this case the state remains unchanged. If N = 0 go to Buffer Program Confirm. Else (not = 0) go to Buffer Program Load 2 (data load) If N = 0 go to Buffer Program Confirm in Erase suspend. Else (not = 0) go to Buffer Program Load 2 in Erase suspend. BEFP is allowed only when Status Register bit SR0 is set to '0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data. 9. Buffer Program will fail at this point if any block address is different from the first address DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 84 R Platform Flash XL High-Density Configuration and Storage Device Table 49: Command Interface States - Lock Table, Next Output State(1,2) Command Input Current CI State Lock/CR Setup(3)( 60h) Blank Check setup (BCh) OTP Setup(3) (C0h) Blank Block Block LockSet CR Check Lock Down Confirm Confirm Confirm Confirm (03h) (CBh) (01h) (2Fh) BEFP Exit(4) (FFFFh) Illegal Command (5) P. E./C. Operation Completed Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Blank Check setup Lock/CR Setup Lock/CR Setup in Erase Suspend Status Register Array Status Register Output Unchanged Status Register DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 85 R Platform Flash XL High-Density Configuration and Storage Device Table 49: Command Interface States - Lock Table, Next Output State(1,2) (Cont'd) Command Input Current CI State Lock/CR Setup(3)( 60h) Blank Check setup (BCh) OTP Setup(3) (C0h) Blank Block Block LockSet CR Check Lock Down Confirm Confirm Confirm Confirm (03h) (CBh) (01h) (2Fh) BEFP Exit(4) (FFFFh) Illegal Command (5) P. E./C. Operation Completed OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Eras e Suspend Buffer Program Suspend Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Blank Check busy Illegal State Notes: 1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank's output state. CI = Command Interface; CR = Configuration Register; BEFP = Buffer Enhanced Factory Program; P/E. C. = Program/Erase Controller. If the P/E.C. is active, both cycles are ignored. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. Illegal commands are those not defined in the command set. Status Register Output Unchanged Array Output Unchanged Output Unchanged 2. 3. 4. 5. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 86 R Platform Flash XL High-Density Configuration and Storage Device Revision History The following table shows the revision history for this document. Date 12/13/07 03/31/08 Version 1.0 2.0 Initial Xilinx release. Revision Added bus operations and advance device specifications: * Expanded "Command Interface," page 14, adding new sections. * Added the following sections: "Status Register," page 23 "Configuration Register," page 26 "Read Modes," page 34 "Dual Operations and Multiple Bank Architecture," page 35 "Block Locking," page 37 "Power-On Reset," page 39 "First Address Latching Sequence," page 41 "Program and Erase Times and Endurance Cycles," page 44 "Maximum Rating," page 45 "DC and AC Parameters," page 45 "Appendix A: Block Address Tables," page 61 "Appendix B: Common Flash Interface," page 65 "Appendix C: Flowcharts and Pseudocodes," page 71 "Appendix D: Command Interface State Tables," page 80 Other corrections and updates: * Corrected resistor values in Figure 7, page 10. * Corrected resistor values and removed external resistors from signal K in Figure 8, page 11. * Updated "Marking Information," page 61. * Data sheet status changed from Advance to Preliminary. * Corrected the nomenclature for the FT64 package. * Replaced section "FPGA Master BPI-Up Configuration Mode." with section "Alternate Configuration Modes," page 11. * Updated Figure 18, page 40 with annotations for TVDDPOR. * Updated Table 21, page 44 to show correct values of VPP. * Updated Table 31, page 58. * Updated trademark references. * Minor corrections throughout. * Updated Figure 1, page 2, Figure 7, page 12, Figure 8, page 22, Figure 12, page 31, Figure 15, page 33, Figure 17, page 39, Figure 18, page 40, and Figure 24, page 46. * Updated Figure 14, page 32, Figure 16, page 33, Figure 20, page 42, Figure 33, page 58, and Figure 34, page 59 to reflect changed timing parameter nomenclature. * Added maximum rating for junction temperature to Table 22, page 45. * Added Table 24, page 46. * Updated Table 2, page 6, Table 4, page 9, Table 9, page 21, Table 21, page 44, and Table 44, page 69. * Added new voltage range information to Table 28, page 50. * Updated Table 32, page 59 to reflect changed timing parameter nomenclature. * Updated Table 19, page 42, Table 20, page 43, Table 29, page 52, Table 30, page 56, Table 31, page 58, and Table 33, page 60. (Added new voltage range information and updated tables to reflect changed timing parameter nomenclature.) 05/14/08 2.1 10/29/08 2.2 DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 87 R Platform Flash XL High-Density Configuration and Storage Device Date 11/30/09 Version 3.0 Revision * See XCN09032, DS617, High-Density Configuration and Storage Device Data Sheet Revision, v3.0, for detailed product revisions: * Product change from preliminary to production phase. * Updated "Features" section. * Removed references and placeholders to VDDQ operation in the 1.7V to 2.0V range. * Added support for Virtex-6 FPGAs. * Removed Figure 7, containing a detailed system application schematic. User is referred to duplicated schematic in UG438, Platform Flash XL Configuration and Storage Device User Guide. * Inserted notes in "Description," page 1 regarding Platform Flash XL support. * Updated Platform Flash XL configuration instructions in "FPGA Configuration Overview," page 8. * Configuration sequence removed from "Slave SelectMAP Configuration Mode," page 9. User is referred to the Configuration Interface section of the respective FPGA Configuration User Guide. * Removed Master SelectMAP Mode and Master BPI-Up Mode subheadings from "Alternate Configuration Modes," page 9. User is referred to UG438, Platform Flash XL Configuration and Storage Device User Guide. * Updated Figure 21, page 41. * Updated Table 4, page 8, Table 29, page 50, Table 33, page 58. * Made typographical edits. 01/07/10 3.0.1 Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS617 (v3.0.1) January 07, 2010 Product Specification www.xilinx.com 88 |
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