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Datasheet, Version 2.1, November 2009
EICEDRIVER(R)
1ED020I12FA Single IGBT Driver IC
Power Management & Drives
Never
stop
thinking.
1ED020I12FA Revision History: Previous Version: Page 14 2009-11-24 2.0 Version 2.1
Subjects (major changes since last revision) Update table No 4.4.6 Dynamic Characteristics
Edition 2009-11-24 Published by Infineon Technologies AG, Campeon 1-12, 85579 Neubiberg, Germany (c) Infineon Technologies AG 2009. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
EICEDRIVER(R)
1ED020I12FA
Single IGBT Driver IC
Product Highlights
* * * * * * Coreless transformer isolated driver Galvanic Insulation Integrated protection features Suitable for operation at high ambient temperature Cost effective technology Automotive Qualified
Features
* * * * * Single channel isolated IGBT Driver For 600V/1200V IGBTs 2A rail-to-rail output Vcesat-detection Active Miller Clamp
Typical Application
* * * * AC and Brushless DC Motor Drives High Voltage DC/DC-Converter UPS-Systems Welding
VCC1
VCC2,H
DESAT
IN+, IN-, /RST EiceDRIVERTM /FLT, RDY CLAMP 1ED020I12FA OUT
VEE2,H GND2,H CPU VCC2,L DESAT
IN+, IN-, /RST EiceDRIVER /FLT, RDY CLAMP
TM
1ED020I12FA
OUT
GND1
VEE2,L GND2,L
Figure 1: Typical Application Type 1ED020I12FA Datasheet Gate drive current +/- 2A 3 Package PG-DSO-20-55 Version 2.1, 2009-11-24
EICEDRIVER(R) 1ED020I12FA
Table of Contents
1 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.6 3 3.1 3.2 4 4.1 4.2 4.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 5 5.1 5.2 5.3 6 7 8 8.1 8.2
Page
6 6 6 6 6 6 6 6 6 7 7 7 7 7
Blockdiagram and Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READY status output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Inverting and Inverting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Miller Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Insulation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . According to DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation . . . . . . . . . . . . . . . . . . . . . . . . According to UL 1577) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 11 12 12 12 13 13 13 14 14 15 16 16 16 16
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reference Layout for Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Printed Circuit Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Datasheet
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1
GND1
Blockdiagram and Application
11 K4
2V
10
VEE2
GND1
12
CLAMP
9
VEE2
IN+
0
&
0
13
t
0
8
CLAMP
/RST IN14
t
LOGIC
TX
RX
VCC2
LOGIC
RDY_LOOP
VEE2
7
VEE2
OUT
/FLT RDY 15
6
VCC2
UVLO
/FLT 16
UVLO
5
NC
/RST
17
4
GND2
LOGIC
VCC1 18
RX
TX
LOGIC
DESAT
K3
9V
I3
3
R
DESAT
GND1
19
GND2
2
VEE2
GND1
20
1
VEE2
Figure 2: Blockdiagram 1ED020I12FA
1ED020I12FA
Figure 3:
Application example
Datasheet
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2
2.1
Functional Description
Introduction 2.2.2 READY status output
The READY output shows the status of three internal protection features. * * * UVLO of the input chip UVLO of the output chip after a short delay Internal signal transmission
The 1ED020I12FA is an advanced IGBT gate driver that can be also used for driving power MOS devices. Control and protection functions are included to make possible the design of high reliability systems. The device consists of two galvanic separated parts. The input chip can be directly connected to a standard 5V DSP or microcontroller with CMOS in/output and the output chip is connected to the high voltage side. An effective active Miller clamp function avoids the need of negative gate driving in most applications and allows the use of a simple bootstrap supply for the high side driver. A rail-to-rail driver output enables the user to provide easy clamping of the IGBTs gate voltage during short circuit of the IGBT. So an increase of short circuit current due to the feedback via the Miller capacitance can be avoided. Further, a rail-to-rail output reduces power dissipation. The device also includes an IGBT desaturation protection with a FAULT status output. A READY status output reports if the device is supplied and operates correctly.
It is not necessary to reset the READY signal since its state only depends on the status of the former mentioned protection signals.
2.2.3
Watchdog Timer
The 1ED020I12FA incorporates two level of signal transmission security implemented through two independent watchdog timers. First level ensures the short term signal integrity by resending the (turn on/off) signals with a watchdog period of typical 500ns. The second level monitors during normal operation the internal signal transmission. If the transmission fails for a given time, the IGBT is switched off and the READY output reports an internal error.
2.2.4
Active Shut-Down
The Active Shut-Down feature ensures a safe IGBT off-state if the output chip is not connected to the power supply.
2.2 2.2.1
Internal Protection Features Undervoltage Lockout (UVLO) 2.3 Non-Inverting and Inverting Inputs
To ensure correct switching of IGBTs the device is equipped with an undervoltage lockout for both chips. If the power supply voltage VVCC1 of the input chip drops below VUVLOL1 a turn-off signal is sent to the output chip before power-down. The IGBT is switched off and the signals at IN+ and IN- are ignored as long as VVCC1 reaches the power-up voltage VUVLOH1 . If the power supply voltage VVCC2 of the output chip goes down below VUVLOL2 the IGBT is switched off and signals from the input chip are ignored as long as VVCC2 reaches the power-up voltage VUVLOH2 .
There are two possible input modes to control the IGBT. At non-inverting mode IN+ controls the driver output while INis set to low. At inverting mode IN- controls the driver output while IN+ is set to high. A minimum input pulse width is defined to filter occasional glitches.
2.4
Driver Output
The output driver section uses only MOSFETs to provide a rail-to-rail output. This feature permits that tight control of gate voltage during on-state and short circuit can be maintained as long as the drivers supply is stable. Due to the low internal voltage drop, switching behaviour of the IGBT is predominantly governed by the gate resistor. Furthermore, it reduces the power to be dissipated by the driver.
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2.5 2.5.1
External Protection Features Desaturation Protection
A desaturation protection ensures the protection of the IGBT at short circuit. When the DESAT voltage goes up and reaches 9V, the output is driven low. Further, the FAULT output is activated until it is cleared by /RST. A programmable blanking time is used to allow enough time for IGBT saturation. Blanking time is provided by a highly precise internal current source and an external capacitor.
2.5.2
Active Miller Clamping
A Miller clamp allows sinking the Miller current during a high dV/dt situation. Therefore, the use of a negative supply voltage can be avoided in many applications. During turnoff, the gate voltage is monitored and the clamp output is activated when the gate voltage goes below 2V (related to VEE2). The clamp is designed for a Miller current up to 1A.
2.5.3
Short Circuit Clamping
During short circuit the IGBTs gate voltage tends to rise because of the feedback via the Miller capacitance. An additional protection circuit connected to OUT and CLAMP limits this voltage to a value slightly higher than the supply voltage. A current of maximum 500 mA for 10us may be fed back to the supply through one of this paths. If higher currents are expected or a tighter clamping is desired external Schottky diodes may be added.
2.6
RESET
The reset input has two functions. Firstly, /RST is in charge of setting back the FAULT output. If /RST is low longer than a given time , /FLT will be reseted at the rising edge of /RST; otherwise, it will remain unchanged. Moreover, it works as enable/shutdown of the input logic.
Datasheet
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3
3.1
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VEE2 VEE2
Pin Configuration and Functionality
Pin Configuration
Symbol Function Negative power supply output side Negative power supply output side Desaturation protection Signal ground output side Not connected Positive power supply output side Driver output Miller clamping Negative power supply output side Negative power supply output side Signal ground input side Signal ground input side Non inverted driver input Inverted driver input Ready output Fault output Reset input Positive power supply input side Signal ground input side Signal ground input side Figure 4: PG-DSO-20-55
1 2 3 4 5 6 7 8 9 VEE2 VEE2 DESAT GND2 NC VCC2 OUT CLAMP VEE2 GND1 20 GND1 19 VCC1 18 /RST 17 /FLT 16 RDY 15 IN- 14 IN+ 13 GND1 12 GND1 11
DESAT GND2 NC VCC2 OUT CLAMP VEE2 VEE2 GND1 GND1 IN+ INRDY FLT RST VCC1 GND1 GND1
10 VEE2
3.2
Pin Functionality
GND1 Ground connection of the input side. IN+ Non-inverting driver input IN+ control signal for the driver output if IN- is set to low. (The IGBT is on if IN+ = high and IN- = low) A minimum pulse width is defined to make the IC robust against glitches at IN+. An internal Pull-Down-Resistor ensures IGBT Off-State. IN- Inverting driver input IN- control signal for driver output if IN+ is set to high. (IGBT is on if IN- = low and IN+ = high) A minimum pulse width is defined to make the IC robust against glitches at IN-. An internal Pull-Up-Resistor ensures IGBT Off-State. /RST (Reset) input Function 1: Enable/shutdown of the input chip. (The IGBT is off if /RST = low). A minimum pulse width is defined to make the IC robust against glitches at IN-. Datasheet 8
Function 2: Resets the DESAT-FAULT-state of the chip if /RST is low for a time TRST. An internal Pull-Up-Resistor is used to ensure FLT status output. /FLT (Fault output) Open-drain output to report a desaturation error of the IGBT (FLT is low if desaturation occurs) RDY (Ready status) Open-drain output to report the correct operation of the device. (RDY = high if both chips are above the UVLO level and the internal chip transmission is faultless) VCC1 5V power supply of the input chip VEE2 Negative power supply pins of the output chip. If no negative supply voltage is available, both pins have to be connected to GND2.
Version 2.1, 2009-11-24
EICEDRIVER(R) 1ED020I12FA
DESAT (Desaturation) Monitoring of the IGBT saturation voltage (VCE) to detect desaturation caused by short circuits. If OUT is high, VCE is above a defined value and a certain blanking time has expired, the desaturation protection is activated and the IGBT is switched off. The blanking time is adjustable by an external capacitor. CLAMP (Clamping) Ties the gate voltage to VEE2 after the IGBT has been switched off at a defined voltage to avoid a parasitic switchon of the IGBT.During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes below 2V (related to VEE2). GND2 Reference ground of the output chip. OUT (Driver output) Output pin to drive an IGBT. The voltage is switched between VEE2 and VCC2. In normal operating mode Vout is controlled by IN+, IN- and /RST. During error mode (UVLO, internal error or DESAT) Vout is set to VEE2 independent of the input control signals. VCC2 Positive power supply pin of the output side.
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Electrical Parameters
4
4.1
Electrical Parameters
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. Unless otherwise noted all parameters refer to GND1. Parameter Positive power supply output side Negative power supply output side Maximum power supply voltage output side (VVCC2-VVEE2) Gate driver output Gate driver high output maximum current Gate & Clamp driver low output maximum current Maximum short circuit clamping time Positive power supply input side Logic input voltages (IN+,IN-,RST) Opendrain Logic output voltage (FLT) Opendrain Logic output voltage (RDY) Opendrain Logic output current (FAULT) Opendrain Logic output current (RDY) Pin DESAT voltage Pin CLAMP voltage Junction temperature Storage temperature Power dissipation, Input chip Power dissipation, Output chip Thermal resistance (Input chip active) Thermal resistance (Output chip active) ESD Capability
1) With respect to GND2. 2) may be exceeded during short circuit clamping 3) Output IC power dissipation is derated linearly at 8.5 mW/C above 68C. Input IC power dissipation does not require derating. See section 8.1 for reference layouts for these thermal data. Thermal performance may change significantly with layout and heat dissipation of components in close proximity. 4) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor).
Symbol VVCC2 VVEE2 Vmax2 VOUT IOUT IOUT tCLP VVCC1 VLogicIN VFLT VRDY IFLT IRDY VDESAT VCLAMP TJ TS PD, IN PD, OUT RTHJA,IN RTHJA,OUT VESD
Limit Values min. -0.3 -12 max. 20 0.3 28 Vmax2+0.3 2.4 2.4
Unit Remarks V V V V A A us V V V V mA mA
1) 1) 1)
VVEE2-0.3
t = 2s t = 2s ICLAMP/OUT = 500mA
-0.3 -0.3 -0.3 -0.3
10 6.5 6.5 6.5 6.5 10 10 VVCC2 +0.3 VVCC2+0.3
2)

-0.3 VVEE2-0.3 -40 -55
VVEE2 = -8V
150 150 100 700 139 117 1
C C mW mW K/W K/W kV
3)

@TA = 25 @TA = 25 @TA = 25C @TA = 25C
2)3) 2) 2)
Human Body Model4)
Datasheet
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Electrical Parameters
4.2
Operating Parameters
Note: Within the operating range the IC operates as described in the functional description. Unless otherwise noted all parameters refer to GND1. Parameter Positive power supply output side Negative power supply output side Maximum power supply voltage output side (VVCC2-VVEE2) Positive power supply input side Logic input voltages (IN+,IN-,RST) Pin CLAMP voltage Pin DESAT voltage Ambient temperature Common mode transient immunity
1) With respect to GND2. 2) may be exceeded during short circuit clamping 3) The parameter is not subject to production test - verified by design/characterization
3)
Symbol VVCC2 VVEE2 Vmax2 VVCC1 VLogicIN VCLAMP VDESAT TA |VISO/dt|
Limit Values min. 13 -12 max. 20 0 28 5.5 5.5 VVCC22) VVCC2 125 50
Unit V V V V V V V C
Remarks
1) 1)
4.5 -0.3 VVEE2-0.3 -0.3 -40 --
1)
kV/s @ 500V
4.3
Parameter
Recommended Operating Parameters
Symbol VVCC2 VVEE2 VVCC1 Values 15 -8 5 Unit Remarks V V V
1) 1)
Note: Unless otherwise noted all parameters refer to GND1.
Positive power supply output side Negative power supply output side Positive power supply input side
1) With respect to GND2.
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Electrical Parameters
4.4
Electrical Characteristics
Note: The electrical characteristics involve the spread of values for the supply voltages, load and junction temperature range from -40C to +150C. Typical values represent the median values, which are related to production processes at TJ = 25C. Unless otherwise noted all voltages are given with respect to GND.
4.4.1
Parameter
Voltage Supply.
Symbol VUVLOH1 VUVLOL1 3.5 0.15 VHYS1 VUVLOH2 VUVLOL2 VHYS2 IQ1 0.7 Limit Values min. typ. 4.1 3.8 max. 4.3 V Unit Test Conditions
UVLO Threshold Input Chip UVLO Hysteresis Input Chip (VUVLOH1 - VUVLOL1) UVLO Threshold Output Chip UVLO Hysteresis Output Chip (VUVLOH1 - VUVLOL1) Quiescent Current Input Chip
12.0 11.0 0.9

12.6
V V V V V mA VVCC1 =5V IN+ = High, IN- = Low =>OUT = High, RDY = High, /FLT = High VVCC2 =15V VVEE2 =-8V IN+ = High, IN- = Low =>OUT = High, RDY = High, /FLT = High
10.4

9
7
Quiescent Current Output Chip
IQ2
4
6
mA
4.4.2
Parameter
Logic Input and Output
Symbol VIN+L,VINL,VRSTL VIN+H,VIN- 3.5 HVRSTH IIN-,IRST IIN+, IPRDY, IPFLT TMININ+, TMININTMINRST TRST VFLTL VRDYL 30 30 800 Limit Values min. typ. max. 1.5 V Unit Test Conditions
IN+,IN-, RST Low Input Voltage IN+,IN-, RST High Input Voltage IN-, RST Input Current IN+ Input Current RDY,FLT Pull Up Current Input Pulse Suppression IN+, INInput Pulse Suppression RST for ENABLE/SHUTDOWN Pulse Width RST for Reseting FLT FLT Low Voltage RDY Low Voltage

400 400 400
V uA uA uA VIN-=GND1 VRST =GND1 VIN+=VCC1 VRDY=GND1 VFLT=GND1

100 100 100 40 40

300 300
ns ns ns mV mV ISINK(FLT) = 5mA ISINK(RDY) = 5mA Version 2.1, 2009-11-24

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Datasheet
EICEDRIVER(R) 1ED020I12FA
Electrical Parameters
4.4.3
Parameter
Gate Driver
Symbol min. VOUTH1 VOUTH2 VOUTH3 VOUTH4 VVCC2-1.2 VVCC2-2.5 VVCC2-9 -1.5 Limit Values typ. VVCC2-0.8 VVCC2-2 VVCC2-5 VVCC2-10 -2 max. Unit Test Conditions
High Level Output Voltage
High Level Output Peak Current Low Level Output Voltage
IOUTH VOUTL1 VOUTL2 VOUTL3 VOUTL4

V V V V A V V V V A
IOUTH = -20mA IOUTH = -200mA IOUTH = -1A IOUTH = -2A IN+ = High, IN- = Low; OUT = High IOUTL = 20mA IOUTL = 200mA IOUTL = 1A IOUTL = 2A IN+ = Low, IN- = Low; OUT = Low, VVCC2 =15V, VVEE2 =-8V

1.5
VVEE2+0.04 VVEE2 +0.09 VVEE2+0.3 VVEE2+2.1 VVEE2+7 2 VVEE2 +0.85 VVEE2 +5.0 -- --
Low Level Output Peak Current
IOUTL
4.4.4
Parameter
Active Miller Clamp
Symbol min. VCLAMPL1 VCLAMPL2 VCLAMPL3 Limit Values typ. VVEE2+0.3 VVEE2+1.9 2 1.6 max. IOUTL = 20mA IOUTL = 200mA IOUTL = 1A
1)
Unit Test Conditions
Low Level Clamp Voltage
VVEE2+0.03 VVEE2 +0.08 V VVEE2 +0.8 VVEE2 +4.8 V V A V
Low Level Clamp Current Clamp Threshold Voltage
ICLAMPL VCLAMP
2.1
2.4
Related to VEE2
1) The parameter is not subject to production test - verified by design/characterization
4.4.5
Parameter
Short Circuit Clamping
Symbol VCLPout Limit Values min. typ. 0.8 max. 1.3 V IN+=High, IN-=Low, OUT=High IOUT = 500mA (pulse test,tCLPmax=10us) IN+=High, IN-=Low, OUT=High ICLAMP = 500mA (pulse test,tCLPmax=10us) IN+=High, IN-=Low, OUT=High ICLAMP = 20mA Unit Test Conditions
Clamping voltage (OUT) (VOUT-VVCC2)
Clamping voltage (CLAMP) (VVCLAMP-VVCC2)
VCLPclamp
1.3
V
Clamping voltage (CLAMP)
VCLPclamp
0.7
1.1
V
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Electrical Parameters
4.4.6
Parameter
Dynamic Characteristics
Symbol TPDON TPDOFF TPDISTO TPDONt TPDOFFt TPDISTOt TPDONt TPDOFFt TPDISTOt TRISE Limit Values min. typ. 185 165 -20 190 190 0 190 160 -30 30 max. 7501) 185 555
1)
Unit Test Conditions ns ns ns ns ns ns ns ns ns ns VVCC1 =5V VVCC2 =15V,VVEE2 =-8V CLOAD= 100pF VIN+=50%, VOUT=50% @ TA =25C VVCC1 =5V VVCC2 =15V,VVEE2 =-8V CLOAD= 100pF VIN+=50%, VOUT=50% @ TA =125C VVCC1 =5V VVCC2 =15V,VVEE2 =-8V CLOAD= 100pF VIN+=50%, VOUT=50% @ TA =-40C VVCC2 =15V,VVEE2 =-8V CLOAD= 1nF VL 10% ,VH 90% VVCC2 =15V,VVEE2 =-8V CLOAD= 34nF VL 10% ,VH 90% VVCC2 =15V,VVEE2 =-8V CLOAD= 1nF VL 10% ,VH 90% VVCC2 =15V,VVEE2 =-8V CLOAD= 34nF VL 10% ,VH 90%
Input to output propagation delay ON Input to output propagation delay OFF Input to output propagation delay distortion Input to output propagation delay ON variation due to temp Input to output propagation delay OFF variation due to temp Input to output propagation delay distortion variation due to temp Input to output propagation delay ON variation due to temp Input to output propagation delay OFF variation due to temp Input to output propagation delay distortion variation due to temp Rise Time
160 145 -50 160 160 -30 160 130 -60 10
990 1) 220 800 1) 990 1) 190 770 1) 60
200
400
800
ns
Fall Time
TFALL
10
50
90
ns
200
450
600
ns
1) The maximum value of input to output propagation delay ON occures only in case of electromagnetic interferences, typically the input to output delay is 205ns at TA =25C, one worst case watchdog clock cycle shorter (see chapter 2.2.3). The turn OFF-signal is prioritized/dominant and will not show up this behavior.
Datasheet
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Electrical Parameters
4.4.7
Parameter
Desaturation protection
Symbol IDESATC IDESATD VDESAT VDESAT TDESATOUT TDESATFLT VDESATL Limit Values min. typ. 250 2 9 8.6 100 max. 275 uA VVCC2 =15V,VVEE2 =-8V VDESAT=2V 225 1 8.3 7.6 Unit Test Conditions
Blanking Capacitor Charge Current Blanking Capacitor Discharge Current Desaturation Reference Level Desaturation Reference Level Desaturation Sense to OUT Low Delay Desaturation Sense to FLT Low Delay Desaturation Low Voltage
9.5 9.5 150 2.25
mA VVCC2 =15V,VVEE2 =-8V VDESAT=6V V V ns us V VVCC2 =15V,VVEE2 =-8V VVCC2 =15V,VVEE2 =0V VOUT =90% CLOAD= 1nF VFLT =10%; IFLT =5mA IN+=Low, IN-=Low, OUT=Low

0.4
0.6
0.95
4.4.8
Parameter
Active Shut Down
Symbol VACTSD
1)
Limit Values min. typ. max. 4
Unit Test Conditions
Active Shut Down Voltage
1) With reference to VEE2
V
IOUT=-200mA, VCC2 open
Datasheet
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Insulation Characteristics
5
5.1
Description
Insulation Characteristics
Complies with DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation
Symbol Characteristic I-IV I-III I-II 40/125/21 2 CLR CPG CTI VIORM VIOTM VIOSM 8 8 175 1420 6000 6000 VPEAK VPEAK V mm mm Unit
Installation classification per EN 60664-1, Table 1 for rated mains voltage 150 VRMS for rated mains voltage 300 VRMS for rated mains voltage 600 VRMS Climatic Classification Pollution Degree (EN 60664-1) Minimum External Clearance Minimum External Creepage Minimum Comparative Tracking Index Maximum Repetitive Insulation Voltage Highest Allowable Overvoltage
1)
Maximum Surge Insulation Voltage
5.2
Description
Complies with UL 1577
Symbol VISO VISO Characteristic 3750 4500 Unit Vrms Vrms
Insulation Withstand Voltage / 1min Insulation Test Voltage / 1sec
5.3
Reliability
For Qualification Report please contact your local Infineon Technologies office.
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Timing Diagrams
6
Timing Diagrams
IN
OUT
TPDELAY TPDELAY
Figure 5: propagation delay
IN+ IN-
RST OUT
Figure 6: Turn-on and Turn-off
IN+ IN-
9V DESAT RDY FLT 1.0...2.25us RST Tdesatflt
Figure 7: Desaturation Fault
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Timing Diagrams
IN+ IN-
Vcc1 Vcc2 OUT
RDY FLT RST
Figure 8: UVLO
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Package Outlines
7
Package Outlines
Figure 9: PG-DSO-20-55 (Plastic Dual Small Outline Package)
Datasheet
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Application Notes
8
8.1
Application Notes
Reference Layout for Thermal Data
The PCB layout shown in figure 12 represents the reference layout used for the thermal characterisation. Pins 11, 12, 19 and 20 (GND1) and pins 1, 2, 9 and 10 (VEE2) require ground plane connections for achiving maximum power dissipation. The 1ED020I12FA is conceived to dissipate most of the heat generated through this pins.
PCB + Top-Layer
PCB + Bottom-Layer
Figure 10: Reference layout for thermal data (Copper thickness 102m)
8.2
Printed Circuit Board Guidelines
Following factors should be taken into account for an optimum PCB layout. - Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits. - The same minimum distance between two adjacent high-side isolated parts of the PCB should be maintained to increase the effective isolation and reduce parasitic coupling. - In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be kept as short as possible.
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Application Notes
Datasheet
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Total Quality Management
Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Wir werden Sie uberzeugen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced.
www.infineon.com/gatedriver
Published by Infineon Technologies AG

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