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 PIC32MX5XX/6XX/7XX Family Data Sheet
High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers
2010 Microchip Technology Inc.
Preliminary
DS61156C
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-037-9
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS61156C-page 2
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers
High-Performance 32-Bit RISC CPU:
* MIPS32(R) M4KTM 32-bit core with 5-stage pipeline * 80 MHz maximum frequency * 1.56 DMIPS/MHz (Dhrystone 2.1) performance at zero Wait state Flash access * Single-cycle multiply and high-performance divide unit * MIPS16eTM mode for up to 40% smaller code size * Two sets of 32 core register files (32-bit) to reduce interrupt latency * Prefetch Cache module to speed execution from Flash
Peripheral Features (Continued):
* Internal 8 MHz and 32 kHz oscillators * Six UART modules with: - RS-232, RS-485 and LIN 1.2 support - IrDA(R) with on-chip hardware encoder and decoder * Up to four SPI modules * Up to five I2CTM modules * Separate PLLs for CPU and USB clocks * Parallel Master and Slave Port (PMP/PSP) with 8-bit and 16-bit data, and up to 16 address lines * Hardware Real-Time Clock/Calendar (RTCC) * Five 16-bit Timers/Counters (two 16-bit pairs combine to create two 32-bit timers) * Five Capture inputs * Five Compare/PWM outputs * Five external interrupt pins * High-speed I/O pins capable of toggling at up to 80 MHz * High-current sink/source (18 mA/18 mA) on all I/O pins * Configurable open-drain output on digital I/O pins
Microcontroller Features:
* Operating voltage range of 2.3V to 3.6V * 256K to 512K Flash memory (plus an additional 12 KB of Boot Flash) * 64K to 128K SRAM memory * Pin-compatible with most PIC24/dsPIC(R) devices * Multiple power management modes * Multiple interrupt vectors with individually programmable priority * Fail-Safe Clock Monitor mode * Configurable Watchdog Timer with on-chip Low-Power RC oscillator for reliable operation
Debug Features:
* Two programming and debugging Interfaces: - 2-wire interface with unintrusive access and real-time data exchange with application - 4-wire MIPS(R) standard enhanced JTAG interface * Unintrusive hardware-based instruction trace * IEEE Standard 1149.2 compatible (JTAG) boundary scan
Peripheral Features:
* Atomic Set, Clear and Invert operation on select peripheral registers * 8-channel hardware DMA with automatic data size detection * USB 2.0-compliant full-speed device and On-The-Go (OTG) controller: - Dedicated DMA channels * 10/100 Mbps Ethernet MAC with MII and RMII interface: - Dedicated DMA channels * CAN module: - 2.0B Active with DeviceNetTM addressing support - Dedicated DMA channels * 3 MHz to 25 MHz crystal oscillator
Analog Features:
* Up to 16-channel, 10-bit Analog-to-Digital Converter: - 1 Msps conversion rate - Conversion available during Sleep and Idle * Two Analog Comparators * 5V tolerant input pins (digital pins only)
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 3
PIC32MX5XX/6XX/7XX
TABLE 1: PIC32MX FEATURES
Timers/Capture/Compare Program Memory (KB) 10-Bit 1 Msps ADC (Channels) Data Memory (KB) DMA Channels (Programmable/ Dedicated)
Comparators
PIC32MX575F256H PIC32MX675F256H PIC32MX775F256H PIC32MX575F512H PIC32MX675F512H PIC32MX695F512H PIC32MX775F512H PIC32MX795F512H PIC32MX575F256L
64 64 64 64 64 64 64 64
256 + 12(1) 256 + 12(1) 256 + 12(1) 512 + 12(1) 512 + 12(1)
64 64 64 64 64
1 1 1 1 1 1 1 1 1
0 1 1 0 1 1 1 1 0
1 0 2 1 0 0 2 2 1
5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5
8/4 8/4 8/8 8/4 8/4 8/4 8/8 8/8 8/4
6 6 6 6 6 6 6 6 6
3 3 3 3 3 3 3 3 4
4 4 4 4 4 4 4 4 5
16 16 16 16 16 16 16 16 16
2 2 2 2 2 2 2 2 2
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
No No No No No No No No
PT, MR PT, MR PT, MR PT, MR PT, MR PT, MR PT, MR PT, MR PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG
512 + 12(1) 128 512 + 12(1) 64
512 + 12(1) 128 64
100 256 + 12(1)
Yes Yes Yes
PIC32MX675F256L
100 256 + 12(1)
64
1
1
0
5/5/5
8/4
6
4
5
16
2
Yes Yes Yes
PIC32MX775F256L
100 256 + 12(1)
64
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PIC32MX575F512L
100 512 + 12(1)
64
1
0
1
5/5/5
8/4
6
4
5
16
2
Yes Yes Yes
PIC32MX675F512L
100 512 + 12(1) 512 + 12(1)
64
1
1
0
5/5/5
8/4
6
4
5
16
2
Yes Yes Yes
PIC32MX695F512L
100
128
1
1
0
5/5/5
8/4
6
4
5
16
2
Yes Yes Yes
PIC32MX775F512L
100 512 + 12(1)
64
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PIC32MX795F512L Legend: Note 1: 2: 3: 4:
100 512 + 12(1) 128
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PF, PT = TQFP MR = QFN BG = XBGA This device features 12 KB boot Flash memory. CTS and RTS pins may not be available for all UART modules. Refer to the "Pin Diagrams" section for more information. Some pins between the UART, SPI and I2C modules may be shared. Refer to the "Pin Diagrams" section for more information. Refer to Section 32.0 "Packaging Information" for detailed information.
DS61156C-page 4
Preliminary
2010 Microchip Technology Inc.
Packages(4)
PMP/PSP
UART(2,3)
Ethernet
I2CTM(3)
Device
Trace
SPI(3)
JTAG
CAN
Pins
USB
PIC32MX5XX/6XX/7XX
Pin Diagrams
64-Pin QFN
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL1A/SDO1A/U1ATX/OC4/RD3 SDA1A/SDI1A/U1ARX/OC3/RD2 SCK1A/U1BTX/U1ARTS/OC2/RD1
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0
PIC32MX575F256H PIC32MX575F512H
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 5
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin QFN
EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1
= Pins are up to 5V tolerant
SCL1A/SDO1A/U1ATX/OC4/RD3
ERXCLK/EREFCLK/PMD3/RE3
ERXDV/ECRSDV/PMD2/RE2
AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0
ERXERR/PMD4/RE4
ERXD0/PMD1/RE1
ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
VCAP/VDDCORE
SDA1A/SDI1A/U1ARX/OC3/RD2
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
OC5/IC5/PMWR/CN13/RD4
ERXD1/PMD0/RE0
PMRD/CN14/RD5
VDD
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PIC32MX675F256H PIC32MX675F512H PIC32MX695F512H
41 40 39 38 37 36 35 34 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD AVSS PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VDD VSS TDO/AN11/PMA12/RB11 TDI/AN13/PMA10/RB13 AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TCK/AN12/PMA11/RB12 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS61156C-page 6
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin QFN
= Pins are up to 5V tolerant
ERXCLK/EREFCLKPMD3/RE3
ERXDV/ECRSDV/PMD2/RE2
ERXERR/PMD4/RE4
ERXD0/PMD1/RE1
ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1
SCL1A/SDO1A/U1ATX/OC4/RD3
SDA1A/SDI1A/U1ARX/OC3/RD2
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0
OC5/IC5/PMWR/CN13/RD4
ERXD1/PMD0/RE0
PMRD/CN14/RD5
VCAP/VDDCORE
VDD
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PIC32MX775F256H PIC32MX775F512H PIC32MX795F512H
42 41 40 39 38 37 36 35
10 11 12 13 14
34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AN14/C2RX/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 TMS/AN10/CVREFOUT/PMA13/RB10 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 TCK/AN12/PMA11/RB12 PGED2/AN7/RB7 AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
AVSS AN8/C2TX/SS3A/U3BRX/U3ACTS/C1OUT/RB8 PGEC2/AN6/OCFA/RB6 VDD
VSS
TDI/AN13/PMA10/RB13
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
2010 Microchip Technology Inc.
Preliminary
AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
TDO/AN11/PMA12/RB11
AN9/C2OUT/PMA7/RB9
AVDD
DS61156C-page 7
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin TQFP
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL1A/SDO1A/U1ATX/OC4/RD3 SDA1A/SDI1A/U1ARX/OC3/RD2 SCK1A/U1BTX/U1ARTS/OC2/RD1
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0
PIC32MX575F256H PIC32MX575F512H
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
DS61156C-page 8
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin TQFP
= Pins are up to 5V tolerant
ERXCLK/EREFCLK/PMD3/RE3
ERXDV/ECRSDV/PMD2/RE2
ERXERR/PMD4/RE4
ERXD0/PMD1/RE1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 TCK/AN12/PMA11/RB12 PGED2/AN7/RB7
AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8
EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1
SCL1A/SDO1A/U1ATX/OC4/RD3
SDA1A/SDI1A/U1ARX/OC3/RD2
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
OC5/IC5/PMWR/CN13/RD4
AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0
ERXD1/PMD0/RE0
PMRD/CN14/RD5
VCAP/VDDCORE
VDD
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PIC32MX675F256H PIC32MX675F512H PIC32MX695F512H
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
TMS/AN10/CVREFOUT/PMA13/RB10
AVSS
TDO/AN11/PMA12/RB11
PGEC2/AN6/OCFA/RB6
VDD
2010 Microchip Technology Inc.
Preliminary
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
AN9/C2OUT/PMA7/RB9
TDI/AN13/PMA10/RB13
AVDD
VSS
DS61156C-page 9
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin TQFP
EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1
= Pins are up to 5V tolerant
SCL1A/SDO1A/U1ATX/OC4/RD3
ERXCLK/EREFCLK/PMD3/RE3
ERXDV/ECRSDV/PMD2/RE2
C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0
ERXERR/PMD4/RE4
ERXD0/PMD1/RE1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD AVSS TMS/AN10/CVREFOUT/PMA13/RB10 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VDD VSS AN9/C2OUT/PMA7/RB9 TDO/AN11/PMA12/RB11 TDI/AN13/PMA10/RB13 AN14/C2RX/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 TCK/AN12/PMA11/RB12 AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 AN8/C2TX/SS3A/U3BRX/U3ACTS/C1OUT/RB8 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 48 47 46 45 44 43 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
VCAP/VDDCORE
SDA1A/SDI1A/U1ARX/OC3/RD2
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
OC5/IC5/PMWR/CN13/RD4
ERXD1/PMD0/RE0
PMRD/CN14/RD5
VDD
PIC32MX775F256H PIC32MX775F512H PIC32MX795F512H
42 41 40 39 38 37 36 35 34 33
DS61156C-page 10
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 C1TX/PMD10/RF1 C1RX/PMD11/RF0 VDD VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 PMD13/CN19/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64
VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/IC1/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS SCL1A/SDO1A/U1ATX/RF8 SDA1A/SDI1A/U1ARX/RF2 USBID/RF3
PIC32MX575F512L PIC32MX575F256L
63 62 61 60 59 58 57 56 55 54 53 52 51
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/PMA7/RA9 VREF+/CVREF+/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AC1RX/SS3A/U3BRX/U3ACTS/RF12 AN12/PMA11/RB12 AN13/PMA10/RB13 AN14/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD SS1A/U1BRX/U1ACTS/CN20/RD14 SCK1A/U1BTX/U1ARTS/CN21/RD15
2010 Microchip Technology Inc.
Preliminary
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DS61156C-page 11
Pin Diagrams (Continued)
100-Pin TQFP
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 ETXD0/PMD10/RF1 ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 SCK3A/U3BTX/U3ARTS/RF13 SS3A/U3BRX/U3ACTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14 AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DS61156C-page 12
PIC32MX5XX/6XX/7XX
= Pins are up to 5V tolerant
AERXERR/RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PIC32MX675F256L PIC32MX675F512L PIC32MX695F512L
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10
SS1/IC2/RD9 RTCC/EMDIO/AEMDIO/IC1/RD8 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS SCL1A/SDO1A/U1ATX/RF8 SDA1A/SDI1A/U1ARX/RF2 USBID/RF3
Preliminary
2010 Microchip Technology Inc.
Pin Diagrams (Continued)
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 C2RX/PMD8/RG0 C2TX/ETXERR/PMD9/RG1 C1TX/ETXD0/PMD10/RF1 C1RX/ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AC1RX/SS3A/U3BRX/U3ACTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14 AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
PGED1/AN0/CN2/RB0
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2010 Microchip Technology Inc.
100-Pin TQFP
= Pins are up to 5V tolerant
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10
SS1/IC2/RD9 RTCC/EMDIO/AEMDIO/IC1/RD8
AERXERR/RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/AC2TX/RC2 T4CK/AC2RX/RC3 T5CK/SDI1/RC4 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PIC32MX775F256L PIC32MX775F512L PIC32MX795F512L
AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2
Preliminary
DS61156C-page 13
PIC32MX5XX/6XX/7XX
D+/RG2 D-/RG3 VUSB VBUS SCL1A/SDO1A/U1ATX/RF8 SDA1A/SDI1A/U1ARX/RF2 USBID/RF3
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
121-Pin XBGA(1)
PIC32MX575F256L PIC32MX675F256L PIC32MX775F256L PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L PIC32MX775F512L PIC32MX795F512L
1 2 3 4 5 6 7 8 9 10 11
= Pins are up to 5V tolerant
A
RE4
RE3
RG13
RE0
RG0
RF1
VDD
VSS
RD12
RD2
RD1
B
NC
RG15
RE2
RE1
RA7
RF0
VCAP/ VDDCORE
RD5
RD3
VSS
RC14
C
RE6
VDD
RG12
RG14
RA6
NC
RD7
RD4
VDD
RC13
RD11
D
RC1
RE7
RE5
VSS
VSS
NC
RD6
RD13
RD0
NC
RD10
E
RC4
RC3
RG6
RC2
VDD
RG1
VSS
RA15
RD8
RD9
RA14
F
MCLR
RG8
RG9
RG7
VSS
NC
NC
VDD
RC12
VSS
RC15
G
RE8
RE9
RA0
NC
VDD
VSS
VSS
NC
RA5
RA3
RA4
H
RB5
RB4
VSS
VDD
NC
VDD
NC
VBUS
VUSB
RG2
RA2
J
RB3
RB2
RB7
AVDD
RB11
RA1
RB12
NC
NC
RF8
RG3
K
RB1
RB0
RA10
RB8
NC
RF12
RB14
VDD
RD15
RF3
RF2
L
RB6
RA9
AVSS
RB9
RB10
RF13
RB13
RB15
RD14
RF4
RF5
Note 1: Refer to Table 2, Table 3 and Table 4 for full pin names.
DS61156C-page 14
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 2:
Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 PMD8/RG0 C1TX/PMD10/RF1 VDD VSS IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 C1RX/PMD11/RF0 VCAP/VDDCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) PMD14/CN15/RD6 PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 No Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/RC3 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 T3CK/RC2 VDD PMD9/RG1 VSS
PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES
Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 SDA1/INT4/RA15 RTCC/IC1/RD8 SS1/IC2/RD9 SCL1/INT3/RA14 MCLR SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) VDD OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 INT1/RE8 INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/PMA12/RB11 TCK/RA1 AN12/PMA11/RB12 No Connect (NC) No Connect (NC) SCL1A/SDO1A/U1ATX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/PMA6/RA10 Full Pin Name
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 15
PIC32MX5XX/6XX/7XX
TABLE 2:
Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) AC1RX/SS3A/U3BRX/U3ACTS/RF12 AN14/PMALH/PMA1/RB14 VDD SCK1A/U1BTX/U1ARTS/CN21/RD15 USBID/RF3 SDA1A/SDI1A/U1ARX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/PMA7/RA9
PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED)
Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AN13/PMA10/RB13 AN15/OCFB/PMALL/PMA0/CN12/RB15 SS1A/U1BRX/U1ACTS/CN20/RD14 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Full Pin Name
DS61156C-page 16
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 3:
Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 PMD8/RG0 ETXD0/PMD10/RF1 VDD VSS ETXD2/IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) AERXERR/RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 ETXD1/PMD11/RF0 VCAP/VDDCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) ETXCLK/PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) ETXEN/PMD14/CN15/RD6 ETXD3/PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 No Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/RC3 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 T3CK/RC2 VDD EXTERR/PMD9/RG1 VSS
PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES
Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 Full Pin Name AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/AEMDIO/IC1/RD8 SS1/IC2/RD9 AETXCLK/SCL1/INT3/RA14 MCLR ERXDV/AERXDV/ECRSDV/AECRSDV//SCL2A/SDO2A/ U2ATX/PMA3/CN10/RG8 ERXCLK/AERXCLK/EREFCLK/AEREFCLK//SS2A/U2BRX/ U2ACTS/PMA2/CN11/RG9 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) VDD OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 AERXD0/INT1/RE8 AERXD1/INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/ERXERR/AETXERR/PMA12/RB11 TCK/RA1 AN12/ERXD0/AECRS/PMA11/RB12 No Connect (NC) No Connect (NC) SCL1A/SDO1A/U1ATX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/AERXD3/PMA6/RA10
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 17
PIC32MX5XX/6XX/7XX
TABLE 3:
Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) SS3A/U3BRX/U3ACTS/RF12 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 VDD AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 USBID/RF3 SDA1A/SDI1A/U1ARX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/AERXD2/PMA7/RA9
PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES
Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 SCK3A/U3BTX/U3ARTS/RF13 AN13/ERXD1/AECOL/PMA10/RB13 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Full Pin Name
DS61156C-page 18
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 4:
Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 C2RX/PMD8/RG0 C1TX/ETXD0/PMD10/RF1 VDD VSS ETXD2/IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) AERXERR/RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 C1RX/ETXD1/PMD11/RF0 VCAP/VDDCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) ETXCLK/PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) ETXEN/PMD14/CN15/RD6 ETXD3/PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 No Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/AC2RX/RC3 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 T3CK/AC2TX/RC2 VDD C2TX/EXTERR/PMD9/RG1 VSS
PIN NAMES: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L AND DEVICES
Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 Full Pin Name AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/AEMDIO/IC1/RD8 SS1/IC2/RD9 AETXCLK/SCL1/INT3/RA14 MCLR ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/ U2ATX/PMA3/CN10/RG8 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/ U2ACTS/PMA2/CN11/RG9 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) VDD OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 AERXD0/INT1/RE8 AERXD1/INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/ERXERR/AETXERR/PMA12/RB11 TCK/RA1 AN12/ERXD0/AECRS/PMA11/RB12 No Connect (NC) No Connect (NC) SCL1A/SDO1A/U1ATX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/AERXD3/PMA6/RA10
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 19
PIC32MX5XX/6XX/7XX
TABLE 4:
Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) AC1RX/SS3A/U3BRX/U3ACTS/RF12 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 VDD AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 USBID/RF3 SDA1A/SDI1A/U1ARX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/AERXD2/PMA7/RA9
PIN NAMES: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L AND DEVICES
Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AN13/ERXD1/AECOL/PMA10/RB13 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Full Pin Name
DS61156C-page 20
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Table of Contents
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0 27.0 28.0 29.0 30.0 31.0 32.0 Device Overview ........................................................................................................................................................................ 23 Guidelines for Getting Started with 32-Bit Microcontrollers........................................................................................................ 35 PIC32MX MCU........................................................................................................................................................................... 39 Memory Organization ................................................................................................................................................................. 45 Flash Program Memory............................................................................................................................................................ 105 Resets ...................................................................................................................................................................................... 107 Interrupt Controller ................................................................................................................................................................... 109 Oscillator Configuration ............................................................................................................................................................ 113 Prefetch Cache......................................................................................................................................................................... 115 Direct Memory Access (DMA) Controller ................................................................................................................................ 117 USB On-The-Go (OTG)............................................................................................................................................................ 119 I/O Ports ................................................................................................................................................................................... 121 Timer1 ...................................................................................................................................................................................... 123 Timer2/3, Timer4/5 ................................................................................................................................................................... 125 Input Capture............................................................................................................................................................................ 127 Output Compare....................................................................................................................................................................... 129 Serial Peripheral Interface (SPI)............................................................................................................................................... 131 Inter-Integrated Circuit (I2CTM) ................................................................................................................................................. 133 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 135 Parallel Master Port (PMP) ...................................................................................................................................................... 137 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 139 10-Bit Analog-to-Digital Converter (ADC)................................................................................................................................. 141 Controller Area Network (CAN) ................................................................................................................................................ 143 Ethernet Controller ................................................................................................................................................................... 145 Comparator .............................................................................................................................................................................. 147 Comparator Voltage Reference (CVref) ................................................................................................................................... 149 Power-Saving Features ........................................................................................................................................................... 151 Special Features ...................................................................................................................................................................... 153 Instruction Set .......................................................................................................................................................................... 165 Development Support............................................................................................................................................................... 167 Electrical Characteristics .......................................................................................................................................................... 171 Packaging Information.............................................................................................................................................................. 213
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Errata
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2010 Microchip Technology Inc.
Preliminary
DS61156C-page 21
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 22
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
1.0 DEVICE OVERVIEW
This document contains device-specific information for PIC32MX5XX/6XX/7XX devices. Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC32MX5XX/6XX/7XX family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
FIGURE 1-1:
BLOCK DIAGRAM(1,2)
OSC2/CLKO OSC1/CLKI OSC/SOSC Oscillators FRC/LPRC Oscillators PLL Dividers PLL-USB Timing Generation VCAP/VDDCORE Power-up Timer Voltage Regulator Precision Band Gap Reference USBCLK SYSCLK PBCLK Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset CN1-22 Timer1-5 CAN1, CAN2 PWM OC1-5 VDD, VSS MCLR
Peripheral Bus Clocked by SYSCLK PORTA JTAG BSCAN PORTB USB EJTAG PORTC 32 PORTD INT Priority Interrupt Controller
32
Peripheral Bus Clocked by PBCLK
ETHERNET
DMAC
ICD
MIPS32(R) M4KTM CPU Core IS 32 DS 32 32
IC1-5
32
32
32
32
SPI1,1A,2A,3A
Bus Matrix 32 32 32
I2C1,2,1A, 2A,3A 32
PORTE Prefetch Module PORTF 128 128-Bit Wide Program Flash Memory Flash Controller Data RAM Peripheral Bridge
PMP 10-Bit ADC UART1A,1B,2A, 2B,3A,3B RTCC Comparators
PORTG
Note
1: 2:
Some features are not available on all device variants. BOR functionality is provided when the on-board voltage regulator is enabled.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 23
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 CLKI CLKO
PINOUT I/O DESCRIPTIONS
Pin Number(1) 64-Pin QFN/TQFP 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 39 40 100-Pin TQFP 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 63 64 121-Pin XBGA K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 F9 F11 Pin Type I I I I I I I I I I I I I I I I I O Buffer Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog ST/CMOS External clock source input. Always associated with OSC1 pin function. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Description Analog input channels.
OSC1 OSC2
39 40
63 64
F9 F11
I I/O
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.
SOSCI SOSCO
47 48
73 74
C10 B11
I O
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. -- 32.768 kHz low-power oscillator crystal output.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information.
DS61156C-page 24
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 IC1 IC2 IC3 IC4 IC5 OCFA OC1 OC2 OC3 OC4 OC5 OCFB INT0 INT1 INT2 INT3 INT4
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) 64-Pin QFN/TQFP 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 -- -- -- 42 43 44 45 52 17 46 49 50 51 52 30 46 42 43 44 45 100-Pin TQFP 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 68 69 70 71 79 26 72 76 77 78 81 44 72 18 19 66 67 121-Pin XBGA B11 C10 K2 K1 J2 J1 H2 H1 E3 F4 F2 F3 L8 C8 B8 D7 C7 L10 L11 D8 L9 K9 E9 E10 D11 C11 A9 L1 D9 A11 A10 B9 C8 L8 D9 G1 G2 E11 E8 Pin Type I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O I I I I I I Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- -- -- -- -- ST ST ST ST ST ST Output Compare Fault A input. Output Compare Output 1. Output Compare Output 2 Output Compare Output 3. Output Compare Output 4. Output Compare Output 5. Output Compare Fault B input. External Interrupt 0. External Interrupt 1. External Interrupt 2. External Interrupt 3. External Interrupt 4. Capture Inputs 1-5. Description Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 25
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) 64-Pin QFN/TQFP -- -- -- -- -- -- -- -- -- -- -- -- 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 -- -- -- -- 39 47 48 40 100-Pin TQFP 17 38 58 59 60 61 91 92 28 29 66 67 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 6 7 8 9 63 73 74 64 121-Pin XBGA G3 J6 H11 G10 G11 G9 C5 B5 L2 K3 E11 E8 K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 D1 E4 E2 E1 F9 C10 B11 F11 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST PORTC is a bidirectional I/O port. PORTB is a bidirectional I/O port. Description PORTA is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information.
DS61156C-page 26
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 RF0 RF1 RF2 RF3 RF4 RF5 RF8 RF12 RF13
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) 64-Pin QFN/TQFP 46 49 50 51 52 53 54 55 42 43 44 45 -- -- -- -- 60 61 62 63 64 1 2 3 -- -- 58 59 -- 33 31 32 -- -- -- 100-Pin TQFP 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 87 88 52 51 49 50 53 40 39 121-Pin XBGA D9 A11 A10 B9 C8 B8 D7 C7 E9 E10 D11 C11 A9 D8 L9 K9 A4 B4 B3 A2 A1 D3 C1 D2 G1 G2 B6 A6 K11 K10 L10 L11 J10 K6 L6 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST PORTF is a bidirectional I/O port. PORTE is a bidirectional I/O port. Description PORTD is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 27
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name RG0 RG1 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RG2 RG3 T1CK T2CK T3CK T4CK T5CK U1ACTS U1ARTS U1ARX U1ATX U2ACTS U2ARTS U2ARX U2ATX U3ACTS U3ARTS U3ARX U3ATX U1BRX U1BTX U2BRX U2BTX U3BRX U3BTX SCK1 SDI1
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) 64-Pin QFN/TQFP -- -- 4 5 6 8 -- -- -- -- 37 36 48 -- -- -- -- 43 49 50 51 8 4 5 6 21 29 31 32 43 49 8 4 21 29 -- -- 100-Pin TQFP 90 89 10 11 12 14 96 97 95 1 57 56 74 6 7 8 9 47 48 52 53 14 10 11 12 40 39 49 50 47 48 14 10 40 39 70 9 121-Pin XBGA A5 E6 E3 F4 F2 F3 C3 A3 C4 B2 H10 J11 B11 D1 E4 E2 E1 L9 K9 K11 J10 F3 E3 F4 F2 K6 L6 L10 L11 L9 K9 F3 E3 K6 L6 D11 E1 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I O I O I O I O I O I O I O I O I O I/O I Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST ST Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. UART1A clear to send. UART1A ready to send. UART1A receive. UART1A transmit. UART2A clear to send. UART2A ready to send. UART2A receive. UART2A transmit. UART3A clear to send. UART3A ready to send. UART3A receive. UART3A transmit. UART1B receive. UART1B transmit. UART2B receive. UART2B transmit. UART3B receive. UART3B transmit. Synchronous serial clock input/output for SPI1. SPI1 data in. PORTG input pins. Description PORTG is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information.
DS61156C-page 28
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name SDO1 SS1 SCK1A SDI1A SDO1A SS1A SCK2A SDI2A SDO2A SS2A SCK3A SDI3A SDO3A SS3A SCL1 SDA1 SCL1A SDA1A SCL2 SDA2 SCL2A SDA2A SCL3A SDA3A TMS TCK TDI TDO RTCC
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) 64-Pin QFN/TQFP -- -- 49 50 51 43 4 5 6 8 29 31 32 21 44 43 51 50 -- -- 6 5 32 31 23 27 28 24 42 100-Pin TQFP 72 69 48 52 53 47 10 11 12 14 39 49 50 40 66 67 53 52 58 59 12 11 50 49 17 38 60 61 68 121-Pin XBGA D9 E10 K9 K11 J10 L9 E3 F4 F2 F3 L6 L10 L11 K6 E11 E8 J10 K11 H11 G10 F2 F4 L11 L10 G3 J6 G11 G9 E9 Pin Type O I/O I/O I O I/O I/O I O I/O I/O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O O Buffer Type -- ST ST ST -- ST ST ST -- ST ST ST -- ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- -- SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI1A. SPI1A data in. SPI1A data out. SPI1A slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2A. SPI2A data in. SPI2A data out. SPI2A slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI3A. SPI3A data in. SPI3A data out. SPI3A slave synchronization or frame pulse I/O. Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Synchronous serial clock input/output for I2C1A. Synchronous serial data input/output for I2C1A. Synchronous serial clock input/output for I2C2. Synchronous serial data input/output for I2C2. Synchronous serial clock input/output for I2C2A. Synchronous serial data input/output for I2C2A. Synchronous serial clock input/output for I2C3A. Synchronous serial data input/output for I2C3A. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Real-Time Clock alarm output. Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 29
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name CVREFCVREF+ CVREFOUT C1INC1IN+ C1OUT C2INC2IN+ C2OUT PMA0
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) 64-Pin QFN/TQFP 15 16 23 12 11 21 14 13 22 -- 100-Pin TQFP 28 29 34 21 20 32 23 22 33 44 121-Pin XBGA L2 K3 L5 H2 H1 K4 J2 J1 L4 L8 Pin Type I I O I I O I I O I/O Buffer Type Analog Analog Analog Analog Analog -- Analog Analog -- TTL/ST Description Comparator Voltage Reference (low). Comparator Voltage Reference (high). Comparator Voltage Reference output. Comparator 1 negative input. Comparator 1 positive input. Comparator 1 output. Comparator 2 negative input. Comparator 2 positive input. Comparator 2 output. Parallel Master Port Address Bit 0 input (Buffered Slave modes) and output (Master modes). Parallel Master Port Address Bit 1 input (Buffered Slave modes) and output (Master modes). Parallel Master Port address (Demultiplexed Master modes).
PMA1
--
43
K7
I/O
TTL/ST
PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMCS1 PMCS2
8 6 5 4 16 22 32 31 28 27 24 23 45 44 45 44
14 12 11 10 29 28 50 49 42 41 35 34 71 70 71 70
F3 F2 F4 E3 K3 L2 L11 L10 L7 J7 J5 L5 C11 D11 C11 D11
O O O O O O O O O O O O O O O O
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Parallel Master Port Chip Select 1 strobe. Parallel Master Port Chip Select 2 strobe.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information.
DS61156C-page 30
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMALL PMALH PMRD PMWR VBUS VUSB VBUSON D+ DUSBID C1RX C1TX AC1RX AC1TX C2RX C2TX AC2RX AC2TX ERXD0 ERXD1 ERXD2
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) 64-Pin QFN/TQFP 60 61 62 63 64 1 2 3 -- -- -- -- -- -- -- -- 30 29 53 52 34 35 11 37 36 33 58 59 32 31 29 21 -- -- 61 60 59 100-Pin TQFP 93 94 98 99 100 3 4 5 90 89 88 87 79 80 83 84 44 43 82 81 54 55 20 57 56 51 87 88 40 39 90 89 8 7 41 42 43 121-Pin XBGA A4 B4 B3 A2 A1 D3 C1 D2 A5 E6 A6 B6 A9 D8 D7 C7 L8 K7 B8 C8 H8 H9 H1 H10 J11 K10 B6 A6 K6 L6 A5 E6 E2 E4 J7 L7 K7 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O I P O I/O I/O I I O I O I O 1 O I I I Buffer Type TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST -- -- -- -- Analog -- -- Analog Analog ST ST -- ST -- ST -- ST -- ST ST ST Parallel Master Port address latch enable low byte (Multiplexed Master modes). Parallel Master Port address latch enable high byte (Multiplexed Master modes). Parallel Master Port read strobe. Parallel Master Port write strobe. USB bus power monitor. USB internal transceiver supply. USB Host and OTG bus power control output. USB D+. USB D-. USB OTG ID detect. CAN1 bus receive pin. CAN1 bus transmit pin. Alternate CAN1 bus receive pin. Alternate CAN1 bus transmit pin. CAN2 bus receive pin. CAN2 bus transmit pin. Alternate CAN2 bus receive pin. Alternate CAN2 bus transmit pin. Ethernet Receive Data 0.(2) Ethernet Receive Data 1.(2) Ethernet Receive Data 2.(2) Description Parallel Master Port data (Demultiplexed Master mode) or address/data (Multiplexed Master modes).
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information.
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TABLE 1-1:
Pin Name ERXD3 ERXERR ERXDV ECRSDV ERXCLK EREFCLK ETXD0 ETXD1 ETXD2 ETXD3 ETXERR ETXEN ETXCLK ECOL ECRS EMDC EMDIO AERXD0 AERXD1 AERXD2 AERXD3 AERXERR AERXDV AECRSDV AERXCLK AEREFCLK AETXD0 AETXD1 AETXD2 AETXD3 AETXERR AETXEN AETXCLK AECOL AECRS TRCLK
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) 64-Pin QFN/TQFP 58 64 62 61 63 63 2 3 43 42 54 1 55 44 45 30 49 43 42 -- -- 55 44 44 45 45 59 58 -- -- -- 54 -- -- -- -- 100-Pin TQFP 44 35 12 12 14 14 88 87 79 80 89 83 84 10 11 71 68 18 19 28 29 1 -- -- -- -- 47 48 44 43 35 67 66 42 41 91 121-Pin XBGA L8 J5 F2 F2 F3 F3 A6 B6 A9 D8 E6 D7 C7 E3 F4 C11 E9 G1 G2 L2 K3 B2 -- -- -- -- L9 K9 L8 K7 J5 E8 E11 L7 J7 C5 Pin Type I I I I I I O O O O O O I I I O I/O I I I I I I I I I O O O O O O I I I O Buffer Type ST ST ST ST ST ST -- -- -- -- -- -- ST ST ST -- -- ST ST ST ST ST ST ST ST ST -- -- -- -- -- -- ST ST ST -- Description Ethernet Receive Data 3.(2) Ethernet receive error input.(2) Ethernet receive data valid.(2) Ethernet carrier sense data valid.(2) Ethernet receive clock.(2) Ethernet reference clock.(2) Ethernet Transmit Data 0.(2) Ethernet Transmit Data 1.(2) Ethernet Transmit Data 2.(2) Ethernet Transmit Data 3.(2) Ethernet transmit error.(2) Ethernet transmit enable.(2) Ethernet transmit clock.(2) Ethernet collision detect.(2) Ethernet carrier sense.(2) Ethernet management data clock.(2) Ethernet management data.(2) Alternate Ethernet Receive Data 0.(2) Alternate Ethernet Receive Data 1.(2) Alternate Ethernet Receive Data 2.(2) Alternate Ethernet Receive Data 3.(2) Alternate Ethernet receive error input.(2) Alternate Ethernet receive data valid.(2) Alternate Ethernet carrier sense data valid.(2) Alternate Ethernet receive clock.(2) Alternate Ethernet reference clock.(2) Alternate Ethernet Transmit Data 0.(2) Alternate Ethernet Transmit Data 1.(2) Alternate Ethernet Transmit Data 2.(2) Alternate Ethernet Transmit Data 3.(2) Alternate Ethernet transmit error.(2) Alternate Ethernet transmit enable.(2) Alternate Ethernet transmit clock.(2) Alternate Ethernet collision detect.(2) Alternate Ethernet carrier sense.(2) Trace clock.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information.
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TABLE 1-1:
Pin Name TRD0 TRD1 TRD2 TRD3 PGED1 PGEC1 PGED2 PGEC2 MCLR AVDD AVSS VDD
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) 64-Pin QFN/TQFP -- -- -- -- 16 15 18 17 7 19 20 100-Pin TQFP 97 96 95 92 25 24 27 26 13 30 31 121-Pin XBGA A3 C3 C4 B5 K2 K1 J3 L1 F1 J4 L3 A7, C2, C9, E5, K8, F8, G5, H4, H6 B7 A8, B10, D4, D5, E7, F5, F10, G6, G7, H3 K3 L2 Pin Type O O O O I/O I I/O I I/P P P P Buffer Type -- -- -- -- ST ST ST ST ST P P -- Data I/O pin for Programming/Debugging Communication Channel 1. Clock input pin for Programming/Debugging Communication Channel 1. Data I/O pin for Programming/Debugging Communication Channel 2. Clock input pin for Programming/Debugging Communication Channel 2. Master Clear (Reset) input. This pin is an active-low Reset to the device. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Description Trace Data Bits 0-3.
10, 26, 38, 2, 16, 37, 57 46, 62, 86
VCAP/ VDDCORE VSS
56 9, 25, 41
85 15, 36, 45, 65, 75
P P
-- --
CPU logic filter capacitor connection. Ground reference for logic and I/O pins. This pin must be connected at all times.
VREF+ VREF-
16 15
29 28
I I
Analog Analog
Analog voltage reference (high) input. Analog voltage reference (low) input.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability. 2: See Section 24.0 "Ethernet Controller" for more information.
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NOTES:
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2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS
2.2 Decoupling Capacitors
The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: A value of 0.1 F (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within onequarter inch (6 mm) in length. * Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F. * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32) 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
2.1
Basic Connection Requirements
Getting started with the PIC32MX5XX/6XX/7XX family of 32-bit Microcontrollers (MCU) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: * All VDD and VSS pins (see Section 2.2 "Decoupling Capacitors") * All AVDD and AVSS pins-even if the ADC module is not used (see Section 2.2 "Decoupling Capacitors") * VCAP/VDDCORE pin (see Section 2.3 "Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)") * MCLR pin (see Section 2.4 "Master Clear (MCLR) Pin") * PGECx/PGEDx pins-used for In-Circuit Serial Programming (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins") * OSC1 and OSC2 pins-when external oscillator source is used (see Section 2.8 "External Oscillator Pins") The following pin may be required, as well: VREF+/VREF- pins-used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected, regardless of ADC use and the ADC voltage reference source.
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FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION
0.1 F Ceramic CBP VDD VSS
2.4
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device functions: * Device Reset * Device programming and debugging Pulling The MCLR pin low generates a device Reset. Figure 2-2 shows a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin.
VDD R R1
MCLR VCAP/VDDCORE
CEFC
C
PIC32MX
VSS VDD VDD VSS 0.1 F Ceramic CBP 0.1 F Ceramic CBP AVDD AVSS VDD 0.1 F Ceramic CBP VSS
0.1 F Ceramic CBP
10
2.2.1
BULK CAPACITORS
The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 F to 47 F. This capacitor should be located as close to the device as possible.
FIGURE 2-2:
EXAMPLE OF MCLR PIN CONNECTIONS
VDD R R1 JP C MCLR PIC32MX
2.3
2.3.1
Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)
INTERNAL REGULATOR MODE
A low-ESR (1 ohm) capacitor is required on the VCAP/VDDCORE pin, which is used to stabilize the internal voltage regulator output. The VCAP/VDDCORE pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 31.0 "Electrical Characteristics" for additional information on CEFC specifications.
Note 1:
R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R1 470 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during POR.
2:
3:
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2.5 ICSP Pins 2.6 JTAG
The PGECx and PGEDx pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB(R) ICD 2, MPLAB ICD 3, or MPLAB REAL ICETM. For more information on ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip web site. * "MPLAB(R) ICD 2 In-Circuit Debugger User's Guide" DS51331 * "Using MPLAB(R) ICD 2" (poster) DS51265 * "MPLAB(R) ICD 2 Design Advisory" DS51566 * "Using MPLAB(R) ICD 3" (poster) DS51765 * "MPLAB(R) ICD 3 Design Advisory" DS51764 * "MPLAB(R) REAL ICETM In-Circuit Debugger User's Guide" DS51616 * "Using MPLAB(R) REAL ICETM Emulator" (poster) DS51749 The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements.
2.7
Trace
The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time instruction trace. When used for trace the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a 22 ohm series resistor between the trace pins and the trace connector.
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2.8 External Oscillator Pins 2.9
Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3.
Configuration of Analog and Digital Pins During ICSP Operations
If MPLAB ICD 2, ICD 3, or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as "digital" pins by setting all bits in the ADPCFG register. The bits in this register that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3, or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 2, ICD 3, or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic '0', which may affect user application functionality.
FIGURE 2-3:
SUGGESTED OSCILLATOR CIRCUIT PLACEMENT
Oscillator Secondary Guard Trace Guard Ring Main Oscillator
2.10
Unused I/Os
Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternatively, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input.
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3.0 PIC32MX MCU
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. "MCU" (DS61113) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32(R) M4K(R) Processor Core are available at http://www.mips.com. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The MCU module is the heart of the PIC32MX5XX/6XX/7XX family processor. The MCU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions MIPS16eTM Code Compression - 16-bit encoding of 32-bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE & RESTORE macro instructions for setting up and tearing down stack frames within subroutines - Improved support for handling 8 and 16-bit data types Simple Fixed Mapping Translation (FMT) mechanism Simple Dual Bus Interface - Independent 32-bit address and data busses - Transactions can be aborted to improve interrupt latency Autonomous Multiply/Divide Unit - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension-dependent) Power Control - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks EJTAG Debug and Instruction Trace - Support for single stepping - Virtual instruction and data address/value - Breakpoints - PC tracing with trace compression
*
* *
*
3.1
Features
*
* 5-Stage Pipeline * 32-Bit Address and Data Paths * MIPS32 Enhanced Architecture (Release 2) - Multiply-Accumulate and Multiply-Subtract instructions - Targeted Multiply instruction - Zero/One Detect instructions - WAIT instruction - Conditional Move instructions (MOVN, MOVZ) - Vectored interrupts - Programmable exception vector base
*
FIGURE 3-1: MCU
MCU BLOCK DIAGRAM
EJTAG Trace TAP Trace I/F Off-Chip Debug I/F Dual Bus I/F Bus Matrix
DS61156C-page 39
MDU
Execution Core (RF/ALU/Shift)
FMT
Bus Interface
System Coprocessor
Power Management
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PIC32MX5XX/6XX/7XX
3.2 Architecture Overview
3.2.2 MULTIPLY/DIVIDE UNIT (MDU)
The PIC32MX5XX/6XX/7XX family core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: * * * * * * * * Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller The PIC32MX5XX/6XX/7XX family core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (`32' of 32x16) represents the rs operand. The second number (`16' of 32x16) represents the rt operand. The PIC32MX core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit wide rs, 15 iterations are skipped and for a 24-bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32MX core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks.
3.2.1
EXECUTION UNIT
The PIC32MX5XX/6XX/7XX family core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: * 32-bit adder used for calculating the data address * Address unit for calculating the next instruction address * Logic for branch determination and branch target address calculation * Load aligner * Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results * Leading Zero/One detect unit for implementing the CLZ and CLO instructions * Arithmetic Logic Unit (ALU) for performing bitwise logical operations * Shifter and store aligner
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TABLE 3-1: PIC32MX5XX/6XX/7XX FAMILY CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU MUL DIV/DIVU Operand Size (mul rt) (div rs) 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. Latency 1 2 2 3 12 19 26 33 Repeat Rate 1 2 1 2 11 18 25 32
3.2.3
SYSTEM CONTROL COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor's diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e, is also available by accessing the CP0 registers, listed in Table 3-2.
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TABLE 3-2:
Register Number 0-6 7 8 9 10 11 12 12 12 12 13 14 15 15 16 16 16 16 17-22 23 24 25-29 30 31 Note 1: 2:
COPROCESSOR 0 REGISTERS
Register Name Function Reserved in the PIC32MX5XX/6XX/7XX family core. Enables access via the RDHWR instruction to selected hardware registers. Reports the address for the most recent address-related exception. Processor cycle count. Reserved in the PIC32MX5XX/6XX/7XX family core. Timer interrupt control. Processor status and control. Interrupt system status and control. Shadow register set status and control. Provides mapping from vectored interrupt to a shadow set. Cause of last general exception. Program counter at last exception. Processor identification and revision. Exception vector base register. Configuration register. Configuration Register 1. Configuration Register 2. Configuration Register 3. Reserved in the PIC32MX5XX/6XX/7XX family core. Debug control and exception status. Program counter at last debug exception. Reserved in the PIC32MX5XX/6XX/7XX family core. Program counter at last error. Debug handler scratchpad register.
(1)
Reserved HWREna BadVAddr(1) Count(1) Reserved Compare Status(1) IntCtl
(1)
SRSCtl(1) SRSMap(1) Cause(1) EPC
(1)
PRId EBASE Config Config1 Config2 Config3 Reserved Debug
(2)
DEPC(2) Reserved ErrorEPC(1) DESAVE
(2)
Registers used in exception processing. Registers used during debug.
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Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority.
TABLE 3-3:
Exception Reset DSS DINT NMI Interrupt DIB AdEL IBE DBp Sys Bp RI CpU CEU Ov Tr DDBL/DDBS AdEL AdES DBE DDBL
PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES
Description Assertion MCLR or a Power-on Reset (POR). EJTAG debug single step. EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register. Assertion of NMI signal. Assertion of unmasked hardware or software interrupt signal. EJTAG debug hardware instruction break matched. Fetch address alignment error. Fetch reference to protected address. Instruction fetch bus error. EJTAG breakpoint (execution of SDBBP instruction). Execution of SYSCALL instruction. Execution of BREAK instruction. Execution of a reserved instruction. Execution of a coprocessor instruction for a coprocessor that is not enabled. Execution of a CorExtend instruction when CorExtend is not enabled. Execution of an arithmetic instruction that overflowed. Execution of a trap (when trap condition is true). EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value). Load address alignment error. Load reference to protected address. Store address alignment error. Store to protected address. Load or store bus error. EJTAG data hardware breakpoint matched in load data compare.
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PIC32MX5XX/6XX/7XX
3.3 Power Management 3.4 EJTAG Debug Support
The PIC32MX5XX/6XX/7XX family core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or Halting the clocks, which reduces system power consumption during Idle periods. The PIC32MX5XX/6XX/7XX family core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the PIC32MX5XX/6XX/7XX family core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, singlestep exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the PIC32MX5XX/6XX/7XX family core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define which registers are selected and how they are used.
3.3.1
INSTRUCTION-CONTROLLED POWER MANAGEMENT
The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see Section 27.0 "Power-Saving Features".
3.3.2
LOCAL CLOCK GATING
The majority of the power consumed by the PIC32MX5XX/6XX/7XX family core is in the clock tree and clocking registers. The PIC32MX family uses extensive use of local gated clocks to reduce this dynamic power consumption.
DS61156C-page 44
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
4.0
Note:
MEMORY ORGANIZATION
This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. For detailed information, refer to Section 3. "Memory Organization" (DS61115) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32).
4.1
PIC32MX5XX/6XX/7XX Memory Layout
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program, data memory, SFRs and Configuration registers, reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX5XX/6XX/7XX devices to execute from data memory. Key features include: * 32-bit native data width * Separate User (KUSEG) and Kernel (KSEG0/KSEG1) mode address space * Flexible program Flash memory partitioning * Flexible data RAM partitioning for data and program space * Separate boot Flash memory for protected code * Robust bus exception handling to intercept runaway code * Simple memory mapping with Fixed Mapping Translation (FMT) unit * Cacheable (KSEG0) and non-cacheable (KSEG1) address regions
PIC32MX5XX/6XX/7XX microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU. The memory maps for the PIC32MX5XX/6XX/7XX devices are shown in Figure 4-1, Figure 4-2 and Figure 4-3.
4.1.1
PERIPHERAL REGISTERS LOCATIONS
Table 4-1 through Table 4-44 contain the peripheral address maps for the PIC32MX5XX/6XX/7XX devices. Peripherals located on the PB bus are mapped to 512-byte boundaries. Peripherals on the FPB bus are mapped to 4-Kbyte boundaries.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 45
PIC32MX5XX/6XX/7XX
FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L, PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND PIC32MX775F256L DEVICES(1)
Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD040000 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0010000 0xA000FFFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D040000 0x9D03FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00010000 0x0000FFFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D040000 0x1D03FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF
Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information).
DS61156C-page 46
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L, PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND PIC32MX775F512L DEVICES
Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0010000 0xA000FFFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D080000 0x9D07FFFF Program Flash(2) 0x9D000000 0x80010000 0x8000FFFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM
(2)
Physical Memory Map 0xFFFFFFFF
Reserved Device Configuration Registers
Reserved
Reserved
Reserved
KSEG1
SFRs
Reserved
0x1FC03000 Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 Reserved 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D080000 Reserved 0x1D07FFFF Program Flash(2) 0x1D000000 0x00010000 0x0000FFFF 0x00000000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF
Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information).
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 47
PIC32MX5XX/6XX/7XX
FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H AND PIC32MX795F512L DEVICES
Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0020000 0xA001FFFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D080000 0x9D07FFFF Program Flash(2) 0x9D000000 0x80020000 0x8001FFFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00020000 0x0001FFFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D080000 0x1D07FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF
Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information).
DS61156C-page 48
Preliminary
2010 Microchip Technology Inc.
2010 Microchip Technology Inc.
TABLE 4-1:
Virtual Address (BF88_#) Register Name
BUS MATRIX REGISTER MAP
Bit Range Bits All Resets 0040 -- -- -- 0000 0000 -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 xxxx xxxx -- -- -- -- -- -- -- -- -- -- -- -- BMXPUPBA<19:16> 0000 0000 xxxx xxxx BMXBOOTSZ<31:0> 0000 3000 BMXPUPBA<15:0> BMXPFMSZ<31:0>
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
2000
BMXCON(1)
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
BMXCHEDMA -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- BMXWSDRM -- -- --
-- -- --
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F -- -- -- -- -- BMXARB<2:0> --
2010 BMXDKPBA(1) 2020 BMXDUDBA(1) 2030 BMXDUPBA(1) 2040 BMXDRMSZ 2050 BMXPUPBA(1) 2060 BMXPFMSZ
BMXDKPBA<15:0> BMXDUDBA<15:0> BMXDUPBA<15:0> BMXDRMSZ<31:0>
Preliminary
DS61156C-page 49
PIC32MX5XX/6XX/7XX
2070 BMXBOOTSZ Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-2:
Virtual Address (BF88_#) Bit Range Register Name
INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES(1)
Bits All Resets
DS61156C-page 50
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON 1010 INTSTAT 1020 IPTMR
31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- --
-- FRZ -- --
-- -- -- --
-- MVEC -- --
-- -- -- --
-- --
-- TPC<2:0> -- RIPL<2:0>
-- --
-- -- -- --
-- -- -- --
-- -- --
-- INT4EP --
-- INT3EP -- VEC<5:0>
-- INT2EP --
-- INT1EP --
SS0 --
0000
INT0EP 0000 0000 0000 0000 0000
IPTMR<31:0> U1ATXIF U1ARXIF I2C1ASIF INT2IF -- -- -- U3BTXIF U1ARXIE I2C1ASIE INT2IE -- -- -- U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> U1AEIF -- IC2IF USBIF U3ARXIF -- T2IF FCEIF U3AEIF -- INT1IF DMA7IF U2ATXIF OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF -- U2BEIF OC5IE OC1IE DMA6IE U2ARXIE I2C2ASIE -- U2BEIE -- -- -- -- IC5IF IC1IF DMA5IF U2AEIF CMP2IF -- CMP1IF -- U1BEIF INT4IE INT0IE DMA3IE CMP1IE -- U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> PMPIF -- PMPEIF OC4IE CS1IE DMA2IE PMPIE -- PMPEIE AD1IF -- IC5EIF IC4IE CS0IE CNIF -- T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF T4IF CTIF
1030
IFS0
31:16 I2C1MIF 15:0 31:16 INT3IF IC3EIF RTCCIF -- --
I2CSIF OC3IF IC2EIF FSCMIF -- --
I2CBIF IC3IF IC1EIF -- -- --
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF T3IF -- -- -- -- U1ATXIE I2C1ABIF OC2IF CAN1IF U3ATXIF
0000
0000
DMA1IF DMA0IF 0000
Preliminary
2010 Microchip Technology Inc.
1040
IFS1
15:0 31:16 15:0
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF I2C3ASIF I2C3ASIF I2C2AMIF -- U3BEIF -- IC2IE USBIE U3ARXIE -- U2BTXIF -- T2IE FCEIE U3AEIE -- U2BRXIF -- INT1IE DMA7IE U2ATXIE I2C2ABIF -- -- U3BRXIF U1AEIE IC5IE IC1IE DMA5IE U2AEIE
0000
1050
IFS2
0000
U1BTXIF U1BRXIF T5IE T1IE DMA4IE CMP2IE --
IC4EIF 0000 T4IE CTIE
1060
IEC0
31:16 I2C1MIE I2C1SIE 15:0 31:16 INT3IE IC3EIE RTCCIE -- -- -- -- -- -- OC3IE IC2EIE FSCMIE -- -- -- -- -- --
I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE IC3IE IC1EIE -- -- -- -- -- -- -- T3IE -- -- -- -- I2C1ABIE OC2IE CAN1IE U3ATXIE
0000
0000
DMA1IE DMA0IE 0000 AD1IE -- IC5EIE CNIE --
1070
IEC1
15:0 31:16 15:0 31:16 15:0 31:16 15:0
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE -- U3BEIE -- U2BTXIE -- U2BRXIE -- -- -- -- I2C2ABIE -- -- -- -- -- -- U3BRXIE
0000
1080 1090 10A0 Legend:
IEC2 IPC0 IPC1
0000
U1BTXIE U1BRXIE
IC4EIE 0000 0000 0000 0000 0000
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Note 1:
TABLE 4-2:
Virtual Address (BF88_#) Bit Range Register Name
INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES(1) (CONTINUED)
Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2010 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10B0 10C0 10D0 10E0
IPC2 IPC3 IPC4 IPC5
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> -- IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> U2AIP<2:0> --
INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> -- -- IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0> -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0> SPI1AIP<2:0> I2C1AIP<2:0>
OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> CAN1IS<1:0> FCEIS<1:0> U2BIS<1:0> -- -- --
10F0
IPC6
15:0
Preliminary
DS61156C-page 51
1100
IPC7
31:16 15:0 31:16
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- --
SPI2AIP<2:0> I2C2AIP<2:0> CMP1IP<2:0> RTCCIP<2:0> -- DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> -- USBIP<2:0> U3BIP<2:0> U1BIP<2:0> --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> CAN1IP<2:0> FCEIP<2:0> U2BIP<2:0> --
PIC32MX5XX/6XX/7XX
0000 0000
1110
IPC8
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
0000
1120 1130 1140 1150
IPC9 IPC10 IPC11 IPC12
DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0> -- -- USBIS<1:0> U3BIS<1:0> U1BIS<1:0>
0000 0000 0000 0000 0000 0000 0000 0000
Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Virtual Address (BF88_#)
DS61156C-page 52
PIC32MX5XX/6XX/7XX
TABLE 4-3:
INTERRUPT REGISTER MAP FOR THE PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES(1)
Bits All Resets
0000 0000 0000 0000 0000 0000 OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF -- U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF -- U1BRXIF T5IE T1IE DMA4IE CMP2IE -- U1BRXIE CMP1IF -- U1BEIF INT4IE INT0IE DMA3IE CMP1IE -- U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> PMPIF -- PMPEIF OC4IE CS1IE DMA2IE PMPIE -- PMPEIE AD1IF -- IC5EIF IC4IE CS0IE DMA1IE AD1IE -- IC5EIE CNIF -- IC4EIF T4IE CTIE DMA0IE CNIE -- IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2C2ABIF -- U1BTXIF IC5IE IC1IE DMA5IE U2AEIE I2C2ABIE -- U1BTXIE -- -- -- -- -- -- -- -- T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON 1010 INTSTAT 1020 IPTMR
31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- --
-- FRZ -- --
-- -- -- --
-- MVEC -- --
-- -- -- --
-- --
-- TPC<2:0> -- RIPL<2:0>
-- --
-- -- -- --
-- -- -- --
-- -- --
-- INT4EP --
-- INT3EP --
-- INT2EP --
-- INT1EP --
SS0 INT0EP --
VEC<5:0>
IPTMR<31:0> U1ATXIF U1ARXIF U1AEIF -- IC2IF USBIF U3ARXIF I2C3ASIF -- U3BEIF -- IC2IE USBIE U3ARXIE -- T2IF FCEIF U3AEIF I2C3ASIF -- U2BTXIF -- T2IE FCEIE U3AEIE -- INT1IF DMA7IF U2ATXIF I2C2AMIF -- U2BRXIF -- INT1IE DMA7IE U2ATXIE I2C1ABIF OC2IF -- U3ATXIF
1030
IFS0
31:16 15:0 31:16
I2C1MIF INT3IF IC3EIF RTCCIF -- --
I2CSIF OC3IF IC2EIF FSCMIF -- -- I2C1SIE OC3IE IC2EIE FSCMIE -- -- -- -- -- -- -- -- -- --
I2CBIF IC3IF IC1EIF --
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF I2C1ASIF T3IF ETHIF -- INT2IF -- -- --
1040
IFS1
Preliminary
2010 Microchip Technology Inc.
15:0 31:16 15:0
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF -- U3BRXIF U1AEIE I2C1ABIE OC2IE -- U3ATXIE
1050
IFS2
-- I2C1BIE IC3IE IC1EIE -- -- -- -- -- -- -- -- -- -- --
-- U1ATXIE
U3BTXIF U1ARXIE
1060
IEC0
31:16 I2C1MIE 15:0 31:16 INT3IE IC3EIE RTCCIE -- -- -- -- -- -- -- -- -- --
SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE T3IE ETHIE -- -- -- INT2IE -- -- -- U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0>
1070
IEC1
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE -- U2BTXIE -- U2BRXIE -- -- -- -- -- -- -- -- -- U2BEIE -- -- -- -- -- -- -- -- -- U3BRXIE -- U3BEIE
1080 1090 10A0 10B0 10C0 Legend: Note 1:
IEC2 IPC0 IPC1 IPC2 IPC3
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-3:
Virtual Address (BF88_#)
INTERRUPT REGISTER MAP FOR THE PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES(1) (CONTINUED)
Bits All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2010 Microchip Technology Inc.
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10D0 10E0
IPC4 IPC5
31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- -- --
INT4IP<2:0> IC4IP<2:0> -- IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> U2AIP<2:0> --
INT4IS<1:0> IC4IS<1:0> -- -- IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0> -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0> SPI1AIP<2:0> I2C1AIP<2:0>
OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> -- -- -- FCEIS<1:0> U2BIS<1:0> ETHIS<1:0>
10F0
IPC6
15:0
1100
IPC7
31:16 15:0
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- --
SPI2AIP<2:0> I2C2AIP<2:0> CMP1IP<2:0> RTCCIP<2:0> -- DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> -- USBIP<2:0> U3BIP<2:0> U1BIP<2:0> --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> -- FCEIP<2:0> U2BIP<2:0> ETHIP<2:0>
Preliminary
DS61156C-page 53
31:16 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
PIC32MX5XX/6XX/7XX
1120 1130 1140 1150 Legend: Note 1:
IPC9 IPC10 IPC11 IPC12
DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0> -- -- USBIS<1:0> U3BIS<1:0> U1BIS<1:0>
0000 0000 0000 0000 0000 0000 0000 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Virtual Address (BF88_#)
DS61156C-page 54
PIC32MX5XX/6XX/7XX
TABLE 4-4:
INTERRUPT REGISTER MAP FOR PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits All Resets
0000 0000 0000 0000 0000 0000 OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF -- U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF -- U1BRXIF T5IE T1IE DMA4IE CMP2IE -- U1BRXIE CMP1IF -- U1BEIF INT4IE INT0IE DMA3IE CMP1IE -- U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> PMPIF -- PMPEIF OC4IE CS1IE DMA2IE PMPIE -- PMPEIE AD1IF -- IC5EIF IC4IE CS0IE DMA1IE AD1IE -- IC5EIE CNIF -- IC4EIF T4IE CTIE DMA0IE CNIE -- IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2C2ABIF -- U1BTXIF IC5IE IC1IE DMA5IE U2AEIE I2C2ABIE -- U1BTXIE -- -- -- -- -- -- -- -- T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON 1010 INTSTAT 1020 IPTMR
31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- --
-- FRZ -- --
-- -- -- --
-- MVEC -- --
-- -- -- --
-- --
-- TPC<2:0> -- RIPL<2:0>
-- --
-- -- -- --
-- -- -- --
-- -- --
-- INT4EP --
-- INT3EP --
-- INT2EP --
-- INT1EP --
SS0 INT0EP --
VEC<5:0>
IPTMR<31:0> U1ATXIF U1ARXIF I2C1ASIF INT2IF CAN2IF -- -- U3BTXIF U1ARXIE U1AEIF -- IC2IF USBIF U3ARXIF I2C3ASIF -- U3BEIF -- IC2IE USBIE U3ARXIE -- T2IF FCEIF U3AEIF I2C3ASIF -- U2BTXIF -- T2IE FCEIE U3AEIE -- INT1IF DMA7IF U2ATXIF I2C2AMIF -- U2BRXIF -- INT1IE DMA7IE U2ATXIE I2C1ABIF OC2IF CAN1IF U3ATXIF
1030
IFS0
31:16 15:0 31:16
I2C1MIF INT3IF IC3EIF RTCCIF -- -- I2C1MIE INT3IE IC3EIE RTCCIE -- -- -- -- -- -- -- -- -- --
I2CSIF OC3IF IC2EIF FSCMIF -- -- I2C1SIE OC3IE IC2EIE FSCMIE -- -- -- -- -- -- -- -- -- --
I2CBIF IC3IF IC1EIF -- -- -- I2C1BIE IC3IE IC1EIE -- -- -- -- -- -- -- -- -- -- --
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF T3IF ETHIF -- -- -- U1ATXIE
1040
IFS1
Preliminary
2010 Microchip Technology Inc.
15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF -- U3BRXIF U1AEIE I2C1ABIE OC2IE CAN1IE U3ATXIE
1050
IFS2
1060
IEC0
SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE T3IE ETHIE -- -- -- INT2IE CAN2IE -- -- U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0>
1070
IEC1
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE -- U2BTXIE -- U2BRXIE -- -- -- -- -- -- -- -- -- U2BEIE -- -- -- -- -- -- -- -- -- U3BRXIE -- U3BEIE
1080 1090 10A0 10B0 10C0 Legend: Note 1:
IEC2 IPC0 IPC1 IPC2 IPC3
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-4:
Virtual Address (BF88_#)
INTERRUPT REGISTER MAP FOR PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) (CONTINUED)
Bits All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2010 Microchip Technology Inc.
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10D0 10E0
IPC4 IPC5
31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- -- --
INT4IP<2:0> IC4IP<2:0> -- IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> U2AIP<2:0> --
INT4IS<1:0> IC4IS<1:0> -- -- IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0> -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0> SPI1AIP<2:0> I2C1AIP<2:0>
OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> CAN1IS<1:0> FCEIS<1:0> U2BIS<1:0> ETHIS<1:0>
10F0
IPC6
15:0
1100
IPC7
31:16 15:0
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
SPI2AIP<2:0> I2C2AIP<2:0> CMP1IP<2:0> RTCCIP<2:0> -- DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> CAN2IP<2:0> USBIP<2:0> U3BIP<2:0> U1BIP<2:0>
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> CAN1IP<2:0> FCEIP<2:0> U2BIP<2:0> ETHIP<2:0>
Preliminary
DS61156C-page 55
31:16 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
PIC32MX5XX/6XX/7XX
1120 1130 1140 1150 Legend: Note 1:
IPC9 IPC10 IPC11 IPC12
DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0> CAN2IS<1:0> USBIS<1:0> U3BIS<1:0> U1BIS<1:0>
0000 0000 0000 0000 0000 0000 0000 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-5:
Virtual Address (BF88_#) Bit Range Register Name
INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES(1)
Bits All Resets
DS61156C-page 56
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON 1010 INTSTAT 1020 IPTMR
31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- --
-- FRZ -- --
-- -- -- --
-- MVEC -- --
-- -- -- --
-- --
-- TPC<2:0> -- RIPL<2:0>
-- --
-- -- -- --
-- -- -- --
-- -- --
-- INT4EP --
-- INT3EP --
-- INT2EP --
-- INT1EP --
SS0 INT0EP --
0000 0000 0000 0000 0000 0000
VEC<5:0>
IPTMR<31:0> U1ATXIF U1ARXIF I2C1ASIF INT2IF -- I2C2BIF -- U3BTXIF U1ARXIE U1AEIF SPI1TXIF IC2IF USBIF U3ARXIF I2C3ASIF -- U3BEIF SPI1RXIF T2IF FCEIF U3AEIF I2C3ASIF -- U2BTXIF SPI1EIF INT1IF DMA7IF U2ATXIF I2C2AMIF -- U2BRXIF SPI1EIE INT1IE DMA7IE U2ATXIE OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF -- U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF -- U1BRXIF T5IE T1IE DMA4IE CMP2IE -- U1BRXIE CMP1IF -- U1BEIF INT4IE INT0IE DMA3IE CMP1IE -- U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> PMPIF -- PMPEIF OC4IE CS1IE DMA2IE PMPIE -- PMPEIE AD1IF -- IC5EIF IC4IE CS0IE DMA1IE AD1IE -- IC5EIE CNIF -- IC4EIF T4IE CTIE DMA0IE CNIE -- IC4EIE T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF
1030
IFS0
31:16 15:0 31:16
I2C1MIF INT3IF IC3EIF RTCCIF -- -- I2C1MIE INT3IE IC3EIE RTCCIE -- -- -- -- -- -- -- -- -- -- -- --
I2CSIF OC3IF IC2EIF FSCMIF -- -- I2C1SIE OC3IE IC2EIE FSCMIE -- -- -- -- -- -- -- -- -- -- -- --
I2CBIF IC3IF IC1EIF I2C2MIF -- -- I2C1BIE IC3IE IC1EIE I2C2MIE -- -- -- -- -- -- -- -- -- -- -- --
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF T3IF -- I2C2SIF -- -- U1ATXIE I2C1ABIF OC2IF CAN1IF U3ATXIF
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
1040
IFS1
15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF I2C2ABIF -- U1BTXIF IC5IE IC1IE DMA5IE U2AEIE I2C2ABIE -- U1BTXIE -- -- -- -- -- -- -- -- -- -- -- U3BRXIF U1AEIE SPI1TXIE SPI1RXIE IC2IE USBIE U3ARXIE T2IE FCEIE U3AEIE I2C1ABIE OC2IE CAN1IE U3ATXIE
Preliminary
2010 Microchip Technology Inc.
1050
IFS2
1060
IEC0
SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE T3IE -- I2C2SIE -- -- INT2IE -- I2C2BIE -- U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0>
1070
IEC1
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE -- U3BRXIE -- U3BEIE -- U2BTXIE -- U2BRXIE -- -- -- -- -- -- -- -- -- -- -- U2BEIE -- -- -- -- -- -- -- -- -- --
1080 1090 10A0 10B0 10C0 10D0 Legend: Note 1:
IEC2 IPC0 IPC1 IPC2 IPC3 IPC4
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-5:
Virtual Address (BF88_#) Bit Range Register Name
INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES(1) (CONTINUED)
Bits All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2010 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10E0
IPC5
31:16 15:0 31:16
-- -- -- --
-- -- -- --
-- -- -- --
SPI1IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> U2AIP<2:0>
SPI1IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0> -- -- -- USBIS<1:0> U3BIS<1:0> U1BIS<1:0>
-- -- -- --
-- -- -- --
-- -- -- --
OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0> SPI1AIP<2:0> I2C1AIP<2:0>
OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> CAN1IS<1:0> FCEIS<1:0> U2BIS<1:0> -- -- --
10F0
IPC6
15:0
1100
IPC7
31:16 15:0 31:16
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
SPI2AIP<2:0> I2C2AIP<2:0> CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> -- USBIP<2:0> U3BIP<2:0> U1BIP<2:0>
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> CAN1IP<2:0> FCEIP<2:0> U2BIP<2:0> --
1110
IPC8
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
Preliminary
DS61156C-page 57
1120 1130 1140 1150 Legend: Note 1:
IPC9 IPC10 IPC11 IPC12
PIC32MX5XX/6XX/7XX
0000 0000 0000 0000 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Virtual Address (BF88_#)
DS61156C-page 58
PIC32MX5XX/6XX/7XX
TABLE 4-6:
INTERRUPT REGISTER MAP FOR PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES(1)
Bits All Resets
0000 0000 0000 0000 0000 0000 OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF -- U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF -- U1BRXIF T5IE T1IE DMA4IE CMP2IE -- U1BRXIE CMP1IF -- U1BEIF INT4IE INT0IE DMA3IE CMP1IE -- U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> PMPIF -- PMPEIF OC4IE CS1IE DMA2IE PMPIE -- PMPEIE AD1IF -- IC5EIF IC4IE CS0IE DMA1IE AD1IE -- IC5EIE CNIF -- IC4EIF T4IE CTIE DMA0IE CNIE -- IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2C2ABIF -- U1BTXIF IC5IE IC1IE DMA5IE U2AEIE I2C2ABIE -- U1BTXIE -- -- -- -- -- -- -- -- T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON 1010 INTSTAT 1020 IPTMR
31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- --
-- FRZ -- --
-- -- -- --
-- MVEC -- --
-- -- -- --
-- --
-- TPC<2:0> -- RIPL<2:0>
-- --
-- -- -- --
-- -- -- --
-- -- --
-- INT4EP --
-- INT3EP --
-- INT2EP --
-- INT1EP --
SS0 INT0EP --
VEC<5:0>
IPTMR<31:0> U1ATXIF U1ARXIF U1AEIF SPI1TXIF IC2IF USBIF U3ARXIF I2C3ASIF -- U3BEIF SPI1RXIF T2IF FCEIF U3AEIF I2C3ASIF -- U2BTXIF SPI1EIF INT1IF DMA7IF U2ATXIF I2C2AMIF -- U2BRXIF SPI1EIE INT1IE DMA7IE U2ATXIE I2C1ABIF OC2IF -- U3ATXIF
1030
IFS0
31:16 15:0 31:16
I2C1MIF INT3IF IC3EIF RTCCIF -- -- I2C1MIE INT3IE IC3EIE RTCCIE -- -- -- -- -- -- -- -- -- --
I2CSIF OC3IF IC2EIF FSCMIF -- -- I2C1SIE OC3IE IC2EIE FSCMIE -- -- -- -- -- -- -- -- -- --
I2CBIF IC3IF IC1EIF I2C2MIF -- -- I2C1BIE IC3IE IC1EIE I2C2MIE -- -- -- -- -- -- -- -- -- --
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF I2C1ASIF T3IF ETHIF I2C2SIF -- -- U1ATXIE INT2IF -- I2C2BIF -- U3BTXIF U1ARXIE
1040
IFS1
Preliminary
2010 Microchip Technology Inc.
15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF -- U3BRXIF U1AEIE I2C1ABIE OC2IE -- U3ATXIE IC2IE USBIE U3ARXIE T2IE FCEIE U3AEIE
1050
IFS2
1060
IEC0
SPI1ATXIE SPI1ARXIE SPI1AEIE SPI1TXIE SPI1RXIE I2C1AMIE I2C1ASIE T3IE ETHIE I2C2SIE -- -- INT2IE -- I2C2BIE -- U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0>
1070
IEC1
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE -- U2BTXIE -- U2BRXIE -- -- -- -- -- -- -- -- -- U2BEIE -- -- -- -- -- -- -- -- -- U3BRXIE -- U3BEIE
1080 1090 10A0 10B0 10C0 Legend: Note 1:
IEC2 IPC0 IPC1 IPC2 IPC3
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-6:
Virtual Address (BF88_#)
INTERRUPT REGISTER MAP FOR PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES(1) (CONTINUED)
Bits All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2010 Microchip Technology Inc.
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10D0 10E0
IPC4 IPC5
31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
INT4IP<2:0> IC4IP<2:0> SPI1IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> U2AIP<2:0>
INT4IS<1:0> IC4IS<1:0> SPI1IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0> -- -- -- USBIS<1:0> U3BIS<1:0> U1BIS<1:0>
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0> SPI1AIP<2:0> I2C1AIP<2:0>
OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> -- -- -- FCEIS<1:0> U2BIS<1:0> ETHIS<1:0>
10F0
IPC6
15:0
1100
IPC7
31:16 15:0
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
SPI2AIP<2:0> I2C2AIP<2:0> CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> -- USBIP<2:0> U3BIP<2:0> U1BIP<2:0>
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> -- FCEIP<2:0> U2BIP<2:0> ETHIP<2:0>
Preliminary
DS61156C-page 59
31:16 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
PIC32MX5XX/6XX/7XX
1120 1130 1140 1150 Legend: Note 1:
IPC9 IPC10 IPC11 IPC12
0000 0000 0000 0000 0000 0000 0000 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Virtual Address (BF88_#)
DS61156C-page 60
PIC32MX5XX/6XX/7XX
TABLE 4-7:
INTERRUPT REGISTER MAP FOR PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits All Resets
0000 0000 0000 0000 0000 0000 OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF -- U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF -- U1BRXIF T5IE T1IE DMA4IE CMP2IE -- U1BRXIE CMP1IF -- U1BEIF INT4IE INT0IE DMA3IE CMP1IE -- U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> PMPIF -- PMPEIF OC4IE CS1IE DMA2IE PMPIE -- PMPEIE AD1IF -- IC5EIF IC4IE CS0IE DMA1IE AD1IE -- IC5EIE CNIF -- IC4EIF T4IE CTIE DMA0IE CNIE -- IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2C2ABIF -- U1BTXIF IC5IE IC1IE DMA5IE U2AEIE I2C2ABIE -- U1BTXIE -- -- -- -- -- -- -- -- T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON 1010 INTSTAT 1020 IPTMR
31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- --
-- FRZ -- --
-- -- -- --
-- MVEC -- --
-- -- -- --
-- --
-- TPC<2:0> -- RIPL<2:0>
-- --
-- -- -- --
-- -- -- --
-- -- --
-- INT4EP --
-- INT3EP --
-- INT2EP --
-- INT1EP --
SS0 INT0EP --
VEC<5:0>
IPTMR<31:0> U1ATXIF U1ARXIF I2C1ASIF INT2IF CAN2IF I2C2BIF -- U3BTXIF U1ARXIE U1AEIF SPI1TXIF IC2IF USBIF U3ARXIF I2C3ASIF -- U3BEIF SPI1RXIF T2IF FCEIF U3AEIF I2C3ASIF -- U2BTXIF SPI1EIF INT1IF DMA7IF U2ATXIF I2C2AMIF -- U2BRXIF SPI1EIE INT1IE DMA7IE U2ATXIE I2C1ABIF OC2IF CAN1IF U3ATXIF
1030
IFS0
31:16 15:0 31:16
I2C1MIF INT3IF IC3EIF RTCCIF -- -- I2C1MIE INT3IE IC3EIE RTCCIE -- -- -- -- -- -- -- -- -- --
I2CSIF OC3IF IC2EIF FSCMIF -- -- I2C1SIE OC3IE IC2EIE FSCMIE -- -- -- -- -- -- -- -- -- --
I2CBIF IC3IF IC1EIF I2C2MIF -- -- I2C1BIE IC3IE IC1EIE I2C2MIE -- -- -- -- -- -- -- -- -- --
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF T3IF ETHIF I2C2SIF -- -- U1ATXIE
1040
IFS1
Preliminary
2010 Microchip Technology Inc.
15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF -- U3BRXIF U1AEIE SPI1TXIE SPI1RXIE IC2IE USBIE U3ARXIE T2IE FCEIE U3AEIE
1050
IFS2
1060
IEC0
SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE I2C1ABIE T3IE ETHIE I2C2SIE -- -- INT2IE CAN2IE I2C2BIE -- U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0> OC2IE CAN1IE U3ATXIE
1070
IEC1
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE -- U2BTXIE -- U2BRXIE -- -- -- -- -- -- -- -- -- U2BEIE -- -- -- -- -- -- -- -- -- U3BRXIE -- U3BEIE
1080 1090 10A0 10B0 10C0 Legend: Note 1:
IEC2 IPC0 IPC1 IPC2 IPC3
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-7:
Virtual Address (BF88_#)
INTERRUPT REGISTER MAP FOR PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Bits All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2010 Microchip Technology Inc.
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10D0 10E0
IPC4 IPC5
31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
INT4IP<2:0> IC4IP<2:0> SPI1IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> U2AIP<2:0>
INT4IS<1:0> IC4IS<1:0> SPI1IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0> CAN2IS<1:0> USBIS<1:0> U3BIS<1:0> U1BIS<1:0>
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0> SPI1AIP<2:0> I2C1AIP<2:0>
OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> CAN1IS<1:0> FCEIS<1:0> U2BIS<1:0> ETHIS<1:0>
10F0
IPC6
15:0
1100
IPC7
31:16 15:0
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
SPI2AIP<2:0> I2C2AIP<2:0> CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> CAN2IP<2:0> USBIP<2:0> U3BIP<2:0> U1BIP<2:0>
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> CAN1IP<2:0> FCEIP<2:0> U2BIP<2:0> ETHIP<2:0>
Preliminary
DS61156C-page 61
31:16 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
PIC32MX5XX/6XX/7XX
1120 1130 1140 1150 Legend: Note 1:
IPC9 IPC10 IPC11 IPC12
0000 0000 0000 0000 0000 0000 0000 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-8:
Virtual Address (BF80_#) Bit Range Register Name
TIMER1-TIMER5 REGISTER MAP(1)
Bits All Resets
DS61156C-page 62
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
0600 T1CON 0610 0620 TMR1 PR1
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- -- -- ON -- -- -- ON -- -- -- ON -- -- -- ON -- --
-- FRZ -- -- -- FRZ -- -- -- FRZ -- -- -- FRZ -- -- -- FRZ -- --
-- SIDL -- -- -- SIDL -- -- -- SIDL -- -- -- SIDL -- -- -- SIDL -- --
-- TWDIS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- TWIP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- TGATE -- -- -- TGATE -- -- -- TGATE -- -- -- TGATE -- -- -- TGATE -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- TCKPS<2:0> -- -- -- TCKPS<2:0> -- -- -- TCKPS<2:0> -- -- -- TCKPS<2:0> -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- T32 -- -- -- -- -- -- -- T32 -- -- -- -- -- --
-- TSYNC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- TCS -- -- -- TCS -- -- -- TCS -- -- -- TCS -- -- -- TCS -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF
TCKPS<1:0>
TMR1<15:0> PR1<15:0>
0800 T2CON 0810 0820 TMR2 PR2
TMR2<15:0> PR2<15:0>
0A00 T3CON 0A10 0A20 TMR3 PR3
Preliminary
2010 Microchip Technology Inc.
TMR3<15:0> PR3<15:0>
0C00 T4CON 0C10 0C20 TMR4 PR4
TMR4<15:0> PR4<15:0>
0E00 T5CON 0E10 0E20 Legend: Note 1: TMR5 PR5
TMR5<15:0> PR5<15:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
2010 Microchip Technology Inc.
TABLE 4-9:
Virtual Address (BF80_#) Register Name
INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP
Bits All Resets
0000 0000 xxxx xxxx -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- 0000 0000 xxxx xxxx -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- 0000 0000 xxxx xxxx -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- 0000 0000 xxxx xxxx -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- 0000 0000 xxxx xxxx
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
2000 2010 2200 2210 2400 2410 2600 2610 2800 2810
IC1CON(1) IC1BUF IC2CON(1) IC2BUF IC3CON
(1)
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- ON
-- FRZ
-- SIDL
-- --
-- --
-- --
-- FEDGE
-- C32
-- ICTMR
-- ICI<1:0>
--
-- ICOV
-- ICBNE
--
-- ICM<2:0>
--
IC1BUF<31:0> -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR
IC2BUF<31:0> -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR
IC3BUF IC4CON
(1)
IC3BUF<31:0> -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR
Preliminary
DS61156C-page 63
IC4BUF IC5CON(1) IC5BUF
IC4BUF<31:0> -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR
PIC32MX5XX/6XX/7XX
IC5BUF<31:0>
Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-10:
Virtual Address (BF80_#) Bit Range Register Name
OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP(1)
Bits All Resets
DS61156C-page 64
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3000 OC1CON 3010 3020 OC1R OC1RS
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- ON
-- FRZ
-- SIDL
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- OC32
-- OCFLT
-- OCTSEL
--
-- OCM<2:0>
--
0000 0000 xxxx xxxx xxxx xxxx
OC1R<31:0> OC1RS<31:0> -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> --
3200 OC2CON 3210 3220 OC2R OC2RS
0000 0000 xxxx xxxx xxxx xxxx
OC2R<31:0> OC2RS<31:0> -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> --
3400 OC3CON 3410 3420 OC3R OC3RS
0000 0000 xxxx xxxx xxxx xxxx
Preliminary
2010 Microchip Technology Inc.
OC3R<31:0> OC3RS<31:0> -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> --
3600 OC4CON 3610 3620 OC4R OC4RS
0000 0000 xxxx xxxx xxxx xxxx
OC4R<31:0> OC4RS<31:0> -- ON -- FRZ -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> --
3800 OC5CON 3810 3820 Legend: Note 1: OC5R OC5RS
0000 0000 xxxx xxxx xxxx xxxx
OC5R<31:0> OC5RS<31:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-11:
Virtual Address (BF80_#) Register Name
I2C1, I2C1A, I2C2A AND I2C3A REGISTER MAP(1)
Bits All Resets
0000 0000 0000 0000 0000 0000 -- -- -- -- -- RCEN -- S -- -- -- -- -- -- RCEN -- S -- -- -- -- -- PEN -- R/W -- -- -- -- -- -- PEN -- R/W -- -- -- -- -- RSEN -- RBF -- -- -- -- -- -- RSEN -- RBF -- -- -- -- -- SEN -- TBF -- -- -- -- -- -- SEN -- TBF 0000 0000 0000 0000 -- -- -- ACKEN -- P -- -- -- -- -- -- ACKEN -- P 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2CT1DATA<7:0> -- -- GCEN -- IWCOL -- -- STREN -- I2COV -- -- ACKDT -- D/A I2CR1DATA<7:0> I2CT1DATA<7:0> -- -- GCEN -- IWCOL -- -- -- -- -- -- STREN -- I2COV -- -- -- -- -- -- ACKDT -- D/A -- -- -- -- ADD<9:0> -- -- -- -- -- -- -- DISSLW -- GCSTAT -- -- -- -- -- -- -- SMEN -- ADD10 MSK<9:0> I2C1BRG<11:0> -- -- -- -- -- STRICT -- -- -- -- -- -- -- A10M -- BCL I2CR1DATA<7:0>
2010 Microchip Technology Inc.
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5000 I2C1ACON 5010 I2C1ASTAT 5020 I2C1AADD 5030 I2C1AMSK 5040 I2C1ABRG 5050 I2C1ATRN
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- ACKSTAT -- -- -- -- -- -- -- -- -- -- -- ON -- ACKSTAT -- -- -- -- -- -- -- -- -- -- -- ON -- ACKSTAT
-- FRZ -- TRSTAT -- -- -- -- -- -- -- -- -- -- -- FRZ -- TRSTAT -- -- -- -- -- -- -- -- -- -- -- FRZ -- TRSTAT
-- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- SIDL -- --
-- SCLREL -- -- -- -- -- -- -- -- -- -- -- -- -- SCLREL -- -- -- -- -- -- -- -- -- -- -- -- -- SCLREL -- --
-- STRICT -- -- -- -- -- -- -- -- -- -- -- -- STRICT -- -- -- -- -- -- --
-- A10M -- BCL -- -- -- -- -- -- -- -- -- -- A10M -- BCL -- -- -- -- --
-- DISSLW -- GCSTAT -- -- -- -- -- -- -- -- DISSLW -- GCSTAT --
-- SMEN -- ADD10 -- -- -- -- -- -- -- -- SMEN -- ADD10 --
-- GCEN -- IWCOL -- -- -- --
-- STREN -- I2COV -- -- -- --
-- ACKDT -- D/A -- -- -- --
-- ACKEN -- P -- -- --
-- RCEN -- S --
-- PEN -- R/W --
-- RSEN -- RBF --
-- SEN -- TBF --
ADD<9:0> MSK<9:0> I2C1BRG<11:0>
5060 I2C1ARCV 5100 I2C2ACON 5110 I2C2ASTAT 5120 I2C2AADD 5130 I2C2AMSK 5140 I2C2ABRG 5150 I2C2ATRN
Preliminary
DS61156C-page 65
PIC32MX5XX/6XX/7XX
5160 I2C2ARCV 5200 I2C3ACON 5210 I2C3ASTAT Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-11:
Virtual Address (BF80_#) Register Name
I2C1, I2C1A, I2C2A AND I2C3A REGISTER MAP(1) (CONTINUED)
Bits All Resets Bit Range
DS61156C-page 66
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5220 I2C3AADD 5230 I2C3AMSK 5240 I2C3ABRG 5250 I2C3ATRN
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- -- -- -- -- -- -- ON -- ACKSTAT -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- FRZ -- TRSTAT -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- SCLREL -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- STRICT -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- A10M -- BCL -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- DISSLW -- GCSTAT -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- SMEN -- ADD10 -- -- -- -- -- -- --
-- -- -- -- -- -- GCEN -- IWCOL -- -- -- -- --
-- -- -- -- -- -- STREN -- I2COV -- -- -- -- --
-- -- -- -- -- -- ACKDT -- D/A -- -- -- -- --
-- -- -- -- -- -- ACKEN -- P -- -- -- -- --
-- -- -- -- -- -- RCEN -- S -- -- -- -- --
-- -- -- -- -- -- PEN -- R/W -- -- -- -- --
-- -- -- -- -- -- RSEN -- RBF -- -- -- -- --
-- -- -- -- -- -- SEN -- TBF -- -- -- -- --
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
ADD<9:0> MSK<9:0> I2C1BRG<11:0> I2CT1DATA<7:0> I2CR1DATA<7:0>
5260 I2C3ARCV 5300 5310 5320 5330 5340 5350 5360 Legend: Note 1: I2C1CON I2C1STAT I2C1ADD I2C1MSK I2C1BRG I2C1TRN I2C1RCV
Preliminary
2010 Microchip Technology Inc.
ADD<9:0> MSK<9:0> I2C1BRG<11:0> I2CT1DATA<7:0> I2CR1DATA<7:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
2010 Microchip Technology Inc.
TABLE 4-12:
Virtual Address (BF80_#)
I2C2 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits All Resets
0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 -- -- 0000 0000 0000 0000 I2CT1DATA<7:0> -- -- -- I2CR1DATA<7:0>
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5400 I2C2CON 5410 I2C2STAT 5420 I2C2ADD 5430 I2C2MSK 5440 I2C2BRG 5450 I2C2TRN
31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- -- -- -- -- -- -- -- -- -- --
-- FRZ -- TRSTAT -- -- -- -- -- -- -- -- -- --
-- SIDL -- -- -- -- -- -- -- -- -- -- -- --
-- SCLREL -- -- -- -- -- -- -- -- -- -- -- --
-- STRICT -- -- -- -- -- -- -- -- -- -- --
-- A10M -- BCL -- -- -- -- -- -- -- -- --
-- DISSLW -- GCSTAT -- -- -- -- -- -- --
-- SMEN -- ADD10 -- -- -- -- -- -- --
-- GCEN -- IWCOL -- -- -- --
-- STREN -- I2COV -- -- -- --
-- ACKDT -- D/A -- -- -- --
-- ACKEN -- P -- -- --
-- RCEN -- S --
-- PEN -- R/W --
-- RSEN -- RBF --
-- SEN -- TBF --
15:0 ACKSTAT
ADD<9:0> MSK<9:0> I2C2BRG<11:0>
Preliminary
DS61156C-page 67
5460 I2C2RCV Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
PIC32MX5XX/6XX/7XX
DS61156C-page 68
PIC32MX5XX/6XX/7XX
TABLE 4-13:
Virtual Address (BF80_#) Register Name
UART1A, UART1B, UART2A, UART2B, UART3A AND UART3B REGISTER MAP
Bits All Resets
0000 0000 0000 FERR -- -- -- -- OERR -- -- -- -- URXDA -- -- -- -- STSEL URXDA -- -- -- -- STSEL URXDA -- -- -- -- STSEL URXDA -- 0110 0000 0000 0000 0000 0000 0000 -- LPBACK -- ABAUD ADDEN -- -- -- -- ABAUD ADDEN -- -- -- -- ABAUD ADDEN -- -- RXINV RIDLE -- -- -- -- RXINV RIDLE -- -- -- -- RXINV RIDLE -- -- BRGH PERR -- -- -- -- BRGH PERR -- -- -- -- BRGH PERR -- 0000 0000 0000 FERR -- -- -- -- OERR -- -- -- -- 0110 0000 0000 0000 0000 0000 0000 -- LPBACK 0000 0000 0000 FERR -- -- -- -- OERR -- -- -- -- 0110 0000 0000 0000 0000 0000 0000 -- LPBACK 0000 0000 0000 FERR -- OERR -- 0110 0000 0000 PDSEL<1:0> PDSEL<1:0> PDSEL<1:0>
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6000 U1AMODE(1) 6010 U1ASTA
(1)
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- -- -- -- -- -- -- ON -- -- -- -- -- -- -- ON -- -- -- -- -- -- -- ON -- -- --
-- FRZ -- -- -- -- -- -- -- FRZ -- -- -- -- -- -- -- FRZ -- -- -- -- -- -- -- FRZ -- -- --
-- SIDL -- UTXINV -- -- -- -- -- -- SIDL -- UTXINV -- -- -- -- -- -- SIDL -- UTXINV -- -- -- -- -- -- SIDL -- UTXINV -- --
-- IREN -- URXEN -- -- -- -- -- -- IREN -- URXEN -- -- -- -- -- -- IREN -- URXEN -- -- -- -- -- -- IREN -- URXEN -- --
-- RTSMD -- UTXBRK -- -- -- -- -- -- -- -- UTXBRK -- -- -- -- -- -- RTSMD -- UTXBRK -- -- -- -- -- -- -- -- UTXBRK -- --
-- -- -- UTXEN -- -- -- -- -- -- -- -- UTXEN -- -- -- -- -- -- -- -- UTXEN -- -- -- -- -- -- -- -- UTXEN -- --
-- -- UTXBF -- -- -- -- -- -- -- -- UTXBF -- -- -- -- -- -- -- UTXBF -- -- -- -- -- -- -- -- UTXBF -- --
-- ADM_EN TRMT -- TX8 -- RX8 -- -- -- ADM_EN TRMT -- TX8 -- RX8 -- -- ADM_EN TRMT -- TX8 -- RX8 -- -- -- ADM_EN TRMT -- TX8
-- WAKE
-- LPBACK
-- ABAUD ADDEN -- -- --
-- RXINV RIDLE -- -- --
-- BRGH PERR -- -- --
--
--
-- STSEL
UEN<1:0>
PDSEL<1:0>
ADDR<7:0> URXISEL<1:0> -- -- -- -- WAKE -- -- --
UTXISEL<1:0>
6020 U1ATXREG 6030 U1ARXREG 6040 U1ABRG
(1)
Transmit Register Receive Register
BRG<15:0>
6200 U1BMODE 6210
(1)
U1BSTA(1)
ADDR<7:0> URXISEL<1:0> -- -- -- -- WAKE -- -- --
Preliminary
2010 Microchip Technology Inc.
UTXISEL<1:0>
6220 U1BTXREG 6230 U1BRXREG 6240 U1BBRG(1)
(1)
Transmit Register Receive Register
BRG<15:0> UEN<1:0>
6400 U2AMODE 6410 U2ASTA
(1)
ADDR<7:0> URXISEL<1:0> -- -- -- -- WAKE -- -- --
UTXISEL<1:0>
6420 U2ATXREG 6430 U2ARXREG 6440 U2ABRG 6600 6610
(1)
Transmit Register Receive Register
BRG<15:0>
U2BMODE(1) U2BSTA
(1)
ADDR<7:0> URXISEL<1:0> -- --
UTXISEL<1:0>
6620 U2BTXREG Legend: Note 1:
Transmit Register
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-13:
Virtual Address (BF80_#) Register Name
UART1A, UART1B, UART2A, UART2B, UART3A AND UART3B REGISTER MAP (CONTINUED)
Bits All Resets
0000 0000 -- -- -- -- -- -- STSEL URXDA -- -- -- -- STSEL URXDA -- -- -- 0000 0000 -- LPBACK -- ABAUD ADDEN -- -- -- -- ABAUD ADDEN -- -- -- -- RXINV RIDLE -- -- -- -- RXINV RIDLE -- -- -- -- BRGH PERR -- -- -- -- BRGH PERR -- -- -- 0000 0000 0000 FERR -- -- -- -- OERR -- -- -- -- 0110 0000 0000 0000 0000 0000 0000 -- LPBACK 0000 0000 0000 PDSEL<1:0> FERR -- -- -- OERR -- -- -- PDSEL<1:0>
2010 Microchip Technology Inc.
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6630 U2BRXREG 6640 U2BBRG
(1)
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- ON -- -- -- -- -- -- -- ON -- -- -- -- -- --
-- -- -- -- FRZ -- -- -- -- -- -- -- FRZ -- -- -- -- -- --
-- -- -- -- SIDL -- UTXINV -- -- -- -- -- -- SIDL -- UTXINV -- -- -- -- --
-- -- -- -- IREN -- URXEN -- -- -- -- -- -- IREN -- URXEN -- -- -- -- --
-- -- -- -- RTSMD -- UTXBRK -- -- -- -- -- -- -- -- UTXBRK -- -- -- -- --
-- -- -- -- -- -- UTXEN -- -- -- -- -- -- -- -- UTXEN -- -- -- -- --
-- -- -- -- -- UTXBF -- -- -- -- -- -- -- -- UTXBF -- -- -- -- --
-- RX8 -- -- ADM_EN TRMT -- TX8 -- RX8 -- -- -- ADM_EN TRMT -- TX8 -- RX8 --
-- -- -- WAKE
-- --
-- --
-- --
-- --
--
--
--
Receive Register
BRG<15:0> UEN<1:0>
6800 U3AMODE 6810
(1)
U3ASTA(1)
ADDR<7:0> URXISEL<1:0> -- -- -- -- WAKE -- -- --
UTXISEL<1:0>
6820 U3ATXREG 6830 U3ARXREG 6840 U3ABRG(1)
(1)
Transmit Register Receive Register
BRG<15:0>
Preliminary
DS61156C-page 69
6A00 U3BMODE 6A10 U3BSTA
(1)
ADDR<7:0> URXISEL<1:0> -- -- -- -- -- --
PIC32MX5XX/6XX/7XX
UTXISEL<1:0>
0110 0000 0000 0000 0000 0000 0000
6A20 U3BTXREG 6A30 U3BRXREG 6A40 U3BBRG Legend: Note 1:
(1)
Transmit Register Receive Register
BRG<15:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-14:
Virtual Address (BF80_#) Bit Range Register Name
SPI1A, SPI2A AND SPI3A REGISTER MAP(1)
Bits All Resets
DS61156C-page 70
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5800 SPI1ACON 5810 SPI1ASTAT 5820 SPI1ABUF 5830 SPI1ABRG 5A00 SPI2ACON 5A10 SPI2ASTAT 5A20 SPI2ABUF 5A30 SPI2ABRG 5C00 SPI3ACON 5C10 SPI3ASTAT 5C20 SPI3ABUF 5C30 SPI3ABRG Legend: Note 1:
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
FRMEN ON -- --
FRMSYNC FRMPOL FRZ -- -- SIDL -- --
MSSEN DISSDO --
FRMSYPW MODE32 SPIBUSY
FRMCNT<2:0> MODE16 -- SMP -- CKE SPITUR
-- SSEN -- SRMT
-- CKP -- SPIROV
-- MSTEN -- SPIRBE
-- -- --
--
-- TXBUFELM<4:0>
SPIFE
ENHBUF 0000 0000 0000 SPIRBF 0000 0000 0000
STXISEL<1:0> SPITBE --
SRXISEL<1:0> SPITBF
RXBUFELM<4:0>
DATA<31:0> -- -- FRMEN ON -- -- -- -- FRZ -- -- -- -- SIDL -- -- -- -- -- MSSEN DISSDO -- -- FRMSYPW MODE32 SPIBUSY -- -- MODE16 -- -- -- FRMCNT<2:0> SMP -- CKE SPITUR -- SSEN -- SRMT -- CKP -- SPIROV -- MSTEN -- SPIRBE -- -- -- -- -- -- BRG<8:0> -- -- -- -- TXBUFELM<4:0> SPITBE -- SPITBF SPIRBF SPIFE STXISEL<1:0> SRXISEL<1:0> -- -- -- --
0000 0000
FRMSYNC FRMPOL
ENHBUF 0000 0000 0000 0000 0000 0000
RXBUFELM<4:0>
DATA<31:0> -- -- FRMEN ON -- -- -- -- FRZ -- -- -- -- SIDL -- -- -- -- -- MSSEN DISSDO -- -- FRMSYPW MODE32 SPIBUSY -- -- MODE16 -- -- -- FRMCNT<2:0> SMP -- CKE SPITUR -- SSEN -- SRMT -- CKP -- SPIROV -- MSTEN -- SPIRBE -- -- -- -- -- -- BRG<8:0> -- -- -- -- TXBUFELM<4:0> SPITBE -- SPITBF SPIRBF SPIFE STXISEL<1:0> SRXISEL<1:0> -- -- -- --
Preliminary
2010 Microchip Technology Inc.
0000 0000
FRMSYNC FRMPOL
ENHBUF 0000 0000 0000 0000 0000 0000
RXBUFELM<4:0>
DATA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BRG<8:0> -- -- -- --
0000 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
2010 Microchip Technology Inc.
TABLE 4-15:
Virtual Address (BF80_#)
SPI1 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits All Resets
0000 0000 SPIRBF 0000 0000 0000 -- -- -- BRG<8:0> -- -- -- -- 0000 0000
Register Name
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5E00 SPI1CON 5E10 SPI1STAT 5E20 SPI1BUF
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
FRMEN ON -- --
FRMSYNC FRMPOL FRZ -- -- SIDL -- --
MSSEN DISSDO --
FRMSYPW MODE32 SPIBUSY
FRMCNT<2:0> MODE16 -- SMP -- CKE SPITUR
-- SSEN -- SRMT
-- CKP -- SPIROV
-- MSTEN -- SPIRBE
-- -- --
--
-- TXBUFELM<4:0>
SPIFE
ENHBUF 0000
STXISEL<1:0> SPITBE --
SRXISEL<1:0> SPITBF
RXBUFELM<4:0>
DATA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
5E30 SPI1BRG Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Preliminary
DS61156C-page 71
PIC32MX5XX/6XX/7XX
DS61156C-page 72
PIC32MX5XX/6XX/7XX
TABLE 4-16:
Virtual Address (BF80_#) Register Name Bit Range
ADC REGISTER MAP
Bits All Resets
0000 0000 0000 0000 0000 0000 CH0SA<3:0> -- -- PCFG3 -- CSSL3 -- -- PCFG2 -- CSSL2 -- -- PCFG1 -- CSSL1 -- -- PCFG0 -- CSSL0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
9000 AD1CON1(1) 9010 AD1CON2 9020 AD1CON3 9040
(1)
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- VCFG2 -- ADRC CH0NB -- -- PCFG15 -- CSSL15
-- FRZ -- VCFG1 -- -- -- -- -- PCFG14 -- CSSL14
-- SIDL -- VCFG0 -- -- -- -- -- PCFG13 -- CSSL13
-- -- -- OFFCAL -- -- -- -- PCFG12 -- CSSL12
-- -- -- -- --
-- -- CSCNA -- SAMC<4:0>
-- FORM<2:0> -- -- --
-- -- -- --
-- -- BUFS -- CH0NA
-- SSRC<2:0> -- -- -- -- -- -- PCFG6 -- CSSL6
-- -- -- -- -- -- PCFG5 -- CSSL5
-- CLRASAM -- -- -- -- -- PCFG4 -- CSSL4
-- -- -- --
-- ASAM -- --
-- SAMP -- BUFM --
-- DONE -- ALTS --
SMPI<3:0> ADCS<7:0>
(1)
AD1CHS(1)
CH0SB<3:0> -- -- PCFG11 -- CSSL11 -- -- PCFG10 -- CSSL10 -- -- PCFG9 -- CSSL9 -- -- PCFG8 -- CSSL8
-- -- PCFG7 -- CSSL7
9060 AD1PCFG(1) 9050 AD1CSSL
(1)
9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7
ADC Result Word 0 (ADC1BUF0<31:0>) ADC Result Word 1 (ADC1BUF1<31:0>) ADC Result Word 2 (ADC1BUF2<31:0>) ADC Result Word 3 (ADC1BUF3<31:0>) ADC Result Word 4 (ADC1BUF4<31:0>) ADC Result Word 5 (ADC1BUF5<31:0>) ADC Result Word 6 (ADC1BUF6<31:0>) ADC Result Word 7 (ADC1BUF7<31:0>) ADC Result Word 8 (ADC1BUF8<31:0>) ADC Result Word 9 (ADC1BUF9<31:0>) ADC Result Word A (ADC1BUFA<31:0>) ADC Result Word B (ADC1BUFB<31:0>)
Preliminary
2010 Microchip Technology Inc.
90F0 ADC1BUF8 9100 ADC1BUF9 9110 ADC1BUFA 9120 ADC1BUFB Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-16:
Virtual Address (BF80_#) Register Name Bit Range
ADC REGISTER MAP (CONTINUED)
Bits All Resets
0000 0000 0000 0000 0000 0000 0000 0000
2010 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF Legend: Note 1:
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>)
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Preliminary
DS61156C-page 73
PIC32MX5XX/6XX/7XX
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3030 DCRCCON 3040 DCRCDATA 3050 DCRCXOR Legend: Note 1:
31:16 15:0 31:16 15:0 31:16 15:0
-- --
-- --
BYTO<1:0> --
WBO
-- PLEN<4:0>
--
BITO
-- CRCEN
-- CRCAPP
-- CRCTYP
-- --
-- --
--
-- CRCCH<2:0>
--
0000 0000 0000 0000 0000 0000
DCRCDATA<31:0> DCRCXOR<31:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
All Resets
Bit Range
Register Name
DS61156C-page 74
PIC32MX5XX/6XX/7XX
TABLE 4-17:
Virtual Address (BF88_#) Register Name
DMA GLOBAL REGISTER MAP
Bits All Resets
0000 0000 0000 0000 0000 0000
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3000 DMACON(1) 3010 DMASTAT
31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- --
-- FRZ -- --
-- -- -- --
-- SUSPEND -- --
-- BUSY -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- RDWR
-- -- --
-- -- -- DMACH<2:0>
-- -- --
3020 DMAADDR Legend: Note 1:
DMAADDR<31:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-18:
DMA CRC REGISTER MAP(1)
Bits
Preliminary
2010 Microchip Technology Inc.
TABLE 4-19:
Virtual Address (BF88_#) Register Name
DMA CHANNELS 0-7 REGISTER MAP(1)
Bits All Resets
0000 0000 00FF -- CHCCIE CHCCIF -- CHTAIE CHTAIF -- CHERIE CHERIF FF00 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- CHAED CABORT CHSHIE CHSHIF -- -- -- -- -- -- -- -- CHCHN PATEN CHDDIE CHDDIF -- -- -- -- -- -- -- -- CHAEN SIRQEN CHDHIE CHDHIF -- -- -- -- -- -- -- -- -- AIRQEN CHBCIE CHBCIF -- -- -- -- -- -- -- -- CHEDET -- CHCCIE CHCCIF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF -- CHTAIE CHTAIF -- CHERIE CHERIF FF00 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- 0000 0000 CHPRI<1:0> CHPDAT<7:0> -- CHEN CFORCE -- -- -- -- -- -- CHSDIE CHSDIF
2010 Microchip Technology Inc.
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3060 DCH0CON 3070 DCH0ECON 3080 3090 DCH0INT DCH0SSA
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- CHBUSY -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- CHCHNS --
-- CHEN CFORCE
-- CHAED CABORT CHSHIE CHSHIF
-- CHCHN PATEN CHDDIE CHDDIF
-- CHAEN SIRQEN CHDHIE CHDHIF
-- -- AIRQEN CHBCIE CHBCIF
-- CHEDET
--
--
CHPRI<1:0>
CHAIRQ<7:0> CHSDIE CHSDIF
CHSIRQ<7:0> -- --
CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- -- CHBUSY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- -- -- -- -- -- -- --
30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR 3110 DCH0DAT
CHSSIZ<15:0> CHDSIZ<15:0> CHSPTR<15:0> CHDPTR<15:0> CHCSIZ<15:0> CHCPTR<15:0>
Preliminary
DS61156C-page 75
PIC32MX5XX/6XX/7XX
3120 DCH1CON 3130 DCH1ECON 3140 3150 DCH1INT DCH1SSA
CHAIRQ<7:0>
CHSIRQ<7:0>
CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- --
3160 DCH1DSA 3170 DCH1SSIZ Legend: Note 1:
CHSSIZ<15:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-19:
Virtual Address (BF88_#) Register Name
DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits All Resets Bit Range
DS61156C-page 76
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3200 3210 DCH2INT DCH2SSA
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- -- -- -- CHBUSY -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- CHCHNS --
-- -- -- -- -- -- -- CHEN CFORCE
-- -- -- -- -- -- -- CHAED CABORT CHSHIE CHSHIF
-- -- -- -- -- -- -- CHCHN PATEN CHDDIE CHDDIF
-- -- -- -- -- -- -- CHAEN SIRQEN CHDHIE CHDHIF
-- -- -- -- -- -- -- -- AIRQEN CHBCIE CHBCIF
-- -- -- -- -- -- -- CHEDET -- CHCCIE CHCCIF
-- -- -- -- -- -- --
-- -- -- -- -- -- --
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000
CHDSIZ<15:0> CHSPTR<15:0> CHDPTR<15:0> CHCSIZ<15:0> CHCPTR<15:0> CHPDAT<7:0> CHPRI<1:0> -- CHTAIE CHTAIF -- CHERIE CHERIF
Preliminary
2010 Microchip Technology Inc.
CHAIRQ<7:0> CHSDIE CHSDIF
CHSIRQ<7:0> -- --
CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
3220 DCH2DSA 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR 3260 DCH2DPTR 3270 DCH2CSIZ 3280 DCH2CPTR 3290 DCH2DAT
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
CHSSIZ<15:0> CHDSIZ<15:0> CHSPTR<15:0> CHDPTR<15:0> CHCSIZ<15:0> CHCPTR<15:0> CHPDAT<7:0>
Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-19:
Virtual Address (BF88_#) Register Name
DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits All Resets
0000 0000 00FF -- CHCCIE CHCCIF -- CHTAIE CHTAIF -- CHERIE CHERIF FF00 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- CHAED CABORT CHSHIE CHSHIF -- -- -- -- -- -- -- -- CHCHN PATEN CHDDIE CHDDIF -- -- -- -- -- -- -- -- CHAEN SIRQEN CHDHIE CHDHIF -- -- -- -- -- -- -- -- -- AIRQEN CHBCIE CHBCIF -- -- -- -- -- -- -- -- CHEDET -- CHCCIE CHCCIF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 0000
2010 Microchip Technology Inc.
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
32A0 DCH3CON 32B0 DCH3ECON 32C0 DCH3INT
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- CHBUSY -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- CHCHNS --
-- CHEN CFORCE
-- CHAED CABORT CHSHIE CHSHIF
-- CHCHN PATEN CHDDIE CHDDIF
-- CHAEN SIRQEN CHDHIE CHDHIF
-- -- AIRQEN CHBCIE CHBCIF
-- CHEDET
--
--
CHPRI<1:0>
CHAIRQ<7:0> CHSDIE CHSDIF
CHSIRQ<7:0> -- --
32D0 DCH3SSA 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ 3340 DCH3CPTR 3350 DCH3DAT
CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- -- CHBUSY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- CFORCE -- -- CHSDIE CHSDIF -- CHEN -- -- -- -- -- -- --
CHSSIZ<15:0> CHDSIZ<15:0> CHSPTR<15:0> CHDPTR<15:0> CHCSIZ<15:0> CHCPTR<15:0> CHPDAT<7:0> CHPRI<1:0> -- CHTAIE CHTAIF -- CHERIE CHERIF
Preliminary
DS61156C-page 77
PIC32MX5XX/6XX/7XX
0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- 0000 0000
3360 DCH4CON 3370 DCH4ECON 3380 3390 DCH4INT DCH4SSA
CHAIRQ<7:0>
CHSIRQ<7:0>
CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- --
33A0 DCH4DSA 33B0 DCH4SSIZ Legend: Note 1:
CHSSIZ15:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-19:
Virtual Address (BF88_#) Register Name
DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits All Resets Bit Range
DS61156C-page 78
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
33C0 DCH4DSIZ 33D0 DCH4SPTR 33E0 DCH4DPTR 33F0 DCH4CSIZ 3400 DCH4CPTR 3410 DCH4DAT
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- -- -- -- CHBUSY -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- CHCHNS --
-- -- -- -- -- -- -- CHEN CFORCE
-- -- -- -- -- -- -- CHAED CABORT CHSHIE CHSHIF
-- -- -- -- -- -- -- CHCHN PATEN CHDDIE CHDDIF
-- -- -- -- -- -- -- CHAEN SIRQEN CHDHIE CHDHIF
-- -- -- -- -- -- -- -- AIRQEN CHBCIE CHBCIF
-- -- -- -- -- -- -- CHEDET -- CHCCIE CHCCIF
-- -- -- -- -- -- --
-- -- -- -- -- -- --
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000
CHDSIZ<15:0> CHSPTR<15:0> CHDPTR<15:0> CHCSIZ<15:0> CHCPTR<15:0> CHPDAT<7:0> CHPRI<1:0> -- CHTAIE CHTAIF -- CHERIE CHERIF
3420 DCH5CON 3430 DCH5ECON 3440 3450 3460 DCH5INT DCH5SSA DCH5DSA
Preliminary
2010 Microchip Technology Inc.
CHAIRQ<7:0> CHSDIE CHSDIF
CHSIRQ<7:0> -- --
CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
3470 DCH5SSIZ 3480 DCH5DSIZ 3490 DCH5SPTR 34A0 DCH5DPTR 34B0 DCH5CSIZ 34C0 DCH5CPTR 34D0 DCH5DAT Legend: Note 1:
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
CHSSIZ<15:0> CHDSIZ<15:0> CHSPTR<15:0> CHDPTR<15:0> CHCSIZ<15:0> CHCPTR<15:0> CHPDAT<7:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-19:
Virtual Address (BF88_#) Register Name
DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits All Resets
0000 0000 00FF -- CHCCIE CHCCIF -- CHTAIE CHTAIF -- CHERIE CHERIF FF00 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- CHAED CABORT CHSHIE CHSHIF -- -- -- -- -- -- -- -- CHCHN PATEN CHDDIE CHDDIF -- -- -- -- -- -- -- -- CHAEN SIRQEN CHDHIE CHDHIF -- -- -- -- -- -- -- -- -- AIRQEN CHBCIE CHBCIF -- -- -- -- -- -- -- -- CHEDET -- CHCCIE CHCCIF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 0000
2010 Microchip Technology Inc.
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
34E0 DCH6CON 34F0 DCH6ECON 3500 3510 DCH6INT DCH6SSA
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- CHBUSY -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- CHCHNS --
-- CHEN CFORCE
-- CHAED CABORT CHSHIE CHSHIF
-- CHCHN PATEN CHDDIE CHDDIF
-- CHAEN SIRQEN CHDHIE CHDHIF
-- -- AIRQEN CHBCIE CHBCIF
-- CHEDET
--
--
CHPRI<1:0>
CHAIRQ<7:0> CHSDIE CHSDIF
CHSIRQ<7:0> -- --
CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- -- CHBUSY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- CFORCE -- -- CHSDIE CHSDIF -- CHEN -- -- -- -- -- -- --
3520 DCH6DSA 3530 DCH6SSIZ 3540 DCH6DSIZ 3550 DCH6SPTR 3560 DCH6DPTR 3570 DCH6CSIZ 3580 DCH6CPTR 3590 DCH6DAT
CHSSIZ<15:0> CHDSIZ<15:0> CHSPTR<15:0> CHDPTR<15:0> CHCSIZ<15:0> CHCPTR<15:0> CHPDAT<7:0> CHPRI<1:0> -- CHTAIE CHTAIF -- CHERIE CHERIF
Preliminary
DS61156C-page 79
PIC32MX5XX/6XX/7XX
0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- 0000 0000
35A0 DCH7CON 35B0 DCH7ECON 35C0 DCH7INT
CHAIRQ<7:0>
CHSIRQ<7:0>
35D0 DCH7SSA 35E0 DCH7DSA 35F0 DCH7SSIZ Legend: Note 1:
CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- --
CHSSIZ<15:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-19:
Virtual Address (BF88_#) Register Name
DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits All Resets Bit Range
DS61156C-page 80
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3600 DCH7DSIZ 3610 DCH7SPTR 3620 DCH7DPTR 3630 DCH7CSIZ 3640 DCH7CPTR 3650 DCH7DAT
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
CHDSIZ<15:0> CHSPTR<15:0> CHDPTR<15:0> CHCSIZ<15:0> CHCPTR<15:0> CHPDAT<7:0>
Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Preliminary
2010 Microchip Technology Inc.
TABLE 4-20:
Virtual Address (BF80_#) Bit Range Register Name
COMPARATOR REGISTER MAP(1)
Bits All Resets
0000 0000 0000 0000 0000 0000
Virtual Address (BF80_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register Name
2010 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
A000 CM1CON A010 CM2CON A060 CMSTAT
31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- ON -- --
-- COE -- COE -- FRZ
-- CPOL -- CPOL -- SIDL
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- COUT -- COUT -- --
-- -- -- --
-- -- -- --
-- -- -- -- -- --
-- CREF -- CREF -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- C2OUT
-- -- -- C1OUT
EVPOL<1:0> EVPOL<1:0>
CCH<1:0> CCH<1:0>
Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-21:
COMPARATOR VOLTAGE REFERENCE REGISTER MAP(1)
Bits
Preliminary
DS61156C-page 81
PIC32MX5XX/6XX/7XX
9800 CVRCON Legend: Note 1:
31:16 15:0
-- ON
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- CVROE
-- CVRR
-- CVRSS
--
--
--
--
0000 0000
CVR<3:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Virtual Address (BF80_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
F000 OSCCON F010 OSCTUN
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- ON -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
PLLODIV<2:0> COSC<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
RCDIV<2:0> NOSC<2:0> -- -- -- -- -- CM -- -- -- -- -- -- -- VREGS -- --
-- CLKLOCK -- -- -- -- -- EXTR -- --
SOSCRDY ULOCK -- -- -- -- SWR -- --
-- LOCK -- -- -- -- -- --
PBDIV<1:0> SLPEN -- -- SWDTPS<4:0> -- WDTO -- -- -- SLEEP -- -- -- IDLE -- -- CF -- -- -- --
PLLMULT<2:0> UFRCEN SOSCEN -- -- -- -- BOR -- -- OSWEN -- -- WDTCLR -- POR -- SWRST
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
TUN<5:0>
0000 WDTCON
F600
RCON
F610 RSWRST Legend: Note 1: 2:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
All Resets(2)
Bit Range
Register Name
DS61156C-page 82
PIC32MX5XX/6XX/7XX
TABLE 4-22:
Virtual Address (BF80_#) Register Name
FLASH CONTROLLER REGISTER MAP
Bits All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
F400 NVMCON(1) F410 NVMKEY
(1)
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- WR
-- WREN
-- WRERR
-- LVDERR
-- LVDSTAT
-- --
-- --
-- --
-- --
-- --
-- --
-- --
--
--
--
--
NVMOP<3:0>
NVMKEY<31:0> NVMADDR<31:0> NVMDATA<31:0> NVMSRCADDR<31:0>
F420 NVMADDR F430 F440 Legend: Note 1:
NVMDATA NVMSRC ADDR
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Preliminary
2010 Microchip Technology Inc.
TABLE 4-23:
SYSTEM CONTROL REGISTER MAP(1,2)
Bits
Virtual Address (BF88_#)
All Resets
Bit Range
Register Name
2010 Microchip Technology Inc.
TABLE 4-24:
Virtual Address (BF88_#)
PORTA REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits All Resets
0000 C6FF 0000 xxxx 0000 xxxx 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6000 6010 6020 6030 Legend: Note
TRISA PORTA LATA ODCA
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- TRISA15 -- RA15 -- LATA15 -- ODCA15
-- TRISA14 -- RA14 -- LATA14 -- ODCA14
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISA10 -- RA10 -- LATA10 -- ODCA10
-- TRISA9 -- RA9 -- LATA9 -- ODCA9
-- -- -- -- -- -- -- --
-- TRISA7 -- RA7 -- LATA7 -- ODCA7
-- TRISA6 -- RA6 -- LATA6 -- ODCA6
-- TRISA5 -- RA5 -- LATA5 -- ODCA5
-- TRISA4 -- RA4 -- LATA4 -- ODCA4
-- TRISA3 -- RA3 -- LATA3 -- ODCA3
-- TRISA2 -- RA2 -- LATA2 -- ODCA2
-- TRISA1 -- RA1 -- LATA1 -- ODCA1
-- TRISA0 -- RA0 -- LATA0 -- ODCA0
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
1:
Preliminary
DS61156C-page 83
TABLE 4-25:
PORTB REGISTER MAP(1)
Bits
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6040 6050 6060 6070 Legend: Note
TRISB PORTB LATB ODCB
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- TRISB15 -- RB15 -- LATB15 -- ODCB15
-- TRISB14 -- RB14 -- LATB14 -- ODCB14
-- TRISB13 -- RB13 -- LATB13 -- ODCB13
-- TRISB12 -- RB12 -- LATB12 -- ODCB12
-- TRISB11 -- RB11 -- LATB11 -- ODCB11
-- TRISB10 -- RB10 -- LATB10 -- ODCB10
-- TRISB9 -- RB9 -- LATB9 -- ODCB9
-- TRISB8 -- RB8 -- LATB8 -- ODCB8
-- TRISB7 -- RB7 -- LATB7 -- ODCB7
-- TRISB6 -- RB6 -- LATB6 -- ODCB6
-- TRISB5 -- RB5 -- LATB5 -- ODCB5
-- TRISB4 -- RB4 -- LATB4 -- ODCB4
-- TRISB3 -- RB3 -- LATB3 -- ODCB3
-- TRISB2 -- RB2 -- LATB2 -- ODCB2
-- TRISB1 -- RB1 -- LATB1 -- ODCB1
-- TRISB0 -- RB0 -- LATB0 -- ODCB0
0000 FFFF 0000 xxxx 0000 xxxx 0000 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
1:
Virtual Address (BF88_#)
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6080
TRISC
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- TRISC15 -- RC15 -- LATC15 -- ODCC15
-- TRISC14 -- RC14 -- LATC14 -- ODCC14
-- TRISC13 -- RC13 -- LATC13 -- ODCC13
-- TRISC12 -- RC12 -- LATC12 -- ODCC12
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISC4 -- RC4 -- LATC4 -- ODCC4
-- TRISC3 -- RC3 -- LATC3 -- ODCC3
-- TRISC2 -- RC2 -- LATC2 -- ODCC2
-- TRISC1 -- RC1 -- LATC1 -- ODCC1
-- -- -- -- -- -- -- --
0000 F00F 0000 xxxx 0000 xxxx 0000 0000
6090 PORTC 60A0 60B0 LATC ODCC
Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
All Resets
Bit Range
Register Name
DS61156C-page 84
PIC32MX5XX/6XX/7XX
TABLE 4-26:
PORTC REGISTER MAP FOR PIC32MX575F256H, PIC32MX675F256H, PIC32MX575F512H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits All Resets
0000 F000 0000 xxxx 0000 xxxx 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6080 6090 60A0 60B0 Legend: Note
TRISC PORTC LATC ODCC
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- TRISC15 -- RC15 -- LATC15 -- ODCC15
-- TRISC14 -- RC14 -- LATC14 -- ODCC14
-- TRISC13 -- RC13 -- LATC13 -- ODCC13
-- TRISC12 -- RC12 -- LATC12 -- ODCC12
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
1:
Preliminary
2010 Microchip Technology Inc.
TABLE 4-27:
PORTC REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
60C0
TRISD
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- TRISD15 -- RD15 -- LAT15 -- ODCD15
-- TRISD14 -- RD14 -- LAT14 -- ODCD14
-- TRISD13 -- RD13 -- LAT13 -- ODCD13
-- TRISD12 -- RD12 -- LAT12 -- ODCD12
-- TRISD11 -- RD11 -- LATD11 -- ODCD11
-- TRISD10 -- RD10 -- LATD10 -- ODCD10
-- TRISD9 -- RD9 -- LATD9 -- ODCD9
-- TRISD8 -- RD8 -- LATD8 -- ODCD8
-- TRISD7 -- RD7 -- LATD7 -- ODCD7
-- TRISD6 -- RD6 -- LATD6 -- ODCD6
-- TRISD5 -- RD5 -- LATD5 -- ODCD5
-- TRISD4 -- RD4 -- LATD4 -- ODCD4
-- TRISD3 -- RD3 -- LATD3 -- ODCD3
-- TRISD2 -- RD2 -- LATD2 -- ODCD2
-- TRISD1 -- RD1 -- LATD1 -- ODCD1
-- TRISD0 -- RD0 -- LATD0 -- ODCD0
0000 FFFF 0000 xxxx 0000 xxxx 0000 0000
60D0 PORTD 60E0 60F0 Legend: Note 1: LATD ODCD
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
All Resets
Bit Range
Register Name
2010 Microchip Technology Inc.
TABLE 4-28:
Virtual Address (BF88_#)
PORTD REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits All Resets
0000 0FFF 0000 xxxx 0000 xxxx 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
60C0 60D0 60E0 60F0 Legend: Note
TRISD PORTD LATD ODCD
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISD11 -- RD11 -- LATD11 -- ODCD11
-- TRISD10 -- RD10 -- LATD10 -- ODCD10
-- TRISD9 -- RD9 -- LATD9 -- ODCD9
-- TRISD8 -- RD8 -- LATD8 -- ODCD8
-- TRISD7 -- RD7 -- LATD7 -- ODCD7
-- TRISD6 -- RD6 -- LATD6 -- ODCD6
-- TRISD5 -- RD5 -- LATD5 -- ODCD5
-- TRISD4 -- RD4 -- LATD4 -- ODCD4
-- TRISD3 -- RD3 -- LATD3 -- ODCD3
-- TRISD2 -- RD2 -- LATD2 -- ODCD2
-- TRISD1 -- RD1 -- LATD1 -- ODCD1
-- TRISD0 -- RD0 -- LATD0 -- ODCD0
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
1:
Preliminary
DS61156C-page 85
TABLE 4-29:
PORTD REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
PIC32MX5XX/6XX/7XX
Bits
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6100 6110 6120 6130 Legend: Note
TRISE PORTE LATE ODCE
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISE9 -- RE9 -- LATE9 -- ODCE9
-- TRISE8 -- RE8 -- LATE8 -- ODCE8
-- TRISE7 -- RE7 -- LATE7 -- ODCE7
-- TRISE6 -- RE6 -- LATE6 -- 0DCE6
-- TRISE5 -- RE5 -- LATE5 -- ODCE5
-- TRISE4 -- RE4 -- LATE4 -- ODCE4
-- TRISE3 -- RE3 -- LATE3 -- ODCE3
-- TRISE2 -- RE2 -- LATE2 -- ODCE2
-- TRISE1 -- RE1 -- LATE1 -- ODCE1
-- TRISE0 -- RE0 -- LATE0 -- ODCE0
0000 03FF 0000 xxxx 0000 xxxx 0000 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
1:
All Resets
Bit Range
Register Name
2010 Microchip Technology Inc.
TABLE 4-30:
Virtual Address (BF88_#)
PORTE REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits All Resets
0000 00FF 0000 xxxx 0000 xxxx 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6100 6110 6120 6130 Legend: Note
TRISE PORTE LATE ODCE
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISE7 -- RE7 -- LATE7 -- ODCE7
-- TRISE6 -- RE6 -- LATE6 -- 0DCE6
-- TRISE5 -- RE5 -- LATE5 -- ODCE5
-- TRISE4 -- RE4 -- LATE4 -- ODCE4
-- TRISE3 -- RE3 -- LATE3 -- ODCE3
-- TRISE2 -- RE2 -- LATE2 -- ODCE2
-- TRISE1 -- RE1 -- LATE1 -- ODCE1
-- TRISE0 -- RE0 -- LATE0 -- ODCE0
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
1:
Preliminary
DS61156C-page 86
TABLE 4-31:
PORTE REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
PIC32MX5XX/6XX/7XX
Bits
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6140 6150 6160 6170 Legend: Note
TRISF PORTF LATF ODCF
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISF13 -- RF13 -- LATF13 -- ODCF13
-- TRISF12 -- RF12 -- LATF12 -- ODCF12
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISF8 -- RF8 -- LATF8 -- ODCF8
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISF5 -- RF5 -- LATF5 -- ODCF5
-- TRISF4 -- RF4 -- LATF4 -- ODCF4
-- TRISF3 -- RF3 -- LATF3 -- ODCF3
-- TRISF2 -- RF2 -- LATF2 -- ODCF2
-- TRISF1 -- RF1 -- LATF1 -- ODCF1
-- TRISF0 -- RF0 -- LATF0 -- ODCF0
0000 313F 0000 xxxx 0000 xxxx 0000 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
1:
All Resets
Bit Range
Register Name
2010 Microchip Technology Inc.
TABLE 4-32:
Virtual Address (BF88_#)
PORTF REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits All Resets
0000 003B 0000 xxxx 0000 xxxx 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6140
TRISF
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISF5 -- RF5 -- LATF5 -- ODCF5
-- TRISF4 -- RF4 -- LATF4 -- ODCF4
-- TRISF3 -- RF3 -- LATF3 -- ODCF3
-- -- -- -- -- -- -- --
-- TRISF1 -- RF1 -- LATF1 -- ODCF1
-- TRISF0 -- RF0 -- LATF0 -- ODCF0
6150 PORTF 6160 6170 Legend: Note 1: LATF ODCF
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Preliminary
DS61156C-page 87
TABLE 4-33:
PORTF REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
PIC32MX5XX/6XX/7XX
Bits
Virtual Address (BF88_#)
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6180
TRISG
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- TRISG15 -- RG15 -- LATG15 -- ODCG15
-- TRISG14 -- RG14 -- LATG14 -- ODCG14
-- TRISG13 -- RG13 -- LATG13 -- ODCG13
-- TRISG12 -- RG12 -- LATG12 -- ODCG12
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISG9 -- RG9 -- LATG9 -- ODCG9
-- TRISG8 -- RG8 -- LATG8 -- ODCG8
-- TRISG7 -- RG7 -- LATG7 -- ODCG7
-- TRISG6 -- RG6 -- LATG6 -- ODCG6
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISG3 -- RG3 -- LATG3 -- ODCG3
-- TRISG2 -- RG2 -- LATG2 -- ODCG2
-- TRISG1 -- RG1 -- LATG1 -- ODCG1
-- TRISG0 -- RG0 -- LATG0 -- ODCG0
0000 F3CF 0000 xxxx 0000 xxxx 0000 0000
6190 PORTG 61A0 61B0 Legend: Note 1: LATG ODCG
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
All Resets
Bit Range
Register Name
DS61156C-page 88
PIC32MX5XX/6XX/7XX
TABLE 4-34:
PORTG REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits All Resets
0000 03CC 0000 xxxx 0000 xxxx 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6180
TRISG
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISG9 -- RG9 -- LATG9 -- ODCG9
-- TRISG8 -- RG8 -- LATG8 -- ODCG8
-- TRISG7 -- RG7 -- LATG7 -- ODCG7
-- TRISG6 -- RG6 -- LATG6 -- ODCG6
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- TRISG3 -- RG3 -- LATG3 -- ODCG3
-- TRISG2 -- RG2 -- LATG2 -- ODCG2
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
6190 PORTG 61A0 61B0 LATG ODCG
Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Preliminary
2010 Microchip Technology Inc.
TABLE 4-35:
PORTG REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
Virtual Address (BF88_#)
All Resets
Bit Range
Register Name
2010 Microchip Technology Inc.
TABLE 4-36:
Virtual Address (BF88_#)
CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES(1)
Bits All Resets
0000 0000 0000 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
61C0 CNCON 61D0 61E0 Legend: Note 1: CNEN CNPUE
31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- CNEN15 --
-- FRZ -- CNEN14 --
-- SIDL -- CNEN13 --
-- -- -- CNEN12 --
-- -- -- CNEN11 --
-- -- -- CNEN10 --
-- -- -- CNEN9 -- CNPUE9
-- -- -- CNEN8 -- CNPUE8
-- -- -- CNEN7 -- CNPUE7
-- -- -- CNEN6 -- CNPUE6
-- -- CNEN21 CNEN5 CNPUE21 CNPUE5
-- -- CNEN20 CNEN4 CNPUE20 CNPUE4
-- -- CNEN19 CNEN3 CNPUE3
-- -- CNEN18 CNEN2 CNPUE2
-- -- CNEN17 CNEN1 CNPUE1
-- -- CNEN16 CNEN0 CNPUE0
CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000
CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-37:
CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits
Preliminary
DS61156C-page 89
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
61C0 CNCON 61D0 61E0 Legend: Note 1: CNEN CNPUE
31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- CNEN15 --
-- FRZ -- CNEN14 --
-- SIDL -- CNEN13 --
-- -- -- CNEN12 --
-- -- -- CNEN11 --
-- -- -- CNEN10 --
-- -- -- CNEN9 -- CNPUE9
-- -- -- CNEN8 -- CNPUE8
-- -- -- CNEN7 -- CNPUE7
-- -- -- CNEN6 -- CNPUE6
-- -- -- CNEN5 -- CNPUE5
-- -- -- CNEN4 -- CNPUE4
-- -- -- CNEN3 -- CNPUE3
-- -- CNEN18 CNEN2 CNPUE2
-- -- CNEN17 CNEN1 CNPUE1
-- -- CNEN16 CNEN0 CNPUE0
0000 0000 0000 0000 0000
CNPUE18 CNPUE17 CNPUE16 0000
CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-38:
Virtual Address (BF80_#) Bit Range Register Name
PARALLEL MASTER PORT REGISTER MAP(1)
Bits All Resets
Virtual Address (BF80_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
F200 DDPCON
31:16 15:0
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- JTAGEN
-- TROEN
-- --
-- --
0000 0008
Legend:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
All Resets
Bit Range
Register Name
DS61156C-page 90
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
7000
PMCON
31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- BUSY --
-- FRZ -- --
-- SIDL -- --
-- -- --
-- -- --
-- PMPTTL -- MODE16 --
-- PTWREN -- --
-- PTRDEN -- --
-- -- --
-- -- --
-- ALP -- --
-- CS2P -- --
-- CS1P -- --
-- -- -- --
-- WRSP -- --
-- RDSP -- --
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
ADRMUX<1:0> INCM<1:0>
CSF<1:0> WAITB<1:0> ADDR<13:0>
7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 7050 7060 Legend: Note 1: PMDIN PMAEN PMSTAT
IRQM<1:0>
MODE<1:0>
WAITM<3:0>
WAITE<1:0>
15:0 CS2EN/A15 CS1EN/A14
DATAOUT<31:0> DATAIN<31:0> -- -- IBF -- -- IBOV -- -- -- -- -- -- -- -- IB3F -- -- IB2F -- -- IB1F -- -- IB0F -- -- OBE -- -- OBUF -- -- -- -- -- -- -- -- OB3E -- -- OB2E -- -- OB1E -- -- OB0E
0000 0000 0000 0080
PTEN<15:0>
Preliminary
2010 Microchip Technology Inc.
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-39:
PROGRAMMING AND DIAGNOSTICS REGISTER MAP
Bits
TABLE 4-40:
Virtual Address (BF88_#) Register Name
PREFETCH REGISTER MAP
Bits All Resets
0000 -- 0000 0000 00xx LLOCK -- -- LTYPE -- -- -- -- -- xxx0 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx CHELRU<24:16> CHELRU<15:0> CHEHIT<31:0> CHEMIS<31:0> CHEPFABT<31:0> 0000
2010 Microchip Technology Inc.
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
4000 CHECON(1,2) 4010 CHEACC
(1)
31:16 15:0 15:0 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- -- LMASK<15:5>
-- -- -- -- --
-- -- -- -- --
-- -- -- --
-- -- -- --
-- -- --
-- -- --
-- -- --
-- --
-- PFMWS<2:0> --
CHECOH 0000
DCSZ<1:0>
PREFEN<1:0>
31:16 CHEWEN 31:16 LTAGBOOT --
CHEIDX<3:0> LVALID
4020 CHETAG(1) 4030 CHEMSK(1) 4040 4050 4060 4070 4080 4090 40A0 CHEW0 CHEW1 CHEW2 CHEW3 CHELRU CHEHIT CHEMIS
LTAG<23:16> -- -- -- -- -- -- --
LTAG<15:4>
CHEW0<31:0> CHEW1<31:0> CHEW2<31:0> CHEW3<31:0> -- -- -- -- -- -- --
Preliminary
DS61156C-page 91
PIC32MX5XX/6XX/7XX
0000 xxxx xxxx xxxx xxxx xxxx xxxx
40C0 CHEPFABT Legend: Note 1: 2:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset value is dependent on DEVCFGx configuration.
TABLE 4-41:
Virtual Address (BF80_#) Bit Range Register Name
RTCC REGISTER MAP(1)
Bits All Resets
DS61156C-page 92
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
0200
RTCCON
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- ALRMEN
-- FRZ -- CHIME
-- SIDL -- PIV
-- -- -- ALRMSYNC
-- -- --
-- -- -- -- -- -- -- RTSECSEL RTCCLKON -- --
CAL<9:0> -- -- -- -- RTCWREN RTCSYNC HALFSEC -- -- -- RTCOE --
0000 0000 0000 0000 MIN01<3:0> -- -- -- -- -- -- -- -- -- MONTH01<3:0> WDAY01<3:0> MIN01<3:0> -- -- -- MONTH01<3:0> WDAY01<3:0> xxxx xx00 xxxx xx00 xxxx xx00 00xx xx0x
0210 RTCALRM 0220 RTCTIME
AMASK<3:0> HR01<3:0> SEC01<3:0> YEAR01<3:0> DAY01<3:0> HR01<3:0> SEC01<3:0> -- -- -- -- -- MIN10<3:0> -- -- -- -- -- -- -- -- MONTH10<3:0> MIN10<3:0> MONTH10<3:0>
ARPT<7:0>
HR10<3:0> SEC10<3:0> YEAR10<3:0> DAY10<3:0> HR10<3:0> SEC10<3:0> -- -- -- -- -- DAY10<3:0>
0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend:
--
--
DAY01<3:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Preliminary
2010 Microchip Technology Inc.
TABLE 4-42:
Virtual Address (BFC0_#) Bit Range Register Name
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
Bits All Resets
xxxx xxxx -- -- -- -- -- -- FPLLMULT<2:0> -- FSOSCEN -- -- -- -- -- ICESEL -- -- -- -- -- FPLLODIV<2:0> FPLLIDIV<2:0> WDTPS<4:0> FNOSC<2:0> PWP<7:4> DEBUG<1:0> xxxx xxxx xxxx xxxx xxxx xxxx
Virtual Address (BF80_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register Name
2010 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
2FF0 DEVCFG3 2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 Legend:
31:16 FVBUSIO FUSBIDIO 15:0 31:16 15:0 31:16 15:0 31:16 15:0 -- FUPLLEN -- -- -- -- -- --
FSCMIO -- -- -- --
-- -- -- -- CP
-- -- -- -- -- -- --
FCANIO -- -- OSCIOFNC -- --
FETHIO --
FMIIEN -- -- BWP --
-- -- -- FWDTEN IESO -- --
--
--
--
--
FSRSSEL<2:0>
USERID<15:0> FUPLLIDIV<2:0> -- -- -- POSCMOD<1:0>
FCKSM<1:0>
FPBDIV<1:0>
PWP<3:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 4-43:
DEVICE AND REVISION ID SUMMARY(1)
Bits
Preliminary
DS61156C-page 93
PIC32MX5XX/6XX/7XX
F220
DEVID
31:16 15:0
VER<3:0> DEVID<15:0>
DEVID<27:16>
xxxx xxxx
Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values are dependent on the device variant. Refer to the "PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification" (DS80480) for more information.
DS61156C-page 94
PIC32MX5XX/6XX/7XX
TABLE 4-44:
Virtual Address (BF88_#) Register Name
USB REGISTER MAP
Bits All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- EP<3:0> -- -- -- FRMH<2:0> -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 0000 0000
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5040 5050
U1OTGIR U1OTGIE
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- IDIF -- IDIE -- ID -- -- UACTPND -- STALLIF -- STALLIE -- BTSEF -- BTSEE -- -- JSTATE -- LSPDEN -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- LSTATE -- -- -- --
-- ACTVIF -- ACTVIE -- -- -- -- -- IDLEIF -- IDLEIE -- BTOEF -- BTOEE -- -- USBRST -- -- BDTPTRL<7:1> -- -- -- --
-- -- -- SESVD -- -- -- TRNIF -- TRNIE -- DFN8EF -- DFN8EE -- DIR -- HOSTEN -- DEVADDR<6:0> --
-- -- -- SESEND -- OTGEN -- -- -- SOFIF -- SOFIE -- CRC16EF -- CRC16EE -- PPBI -- RESUME --
-- -- -- -- -- -- -- VBUSCHG -- -- UERRIF -- UERRIE -- CRC5EF EOFEF -- CRC5EE EOFEE -- -- -- PPBRST --
-- -- -- VBUSVD -- VBUSDIS -- -- URSTIF -- URSTIE -- PIDEF -- PIDEE -- -- -- USBEN SOFEN --
T1MSECIF LSTATEIF T1MSECIE LSTATEIE
SESVDIF SESENDIF SESVDIE SESENDIE
VBUSVDIF 0000 VBUSVDIE 0000
5060 U1OTGSTAT 5070 U1OTGCON 5080 U1PWRC
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON USLPGRD USBBUSY
USUSPEND USBPWR
5200
U1IR
15:0 31:16
ATTACHIF RESUMEIF -- --
DETACHIF 0000
Preliminary
2010 Microchip Technology Inc.
5210
U1IE
15:0 31:16
ATTACHIE RESUMEIE -- BMXEF -- BMXEE -- -- SE0 -- -- -- -- -- -- -- DMAEF -- DMAEE -- -- PKTDIS TOKBUSY -- -- -- -- -- -- PID<3:0>
DETACHIE 0000
5220
U1EIR
15:0 31:16
5230
U1EIE
15:0 31:16 15:0 31:16
5240
U1STAT
ENDPT<3:0>
5250
U1CON
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
5260 5270 5280 5290 52A0 Legend:
U1ADDR U1BDTP1 U1FRML U1FRMH U1TOK
FRML<7:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 4-44:
Virtual Address (BF88_#) Register Name
USB REGISTER MAP (CONTINUED)
Bits All Resets
0000 0000 -- -- -- -- -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- -- -- -- -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- -- -- -- -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- -- -- -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 UASUSPND 0001
2010 Microchip Technology Inc.
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
52B0 52C0 52D0 52E0 5300 5310 5320 5330 5340 5350 5360 5370 5380 5390 53A0 53B0 53C0 53D0 Legend:
U1SOF U1BDTP2 U1BDTP3 U1CNFG1 U1EP0 U1EP1 U1EP2 U1EP3 U1EP4 U1EP5 U1EP6 U1EP7 U1EP8 U1EP9 U1EP10 U1EP11 U1EP12 U1EP13
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- UTEYE -- LSPD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- UOEMON -- RETRYDIS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- USBFRZ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- CNT<7:0> -- -- -- USBSIDL -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS
--
--
--
--
BDTPTRH<7:0> BDTPTRU<7:0>
Preliminary
DS61156C-page 95
PIC32MX5XX/6XX/7XX
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 4-44:
Virtual Address (BF88_#) Register Name
USB REGISTER MAP (CONTINUED)
Bits All Resets Bit Range
DS61156C-page 96
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
53E0 53F0 Legend:
U1EP14 U1EP15
31:16 15:0 31:16 15:0
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- EPCONDIS -- EPCONDIS
-- EPRXEN -- EPRXEN
-- EPTXEN -- EPTXEN
-- EPSTALL -- EPSTALL
-- EPHSHK -- EPHSHK
0000 0000 0000 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Preliminary
2010 Microchip Technology Inc.
2010 Microchip Technology Inc.
TABLE 4-45:
CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits All Resets
0400 0000 0000 0000 RBIE RBIF -- RXWARN TBIE TBIF -- 0000 0000 0000 0000 TXWARN EWARN 0000 0000 FIFOIP17 FIFOIP16 0000 FIFOIP1 RXOVF1 FIFOIP0 0000 RXOVF0 0000 FIFOIP2 RXOVF2
Virtual Address (BF88_#)
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
B000 B010 B020 B030 B040
C1CON C1CFG C1INT C1VEC C1TREC C1FSTAT C1RXOVF C1TMR C1RXM0 C1RXM1 C1RXM2 C1RXM3
31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- IVRIE IVRIF -- -- --
-- -- -- SAM WAKIE WAKIF -- -- -- FIFOIP30 FIFOIP14
-- SIDLE -- CERRIE CERRIF -- -- --
-- -- -- SEG1PH<2:0> SERRIE SERRIF -- --
ABAT BUSY -- RBOVIE RBOVIF -- -- TEC<7:0> -- -- -- -- --
REQOP<2:0> -- -- PRSEG<2:0> -- -- -- -- FIFOIP25 FIFOIP9 RXOVF9 -- -- -- -- FIFOIP24 FIFOIP8 RXOVF24 RXOVF8 -- -- -- -- -- -- -- -- -- FIFOIP23 FIFOIP7 RXOVF7
OPMOD<2:0> -- WAKFIL -- -- -- -- -- -- -- -- -- TXBO
CANCAP -- -- -- -- TXBP
-- -- BRP<5:0> MODIE MODIF -- ICOD<6:0> RXBP
-- DNCNT<4:0>
-- SEG2PH<2:0>
--
15:0 SEG2PHTS
SJW<1:0>
CTMRIE CTMRIF --
FILHIT<4:0> -- FIFOIP26 FIFOIP10
REC<7:0> FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP6 RXOVF6 FIFOIP5 RXOVF5 FIFOIP4 RXOVF4 FIFOIP3 RXOVF3
B050 B060 B070 B080 B090 B0A0 B0B0
31:16 FIFOIP31 15:0 FIFOIP15
FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP13 FIFOIP12 FIFOIP11
Preliminary
DS61156C-page 97
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 15:0 15:0 15:0 FLTEN3 FLTEN1 FLTEN7 FLTEN5 FLTEN9 FLTEN13 FLTEN17 MSEL3<1:0> MSEL1<1:0> MSEL7<1:0> MSEL5<1:0> MSEL11<1:0> MSEL9<1:0> MSEL15<1:0> MSEL13<1:0> MSEL19<1:0> MSEL17<1:0> FSEL3<4:0> FSEL1<4:0> FSEL7<4:0> FSEL5<4:0> FSEL11<4:0> FSEL9<4:0> FSEL15<4:0> FSEL13<4:0> FSEL19<4:0> FSEL17<4:0> SID<10:0> SID<10:0> SID<10:0> SID<10:0>
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
CANTS<15:0> CANTSPRE<15:0> --- EID<15:0> --- EID<15:0> --- EID<15:0> --- EID<15:0> FLTEN2 FLTEN0 FLTEN6 FLTEN4 FLTEN10 FLTEN8 FLTEN14 FLTEN12 FLTEN18 FLTEN16 MSEL2<1:0> MSEL0<1:0> MSEL6<1:0> MSEL4<1:0> MSEL10<1:0> MSEL8<1:0> MSEL14<1:0> MSEL12<1:0> MSEL18<1:0> MSEL16<1:0> FSEL2<4:0> FSEL0<4:0> FSEL6<4:0> FSEL4<4:0> FSEL10<4:0> FSEL8<4:0> FSEL14<4:0> FSEL12<4:0> FSEL18<4:0> FSEL16<4:0: MIDE -- EID<17:16> MIDE -- EID<17:16> MIDE -- EID<17:16> MIDE -- EID<17:16>
PIC32MX5XX/6XX/7XX
0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
B0C0 C1FLTCON0 B0D0 C1FLTCON1 B0E0 C1FLTCON2 B0F0 C1FLTCON3 B100 C1FLTCON4 Legend: Note 1:
31:16 FLTEN11 31:16 FLTEN15 31:16 FLTEN19
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-45:
CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Bits All Resets Bit Range
Virtual Address (BF88_#)
Register Name
DS61156C-page 98
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
B110 C1FLTCON5 B120 C1FLTCON6 B130 C1FLTCON7 B140 B340 C1RXFn (n = 0-31) C1FIFOBA
31:16 FLTEN23 15:0 15:0 15:0 31:16 15:0 31:16 15:0 -- -- -- -- FLTEN21 FLTEN25 FLTEN29 31:16 FLTEN27 31:16 FLTEN31
MSEL23<1:0> MSEL21<1:0> MSEL27<1:0> MSEL25<1:0> MSEL31<1:0> MSEL29<1:0>
FSEL23<4:0> FSEL21<4:0> FSEL27<4:0> FSEL25<4:0> FSEL31<4:0> FSEL29<4:0> SID<10:0>
FLTEN22 FLTEN20 FLTEN26 FLTEN24 FLTEN30 FLTEN28 EID<15:0> C1FIFOBA<31:0>
MSEL22<1:0> MSEL20<1:0> MSEL26<1:0> MSEL24<1:0> MSEL30<1:0> MSEL28<1:0> --- EXID
FSEL22<4:0> FSEL20<4:0> FSEL26<4:0> FSEL24<4:0> FSEL30<4:0> FSEL28<4:0> -- EID<17:16>
0000 0000 0000 0000 0000 0000 xxxx xxxx 0000 0000
C1FIFOCONn 31:16 B350 (n = 0-31) 15:0 B360 C1FIFOINTn (n = 0-31) 31:16 15:0
-- FRESET -- --
-- UINC -- --
-- DONLY -- --
-- -- -- --
-- --
-- --
-- --
-- TXEN -- --
-- TXABAT -- --
-- TXLARB -- -- TXERR -- -- TXREQ
FSIZE<4:0> RTREN TXPRI<1:0>
0000 0000 RXN 0000 EMPTYIE RXN 0000 EMPTYIF 0000 0000
Preliminary
2010 Microchip Technology Inc.
TXNFULLIE TXHALFIE TXEMPTYIE TXNFULLIF TXHALFIF TXEMPTYIF
RXOVFLIE RXFULLIE RXHALFIE RXOVFLIF RXFULLIF RXHALFIF
B370 B380
C1FIFOUAn 31:16 (n = 0-31) 15:0 C1FIFOCIn 31:16 (n = 0-31) 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- --
C1FIFOUA<31:0> -- -- -- -- -- -- -- -- -- -- -- C1FIFOCI<4:0> -- --
0000 0000
Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
2010 Microchip Technology Inc.
TABLE 4-46:
Virtual Address (BF88_#)
CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits All Resets
0400 0000 0000 0000 RBIE RBIF -- RXWARN TBIE TBIF -- EWARN 0000 0000 0000 0000 TXWARN FIFOIP18 FIFOIP2 RXOVF2 0000 0000 FIFOIP17 FIFOIP16 0000 FIFOIP1 RXOVF1 FIFOIP0 RXOVF0 0000 0000 0000 0000 --- EID<15:0> SID<10:0> EID<15:0> SID<10:0> EID<15:0> SID<10:0> EID<15:0> FLTEN3 FLTEN1 FLTEN7 FLTEN5 FLTEN9 FLTEN13 MSEL3<1:0> MSEL1<1:0> MSEL7<1:0> MSEL5<1:0> MSEL11<1:0> MSEL9<1:0> MSEL15<1:0> MSEL13<1:0> FSEL3<4:0> FSEL1<4:0> FSEL7<4:0> FSEL5<4:0> FSEL11<4:0> FSEL9<4:0> FSEL15<4:0> FSEL13<4:0> FLTEN2 FLTEN0 FLTEN6 FLTEN4 FLTEN10 FLTEN8 FLTEN14 FLTEN12 MSEL2<1:0> MSEL0<1:0> MSEL6<1:0> MSEL4<1:0> MSEL10<1:0> MSEL8<1:0> MSEL14<1:0> MSEL12<1:0> FSEL2<4:0> FSEL0<4:0> FSEL6<4:0> FSEL4<4:0> FSEL10<4:0> FSEL8<4:0> FSEL14<4:0> FSEL12<4:0> --- MIDE -- EID<17:16> --- MIDE -- EID<17:16> --- MIDE -- EID<17:16> MIDE -- EID<17:16> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
C000 C010 C020 C030 C040 C050 C060 C070 C080 C0A0 C0B0 C0B0
C2CON C2CFG C2INT C2VEC C2TREC C2FSTAT C2RXOVF C2TMR C2RXM0 C2RXM1 C2RXM2 C2RXM3
31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0
-- ON -- IVRIE IVRIF -- -- --
-- -- -- SAM WAKIE WAKIF -- -- --
-- SIDLE -- CERRIE CERRIF -- -- --
-- -- -- SEG1PH<2:0> SERRIE SERRIF -- --
ABAT BUSY -- RBOVIE RBOVIF -- -- TEC<7:0> FIFOIP27 FIFOIP11 -- -- -- -- --
REQOP<2:0> -- -- PRSEG<2:0> -- -- -- -- FIFOIP25 FIFOIP9 RXOVF9 -- -- -- -- FIFOIP24 FIFOIP8 RXOVF24 RXOVF8 -- -- -- -- -- -- -- -- -- FIFOIP23 FIFOIP7 RXOVF7
OPMOD<2:0> -- WAKFIL -- -- -- -- FIFOIP22 FIFOIP6 RXOVF6 -- -- -- -- -- TXBO FIFOIP21 FIFOIP5 RXOVF5
CANCAP -- -- -- -- TXBP FIFOIP20 FIFOIP4 RXOVF4
-- --
-- DNCNT<4:0>
-- SEG2PH<2:0>
--
15:0 SEG2PHTS
SJW<1:0>
BRP<5:0> MODIE MODIF -- ICOD<6:0> RXBP FIFOIP19 FIFOIP3 RXOVF3 REC<7:0> CTMRIE CTMRIF --
FILHIT<4:0> -- FIFOIP26 FIFOIP10
31:16 FIFOIP31 15:0 FIFOIP15
FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP14 FIFOIP13 FIFOIP12
Preliminary
DS61156C-page 99
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 15:0 15:0 SID<10:0>
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
CANTS<15:0> CANTSPRE<15:0>
PIC32MX5XX/6XX/7XX
C0C0 C2FLTCON0 C0D0 C2FLTCON1 C0E0 C2FLTCON2 C0F0 C2FLTCON3 Legend: Note 1:
31:16 FLTEN11 31:16 FLTEN15
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-46:
Virtual Address (BF88_#)
CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Bits All Resets Bit Range
DS61156C-page 100
PIC32MX5XX/6XX/7XX
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
C100 C2FLTCON4 C110 C2FLTCON5 C120 C2FLTCON6 C130 C2FLTCON7 C140 C340 C2RXFn (n = 0-31) C2FIFOBA
31:16 FLTEN19 15:0 15:0 15:0 15:0 31:16 15:0 31:16 15:0 -- -- -- -- FLTEN17 FLTEN21 FLTEN25 FLTEN29 31:16 FLTEN23 31:16 FLTEN27 31:16 FLTEN31
MSEL19<1:0> MSEL17<1:0> MSEL23<1:0> MSEL21<1:0> MSEL27<1:0> MSEL25<1:0> MSEL31<1:0> MSEL29<1:0>
FSEL19<4:0> FSEL17<4:0> FSEL23<4:0> FSEL21<4:0> FSEL27<4:0> FSEL25<4:0> FSEL31<4:0> FSEL29<4:0> SID<10:0>
FLTEN18 FLTEN16 FLTEN22 FLTEN20 FLTEN26 FLTEN24 FLTEN30 FLTEN28 EID<15:0> C2FIFOBA<31:0>
MSEL18<1:0> MSEL16<1:0> MSEL22<1:0> MSEL20<1:0> MSEL26<1:0> MSEL24<1:0> MSEL30<1:0> MSEL28<1:0> --- EXID
FSEL18<4:0> FSEL16<4:0: FSEL22<4:0> FSEL20<4:0> FSEL26<4:0> FSEL24<4:0> FSEL30<4:0> FSEL28<4:0> -- EID<17:16>
0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx 0000 0000
Preliminary
2010 Microchip Technology Inc.
C2FIFOCONn 31:16 C350 (n = 0-31) 15:0 C360 C2FIFOINTn (n = 0-31) 31:16 15:0
-- FRESET -- --
-- UINC -- --
-- DONLY -- --
-- -- -- --
-- --
-- --
-- --
-- TXEN -- --
-- TXABAT -- --
-- TXLARB -- -- TXERR -- -- TXREQ
FSIZE<4:0> RTREN TXPRI<1:0>
0000 0000 RXN 0000 EMPTYIE RXN 0000 EMPTYIF 0000 0000
TXNFULLIE TXHALFIE TXEMPTYIE TXNFULLIF TXHALFIF TXEMPTYIF
RXOVFLIE RXFULLIE RXHALFIE RXOVFLIF RXFULLIF RXHALFIF
C370 C380
C2FIFOUAn 31:16 (n = 0-31) 15:0 C2FIFOCIn 31:16 (n = 0-31) 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- --
C2FIFOUA<31:0> -- -- -- -- -- -- -- -- -- -- -- C2FIFOCI<4:0> -- --
0000 0000
Legend: Note 1:
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
9000 9010 9020 9030 9040
ETHCON1 ETHCON2 ETHTXST ETHRXST ETHHT0 ETHHT1 ETHPMM0 ETHPMM1 ETHPMCS ETHPMO
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- HTEN -- -- -- -- -- -- -- MPEN -- -- -- TX BUSEIE -- TXBUSE -- -- -- -- -- RX BUSEIE -- RXBUSE -- NOTPM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ON -- -- FRZ -- -- SIDL -- -- -- -- -- -- -- -- -- -- TXRTS -- --
PTV<15:0> RXEN AUTOFC -- RXBUFSZ<6:0> TXSTADDR<31:16> TXSTADDR<15:2> RXSTADDR<31:16> RXSTADDR<15:2> HT<31:0> HT<63:32> PMM<31:0> PMM<63:32> -- -- -- -- -- -- CRC ERREN -- -- -- FW MARKIE -- FWMARK -- RX DONEIE -- RXDONE -- PK TPENDIE -- PKTPEND -- RX ACTIE -- RXACT -- -- -- CRC OKEN -- -- -- RUNT ERREN -- -- -- RUNTEN -- -- -- UCEN -- -- -- NOT MEEN -- -- -- MCEN -- -- -- BCEN -- -- -- -- -- -- -- -- MANFC -- -- -- -- -- -- -- -- -- -- -- --
0000
BUFCDEC 0000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
9050 9060 9070 9080 9090
PMCS<15:0> PMO<15:0>
90A0
ETHRXFC
15:0 31:16 15:0 31:16
PMMODE<3:0> -- -- -- -- -- -- -- -- -- EW MARKIE -- EWMARK
90B0 ETHRXWM
RXFWM<7:0> RXEWM<7:0> -- -- -- -- -- TX DONEIE -- TXDONE -- TX ABORTIE -- TXABORT -- RX BUFNAIE -- RXBUFNA --
0000
90C0
ETHIEN
15:0 31:16 15:0
RX 0000 OVFLWIE --
90D0 Legend:
ETHIRQ
0000
RXOVFLW 0000
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Note
1: 2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset values default to the factory programmed value.
All Resets
Bit Range
Register Name
DS61156C-page 101
PIC32MX5XX/6XX/7XX
TABLE 4-47:
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
Preliminary
2010 Microchip Technology Inc.
TABLE 4-47:
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Bits All Resets Bit Range
Virtual Address (BF88_#)
Register Name
DS61156C-page 102
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
90E0 9100 9110 9120 9130 9140 9150 9160
ETHSTAT
31:16 15:0
-- -- -- -- -- -- -- -- -- -- SOFT RESET -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- SIM RESET -- EXCESS DFR -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- BP NOBKOFF -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- NOBKOFF -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- RESET RMCS -- -- -- -- -- NB2BIPKTGP1<6:0> -- --
-- -- -- -- -- -- -- -- -- -- RESET RFUN -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- RESET TMCS -- LONGPRE -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- RESET TFUN -- PUREPRE -- -- -- -- -- BUSY -- -- -- -- -- -- -- -- -- -- AUTOPAD -- -- -- -- -- -- -- MACMAXF<15:0> -- -- -- -- -- -- -- -- TXBUSY -- -- -- -- -- -- -- -- -- -- VLANPAD -- RXBUSY -- -- -- -- -- -- -- -- -- -- PAD ENABLE --
BUFCNT<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RXPAUSE -- -- -- -- -- -- -- -- -- -- PASSALL -- -- -- -- -- -- -- -- -- --
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
31:16 ETH RXOVFLOW 15:0 31:16 ETH FRMTXOK 15:0 31:16 ETH SCOLFRM 15:0 31:16 ETH MCOLFRM 15:0 31:16 ETH FRMRXOK 15:0 ETH FCSERR 31:16 15:0
RXOVFLWCNT<15:0> FRMTXOKCNT<15:0> SCOLFRMCNT<15:0> MCOLFRMCNT<15:0> FRMRXOKCNT<15:0> FCSERRCNT<15:0> ALGNERRCNT<15:0>
Preliminary
2010 Microchip Technology Inc.
31:16 ETH ALGNERR 15:0 EMACx CFG1 EMACx CFG2 EMACx IPGT EMACx IPGR EMACx CLRT EMACx MAXF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
9200
LOOPBACK TXPAUSE -- CRC ENABLE -- -- -- -- -- -- --
RXENABLE 800D --
0000
9210
DELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082 -- -- -- -- -- -- -- -- -- -- -- -- --
9220 9230 9240 9250 Legend:
0000 0012 0000 0C12 0000 370F 0000 05EE
B2BIPKTGP<6:0> -- NB2BIPKTGP2<6:0> -- RETX<3:0>
CWINDOW<5:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Note
1: 2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset values default to the factory programmed value.
TABLE 4-47:
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Bits All Resets
0000 1000 0000 0000 0000 0000 0000 0100
-- -- -- SCAN -- -- -- -- -- -- -- -- --
2010 Microchip Technology Inc.
Virtual Address (BF88_#)
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
9260
EMACx SUPP EMACx TEST EMACx MCFG EMACx MCMD EMACx MADR EMACx MWTD EMACx MRDD EMACx MIND EMACx SA0(2) EMACx SA1(2) EMACx SA2(2)
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
-- -- -- -- -- RESET MGMT -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RESET RMII -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- PHYADDR<4:0> -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- SPEED RMII -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- --
-- -- --
-- -- -- -- --
-- -- -- TESTBP --
-- -- -- -- NOPRE
-- -- -- --
9270
--
--
TESTPAUSE SHRTQNTA 0000
9280
CLKSEL<3:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LINKFAIL -- -- -- -- -- -- -- -- -- -- -- -- REGADDR<4:0> -- -- -- NOTVALID -- -- --
SCANINC 0020 -- READ --
9290 92A0
-- SCAN --
Preliminary
DS61156C-page 103
92B0 92C0 92D0 9300 9310 9320 Legend:
0000 0000 0000
MWTD<15:0> MRDD<15:0>
PIC32MX5XX/6XX/7XX
0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx
MIIMBUSY 0000
STNADDR6<7:0> STNADDR4<7:0> STNADDR2<7:0>
STNADDR5<7:0> STNADDR3<7:0> STNADDR1<7:0>
x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Note
1: 2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 104
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
5.0 FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. "Flash Program Memory" (DS61121) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. PIC32MX5XX/6XX/7XX devices contain an internal Flash program memory for executing user code. There are three methods by which the user can program this memory: 1. 2. 3. Run-Time Self Programming (RTSP) EJTAG Programming In-Circuit Serial ProgrammingTM (ICSPTM)
RTSP is performed by software executing from either Flash or RAM memory. Information about RTSP techniques is available in Section 5. "Flash Program Memory" (DS61121) in the "PIC32MX Family Reference Manual". EJTAG is performed using the EJTAG port of the device and an EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. The EJTAG and ICSP methods are described in the "PIC32MX Flash Programming Specification" (DS61145), which can be downloaded from the Microchip web site.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 105
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 106
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
6.0 RESETS
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. "Resets" (DS61118) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: * * * * * * POR: Power-on Reset MCLR: Master Clear Reset Pin SWR: Software Reset WDTR: Watchdog Timer Reset BOR: Brown-out Reset CMR: Configuration Mismatch Reset
A simplified block diagram of the Reset module is shown in Figure 6-1.
FIGURE 6-1:
SYSTEM RESET BLOCK DIAGRAM
MCLR Glitch Filter Sleep or Idle Voltage Regulator Enabled VDD WDT Time-out Power-up Timer VDD Rise Detect Brown-out Reset BOR CMR SWR POR SYSRST MCLR
WDTR
Configuration Mismatch Reset Software Reset
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 107
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 108
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
7.0 INTERRUPT CONTROLLER
The PIC32MX5XX/6XX/7XX interrupt module includes the following features: * * * * * * * * * * * * Up to 96 Interrupt Sources Up to 64 Interrupt Vectors Single and Multi-Vector mode Operations Five External Interrupts with Edge Polarity Control Interrupt Proximity Timer Module Freeze in Debug mode Seven User-Selectable Priority Levels for each Vector Four User-Selectable Subpriority Levels within each Priority Dedicated Shadow Set for User-Selectable Priority Level Software can Generate any Interrupt User-Configurable Interrupt Vector Table Location User-Configurable Interrupt Vector Spacing Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. "Interrupt Controller" (DS61108) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. PIC32MX5XX/6XX/7XX devices generate interrupt requests in response to interrupt events from peripheral modules. The interrupt control module exists externally to the CPU logic and prioritizes the interrupt events before presenting them to the CPU.
FIGURE 7-1:
INTERRUPT CONTROLLER MODULE
Interrupt Requests
Vector Number
Interrupt Controller
Priority Level
CPU Core
Shadow Set Number
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 109
PIC32MX5XX/6XX/7XX
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION
IRQ Vector Number Interrupt Bit Location Flag IFS0<0> IFS0<1> IFS0<2> IFS0<3> IFS0<4> IFS0<5> IFS0<6> IFS0<7> IFS0<8> IFS0<9> IFS0<10> IFS0<11> IFS0<12> IFS0<13> IFS0<14> IFS0<15> IFS0<16> IFS0<17> IFS0<18> IFS0<19> IFS0<20> IFS0<21> IFS0<22> IFS0<23> IFS0<24> IFS0<25> IFS0<26> Enable IEC0<0> IEC0<1> IEC0<2> IEC0<3> IEC0<4> IEC0<5> IEC0<6> IEC0<7> IEC0<8> IEC0<9> IEC0<10> IEC0<11> IEC0<12> IEC0<13> IEC0<14> IEC0<15> IEC0<16> IEC0<17> IEC0<18> IEC0<19> IEC0<20> IEC0<21> IEC0<22> IEC0<23> IEC0<24> IEC0<25> IEC0<26> Priority IPC0<4:2> IPC0<12:10> IPC0<20:18> IPC0<28:26> IPC1<4:2> IPC1<12:10> IPC1<20:18> IPC1<28:26> IPC2<4:2> IPC2<12:10> IPC2<20:18> IPC2<28:26> IPC3<4:2> IPC3<12:10> IPC3<20:18> IPC3<28:26> IPC4<4:2> IPC4<12:10> IPC4<20:18> IPC4<28:26> IPC5<4:2> IPC5<12:10> IPC5<20:18> IPC5<28:26> IPC5<28:26> IPC5<28:26> IPC6<4:2> Sub-Priority IPC0<1:0> IPC0<9:8> IPC0<17:16> IPC0<25:24> IPC1<1:0> IPC1<9:8> IPC1<17:16> IPC1<25:24> IPC2<1:0> IPC2<9:8> IPC2<17:16> IPC2<25:24> IPC3<1:0> IPC3<9:8> IPC3<17:16> IPC3<25:24> IPC4<1:0> IPC4<9:8> IPC4<17:16> IPC4<25:24> IPC5<1:0> IPC5<9:8> IPC5<17:16> IPC5<25:24> IPC5<25:24> IPC5<25:24> IPC6<1:0> Interrupt Source(1)
Highest Natural Order Priority CT - Core Timer Interrupt CS0 - Core Software Interrupt 0 CS1 - Core Software Interrupt 1 INT0 - External Interrupt 0 T1 - Timer1 IC1 - Input Capture 1 OC1 - Output Compare 1 INT1 - External Interrupt 1 T2 - Timer2 IC2 - Input Capture 2 OC2 - Output Compare 2 INT2 - External Interrupt 2 T3 - Timer3 IC3 - Input Capture 3 OC3 - Output Compare 3 INT3 - External Interrupt 3 T4 - Timer4 IC4 - Input Capture 4 OC4 - Output Compare 4 INT4 - External Interrupt 4 T5 - Timer5 IC5 - Input Capture 5 OC5 - Output Compare 5 SPI1E - SPI1 Fault SPI1RX - SPI1 Receive Done SPI1TX - SPI1 Transfer Done U1AE - UART1A Error SPI1AE - SPI1A Fault I2C1AB - I2C1A Bus Collision Event U1ARX - UART1A Receiver SPI1ARX - SPI1A Receive Done I2C1AS - I2C1A Slave Event U1ATX - UART1A Transmitter SPI1ATX - SPI1A Transfer Done I2C1AM - I2C1A Master Event I2C1B - I2C1 Bus Collision Event I2C1S - I2C1 Slave Event I2C1M - I2C1 Master Event CN - Input Change Interrupt AD1 - ADC1 Convert Done PMP - Parallel Master Port Note 1: 29 30 31 32 33 34 25 25 25 26 27 28 IFS0<29> IFS0<30> IFS0<31> IFS1<0> IFS1<1> IFS1<2> IEC0<29> IEC0<30> IEC0<31> IEC1<0> IEC1<1> IEC1<2> IPC6<12:10> IPC6<12:10> IPC6<12:10> IPC6<20:18> IPC6<28:26> IPC7<4:2> IPC6<9:8> IPC6<9:8> IPC6<9:8> IPC6<17:16> IPC6<25:24> IPC7<1:0> 28 24 IFS0<28> IEC0<28> IPC6<4:2> IPC6<1:0> 27 24 IFS0<27> IEC0<27> IPC6<4:2> IPC6<1:0> 26 24 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23
Not all interrupt sources are available on all devices. See Table 1 for the list of available peripherals.
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TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
IRQ 35 36 37 Vector Number 29 30 31 Interrupt Bit Location Flag IFS1<3> IFS1<4> IFS1<5> Enable IEC1<3> IEC1<4> IEC1<5> Priority IPC7<12:10> IPC7<20:18> IPC7<28:26> Sub-Priority IPC7<9:8> IPC7<17:16> IPC7<25:24> Interrupt Source(1) CMP1 - Comparator Interrupt CMP2 - Comparator Interrupt U2AE - UART2A Error SPI2AE - SPI2A Fault I2C2AB - I2C2A Bus Collision Event U2ARX - UART2A Receiver SPI2ARX - SPI2A Receive Done I2C2AS - I2C2A Slave Event U2ATX - UART2A Transmitter SPI2ATX - SPI2A Transfer Done IC2AM - I2C2A Master Event U3AE - UART3A Error SPI3AE - SPI3A Fault I2C3AB - I2C3A Bus Collision Event U3ARX - UART3A Receiver SPI3ARX - SPI3A Receive Done I2C3AS - I2C3A Slave Event U3ATX - UART3A Transmitter SPI3ATX - SPI3A Transfer Done IC3AM - I2C3A Master Event I2C2B - I2C2 Bus Collision Event I2C2S - I2C2 Slave Event I2C2M - I2C2 Master Event FSCM - Fail-Safe Clock Monitor RTCC - Real-Time Clock DMA0 - DMA Channel 0 DMA1 - DMA Channel 1 DMA2 - DMA Channel 2 DMA3 - DMA Channel 3 DMA4 - DMA Channel 4 DMA5 - DMA Channel 5 DMA6 - DMA Channel 6 DMA7 - DMA Channel 7 FCE - Flash Control Event USB - USB Interrupt CAN1 - Control Area Network 1 CAN2 - Control Area Network 2 ETH - Ethernet Interrupt IC1E - Input Capture 1 Error IC2E - Input Capture 2 Error IC3E - Input Capture 3 Error IC4E - Input Capture 4 Error IC4E - Input Capture 5 Error PMPE - Parallel Master Port Error U1BE - UART1B Error Note 1:
38
31
IFS1<6>
IEC1<6>
IPC7<28:26>
IPC7<25:24>
39
31
IFS1<7>
IEC1<7>
IPC7<28:26>
IPC7<25:24>
40
32
IFS1<8>
IEC1<8>
IPC8<4:2>
IPC8<1:0>
41
32
IFS1<9>
IEC1<9>
IPC8<4:2>
IPC8<1:0>
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
32 33 33 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 5 9 13 17 21 28 49
IFS1<10> IFS1<11> IFS1<12> IFS1<13> IFS1<14> IFS1<15> IFS1<16> IFS1<17> IFS1<18> IFS1<19> IFS1<20> IFS1<21> IFS1<22> IFS1<23> IFS1<24> IFS1<25> IFS1<26> IFS1<27> IFS1<28> IFS1<29> IFS1<30> IFS1<31> IFS2<0> IFS2<1> IFS2<2> IFS2<3>
IEC1<10> IEC1<11> IEC1<12> IEC1<13> IEC1<14> IEC1<15> IEC1<16> IEC1<17> IEC1<18> IEC1<19> IEC1<20>
IPC8<4:2> IPC8<12:10> IPC8<12:10> IPC8<12:10> IPC8<20:18> IPC8<28:26> IPC9<4:2> IPC9<12:10> IPC9<20:18> IPC9<28:26> IPC10<4:2>
IPC8<1:0> IPC8<9:8> IPC8<9:8> IPC8<9:8> IPC8<17:16> IPC8<25:24> IPC9<1:0> IPC9<9:8> IPC9<17:16> IPC9<25:24> IPC10<1:0> IPC10<9:8>
IEC1<21> IPC10<12:10>
IEC1<22> IPC10<20:18> IPC10<17:16> IEC1<23> IPC10<28:26> IPC10<25:24> IEC1<24> IPC11<4:2> IPC11<1:0> IPC11<9:8> IEC1<25> IPC11<12:10>
IEC1<26> IPC11<20:18> IPC11<17:16> IEC1<27> IPC11<28:26> IPC11<25:24> IEC1<28> IEC1<29> IEC1<30> IEC1<31> IEC2<0> IEC2<1> IEC2<2> IEC2<3> IPC12<4:2> IPC1<12:10> IPC2<12:10> IPC3<12:10> IPC4<12:10> IPC5<12:10> IPC7<4:2> IPC12<12:10> IPC12<1:0> IPC1<9:8> IPC2<9:8> IPC3<9:8> IPC4<9:8> IPC5<9:8> IPC7<1:0> IPC12<9:8>
Not all interrupt sources are available on all devices. See Table 1 for the list of available peripherals.
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TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
IRQ 68 69 70 71 72 73 74 75 -- Vector Number 49 49 50 50 50 51 51 51 -- Interrupt Bit Location Flag IFS2<4> IFS2<5> IFS2<6> IFS2<7> IFS2<8> IFS2<9> IFS2<10> IFS2<11> -- Enable IEC2<4> IEC2<5> IEC2<6> IEC2<7> IEC2<8> IEC2<9> Priority IPC12<12:10> IPC12<12:10> Sub-Priority IPC12<9:8> IPC12<9:8> Interrupt Source(1) U1BRX - UART1B Receiver U1BTX - UART1B Transmitter U2BE - UART2B Error U2BRX - UART2B Receiver U2BTX - UART2B Transmitter U3BE - UART3B Error U3BRX - UART3B Receiver U3BTX - UART3B Transmitter (Reserved) Note 1:
IPC12<20:18> IPC12<17:16> IPC12<20:18> IPC12<17:16> IPC12<20:18> IPC12<17:16> IPC12<28:26> IPC12<25:24>
IEC2<10> IPC12<28:26> IPC12<25:24> IEC2<11> IPC12<28:26> IPC12<25:24> -- -- --
Lowest Natural Order Priority Not all interrupt sources are available on all devices. See Table 1 for the list of available peripherals.
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8.0 OSCILLATOR CONFIGURATION
The PIC32MX5XX/6XX/7XX oscillator system has the following modules and features: * A Total of Four External and Internal Oscillator Options as Clock Sources * On-Chip PLL with User-Selectable Input Divider, Multiplier and Output Divider to Boost Operating Frequency on Select Internal and External Oscillator Sources * On-Chip User-Selectable Divisor Postscaler on Select Oscillator Sources * Software-Controllable Switching Between Various Clock Sources * A Fail-Safe Clock Monitor (FSCM) that Detects Clock Failure and Permits Safe Application Recovery or Shutdown * Dedicated On-Chip PLL for USB Peripheral
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 6. "Oscillator Configuration" (DS61112) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
FIGURE 8-1:
PIC32MX5XX/6XX/7XX FAMILY CLOCK DIAGRAM
USB PLL UFIN USB Clock (48 MHz) PLL x24 div 2 UFRCEN FUPLLEN XT, HS, EC 4 MHz FIN 5 MHz XTPLL, HSPLL, FIN ECPLL, FRCPLL div x div y PLL PLL Input Divider FPLLIDIV<2:0> COSC<2:0> PLL Output Divider PLLODIV<2:0> Postscaler Peripherals div x PBCLK
div x Primary Oscillator (POSC) RF(2) XTAL RS(1) OSC2(4) To Internal Logic Enable div 2 ADC FRC Oscillator 8 MHz typical TUN<5:0>
UFIN 4 MHz FUPLLDIV<2:0>
C1(3)
OSC1
C2(3)
PBDIV<2:0>
PLL Multiplier PLLMULT<2:0>
FRC FRC/16 FRCDIV
CPU and Select Peripherals
div 16 Postscaler
LPRC Oscillator
FRCDIV<2:0> 31.25 kHz typical
LPRC
Secondary Oscillator (SOSC) SOSCO 32.768 kHz SOSCEN and FSOSCEN SOSCI SOSC Clock Control Logic Fail-Safe Clock Monitor A series resistor, RS, may be required for AT strip cut crystals. The internal feedback resistor, RF, is typically in the range of 2 to 10 M Refer to Section 6. "Oscillator Configuration" (DS61112) in the "PIC32MX Family Reference Manual" for help in determining the best oscillator components. PBCLK out is available on the OSC2 pin in certain clock modes. FSCM INT FSCM Event
Notes:
1. 2. 3. 4.
NOSC<2:0> COSC<2:0> OSWEN FSCMEN<1:0>
WDT, PWRT
Timer1, RTCC
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NOTES:
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PIC32MX5XX/6XX/7XX
9.0 PREFETCH CACHE
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. "Prefetch Cache" (DS61119) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching.
9.1
* * * * * * * *
Features
16 Fully Associative Lockable Cache Lines 16-Byte Cache Lines Up to Four Cache Lines Allocated to Data Two Cache Lines with Address Mask to Hold Repeated Instructions Pseudo LRU Replacement Policy All Cache Lines are Software Writable 16-Byte Parallel Memory Fetch Predictive Instruction Prefetch
FIGURE 9-1:
PREFETCH MODULE BLOCK DIAGRAM
FSM CTRL Tag Logic Cache Line
BMX/CPU
CTRL
Bus Ctrl Cache Ctrl Prefetch Ctrl Hit LRU Miss LRU Hit Logic PreFetch Prefetch Pre-Fetch Tag CTRL PreFetch Prefetch Pre-Fetch RDATA Cache Line Address Encode
BMX/CPU
RDATA
PFM
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NOTES:
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PIC32MX5XX/6XX/7XX
10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER
* Automatic Word-Size Detection: - Transfer granularity, down to byte level - Bytes need not be word-aligned at source and destination * Fixed Priority Channel Arbitration * Flexible DMA Channel Operating modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer modes - Channel-to-channel chaining * Flexible DMA Requests: - A DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request source - A DMA transfer abort can be selected from any of the peripheral interrupt sources - Pattern (data) match transfer termination * Multiple DMA Channel Status Interrupts: - DMA channel block transfer complete - Source empty or half empty - Destination full or half full - DMA transfer aborted due to an external event - Invalid DMA address generated * DMA Debug Support Features: - Most recent address accessed by a DMA channel - Most recent DMA channel to transfer data * CRC Generation Module: - CRC module can be assigned to any of the available channels - CRC module is highly configurable
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. "Direct Memory Access (DMA) Controller" (DS61117) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The PIC32MX Direct Memory Access (DMA) controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the PIC32MX (such as Peripheral Bus (PBUS) devices: SPI, UART, I2CTM, etc.) or memory itself. Following are some of the key features of the DMA controller module: * Four Identical Channels, each Featuring: - Auto-Increment Source and Destination Address registers - Source and Destination Pointers - Memory to memory and memory to peripheral transfers
FIGURE 10-1:
INT Controller
DMA BLOCK DIAGRAM
System IRQ
Peripheral Bus
Address Decoder
Channel 0 Control
SE L
I0
Channel 1 Control
I1
Y
Bus Interface
Device Bus + Bus Arbitration
I2
Global Control (DMACON)
Channel n Control
In
L SE
Channel Priority Arbitration
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NOTES:
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PIC32MX5XX/6XX/7XX
11.0 USB ON-THE-GO (OTG)
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. "USB OnThe-Go (OTG)" (DS61126) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module. The PIC32MX USB module includes the following features: * * * * * * * * * USB Full-Speed Support for Host and Device Low-Speed Host Support USB OTG Support Integrated Signaling Resistors Integrated Analog Comparators for VBUS Monitoring Integrated USB Transceiver Transaction Handshaking Performed by Hardware Endpoint Buffering Anywhere in System RAM Integrated DMA to Access System RAM and Flash
Note: IMPORTANT! The implementation and use of the USB specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations.
The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 full-speed and low-speed embedded host, full-speed device or OTG implementation with a minimum of external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller. The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32MX USB OTG module is presented in Figure 11-1.
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FIGURE 11-1: PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM
USBEN USB Suspend CPU Clock Not POST Sleep Primary Oscillator (POST) Div x OSC1
FRC Oscillator 8 MHz Typical TUN<5:0>(4)
UFIN(5)
PLL
Div 2 FUPLLEN(6) UFRCEN(3)
FUPLLIDIV(6) USB Suspend
Sleep or Idle
To Clock Generator for Core and Peripherals
OSC2 (PB Out)(1)
USB Module
USB Voltage Comparators 48 MHz USB Clock(7)
SRP Charge Bus SRP Discharge
Full Speed Pull-up D+(2)
Host Pull-down Transceiver Low Speed Pull-up
Registers and Control Interface SIE
D-(2) DMA Host Pull-down System RAM
ID Pull-up ID(8) Vibes(8)
VUSB
Transceiver Power 3.3V
Note 1: 2: 3: 4: 5: 6: 7: 8:
PB clock is only available on this pin for select EC modes. Pins can be used as digital inputs when USB is not enabled. This bit field is contained in the OSCCON register. This bit field is contained in the OSCTRM register. USB PLL UFIN requirements: 4 MHz. This bit field is contained in the DEVCFG2 register. A 48 MHz clock is required for proper USB operation. Pins can be used as GPIO when the USB module is disabled.
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PIC32MX5XX/6XX/7XX
12.0 I/O PORTS
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. "I/O Ports" (DS61120) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
General purpose I/O pins are the simplest of peripherals. They allow the PIC(R) MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. Following are some of the key features of this module: * Individual Output Pin Open-Drain Enable/Disable * Individual Input Pin Weak Pull-up Enable/Disable * Monitor Selective Inputs and Generate Interrupt when Change in Pin State is Detected * Operation during CPU Sleep and Idle modes * Fast Bit Manipulation using CLR, SET and INV Registers Figure 12-1 shows a block diagram of a typical multiplexed I/O port.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data
PIO Module RD ODC
Data Bus SYSCLK WR ODC RD TRIS
D
Q
ODC CK EN Q 1 0 0 1 D Q 1 0 Output Multiplexers D Q IO Pin LAT CK EN Q TRIS CK EN Q IO Cell
WR TRIS
WR LAT WR PORT RD LAT
1 RD PORT 0 Sleep SYSCLK Synchronization Peripheral Input R Peripheral Input Buffer Q Q D CK Q Q D CK
Legend: Note:
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details. This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here.
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12.1 Parallel I/O (PIO) Ports
12.1.2 DIGITAL INPUTS
All port pins have three registers (TRIS, LAT and PORT) that are directly associated with their operation. TRIS is a Data Direction or Tri-State Control register that determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1 configures the corresponding I/O pin as an input; setting a TRISx register bit = 0 configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device Reset. Certain I/O pins are shared with analog peripherals and default to analog inputs after a device Reset. PORT is a register used to read the current state of the signal applied to the port I/O pins. Writing to a PORTx register performs a write to the port's latch, LATx register, latching the data to the port's I/O pins. LAT is a register used to write data to the port I/O pins. The LATx Latch register holds the data written to either the LATx or PORTx registers. Reading the LATx Latch register reads the last value written to the corresponding PORT or Latch register. Not all port I/O pins are implemented on some devices, therefore, the corresponding PORTx, LATx and TRISx register bits will read as zeros. Pins are configured as digital inputs by setting the corresponding TRIS register bits = 1. When configured as inputs, they are either TTL buffers or Schmitt Triggers. Several digital pins share functionality with analog inputs and default to the analog inputs at POR. Setting the corresponding bit in the AD1PCFG register = 1 enables the pin as a digital pin. The maximum input voltage allowed on the input pins is the same as the maximum VIH specification. Refer to Section 31.0 "Electrical Characteristics" for VIH specification details.
Note:
Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications.
12.1.3
ANALOG INPUTS
12.1.1
CLR, SET AND INV REGISTERS
Every I/O module register has a corresponding CLR (clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as `1' are modified. Bits specified as `0' are not modified. Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read. To set PORTC bit 0, write to the LATSET register: LATCSET = 0x0001; To clear PORTC bit 0, write to the LATCLR register: LATCCLR = 0x0001; To toggle PORTC bit 0, write to the LATINV register: LATCINV = 0x0001;
Note:
Certain pins can be configured as analog inputs used by the ADC and comparator modules. Setting the corresponding bits in the AD1PCFG register = 0 enables the pin as an analog input pin and must have the corresponding TRIS bit set = 1 (input). If the TRIS bit is cleared = 0 (output), the digital output level (VOH or VOL) will be converted. Any time a port I/O pin is configured as analog, its digital input is disabled and the corresponding PORTx register bit will read `0'. The AD1PCFG register has a default value of `0x0000'; therefore, all pins that share ANx functions are analog (not digital) by default.
12.1.4
DIGITAL OUTPUTS
Pins are configured as digital outputs by setting the corresponding TRIS register bits = 0. When configured as digital outputs, these pins are CMOS drivers or can be configured as open-drain outputs by setting the corresponding bits in the ODCx Open-Drain Configuration register. The open-drain feature allows generation of outputs higher than VDD (e.g., 5V) on any desired 5V tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. See the "Pin Diagrams" section for the available pins and their functionality.
Using a PORTxINV register to toggle a bit is recommended because the operation is performed in hardware atomically, using fewer instructions, as compared to the traditional read-modify-write method shown below: PORTC ^= 0x0001;
12.1.5
ANALOG OUTPUTS
Certain pins can be configured as analog outputs, such as the CVREF output voltage used by the comparator module. Configuring the comparator reference module to provide this output will present the analog output voltage on the pin, independent of the TRIS register setting for the corresponding pin.
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13.0 TIMER1
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS61105) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
This family of PIC32MX devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator (SOSC) for Real-Time Clock (RTC) applications. The following modes are supported: * * * * Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer
13.1
Additional Supported Features
* Selectable Clock Prescaler * Timer Operation during CPU Idle and Sleep mode * Fast Bit Manipulation using CLR, SET and INV registers * Asynchronous mode can be used with the SOSC to Function as a Real-Time Clock (RTC).
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM(1)
PR1 Equal
16-Bit Comparator
TSYNC (T1CON<2>) 1 Sync
TMR1 Reset 0 T1IF Event Flag 0 1 Q Q D TGATE (T1CON<7>) TCS (T1CON<1>) ON (T1CON<15>)
TGATE (T1CON<7>)
SOSCO/T1CK SOSCEN SOSCI Gate Sync PBCLK
x1 Prescaler 1, 8, 64, 256
10 00
2 TCKPS<1:0> (T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word, DEVCFG1.
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NOTES:
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14.0 TIMER2/3, TIMER4/5
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS61105) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: * Synchronous Internal 32-Bit Timer * Synchronous Internal 32-Bit Gated Timer * Synchronous External 32-Bit Timer
Note:
In this chapter, references to registers, TxCON, TMRx and PRx, use `x' to represent Timer2 through 5 in 16-bit modes. In 32-bit modes, `x' represents Timer2 or 4; `y' represents Timer3 or 5.
14.1
Additional Supported Features
This family of PIC32MX devices features four synchronous 16-bit timers (default) that can operate as a free-running interval timer for various timing applications and counting external events. The following modes are supported: * Synchronous Internal 16-Bit Timer * Synchronous Internal 16-Bit Gated Timer * Synchronous External 16-Bit Timer
* Selectable Clock Prescaler * Timers Operational during CPU Idle * Time Base for Input Capture and Output Compare modules (Timer2 and Timer3 only) * ADC Event Trigger (Timer3 only) * Fast Bit Manipulation using CLR, SET and INV registers
FIGURE 14-1:
TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)
TMRx Sync
ADC Event Trigger(1)
Equal
Comparator x 16
PRx Reset 0 1 Q Q D TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) TxCK(2) Gate Sync PBCLK
TxIF Event Flag
TGATE (TxCON<7>)
x1 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>)
10 00
Note 1: ADC event trigger is available on Timer3 only. 2: TxCK pins are not available on 64-pin devices.
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FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1)
Reset TMRy TMRx LS Half Word Sync
MS Half Word ADC Event Trigger(3) Equal
32-Bit Comparator
PRy TyIF Event Flag 0 1 TGATE (TxCON<7>)
PRx
Q Q
D
TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>)
TxCK(2) Gate Sync PBCLK
x1 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>)
10 00
Note 1: In this diagram, the use of "x' in registers, TxCON, TMRx, PRx, TxCK, refers to either Timer2 or Timer4; the use of `y' in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5. 2: TxCK pins are not available on 64-pin devices. 3: ADC event trigger is available only on the Timer2/3 pair.
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PIC32MX5XX/6XX/7XX
15.0 INPUT CAPTURE
2. 3. 4.
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. "Input Capture" (DS61122) of the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
Capture timer value on every edge (rising and falling) Capture timer value on every edge (rising and falling), specified edge first. Prescaler Capture Event modes - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin
Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock. Other operational features include: * Device Wake-up from Capture Pin during CPU Sleep and Idle modes * Interrupt on Input Capture Event * 4-Word FIFO Buffer for Capture Values Interrupt Optionally Generated after 1, 2, 3 or 4 Buffer Locations are Filled * Input Capture can also be used to Provide Additional Sources of External Interrupts
The input capture module is useful in applications requiring frequency (period) and pulse measurement. The input capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The following events cause capture events: 1. Simple Capture Event modes - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin
FIGURE 15-1:
ICx Input
INPUT CAPTURE BLOCK DIAGRAM
Timer3 Timer2 ICTMR 0 C32 FIFO Control ICxBUF<31:16> ICxBUF<15:0> 1
Prescaler 1, 4, 16
Edge Detect
ICM<2:0>
ICM<2:0> FEDGE
ICBNE ICOV ICxCON Interrupt Event Generation Data Space Interface
ICI<1:0>
Interrupt
Peripheral Data Bus
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NOTES:
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16.0 OUTPUT COMPARE
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. "Output Capture" (DS61111) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation. The following are some of the key features: * Multiple Output Compare Modules in a Device * Programmable Interrupt Generation on Compare Event * Single and Dual Compare modes * Single and Continuous Output Pulse Generation * Pulse-Width Modulation (PWM) mode * Hardware-Based PWM Fault Detection and Automatic Output Disable * Programmable Selection of 16-Bit or 32-Bit Time Bases * Can Operate from Either of Two Available 16-Bit Time Bases or a Single 32-Bit Time Base
FIGURE 16-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit OCxIF(1)
OCxRS(1)
OCxR(1)
Output Logic 3 OCM<2:0> Mode Select
S R
Q
OCx(1) Output Enable OCFA or OCFB(2)
Comparator
0
1
OCTSEL
0
1
16
16
TMR Register Inputs from Time Bases(3)
Period Match Signals from Time Bases(3)
Note 1: Where `x' is shown, reference is made to the registers associated with the respective output compare channels, 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.
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NOTES:
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17.0 SERIAL PERIPHERAL INTERFACE (SPI)
The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, A/D Converters, etc. The PIC32MX SPI module is compatible with Motorola(R) SPI and SIOP interfaces. Following are some of the key features of this module: * * * * * Master and Slave modes Support Four Different Clock Formats Enhanced Framed SPI Protocol Support User-Configurable 8-Bit, 16-Bit and 32-Bit Data Width Separate SPI FIFO Buffers for Receive and Transmit - FIFO buffers act as 4/8/16-level deep FIFOs based on 32/16/8-bit data width Programmable Interrupt Event on Every 8-Bit, 16-Bit and 32-Bit Data Transfer Operation during CPU Sleep and Idle mode Fast Bit Manipulation using CLR, SET and INV Registers
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. "Serial Peripheral Interface (DS61106) in the "PIC32MX (SPI)" Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
* * *
FIGURE 17-1:
SPI MODULE BLOCK DIAGRAM
Internal Data Bus
SPIxBUF Read SPIxRXB FIFO Write SPIxTXB FIFO
FIFOs Share Address SPIxBUF
Transmit
Receive SPIxSR SDIx SDOx Slave Select and Frame Sync Control bit 0 Shift Control Clock Control
Edge Select Baud Rate Generator
SSx/FSYNC
PBCLK
SCKx
Enable Master Clock Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
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18.0 INTER-INTEGRATED CIRCUIT (I2CTM)
The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard. Figure 18-1 shows the I2C module block diagram. Each I2C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data. Each I2C module offers the following key features: * I2C Interface Supporting both Master and Slave Operation * I2C Slave mode Supports 7 and 10-Bit Address * I2C Master mode Supports 7 and 10-Bit Address * I2C Port allows Bidirectional Transfers between Master and Slaves * Serial Clock Synchronization for I2C Port can be used as a Handshake Mechanism to Suspend and Resume Serial Transfer (SCLREL control) * I2C Supports Multi-Master Operation; Detects Bus Collision and Arbitrates Accordingly * Provides Support for Address Bit Masking
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. "InterIntegrated Circuit" (DS61116) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
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FIGURE 18-1: I2CTM BLOCK DIAGRAM (X = 1 OR 2)
Internal Data Bus I2CxRCV Shift Clock I2CxRSR LSB SDAx Address Match
Read
SCLx
Match Detect
Write I2CxMSK Write Read
I2CxADD Read Start and Stop Bit Detect Start and Stop Bit Generation Control Logic
Write I2CxSTAT Read Write I2CxCON Read
Collision Detect
Acknowledge Generation Clock Stretching
Write
I2CxTRN LSB Shift Clock Reload Control Read
Write I2CxBRG Read
BRG Down Counter
PBCLK
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PIC32MX5XX/6XX/7XX
19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)
1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. "Universal Asynchronous Receiver Transmitter (DS61107) in the "PIC32MX (UART)" Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The primary features of the UART module are: * * * * * * * * * * * * * Full-Duplex, 8-Bit or 9-Bit Data Transmission Even, Odd or No Parity Options (for 8-bit data) One or Two Stop Bits Hardware Auto-Baud Feature Hardware Flow Control Option Fully Integrated Baud Rate Generator (BRG) with 16-Bit Prescaler Baud Rates Ranging from 76 bps to 20 Mbps at 80 MHz 8-Level Deep First-In-First-Out (FIFO) Transmit Data Buffer 8-Level Deep FIFO Receive Data Buffer Parity, Framing and Buffer Overrun Error Detection Support for Interrupt Only on Address Detect (9th bit = 1) Separate Transmit and Receive Interrupts Loopback mode for Diagnostic Support
Note
The UART module is one of the serial I/O modules available in PIC32MX5XX/6XX/7XX family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols, such as RS-232, RS-485, LIN 1.2 and IrDA(R). The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder.
* LIN 1.2 Protocol Support * IrDA Encoder and Decoder with 16x Baud Clock Output for External IrDA Encoder/Decoder Support Figure 19-1 shows a simplified block diagram of the UART.
FIGURE 19-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA(R)
BCLKx
Hardware Flow Control
UxRTS UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
Note:
Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.
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Figure 19-2 and Figure 19-3 illustrate typical receive and transmit timing for the UART module.
FIGURE 19-2:
UART RECEPTION
Char 1 Char 2-4 Char 5-10 Char 11-13
Read to UxRXREG
UxRX
Start 1
Stop
Start 2
Stop 4
Start 5
Stop 10 Start 11
Stop 13
RIDLE Cleared by Software OERR Cleared by Software UxRXIF URXISEL = 00
Cleared by Software
UxRXIF URXISEL = 01
UxRXIF URXISEL = 10
FIGURE 19-3:
TRANSMISSION (8-BIT OR 9-BIT DATA)
8 into TxBUF
Write to UxTXREG TSR BCLK/16 (Shift Clock) UxTX Start Bit 0 Bit 1 Pull from Buffer
Stop
Start
Bit 1
UxTXIF UTXISEL = 00
UxTXIF UTXISEL = 01
UxTXIF UTXISEL = 10
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20.0 PARALLEL MASTER PORT (PMP)
Key features of the PMP module include: * * * * 8-Bit, 16-Bit Interface Up to 16 Programmable Address Lines Up to Two Chip Select Lines Programmable Strobe Options - Individual read and write strobes, or - Read/write strobe with enable strobe Address Auto-Increment/Auto-Decrement Programmable Address/Data Multiplexing Programmable Polarity on Control Signals Parallel Slave Port Support - Legacy addressable - Address support - 4-byte deep auto-incrementing buffer Programmable Wait States Operates during CPU Sleep and Idle modes Fast Bit Manipulation using CLR, SET and INV Registers Freeze Option for In-Circuit Debugging
Note:
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. "Parallel Master Port (PMP)" (DS61128) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
* * * *
* * * *
The PMP is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable.
On 64-pin devices, data pins, PMD<15:8>, are not available.
FIGURE 20-1:
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus Data Bus Control Lines
PIC32MX5XX/6XX/7XX Parallel Master Port
PMA<0> PMALL PMA<1> PMALH
Up to 16-Bit Address
PMA<13:2> PMA<14> PMCS1 PMA<15> PMCS2
Flash EEPROM SRAM
PMRD PMRD/PMWR PMWR PMENB
Microcontroller
LCD
FIFO Buffer
PMD<7:0> PMD<15:8>(1)
16/8-Bit Data (with or without multiplexed addressing)
Note 1:
On 64-pin devices, data pins, PMD<15:8>, are not available in 16-Bit Master modes.
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21.0 REAL-TIME CLOCK AND CALENDAR (RTCC)
Following are some of the key features of this module: * * * * * Time: Hours, Minutes and Seconds 24-Hour Format (Military Time) Visibility of One Half Second Period Provides Calendar: Weekday, Date, Month and Year Alarm Intervals are Configurable for Half of a Second, One Second, 10 Seconds, One Minute, 10 Minutes, One Hour, One Day, One Week, One Month and One Year Alarm Repeat with Decrementing Counter Alarm with Indefinite Repeat: Chime Year Range: 2000 to 2099 Leap Year Correction BCD Format for Smaller Firmware Overhead Optimized for Long-Term Battery Operation Fractional Second Synchronization User Calibration of the Clock Crystal Frequency with Auto-Adjust Calibration Range: 0.66 Seconds Error per Month Calibrates up to 260 ppm of Crystal Error Requirements: External 32.768 kHz Clock Crystal Alarm Pulse or Seconds Clock Output on RTCC Pin
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. "Real-Time Clock and Calendar (RTCC)" (DS61125) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
* * * * * * * * * * * *
The PIC32MX RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time.
FIGURE 21-1:
RTCC BLOCK DIAGRAM
32.768 kHz Input from Secondary Oscillator (SOSC)
RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVAL YEAR, MTH, DAY WKDAY HR, MIN, SEC Comparator MTH, DAY Compare Registers with Masks Repeat Counter ALRMVAL WKDAY HR, MIN, SEC
RTCC Interrupt RTCC Interrupt Logic Alarm Pulse Seconds Pulse RTCC Pin
RTCOE
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22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)
* One Unipolar, Differential Sample and Hold Amplifier (SHA) * Automatic Channel Scan mode * Selectable Conversion Trigger Source * 16-word Conversion Result Buffer * Selectable Buffer Fill modes * Eight Conversion Result Format Options * Operation during CPU Sleep and Idle modes A block diagram of the 10-bit ADC is shown in Figure 22-1. The 10-bit ADC has up to 16 analog input pins, designated AN0-AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. The analog inputs are connected through two multiplexers (MUXs) to one SHA. The analog input MUXs can be switched between two sets of analog inputs between conversions. Unipolar differential conversions are possible on all channels, other than the pin used as the reference, using a reference input pin (see Figure 22-1). The Analog Input Scan mode sequentially converts user-specified channels. A control register specifies which analog input channels will be included in the scanning sequence. The 10-bit ADC is connected to a 16-word result buffer. Each 10-bit result is converted to one of eight 32-bit output formats when it is read from the result buffer.
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. "10-Bit Analog-to-Digital Converter (ADC)" (DS61104) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The PIC32MX5XX/6XX/7XX 10-bit Analog-to-Digital (A/D) Converter (or ADC) includes the following features: * Successive Approximation Register (SAR) Conversion * Up to 1 Msps Conversion Speed * Up to 16 Analog Input Pins * External Voltage Reference Input Pins
FIGURE 22-1:
ADC1 MODULE BLOCK DIAGRAM
VREF+(1) AVDD VREF-(1) AVSS
VCFG<2:0> AN0 AN15 Channel Scan CH0SA<4:0> CSCNA AN1 VREFL ADC1BUFE ADC1BUFF CH0SB<4:0> S/H + SAR ADC VREFH VREFL ADC1BUF0 ADC1BUF1 ADC1BUF2
CH0NA
CH0NB
Alternate Input Selection Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
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FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADRC
FRC
Div 2 ADCS<7:0> 8 ADC Conversion Clock Multiplier 2, 4,..., 512
0
TAD
1
TPB
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23.0 CONTROLLER AREA NETWORK (CAN)
* Message Reception and Transmission: - 32 message FIFOs - Each FIFO can have up to 32 messages for a total of 1024 messages - FIFO can be a transmit message FIFO or a receive message FIFO - User-defined priority levels for message FIFOs used for transmission - 32 acceptance filters for message filtering - Four acceptance filter mask registers for message filtering - Automatic response to remote transmit request - DeviceNetTM addressing support * Additional Features: - Loopback, Listen All Messages and Listen Only modes for self-test, system diagnostics and bus monitoring - Low-power operating modes - CAN module is a bus master on the PIC32MX system bus - Use of DMA is not required - Dedicated time-stamp timer - Dedicated DMA channels - Data Only Message Reception mode Figure 23-1 illustrates the general structure of the CAN module.
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 34. "Controller Area Network (CAN)" in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The Controller Area Network (CAN) module supports the following key features: * Standards Compliance: - Full CAN 2.0B compliance - Programmable bit rate up to 1 Mbps
FIGURE 23-1:
CxTX
PIC32MX CAN MODULE BLOCK DIAGRAM
32 Filters 4 Masks CxRX CAN Module CPU
System Bus
Up to 32 Message Buffers
System RAM Message Buffer 31 Message Buffer 31 Message Buffer 31
Message Buffer Size 2 or 4 Words
Message Buffer 1 Message Buffer 0 FIFO0
Message Buffer 1 Message Buffer 0 FIFO1 CAN Message FIFO (up to 32 FIFOs)
Message Buffer 1 Message Buffer 0 FIFO31
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24.0 ETHERNET CONTROLLER
Following are some of the key features of this module: * * * * * * * * Supports 10/100 Mbps Data Transfer Rates Supports Full-Duplex and Half-Duplex Operation Supports RMII and MII PHY Interface Supports MIIM PHY Management Interface Supports both Manual and Automatic Flow Control RAM Descriptor-Based DMA Operation for Both Receive and Transmit Path Fully Configurable Interrupts Configurable Receive Packet Filtering - CRC Check - 64-Byte Pattern Match - Broadcast, Multicast and Unicast packets - Magic PacketTM - 64-Bit Hash Table - Runt Packet Supports Packet Payload Checksum Calculation Supports Various Hardware Statistics Counters
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 35. "Ethernet Controller" in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The Ethernet controller is a bus master module that interfaces with an off-chip Physical Layer (PHY) to implement a complete Ethernet node in a system.
* *
Figure 24-1 shows a block diagram of the Ethernet controller.
FIGURE 24-1:
ETHERNET CONTROLLER BLOCK DIAGRAM
TX FIFO
TX DMA TX Bus Master
TX BM TX Function
TX Flow Control System Bus RX DMA RX Bus Master
MII/RMII IF RX FIFO RX Flow Control RX BM MAC RX Filter RX Function External PHY
Checksum
MIIM IF
DMA Control Registers
Ethernet DMA
MAC Control and Configuration Registers
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Fast Peripheral Bus
Host IF
Ethernet Controller
Preliminary
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Table 24-1, Table 24-2, Table 24-3 and Table 24-4 show four interfaces and the associated pins that can be used with the Ethernet Controller.
TABLE 24-3:
MII MODE ALTERNATE INTERFACE SIGNALS (FMIIEN = 1, FETHIO = 0)(1)
Description
TABLE 24-1:
MII MODE DEFAULT INTERFACE SIGNALS (FMIIEN = 1, FETHIO = 1)
Description
Pin Name
AEMDC AEMDIO AETXCLK AETXEN AETXD0 AETXD1 AETXD2 AETXD3 AETXERR AERXCLK AERXDV AERXD0 AERXD1 AERXD2 AERXD3 AERXERR AECRS AECOL
Note 1:
Management Clock Management IO Transmit Clock Transmit Enable Transmit Data Transmit Data Transmit Data Transmit Data Transmit Error Receive Clock Receive Data Valid Receive Data Receive Data Receive Data Receive Data Receive Error Carrier Sense Collision Indication MII Alternate Interface is not available on 64-pin devices.
Pin Name
EMDC EMDIO ETXCLK ETXEN ETXD0 ETXD1 ETXD2 ETXD3 ETXERR ERXCLK ERXDV ERXD0 ERXD1 ERXD2 ERXD3 ERXERR ECRS ECOL
Management Clock Management IO Transmit Clock Transmit Enable Transmit Data Transmit Data Transmit Data Transmit Data Transmit Error Receive Clock Receive Data Valid Receive Data Receive Data Receive Data Receive Data Receive Error Carrier Sense Collision Indication
TABLE 24-4: TABLE 24-2: RMII MODE DEFAULT INTERFACE SIGNALS (FMIIEN = 0, FETHIO = 1)
Description
RMII MODE ALTERNATE INTERFACE SIGNALS (FMIIEN = 0, FETHIO = 0)
Description
Pin Name
Pin Name
AEMDC AEMDIO AETXEN AETXD0 AETXD1 AEREFCLK AECRSDV AERXD0 AERXD1 AERXERR
Management Clock Management IO Transmit Enable Transmit Data Transmit Data Reference Clock Carrier Sense - Receive Data Valid Receive Data Receive Data Receive Error
EMDC EMDIO ETXEN ETXD0 ETXD1 EREFCLK ECRSDV ERXDV ERXD0 ERXD1 ERXERR
Management Clock Management IO Transmit Enable Transmit Data Transmit Data Reference Clock Carrier Sense - Receive Data Valid Receive Data Valid Receive Data Receive Data Receive Error
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2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
25.0 COMPARATOR
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. "Comparator" (DS61110) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The PIC32MX5XX/6XX/7XX analog comparator module contains two comparators that can be configured in a variety of ways. Following are some of the key features of this module: * Selectable Inputs Available Include: - Analog inputs multiplexed with I/O pins - On-chip internal absolute Voltage Reference (IVREF) - Comparator Voltage Reference (CVREF) * Outputs can be Inverted * Selectable Interrupt Generation A block diagram of the comparator module is shown in Figure 25-1.
FIGURE 25-1:
COMPARATOR BLOCK DIAGRAM
Comparator 1
CREF ON COUT (CM1CON) C1OUT (CMSTAT)
C1IN+(1) CVREF
(2)
CPOL
C1OUT CCH<1:0> C1 COE
C1INC1IN+ C2IN+ IVREF(2)
Comparator 2
CREF C2IN+ CVREF
(2)
ON
CPOL
COUT (CM2CON) C2OUT (CMSTAT)
C2OUT CCH<1:0> C2 COE
C2INC2IN+ C1IN+ IVREF(2) Note 1: 2:
On devices with a USB module, and when the module is enabled, this pin is controlled by the USB module, and therefore, is not available as a comparator input. Internally connected.
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Preliminary
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NOTES:
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PIC32MX5XX/6XX/7XX
26.0 COMPARATOR VOLTAGE REFERENCE (CVREF)
The CVREF module is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. A block diagram of the module is shown in Figure 26-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output. The comparator voltage reference has the following features: * High and low range selection * Sixteen output levels available for each range * Internally connected to comparators to conserve device pins * Output can be connected to a pin
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20. "Comparator Voltage (DS61109) in the Reference (CVREF)" "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
FIGURE 26-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+ AVDD
CVRSS = 1
CVRSS = 0
8R R R R
CVR<3:0>
CVREN
CVREF
16 Steps
16-to-1 MUX
R
CVREFOUT CVRCON
R R R
CVRR VREFAVSS CVRSS = 1
8R
CVRSS = 0
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Preliminary
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NOTES:
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PIC32MX5XX/6XX/7XX
27.0 POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. "Power-Saving Features" (DS61130) in the "PIC32MX Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
* SOSC Idle mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled. * LPRC Idle mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running. * Sleep mode: the CPU, the system clock source and any peripherals that operate from the system clock source are Halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device.
27.3
Power-Saving Operation
This section describes power-saving features for the PIC32MX5XX/6XX/7XX. The PIC32MX devices offer a total of nine methods and modes, organized into two categories, that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, power saving is controlled by software.
Peripherals and the CPU can be Halted or disabled to further reduce power consumption.
27.3.1
SLEEP MODE
27.1
Power Saving with CPU Running
When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, lowering the PBCLK and by individually disabling modules. These methods are grouped into the following categories: * FRC Run mode: the CPU is clocked from the FRC clock source with or without postscalers. * LPRC Run mode: the CPU is clocked from the LPRC clock source. * SOSC Run mode: the CPU is clocked from the SOSC clock source. In addition, the Peripheral Bus Scaling mode is available where peripherals are clocked at the programmable fraction of the CPU clock (SYSCLK).
Sleep mode has the lowest power consumption of the device power-saving operating modes. The CPU and most peripherals are Halted. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in Sleep. Sleep mode includes the following characteristics: * The CPU is Halted. * The system clock source is typically shut down. See Section 27.3.3 "Peripheral Bus Scaling Method" for specific information. * There can be a wake-up delay based on the oscillator selection. * The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode. * The BOR circuit, if enabled, remains operative during Sleep mode. * The WDT, if enabled, is not automatically cleared prior to entering Sleep mode. * Some peripherals can continue to operate at limited functionality in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART and peripherals that use an external clock input or the internal LPRC oscillator (e.g., RTCC, Timer1 and Input Capture). * I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep. * The USB module can override the disabling of the Posc or FRC. Refer to the USB section for specific details. * Modules can be individually disabled by software prior to entering Sleep in order to further reduce consumption.
27.2
CPU Halted Methods
The device supports two power-saving modes, Sleep and Idle, both of which Halt the clock to the CPU. These modes operate with all clock sources, as listed below: * POSC Idle mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. * FRC Idle mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled.
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The processor will exit, or `wake-up', from Sleep on one of the following events: * On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. * On any form of device Reset. * On a WDT time-out. If the interrupt priority is lower than or equal to the current priority, the CPU will remain Halted, but the PBCLK will start running and the device will enter into Idle mode. The processor will wake or exit from Idle mode on the following events: * On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of the CPU. If the priority of the interrupt event is lower than or equal to current priority of the CPU, the CPU will remain Halted and the device will remain in Idle mode. * On any form of device Reset * On a WDT time-out interrupt
27.3.2
IDLE MODE
27.3.3
In Idle mode, the CPU is Halted but the System Clock (SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is Halted. Peripherals can be individually configured to Halt when entering Idle by setting their respective SIDL bit. Latency, when exiting Idle mode, is very low due to the CPU oscillator source remaining active.
Notes: Changing the PBCLK divider ratio requires recalculation of peripheral timing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a POSC of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing calculation required for a peripheral should be performed with the new PB clock frequency instead of scaling the previous value based on a change in the PB divisor ratio.
PERIPHERAL BUS SCALING METHOD
Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals, such as the interrupt controller, DMA, bus matrix and prefetch cache, are clocked directly from SYSCLK. As a result, they are not affected by PBCLK divisor changes. Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as USB, interrupt controller, DMA, bus matrix and prefetch cache are clocked directly from SYSCLK. As a result, they are not affected by PBCLK divisor changes Changing the PBCLK divisor affects: * The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode, this results in a latency of one to seven SYSCLKs. * The power consumption of the peripherals. Power consumption is directly proportional to the frequency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals. To minimize dynamic power, the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock requirements, such as baud rate accuracy, should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value.
Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator startup delay would be applied when exiting Idle. However, when switching back to POSC, the appropriate PLL and or oscillator start-up/lock delays would be applied. The device enters Idle mode when the SLPEN (OSCCON<4>) bit is clear and a WAIT instruction is executed.
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PIC32MX5XX/6XX/7XX
28.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section in the "PIC32MX Family Reference Manual" (DS61132), which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: * * * * Flexible Device Configuration Watchdog Timer JTAG Interface In-Circuit Serial ProgrammingTM (ICSPTM)
28.1
Configuration Bits
The Configuration bits can be programmed to select various device configurations.
REGISTER 28-1:
r-0 -- bit 31 r-1 -- bit 23 R/P-1 bit 15 r-1 -- bit 7
Legend:
DEVCFG0: DEVICE CONFIGURATION WORD 0
r-1 -- r-1 -- R/P-1 CP r-1 -- r-1 -- r-1 -- R/P-1 BWP bit 24 r-1 -- r-1 -- r-1 -- R/P-1 R/P-1 R/P-1 R/P-1 bit 16 R/P-1 R/P-1 R/P-1 r-1 -- r-1 -- r-1 -- r-1 -- bit 8 r-1 -- r-1 -- r-1 -- R/P-1 ICESEL r-1 -- R/P-1 R/P-1 bit 0
PWP<7:4>
PWP<3:0>
DEBUG<1:0>
R = Readable bit U = Unimplemented bit bit 31 bit 30-29 bit 28
W = Writable bit
P = Programmable bit
r = Reserved bit
-n = Bit Value at POR: (`0', `1', x = Unknown)
Reserved: Write `0' Reserved: Write `1' CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection is disabled 0 = Protection is enabled Reserved: Write `1' BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable Reserved: Write `1'
bit 27-25 bit 24
bit 23-20
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REGISTER 28-1:
bit 19-12
DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
PWP<7:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the one's compliment of the number of write-protected program Flash memory pages. 11111111 = Disabled 11111110 = 0xBD00_0FFF 11111101 = 0xBD00_1FFF 11111100 = 0xBD00_2FFF 11111011 = 0xBD00_3FFF 11111010 = 0xBD00_4FFF 11111001 = 0xBD00_5FFF 11111000 = 0xBD00_6FFF 11110111 = 0xBD00_7FFF 11110110 = 0xBD00_8FFF 11110101 = 0xBD00_9FFF 11110100 = 0xBD00_AFFF 11110011 = 0xBD00_BFFF 11110010 = 0xBD00_CFFF 11110001 = 0xBD00_DFFF 11110000 = 0xBD00_EFFF 11101111 = 0xBD00_FFFF * * * 01111111 = 0xBD07_FFFF Reserved: Write `1' ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit 1 = PGEC2/PGED2 pair is used 0 = PGEC1/PGED1 pair is used Reserved: Write `1' DEBUG<1:0>: Background Debugger Enable bits (forced to `11' if code-protect is enabled) 11 = Debugger is disabled 10 = Debugger is enabled 01 = Reserved (same as `11' setting) 00 = Reserved (same as `11' setting)
bit 11-4 bit 3
bit 2 bit 1-0
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REGISTER 28-2:
r-1 -- bit 31 R/P-1 FWDTEN bit 23 R/P-1 bit 15 R/P-1 IESO bit 7
Legend:
DEVCFG1: DEVICE CONFIGURATION WORD 1
r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- bit 24 r-1 -- r-1 -- R/P-1 R/P-1 R/P-1 WDTPS<4:0> bit 16 R/P-1 R/P-1 R/P-1 r-1 -- R/P-1 OSCIOFNC R/P-1 R/P-1 bit 8 r-1 -- R/P-1 FSOSCEN r-1 -- r-1 -- R/P-1 R/P-1 FNOSC<2:0> bit 0 R/P-1 R/P-1 R/P-1
FCKSM<1:0>
FPBDIV<1:0>
POSCMOD<1:0>
R = Readable bit U = Unimplemented bit bit 31-24 bit 23
W = Writable bit
P = Programmable bit
r = Reserved bit
-n = Bit Value at POR: (`0', `1', x = Unknown)
Reserved: Write `1' FWDTEN: Watchdog Timer Enable bit 1 = The WDT is enabled and cannot be disabled by software 0 = The WDT is not enabled; it can be enabled in software Reserved: Write `1' WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = 10100
bit 22-21 bit 20-16
Note 1: Do not disable POSC (POSCMOD = 11) when using this oscillator source.
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REGISTER 28-2:
bit 15-14
DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Reserved: Write `1' OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00) 0 = CLKO output disabled POSCMOD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = External Clock mode selected IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled) Reserved: Write `1' FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator Reserved: Write `1' FNOSC<2:0>: Oscillator Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 111 = Fast RC Oscillator with divide-by-N (FRCDIV)
bit 13-12
bit 11 bit 10
bit 9-8
bit 7
bit 6 bit 5
bit 4-3 bit 2-0
Note 1: Do not disable POSC (POSCMOD = 11) when using this oscillator source.
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REGISTER 28-3:
r-1 -- bit 31 r-1 -- bit 23 R/P-1 UPLLEN bit 15 r-1 -- bit 7
Legend:
DEVCFG2: DEVICE CONFIGURATION WORD 2
r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- r-1 -- bit 24 r-1 -- r-1 -- r-1 -- r-1 -- R/P-1 R/P-1 FPLLODIV<2:0> bit 16 r-1 -- r-1 -- r-1 -- r-1 -- R/P-1 R/P-1 UPLLIDIV<2:0> bit 8 R/P-1 R/P-1 FPLLMULT<2:0> R/P-1 r-1 -- R/P-1 R/P-1 FPLLIDIV<2:0> bit 0 R/P-1 R/P-1 R/P-1
R = Readable bit U = Unimplemented bit bit 31-19 bit 18-16
W = Writable bit
P = Programmable bit
r = Reserved bit
-n = Bit Value at POR: (`0', `1', x = Unknown)
Reserved: Write `1' FPLLODIV<2:0>: Default Postscaler for PLL bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 UPLLEN: USB PLL Enable bit 1 = Enable USB PLL 0 = Disable and bypass USB PLL Reserved: Write `1' UPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider Reserved: Write `1'
bit 15
bit 14-11 bit 10-8
bit 7
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REGISTER 28-3:
bit 6-4
DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)
FPLLMULT<2:0>: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier Reserved: Write `1' FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider
bit 3 bit 2-0
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REGISTER 28-4:
R/P-1 FVBUSONIO bit 31 r-1 -- bit 23 R/P-x bit 15 R/P-x bit 7
Legend:
DEVCFG3: DEVICE CONFIGURATION WORD 3
R/P-1 r-1 -- r-1 -- r-1 -- R/P-1 FCANIO R/P-1 FETHIO R/P-1 FMIIEN bit 24 r-1 -- r-1 -- r-1 -- r-1 -- R/P-1 R/P-1 FSRSSEL<2:0> bit 16 R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x bit 8 R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x bit 0 R/P-1
FUSBIDIO
USERID<15:8>
USERID<7:0>
R = Readable bit U = Unimplemented bit bit 31
W = Writable bit
P = Programmable bit
r = Reserved bit
-n = Bit Value at POR: (`0', `1', x = Unknown)
FVBUSONIO: USB VBUS_ON Selection bit 1 = VBUSON pin is controlled by the USB module 0 = VBUSON pin is controlled by the port function FUSBIDIO: USB USBID Selection bit 1 = USBID pin is controlled by the USB module 0 = USBID pin is controlled by the port function Reserved: Write `1' FCANIO: CAN I/O Pin Selection bit 1 = Default CAN I/O Pins 0 = Alternate CAN I/O Pins FETHIO: Ethernet I/O Pin Selection bit 1 = Default Ethernet I/O Pins 0 = Alternate Ethernet I/O Pins FMIIEN: Ethernet MII Enable bit 1 = MII is enabled 0 = RMII is enabled Reserved: Write `1' FSRSSEL<2:0>: SRS Select bits 111 = Assign Interrupt Priority 7 to a shadow register set 110 = Assign Interrupt Priority 6 to a shadow register set * * * 001 = Assign Interrupt Priority 1 to a shadow register set 000 = All interrupt priorities are assigned to a shadow register set USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSPTM and JTAG
bit 30
bit 29-27 bit 26
bit 25
bit 24
bit 23-19 bit 18-16
bit 15-0
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PIC32MX5XX/6XX/7XX
REGISTER 28-5:
R bit 31 R bit 23 R bit 15 R bit 7
Legend:
DEVID: DEVICE AND REVISION ID REGISTER
R VER<3:0>(1) R R R R R
(1)
R bit 24
DEVID<27:24>
R
R
R DEVID<23:16>
R
(1)
R
R
R bit 16
R
R
R DEVID<15:8>
R
(1)
R
R
R bit 8
R
R
R
R
R
R
R bit 0
DEVID<7:0>(1)
R = Readable bit U = Unimplemented bit bit 31-28 bit 27-0
Note 1:
W = Writable bit
P = Programmable bit
r = Reserved bit
-n = Bit Value at POR: (`0', `1', x = Unknown)
VER<3:0>: Revision Identifier bits(1) DEVID<27:0>: Device ID(1)
See the "PIC32MX Flash Programming Specification" (DS61145) for a list of Revision and Device ID values.
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28.2 Watchdog Timer (WDT)
This section describes the operation of the WDT and Power-up Timer of the PIC32MX5XX/6XX/7XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. The following are some of the key features of the WDT module: * Configuration or software controlled * User-configurable time-out period * Can wake the device from Sleep or Idle
FIGURE 28-1:
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM
LPRC Control PWRT Enable 1:64 Output
1
PWRT Enable WDT Enable LPRC Oscillator Clock WDTCLR = 1 WDT Enable Wake WDT Enable Reset Event 25-Bit Counter 25 WDT Counter Reset 0 1 Power Save Decoder FWDTPS<4:0>(DEVCFG1<20:16>)
PWRT
Device Reset NMI (Wake-up)
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28.3 On-Chip Voltage Regulator
28.3.3 POWER-UP REQUIREMENTS
All PIC32MX5XX/6XX/7XX devices' core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX5XX/6XX/7XX family incorporate an on-chip regulator providing the required core logic voltage from VDD. A low-ESR capacitor (such as tantalum) must be connected to the VCAP/VDDCORE pin (see Figure 28-2). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Section 31.1 "DC Characteristics".
Note:
The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts.
FIGURE 28-2:
CONNECTIONS FOR THE ON-CHIP REGULATOR
3.3V(1) PIC32MX VDD
It is important that the low-ESR capacitor is placed as close as possible to the VCAP/VDDCORE pin.
28.3.1
ON-CHIP REGULATOR AND POR
VCAP/VDDCORE CEFC(2) (10 F typ) VSS
It takes a fixed delay for the on-chip regulator to generate an output. During this time, designated as TPU, code execution is disabled. TPU is applied every time the device resumes operation after any power-down, including Sleep mode. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of TPWRT at device start-up. See Section 31.0 "Electrical Characteristics" for more information on TPU AND TPWRT.
Note 1:
2:
These are typical operating voltages. Refer to Section 31.1 "DC Characteristics" for the full operating ranges of VDD and VDDCORE. It is important that the low-ESR capacitor is placed as close as possible to the VCAP/VDDCORE pin.
28.3.2
ON-CHIP REGULATOR AND BOR
PIC32MX5XX/6XX/7XX devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage levels are specific in Section 31.1 "DC Characteristics".
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28.4 Programming and Diagnostics
PIC32MX5XX/6XX/7XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include: * Simplified field programmability using two-wire In-Circuit Serial ProgrammingTM (ICSPTM) interfaces * Debugging using ICSP * Programming and debugging capabilities using the EJTAG extension of JTAG * JTAG boundary scan testing for device and board diagnostics PIC32MX devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer.
FIGURE 28-3:
BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS
PGEC1 PGED1 ICSPTM Controller PGEC2 PGED2 ICESEL TDI TDO TCK TMS JTAGEN TRCLK TRD0 TRD1 TRD2 TRD3 DEBUG<1:0> Instruction Trace Controller DEBUG<1:0> JTAG Controller Core
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REGISTER 28-6:
r-0 -- bit 31 r-0 -- bit 23 r-0 -- bit 15 r-0 -- bit 7
Legend:
DDPCON: DEBUG DATA PORT CONTROL REGISTER
r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- bit 24 r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- bit 16 r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- r-0 -- bit 8 r-0 -- r-0 -- r-0 -- R/W-1 JTAGEN R/W-0 TROEN r-0 -- r-0 -- bit 0
R = Readable bit U = Unimplemented bit bit 31-4 bit 3
W = Writable bit
P = Programmable bit
r = Reserved bit
-n = Bit Value at POR: (`0', `1', x = Unknown)
Reserved: Write `0'; ignore read JTAGEN: JTAG Port Enable bit 1 = Enable the JTAG port 0 = Disable the JTAG port TROEN: Trace Output Enable bit 1 = Enable the trace port 0 = Disable the trace port Reserved: Write `1'; ignore read
bit 2
bit 1-0
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29.0 INSTRUCTION SET
The PIC32MX5XX/6XX/7XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. PIC32MX does not support the following features: * Core Extend Instructions * Coprocessor 1 Instructions * Coprocessor 2 Instructions
Note:
Refer to "MIPS32(R) Architecture for Programmers Volume II: The MIPS32(R) Instruction Set" at www.mips.com for more information.
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NOTES:
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30.0 DEVELOPMENT SUPPORT
30.1
The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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30.2 MPLAB C Compilers for Various Device Families 30.5 MPLINK Object Linker/ MPLIB Object Librarian
The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
30.3
HI-TECH C for Various Device Families
The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms.
30.6
MPLAB Assembler, Linker and Librarian for Various Device Families
30.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
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30.7 MPLAB SIM Software Simulator 30.9
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
MPLAB ICD 3 In-Circuit Debugger System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers.
30.8
MPLAB REAL ICE In-Circuit Emulator System
30.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
30.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications.
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31.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................. .-40C to +85C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3)........................................ -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)............................. -0.3V to (VDD + 0.3V) Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.0V Maximum current out of VSS pin(s) .......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2). 3: See the "Pin Diagrams" section for the 5V tolerant pins.
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31.1 DC Characteristics
OPERATING MIPS VS. VOLTAGE
VDD Range (in Volts) Temp. Range (in C) Max. Frequency
TABLE 31-1:
Characteristic
PIC32MX5XX/6XX/7XX 80 MHz (Note 1)
DC5
Note 1:
2.3-3.6V
-40C to +85C
40 MHz maximum for PIC32MX 40 MHz family variants.
TABLE 31-2:
THERMAL OPERATING CONDITIONS
Rating Symbol Min. Typical Max. Unit
PIC32MX5XX/6XX/7XX Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - S IOH) I/O Pin Power Dissipation: I/O = S ({VDD - VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation PDMAX (TJ - TA)/JA W TJ TA -40 -40 -- -- +125 +85 C C
PD
PINT + PI/O
W
TABLE 31-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristics Symbol Typical JA JA JA JA JA Max. Unit Notes 1 1 1 1 1
Package Thermal Resistance, 121-Pin XBGA (10x10x1.1 mm) Package Thermal Resistance, 100-Pin TQFP (14x14x1 mm) Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) Package Thermal Resistance, 64-Pin QFN (9x9x0,9 mm)
Note 1:
40 43 43 47 28
-- -- -- -- --
C/W C/W C/W C/W C/W
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
TABLE 31-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics Min. Typical Max. Units Conditions
DC CHARACTERISTICS Param. Symbol No. Operating Voltage
DC10 DC12 DC16
Supply Voltage
VDD VDR VPOR
RAM Data Retention Voltage (Note 1) VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal
2.3 1.75 1.75
-- -- --
3.6 -- 1.95
V V V
DC17
SVDD
0.00005
--
0.115
V/s
Note 1:
This is the limit to which VDD can be lowered without losing RAM data.
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TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max. Units Conditions DC CHARACTERISTICS Parameter No. Typical(3)
Operating Current (IDD)(1,2)
DC20 DC20c DC21 DC21c DC22 DC22c DC23 DC23c DC25a
Note 1:
6 4 37 25 64 61 85 85 125
9 -- 40 -- 70 -- 98 -- 150
mA mA mA mA mA mA mA mA A
Code executing from Flash Code executing from SRAM Code executing from Flash Code executing from SRAM Code executing from Flash Code executing from SRAM Code executing from Flash Code executing from SRAM +25C
-- -- -- -- -- -- -- -- 3.3V
4 MHz 25 MHz (Note 4) 60 MHz (Note 4) 80 MHz LPRC (31 kHz) (Note 4)
2:
3: 4:
A device's IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption. The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by external square wave from rail-to-rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are disabled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. Data in "Typical" column is at 3.3V, 25C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing.
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TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max. Units Conditions DC CHARACTERISTICS Parameter No. Typical(2)
Idle Current (IIDLE): Core Off, Clock On Base Current (Note 1)
DC30 DC31 DC32 DC33 DC34 DC34a DC34b DC35 DC35a DC35b DC36 DC36a DC36b
Note 1:
4.5 13 28 36 -- -- -- 35 65 600 -- -- --
6.5 15 30 42 40 75 800 -- -- -- 43 106 800
mA mA mA mA A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C
4 MHz 25 MHz (Note 3) 60 MHz (Note 3) 80 MHz 2.3V
3.3V
LPRC (31 kHz) (Note 3)
3.6V
2: 3:
The test conditions for base IDLE current measurements are as follows: System clock is enabled and PBCLK divisor = 1:8. CPU in Idle mode (CPU core Halted). Only digital peripheral modules are enabled (ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing.
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TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max. Units Conditions DC CHARACTERISTICS Parameter No. Typical(2)
Power-Down Current (IPD) (Note 1)
DC40 DC40a DC40b DC40c DC40d DC40e DC40g DC40f DC41 DC41c DC41d DC42 DC42c DC42e DC43 DC43c DC43e
Note 1: 2: 3: 4: 5: 6:
10 36 400 41 22 42 315 410 -- 5 -- -- 23 -- -- 1100 --
40 100 720 120 80 120 400 800 10 -- 20 40 -- 50 1300 -- 1300
A A A A A A A A A A A A A A A A A
-40C +25C +85C +25C -40C +25C +70C +85C 2.3V 3.3V 3.6V 2.3V 3.3V 3.6V 2.5V 3.3V 3.6V Watchdog Timer Current: IWDT (Notes 3, 6) Watchdog Timer Current: IWDT (Note 3) Watchdog Timer Current: IWDT (Note 3) RTCC + Timer1 w/32 kHz Crystal: IRTCC (Notes 3, 6) RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) ADC: IADC (Notes 3, 4, 6) ADC: IADC (Notes 3, 4) ADC: IADC (Notes 3, 4) 3.6V Base Power-Down Current 3.3V Base Power-Down Current 2.3V Base Power-Down Current (Note 6)
Module Differential Current
Base IPD is measured with all digital peripheral modules and being clocked, CPU clock is disabled. All I/Os are configured as inputs and pulled low. WDT and FSCM are disabled. Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. Data is characterized at +70C and not tested. Parameter is for design guidance only. This parameter is characterized, but not tested in manufacturing.
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TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(1) Max. Units Conditions DC CHARACTERISTICS Param. Symbol No. Characteristics Input Low Voltage
VIL DI10
I/O Pins: with TTL Buffer with Schmitt Trigger Buffer VSS VSS VSS VSS VSS VSS VSS -- -- -- -- -- -- -- 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 V V V V V V V
(Note 4) (Note 4) (Note 4) (Note 4) (Note 4)
DI15 DI16 DI17 DI18 DI19 VIH DI20
MCLR
(2)
OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx SDAx, SCLx
Input High Voltage
SMBus disabled (Note 4) SMBus enabled (Note 4)
I/O Pins: with Analog Functions Digital Only with TTL Buffer with Schmitt Trigger Buffer
0.8 VDD 0.8 VDD 0.25 VDD + 0.8V 0.8 VDD 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1
-- -- -- -- -- -- -- -- --
VDD 5.5 5.5 VDD VDD VDD 5.5 5.5
V V V V V V V V V
(Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4)
DI25 DI26 DI27 DI28 DI29
MCLR(2) OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx SDAx, SCLx
SMBus disabled (Note 4) SMBus enabled, 2.3V VPIN 5.5 (Note 4) VDD = 3.3V, VPIN = VSS
DI30
ICNPU IIL
CNxx Pull up Current Input Leakage Current (Note 3)
50
250
400
A
DI50 DI51 DI55 DI56
Note 1: 2:
I/O Ports Analog Input Pins MCLR(2) OSC1
-- -- -- --
-- -- -- --
+1 +1 +1 +1
A A A A
VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT and HS modes
3: 4:
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. This parameter is characterized, but not tested in manufacturing.
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PIC32MX5XX/6XX/7XX
TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions DC CHARACTERISTICS Param. Symbol No. Characteristics Output Low Voltage
VOL DO10 DO16 VOH DO20 DO26
I/O Ports OSC2/CLKO
Output High Voltage
-- -- -- --
-- -- -- -- -- -- -- --
0.4 0.4 0.4 0.4 -- -- -- --
V V V V V V V V
IOL = 7 mA, VDD = 3.6V IOL = 6 mA, VDD = 2.3V IOL = 3.5 mA, VDD = 3.6V IOL = 2.5 mA, VDD = 2.3V IOH = -12 mA, VDD = 3.6V IOH = -12 mA, VDD = 2.3V IOH = -12 mA, VDD = 3.6V IOH = -12 mA, VDD = 2.3V
I/O Ports OSC2/CLKO
2.4 1.4 2.4 1.4
TABLE 31-10: DC CHARACTERISTICS: PROGRAM MEMORY(3)
DC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Programming temperature 0C TA +70C (25C recommended) Min. Typical(1) Max. Units Conditions
Characteristics Program Flash Memory
D130 D131 D132 D134 D135
EP VPR VPEW TRETD IDDP TWW
Cell Endurance VDD for Read VDD for Erase or Write Characteristic Retention Supply Current during Programming Word Write Cycle Time Row Write Cycle Time (Note 2) (128 words per row) Page Erase Cycle Time Chip Erase Cycle Time
1000 VMIN 3.0 20 -- 20 3
-- -- -- -- 10 -- 4.5
-- 3.6 3.6 -- -- 40 --
E/W -40C to +85C V V VMIN = Minimum operating voltage 0C to +40C
Year Provided no other specifications are violated mA
s
0C to +40C 0C to +40C 0C to +40C
D136
TRW
ms
D137
Note 1: 2:
TPE TCE
20 80
-- --
-- --
ms ms
0C to +40C 0C to +40C
3:
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). Refer to the "PIC32MX Flash Programming Specification" (DS61145) for operating conditions during programming and erase cycles.
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TABLE 31-11: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS
DC CHARACTERISTICS Required Flash Wait States Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial SYSCLK Units Comments
0 Wait State 1 Wait State 2 Wait States
0 to 30 31 to 60 61 to 80
MHz
TABLE 31-12: COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Comments
D300 D301
VIOFF VICM
Input Offset Voltage Input Common Mode Voltage
-- 0
7.5 --
25 VDD
mV V
AVDD = VDD, AVSS = VSS AVDD = VDD, AVSS = VSS (Note 2) Max VICM = (VDD - 1)V (Note 2) AVDD = VDD, AVSS = VSS (Notes 1, 2) Comparator module is configured before setting the comparator ON bit. (Note 2)
D302 D303
CMRR TRESP
Common Mode Rejection Ratio Response Time
55 --
-- 150
-- 400
dB ns
D304
ON2OV
Comparator Enabled to Output Valid
--
--
10
s
Note 1: 2:
Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. These parameters are characterized but not tested.
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TABLE 31-13: VOLTAGE REFERENCE SPECIFICATIONS
DC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Comments
D310 D311 D312 D313
Note 1:
VRES VRAA TSET VIREF
Resolution Absolute Accuracy Settling Time
(1)
VDD/24 -- -- --
-- -- -- 0.6
VDD/32 1/2 10 --
LSb LSb
s
Internal Voltage Reference
V
Settling time measured while CVRR = 1 and CVR<3:0> transitions from `0000' to `1111'. This parameter is characterized, but not tested in manufacturing.
TABLE 31-14: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
DC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Comments
D320 D321 D322
VDDCORE Regulator Output Voltage CEFC TPWRT External Filter Capacitor Value Power-up Timer Period
1.62 8 --
1.80 10 64
1.98 -- --
V
F
Capacitor must be low series resistance (1 ohm)
ms
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DS61156C-page 179
PIC32MX5XX/6XX/7XX
31.2 AC Characteristics and Timing Parameters
The information contained in this section defines PIC32MX5XX/6XX/7XX AC characteristics and timing parameters.
TABLE 31-15: AC CHARACTERISTICS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Operating voltage VDD range.
FIGURE 31-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 2 - for OSC2
Load Condition 1 - for all pins except OSC2 VDD/2 RL
Pin VSS
CL
Pin VSS
CL
RL = 464 CL = 50 pF for all pins 50 pF for OSC2 pin (EC mode)
TABLE 31-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(1) Max. Units Conditions
DO56 DO58
Note 1:
CIO CB
All I/O pins and OSC2 SCLx, SDAx
-- --
-- --
50 400
pF pF
EC mode In I2CTM mode
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
FIGURE 31-2:
EXTERNAL CLOCK TIMING
OS20 OS30 OS31
OSC1
OS30 OS31
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TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(1) Max. Units Conditions
OS10
FOSC
External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency
DC 4 3 4 10 10 32
-- -- -- -- -- -- 32.768 --
50 (Note 3) 50 (Note 5) 10 10 25 25 100 --
MHz MHz MHz MHz MHz MHz kHz --
EC (Note 5) ECPLL (Note 4) XT (Note 5) XTPLL (Notes 4, 5) HS (Note 5) HSPLL (Notes 4, 5) SOSC (Note 5) See parameter OS10 for FOSC value EC (Note 5) EC (Note 5)
(Note 5)
OS11 OS12 OS13 OS14 OS15 OS20 TOSC
TOSC = 1/FOSC = TCY (Note 2)
--
OS30 OS31 OS40
TOSL, TOSH TOSR, TOSF TOST
External Clock In (OSC1) High or Low Time External Clock In (OSC1) Rise or Fall Time Oscillator Start-up Timer Period (Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) Primary Clock Fail Safe Time-out Period External Oscillator Transconductance
0.45 x TOSC -- --
-- -- 1024
-- 0.05 x TOSC --
ns ns TOSC
OS41 OS42
TFSCM GM
-- --
2 12
-- --
ms
(Note 5)
mA/V VDD = 3.3V, TA = +25C (Note 5)
Note 1: 2:
3: 4: 5:
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are characterized but are not tested. Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. 40 MHz maximum for PIC32MX 40 MHz family variants. PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing. This parameter is characterized, but not tested in manufacturing.
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TABLE 31-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)
AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics(1) Min. Typical(2) Max. Units Conditions
OS50
FPLLI
PLL Voltage Controlled Oscillator (VCO) Input Frequency Range On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Period Jitter or Cumulative)
4
--
5
MHz
ECPLL, HSPLL, XTPLL, FRCPLL modes
OS51 OS52 OS53
Note 1: 2:
FSYS TLOCK DCLK
60 -- -0.25
-- -- --
120 2 +0.25
MHz ms % Measured over 100 ms period
These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 31-19:
INTERNAL FRC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min. Typical Max. Units Conditions
AC CHARACTERISTICS Param. No.
Characteristics
Internal FRC Accuracy @ 8.00 MHz (Note 1)
F20
Note 1:
FRC
-2
--
+2
%
Frequency calibrated at 25C and 3.3V. The TUN bits can be used to compensate for temperature drift.
TABLE 31-20: INTERNAL RC ACCURACY
AC CHARACTERISTICS Param. No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions
LPRC @ 31.25 kHz (Note 1)
F21
Note 1:
LPRC
-15
--
+15
%
Change of LPRC frequency as VDD changes.
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FIGURE 31-3:
I/O Pin (Input) DI35 DI40 I/O Pin (Output)
Note: Refer to Figure 31-1 for load conditions.
I/O TIMING CHARACTERISTICS
DO31 DO32
TABLE 31-21: I/O TIMING REQUIREMENTS
AC CHARACTERISTICS Param. No. Symbol Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics(2) Min. Typical(1) Max. Units Conditions
DO31 DO32 DI35 DI40
Note 1: 2:
TIOR TIOF TINP TRBP
Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time CNx High or Low Time (input)
-- -- -- -- 10 2
5 5 5 5 -- --
15 10 15 10 -- --
ns ns ns ns ns TSYSCLK
VDD < 2.5V VDD > 2.5V VDD < 2.5V VDD > 2.5V
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. This parameter is characterized, but not tested in manufacturing.
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PIC32MX5XX/6XX/7XX
FIGURE 31-4: POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD
VPOR
(TSYSDLY) SY02
Power-up Sequence (Note 2) SY00 (TPU) (Note 1) CPU Starts Fetching Code
Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD
VPOR
(TSYSDLY) SY02
Power-up Sequence (Note 2) SY00 (TPU) (Note 1) SY10 (TOST) CPU Starts Fetching Code
External VDDCORE Provided Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VDDCORE
VPOR
(TSYSDLY) SY02 Power-up Sequence (Note 3) SY01 (TPWRT) (Note 1) CPU Starts Fetching Code
Note 1: 2: 3:
The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). Includes interval voltage regulator stabilization delay. Power-up Timer (PWRT); only active when the internal voltage regulator is disabled.
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FIGURE 31-5: EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR (SY20) BOR
TBOR (SY30) Reset Sequence
(TSYSDLY) SY02
CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
Reset Sequence
(TSYSDLY) SY02
TOST (SY10)
CPU Starts Fetching Code
TABLE 31-22: RESETS TIMING
AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(2) Max. Units s Conditions
SY00 SY01
TPU TPWRT
Power-up Period Internal Voltage Regulator Enabled Power-up Period External VDDCORE Applied (Power-up timer active)
-- 48
400 64
600 80
-40C to +85C -40C to +85C
ms
SY02
TSYSDLY System Delay Period: Time Required to Reload Device Configuration Fuses plus SYSCLK Delay before First instruction is Fetched. TMCLR TBOR MCLR Pulse Width (low) BOR Pulse Width (low)
--
s + 8 SYSCLK cycles
--
--
-40C to +85C
SY20 SY30
Note 1: 2:
-- --
2 1
-- --
s s
-40C to +85C -40C to +85C
These parameters are characterized, but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Characterized by design but not tested.
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DS61156C-page 185
PIC32MX5XX/6XX/7XX
FIGURE 31-6:
TxCK Tx10 Tx15 OS60 TMRx
Note: Refer to Figure 31-1 for load conditions.
TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
Tx11 Tx20
TABLE 31-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
AC CHARACTERISTICS Param. No. Symbol Characteristics(2) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions
TA10
TTXH
TxCK High Time
Synchronous, with prescaler Asynchronous, with prescaler
[(12.5 ns or 1 TPB)/N] + 25 ns 10 [(12.5 ns or 1 TPB)/N] + 25 ns 10 [(Greater of 25 ns or 2 TPB)/N] + 30 ns [(Greater of 25 ns or 2 TPB)/N] + 50 ns
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- 100
ns ns ns ns ns ns ns ns kHz
Must also meet parameter TA15
TA11
TTXL
TxCK Low Time
Synchronous, with prescaler Asynchronous, with prescaler
Must also meet parameter TA15
TA15
TTXP
TxCK Synchronous, Input Period with prescaler
VDD > 2.7V VDD < 2.7V VDD > 2.7V (Note 3) VDD < 2.7V (Note 3)
Asynchronous, with prescaler
20 50
OS60
FT1
SOSC1/T1CK Oscillator Input Frequency Range (oscillator enabled by setting TCS bit (T1CON<1>))
32
TA20
TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment
--
1
TPB
Note 1: 2: 3:
Timer1 is a Type A. This parameter is characterized, but not tested in manufacturing. N = Prescale Value (1, 8, 64, 256)
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TABLE 31-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS Param. No. TB10 TB11 TB15 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics(1) TxCK Synchronous, with High Time prescaler TxCK Low Time Synchronous, with prescaler Min. [(12.5 ns or 1 TPB)/N] + 25 ns [(12.5 ns or 1 TPB)/N] + 25 ns [(Greater of [(25 ns or 2 TPB)/N] + 30 ns [(Greater of [(25 ns or 2 TPB)/N] + 50 ns TB20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment -- Max. Units -- -- -- -- 1 ns ns ns ns TPB Conditions Must also meet N = prescale parameter TB15 value Must also meet (1, 2, 4, 8, 16, parameter TB15 32, 64, 256) VDD > 2.7V VDD < 2.7V
Symbol TTXH TTXL TTXP
TxCK Input Synchronous, with Period prescaler
Note 1:
These parameters are characterized, but not tested in manufacturing.
FIGURE 31-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10 IC15
Note: Refer to Figure 31-1 for load conditions.
IC11
TABLE 31-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Max. Units Conditions
Characteristics(1)
IC10
TCCL
ICx Input Low Time
[(12.5 ns or 1 TPB)/N] + 25 ns
--
ns
Must also meet parameter IC15. Must also meet parameter IC15.
N = prescale value (1, 4, 16)
IC11
TCCH
ICx Input High Time
[(12.5 ns or 1 TPB)/N] + 25 ns
--
ns
IC15
Note 1:
TCCP
ICx Input Period
[(25 ns or 2 TPB)/N] + 50 ns
--
ns
These parameters are characterized, but not tested in manufacturing.
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DS61156C-page 187
PIC32MX5XX/6XX/7XX
FIGURE 31-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx (Output Compare or PWM mode)
OC11
OC10
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(2) Max. Units Conditions
OC10 OC11
Note 1: 2:
TCCF TCCR
OCx Output Fall Time OCx Output Rise Time
-- --
-- --
-- --
ns ns
See parameter DO32 See parameter DO31
These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
FIGURE 31-9:
OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB OC15 OCx
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
AC CHARACTERISTICS Param No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typical(2) Max Units Conditions
OC15 OC20
Note 1: 2:
TFD TFLT
Fault Input to PWM I/O Change Fault Input Pulse Width
-- 50
-- --
50 --
ns ns
These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
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FIGURE 31-10:
SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SP20 MSb SP31 SDIx MSb In SP40 SP41 Bit 14 - - - -1 Bit 14 - - - - - -1 SP30 LSb In SP21 LSb SP10 SP21 SP20
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SDOx
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(2) Max. Units Conditions
SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP40 SP41
Note 1: 2: 3: 4:
TSCL TSCH TSCF TSCR TDOF TDOR
SCKx Output Low Time (Note 3) SCKx Output High Time (Note 3) SCKx Output Fall Time (Note 4) SCKx Output Rise Time (Note 4) SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4)
TSCK/2 TSCK/2 -- -- -- -- -- -- 10 10
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- 15 20 -- --
ns ns ns ns ns ns ns ns ns ns See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V
TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge
These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins.
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DS61156C-page 189
PIC32MX5XX/6XX/7XX
FIGURE 31-11:
SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SP35 SP20 SP21
SDOX
MSb
Bit 14 - - - - - -1 SP30,SP31
LSb
SDIX SP40
MSb In SP41
Bit 14 - - - -1
LSb In
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85Cfor Industrial Min. Typ.(2) Max. Units Conditions
SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP36 SP40 SP41
Note 1: 2: 3: 4:
TSCL TSCH TSCF TSCR TDOF TDOR
SCKx Output Low Time (Note 3) SCKx Output High Time (Note 3) SCKx Output Fall Time (Note 4) SCKx Output Rise Time (Note 4) SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4)
TSCK/2 TSCK/2 -- -- -- -- -- -- 15 15 20 15 20
-- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- 15 20 -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns VDD > 2.7V VDD < 2.7V VDD > 2.7V VDD < 2.7V See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V
TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDOV2SC, SDOx Data Output Setup to TDOV2SCL First SCKx Edge TDIV2SCH, Setup Time of SDIx Data Input to TDIV2SCL SCKx Edge TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge
These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins.
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FIGURE 31-12:
SSX SP50 SCKX (CKP = 0) SP71 SCKX (CKP = 1) SP35 SDOX MSb SP72 Bit 14 - - - - - -1 SP30,SP31 SDIX SP40 MSb In SP41 Bit 14 - - - -1 LSb In SP73 SP70 SP73 SP72 SP52
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
LSb SP51
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typ.(2) Max. Units Conditions
SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 SP52
Note 1: 2: 3: 4:
TSCL TSCH TSCF TSCR TDOF TDOR TSCH2DOV, TSCL2DOV TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL
SCKx Input Low Time (Note 3) SCKx Input High Time (Note 3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4) SDOx Data Output Valid after SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge
TSCK/2 TSCK/2 -- -- -- -- -- -- 10 10 175 5
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- 15 20 -- -- -- 25
ns ns ns ns ns ns ns ns ns ns ns ns
See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V
TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL TSSH2DOZ SSx to SDOx Output High-Impedance (Note 3)
TSCH2SSH SSx after SCKx Edge TSCK + 20 -- -- ns TSCL2SSH These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 50 pF load on all SPIx pins.
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DS61156C-page 191
PIC32MX5XX/6XX/7XX
FIGURE 31-13:
SSx SP50 SCKx (CKP = 0) SP71 SCKx (CKP = 1) SP35 SP72 MSb Bit 14 - - - - - -1 SP30,SP31 SDIx SDI SP40 MSb In SP41 Bit 14 - - - -1 LSb In LSb SP51 SP73 SP70 SP73 SP72 SP52
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SDOx
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(2) Max. Units Conditions
SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50
Note 1: 2: 3: 4:
TSCL TSCH TSCF TSCR TDOF TDOR
SCKx Input Low Time (Note 3) SCKx Input High Time (Note 3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4)
TSCK/2 TSCK/2 -- -- -- -- -- -- 10 10 175
-- -- 5 5 -- -- -- -- -- -- --
-- -- 10 10 -- -- 20 30 -- -- --
ns ns ns ns ns ns ns ns ns ns ns See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V
TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge
TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL
These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 50 pF load on all SPIx pins.
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Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(2) Max. Units Conditions
SP51
TSSH2DOZ SSx to SDOX Output High-Impedance (Note 4) TSCH2SSH SSx after SCKx Edge TSCL2SSH TSSL2DOV SDOx Data Output Valid after SSx Edge
5
--
25
ns
SP52 SP60
Note 1: 2: 3: 4:
TSCK + 20 --
-- --
-- 25
ns ns
These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 50 pF load on all SPIx pins.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 193
PIC32MX5XX/6XX/7XX
FIGURE 31-14:
SCLx
IM31 IM30 IM33 IM34
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SDAx
Start Condition
Note: Refer to Figure 31-1 for load conditions.
Stop Condition
FIGURE 31-15:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20 IM11 IM10 IM11 IM26 IM21
SCLx
IM10
IM25
IM33
SDAx In
IM40 IM40 IM45
SDAx Out Note: Refer to Figure 31-1 for load conditions.
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Preliminary
2010 Microchip Technology Inc.
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TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min.(1) Max. Units s s s s s s Conditions
IM10
TLO:SCL Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2)
TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 100 0 0 0 TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2)
-- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 0.3 -- -- -- -- -- -- -- -- -- -- -- --
IM11
THI:SCL
Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2)
IM20
TF:SCL
SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode (Note 2)
ns ns ns ns ns ns ns ns ns
s s s s s s s s s s s s
CB is specified to be from 10 to 400 pF
IM21
TR:SCL
SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode (Note 2)
CB is specified to be from 10 to 400 pF
IM25
TSU:DAT Data Input Setup Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 2)
IM26
THD:DAT Data Input Hold Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 2)
IM30
TSU:STA
Start Condition Setup Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 2)
Only relevant for Repeated Start condition After this period, the first clock pulse is generated
IM31
THD:STA Start Condition Hold Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 2)
IM33
TSU:STO Stop Condition Setup Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 2)
IM34
THD:STO Stop Condition Hold Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 2)
ns ns ns
Note 1: 2:
BRG is the value of the I2CTM Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 195
PIC32MX5XX/6XX/7XX
TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min.(1) Max. Units Conditions
IM40
TAA:SCL
Output Valid From Clock
100 kHz mode 400 kHz mode 1 MHz mode (Note 2)
-- -- -- 4.7 1.3 0.5 --
3500 1000 350 -- -- -- 400
ns ns ns
s s s
IM45
TBF:SDA Bus Free Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 2)
The amount of time the bus must be free before a new transmission can start
IM50
Note 1: 2:
CB
Bus Capacitive Loading
pF
BRG is the value of the I2CTM Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS61156C-page 196
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31 IS30 IS33 IS34
SDAx
Start Condition
Note: Refer to Figure 31-1 for load conditions.
Stop Condition
FIGURE 31-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20 IS11 IS10 IS30 IS26 IS21
SCLx
IS31
IS25
IS33
SDAx In
IS40 IS40 IS45
SDAx Out Note: Refer to Figure 31-1 for load conditions.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 197
PIC32MX5XX/6XX/7XX
TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS Param. No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics Min. Max. Units s s s s s s Conditions
Symbol
IS10
TLO:SCL
Clock Low Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 1)
4.7 1.3 0.5 4.0 0.6 0.5 -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 100 0 0 0 4700 600 250 4000 600 250 4000 600 600
-- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 0.3 -- -- -- -- -- -- -- -- --
PBCLK must operate at a minimum of 800 kHz PBCLK must operate at a minimum of 3.2 MHz
IS11
THI:SCL
Clock High Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 1)
PBCLK must operate at a minimum of 800 kHz PBCLK must operate at a minimum of 3.2 MHz
IS20
TF:SCL
SDAx and SCLx Fall Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 1)
ns ns ns ns ns ns ns ns ns ns
s s s s s s s s s s s
CB is specified to be from 10 to 400 pF
IS21
TR:SCL
SDAx and SCLx Rise Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 1)
CB is specified to be from 10 to 400 pF
IS25
TSU:DAT
Data Input Setup Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 1)
IS26
THD:DAT
Data Input Hold Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 1)
IS30
TSU:STA
Start Condition Setup Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 1)
Only relevant for Repeated Start condition
IS31
THD:STA
Start Condition Hold Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 1)
After this period, the first clock pulse is generated
IS33
TSU:STO
Stop Condition Setup Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 1)
Note 1:
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
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Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)
AC CHARACTERISTICS Param. No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristics Min. Max. Units Conditions
Symbol
IS34
THD:STO
Stop Condition Hold Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 1)
4000 600 250 0 0 0 4.7 1.3 0.5 --
-- --
ns ns ns
IS40
TAA:SCL
Output Valid From 100 kHz mode Clock 400 kHz mode 1 MHz mode (Note 1)
3500 1000 350 -- -- -- 400
ns ns ns
s s s
IS45
TBF:SDA
Bus Free Time
100 kHz mode 400 kHz mode 1 MHz mode (Note 1)
The amount of time the bus must be free before a new transmission can start
IS50
Note 1:
CB
Bus Capacitive Loading
pF
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 199
PIC32MX5XX/6XX/7XX
FIGURE 31-18: CAN MODULE I/O TIMING CHARACTERISTICS
CiTx Pin (output) CiRx Pin (input)
Old Value CA10 CA11
New Value
CA20
TABLE 31-34: CAN MODULE I/O TIMING REQUIREMENTS
AC CHARACTERISTICS Param No. Symbol Characteristic(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(2) Max Units Conditions
CA10 CA11 CA20
Note 1: 2:
TioF TioR Tcwf
Port Output Fall Time Port Output Rise Time Pulse Width to Trigger CAN Wake-up Filter
-- -- 500
-- -- --
-- -- --
ns ns ns
See parameter D032 See parameter D031 --
These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
DS61156C-page 200
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-35: ETHERNET MODULE SPECIFICATIONS
AC CHARACTERISTICS Param. No. Device Supply Characteristic Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions
ET20a ET20b ET1 ET2 ET3 ET4 ET5 ET6 ET7 ET8 ET9 ET10
Module VDD Supply Module VDD Supply MDC Duty Cycle MDC Period MDIO Output Delay MDIO Input Delay TX Clock Frequency TX Clock Duty Cycle ETXDx, ETEN, ETXERR Delay RX Clock Frequency RX Clock Duty Cycle ERXDx, ERXDV, ERXERR Delay Reference Clock Frequency Reference Clock Duty Cycle ETXDx, ETEN, Delay ERXDx, ERXDV, ERXERR Delay
2.5 2.7 40 400 10 0 -- 35 0 -- 35 10
-- -- -- -- -- -- 25 -- -- 25 -- --
3.6 3.6 60 -- 10 300 -- 65 25 -- 65 30
V V % ns ns ns MHz % ns MHz % ns For RMII mode only
MIIM Timing Requirements
MII Timing Requirements
RMII Timing Requirements
ET11 ET12 ET13 ET14
-- 35 2 2
50 -- -- --
-- 65 16 16
MHz % ns ns
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 201
PIC32MX5XX/6XX/7XX
TABLE 31-36: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of VDD - 0.3 or 2.5 VSS AVSS + 2.0 2.5 AVSS 2.0 --
--
Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD 3.6 VREFH - 2.0 AVDD 400 3 VREFH AVDD/2 AVDD + 0.3 +/-0.610
V
AD02 AD05 AD05a AD06 AD07 AD08
AVSS VREFH VREFL VREF IREF
Module VSS Supply Reference Voltage High Reference Voltage Low Absolute Reference Voltage (VREFH - VREFL) Current Drain
-- -- -- -- -- 250 -- -- -- -- +/- 0.001
V V V V V
A A (Note 1)
Reference Inputs
VREFH = AVDD (Note 3)
(Note 1) (Note 3)
ADC operating ADC off
Analog Input
AD12
VINH-VINL Full-Scale Input Span VINL VIN Absolute VINL Input Voltage Absolute Input Voltage Leakage Current
VREFL AVSS - 0.3 AVSS - 0.3 --
V V V
A
VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10 k
(Note 1)
AD17
RIN
Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity
--
--
5K
ADC Accuracy - Measurements with External VREF+/VREF-
AD20c Nr AD21c INL AD22c DNL
10 data bits > -1 > -1 -- -- <1 <1
bits LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V (Note 2) LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V LSb VINL = AVSS = 0V, AVDD = 3.3V -- Guaranteed
AD23c GERR AD24n EOFF AD25c
Note 1: 2: 3: 4:
Gain Error Offset Error Monotonicity
> -1 > -1 --
-- -- --
<1 <1 --
--
These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with a 1 kHz sinewave.
DS61156C-page 202
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-36: ADC MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions
ADC Accuracy - Measurements with Internal VREF+/VREF-
AD20d Nr AD21d INL
Resolution Integral Nonlinearity > -1
10 data bits -- <1
bits
(Note 3)
LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Notes 2, 3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) -- dB bits Guaranteed
(Notes 3, 4) (Notes 3, 4)
AD22d DNL
Differential Nonlinearity
> -1
--
<1
AD23d GERR
Gain Error
> -4
--
<4
AD24d EOFF
Offset Error
> -2
--
<2
AD25d
--
Monotonicity Signal to Noise and Distortion Effective Number of Bits
-- 55 9.0
-- 58.5 9.5
-- -- --
Dynamic Performance
AD31b SINAD AD34b ENOB
Note 1: 2: 3: 4:
These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with a 1 kHz sinewave.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 203
PIC32MX5XX/6XX/7XX
TABLE 31-37: 10-BIT CONVERSION RATE PARAMETERS
PIC32MX 10-Bit A/D Converter Conversion Rates(2) ADC Speed Sampling TAD RS Max Minimum Time Min VDD Temperature ADC Channels Configuration
1 Msps to 400 ksps(1)
65 ns
132 ns
500
3.0V to 3.6V
-40C to +85C
VREF- VREF+
ANx
CHX SHA ADC
Up to 400 ksps
200 ns
200 ns
5.0 k
2.5V to 3.6V
-40C to +85C
VREF- VREF+ or or AVSS AVDD CHX SHA ANx or VREFADC
ANx
Up to 300 ksps
200 ns
200 ns
5.0 k
2.5V to 3.6V
-40C to +85C
VREF- VREF+ or or AVSS AVDD CHX SHA ANx or VREFADC
ANx
Note 1: 2:
External VREF- and VREF+ pins must be used for correct operation. These parameters are characterized, but not tested in manufacturing.
DS61156C-page 204
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-38: A/D CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS Param. Symbol No. Clock Parameters Characteristics Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical(1) Max. Units Conditions
AD50 AD55 AD56 AD57 AD60
TAD
TCONV
A/D Clock Period(2) Conversion Time Throughput Rate (Sampling Speed) Sample Time Conversion Start from Sample Trigger(3) Sample Start from Setting Sample (SAMP) bit Conversion Completion to Sample Start (ASAM = 1)(3) Time to Stabilize Analog Stage from A/D Off to A/D On(3)
65 -- -- -- 1 --
-- 12 TAD -- -- -- 1.0 TAD
-- -- 1000 400 31 --
ns -- ksps ksps TAD --
See Table 31-37
Conversion Rate
FCNV TSAMP
TPCS
AVDD = 3.0V to 3.6V AVDD = 2.5V to 3.6V TSAMP must be 132 ns Auto-Convert Trigger (SSRC<2:0> = 111) not selected
Timing Parameters
AD61 AD62 AD63
Note 1: 2: 3:
TPSS TCSS TDPU
0.5 TAD -- --
-- 0.5 TAD --
1.5 TAD -- 2
-- --
s
These parameters are characterized, but not tested in manufacturing. Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. Characterized by design but not tested.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 205
PIC32MX5XX/6XX/7XX
FIGURE 31-19: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50 ADCLK Instruction Execution Set SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 TSAMP CONV ADxIF Buffer(0) Buffer(1) AD55 AD55 Clear SAMP
1
2
3
4
5
6
7
8
5
6
7
8
1 - Software sets ADxCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in the "PIC32MX Family Reference Manual" (DS61132). 3 - Software clears ADxCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 9. 6 - Convert bit 8. 7 - Convert bit 0. 8 - One TAD for end of conversion.
DS61156C-page 206
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-20: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction Execution SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc
Set ADON
TSAMP
CONV ADxIF Buffer(0) Buffer(1)
AD55
AD55
TSAMP
TCONV
1
2
3
4
5
6
7
3
4
5
6
8
3
4
1 - Software sets ADxCON. ADON to start AD operation. 2 - Sampling starts after discharge period. TSAMP is described in the "PIC32MX Family Reference Manual" (DS61132). 3 - Convert bit 9. 4 - Convert bit 8.
5 - Convert bit 0. 6 - One TAD for end of conversion. 7 - Begin conversion of next channel. 8 - Sample for time specified by SAMC<4:0>.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 207
PIC32MX5XX/6XX/7XX
FIGURE 31-21:
CS
PARALLEL SLAVE PORT TIMING
PS5 RD
PS6 WR
PS4
PS7
PMD<7:0> PS1 PS2
PS3
TABLE 31-39: PARALLEL SLAVE PORT REQUIREMENTS
AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions
PS1 PS2 PS3 PS4 PS5 PS6 PS7
Note 1:
TdtV2wrH Data In Valid before WR or CS Inactive (setup time) TwrH2dtI TrdL2dtV TrdH2dtI Tcs TWR TRD WR or CS Inactive to Data-In Invalid (hold time) RD and CS Active to Data-Out Valid RD Activeor CS Inactive to Data-Out Invalid CS Active Time WR Active Time RD Active Time
20 40 -- 0 TPB + 40 TPB + 25 TPB + 25
-- -- -- -- -- -- --
-- -- 60 10 -- -- --
ns ns ns ns ns ns ns
These parameters are characterized, but not tested in manufacturing.
DS61156C-page 208
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-22: PARALLEL MASTER PORT READ TIMING DIAGRAM
TPB TPB TPB TPB TPB TPB TPB TPB
PB Clock
PM4 PMA<13:18> Address PM6 PMD<7:0> Address<7:0> Address<7:0> PM2 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PM7 Data Data
PMCS<2:1>
TABLE 31-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions
PM1 PM2 PM3 PM4 PM5 PM6 PM7
Note 1:
TLAT TADSU
PMALL/PMALH Pulse Width Address Out Valid to PMALL/PMALH Invalid (address setup time)
-- -- -- 5 -- 15 --
1 TPB 2 TPB 1 TPB -- 1 TPB -- 80
-- -- -- -- -- -- --
-- -- -- ns -- ns ns
TADHOLD PMALL/PMALH Invalid to Address Out Invalid (address hold time) TAHOLD TRD TDSU TDHOLD PMRD Inactive to Address Out Invalid (address hold time) PMRD Pulse Width PMRD or PMENB Active to Data In Valid (data setup time) PMRD or PMENB Inactive to Data In Invalid (data hold time)
These parameters are characterized, but not tested in manufacturing.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 209
PIC32MX5XX/6XX/7XX
FIGURE 31-23: PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TPB TPB TPB TPB TPB TPB TPB TPB
PB Clock
Address PM2 + PM3 PMD<7:0> Address<7:0> PM12 PMRD PM11 PMWR PM1 PMALL/PMALH Data PM13
PMA<13:18>
PMCS<2:1>
TABLE 31-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions
PM11 PM12 PM13
Note 1:
TWR TDVSU
PMWR Pulse Width Data Out Valid before PMWR or PMENB goes Inactive (data setup time)
-- -- --
1 TPB 2 TPB 1 TPB
-- -- --
-- -- --
TDVHOLD PMWR or PMEMB Invalid to Data Out Invalid (data hold time)
These parameters are characterized, but not tested in manufacturing.
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Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-42: OTG ELECTRICAL SPECIFICATIONS
AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typical Max. Units Conditions
USB313 VUSB
USB Voltage
3.0
--
3.6
V
Voltage on bus must be in this range for proper USB operation
USB315 VILUSB USB316 VIHUSB USB318 VDIFS USB319 VCM
Input Low Voltage for USB Buffer Input High Voltage for USB Buffer Differential Input Sensitivity Differential Common Mode Range
-- 2.0 -- 0.8
-- -- -- --
0.8 -- 0.2 2.5
V V V V The difference between D+ and Dmust exceed this value while VCM is met 14.25 k load connected to 3.6V 14.25 k load connected to ground
USB320 ZOUT USB321 VOL USB322 VOH
Note 1:
Driver Output Impedance Voltage Output Low Voltage Output High
28.0 0.0 2.8
-- -- --
44.0 0.3 3.6
V V
These parameters are characterized, but not tested in manufacturing.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 211
PIC32MX5XX/6XX/7XX
FIGURE 31-24: EJTAG TIMING CHARACTERISTICS
TTCKeye TTCKhigh TTCKlow Trf
TCK Trf TMS TDI TTsetup TThold TDO TRST* TTRST*low TTDOout TTDOzstate Trf Trf
Trf
Defined
Undefined
TABLE 31-43: EJTAG TIMING REQUIREMENTS
AC CHARACTERISTICS Param. No. Symbol Description(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Max. Units Conditions
EJ1 EJ2 EJ3 EJ4 EJ5 EJ6 EJ7 EJ8 EJ9
Note 1:
TTCKCYC TTCKHIGH TTCKLOW TTSETUP TTHOLD TTDOOUT
TCK Cycle Time TCK High Time TCK Low Time TAP Signals Setup Time Before Rising TCK TAP Signals Hold Time After Rising TCK TDO Output Delay Time From Falling TCK
25 10 10 5 3 -- -- 25 --
-- -- -- -- -- 5 5 -- --
ns ns ns ns ns ns ns ns ns
TTDOZSTATE TDO 3-State Delay Time From Falling TCK TTRSTLOW TRF TRST Low Time TAP Signals Rise/Fall Time, All Input and Output
These parameters are characterized, but not tested in manufacturing.
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32.0
32.1
PACKAGING INFORMATION
Package Marking Information
64-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC32MX575F 512H-80I/PT
e3
0510017
100-Lead TQFP (14x14x1 mm)
Example
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PIC32MX575F 512L-80I/PF e3 0510017
100-Lead TQFP (12x12x1 mm)
Example
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
PIC32MX575F 512L-80I/PT e3 0510017
Legend: XX...X Y YY WW NNN * Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
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PIC32MX5XX/6XX/7XX
32.1 Package Marking Information (Continued)
64-Lead QFN (9x9x0.9 mm) Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC32MX575F 512H-80I/MR
e3
0510017
121-Lead XBGA (10x10x1.1 mm)
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC32MX575F 512H-80I/BG
e3
0510017
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32.2 Package Details
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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APPENDIX A: MIGRATING FROM PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX DEVICES
A.3 Pin Assignments
PIC32MX5XX/6XX/7XX devices have the same pin assignment for peripherals as PIC32MX4XX devices with the following exceptions: * Pins associated with the UART1 and UART2 modules on PIC32MX4XX devices are now associated with the UART1A and UART3A modules, respectively on PIC32MX5XX/6XX/7XX devices * Pins associated with the SPI2 module on PIC32MX4XX devices are now associated with the SPI2A module on PIC32MX5XX/6XX/7XX devices
This appendix provides an overview of considerations for migrating from PIC32MX3XX/4XX devices to the PIC32MX5XX/6XX/7XX family of devices. The code developed for the PIC32MX3XX/4XX devices can be ported to the PIC32MX5XX/6XX/7XX devices after making the appropriate changes outlined below.
A.1
DMA
not support
PIC32MX5XX/6XX/7XX devices do stopping DMA transfers in Idle mode.
A.2
Interrupts
PIC32MX5XX/6XX/7XX devices have persistent interrupts for some of the peripheral modules. This means that the interrupt condition for these peripherals must be cleared before the interrupt flag can be cleared. For example, to clear a UART receive interrupt, the user application must first read the UART Receive register to clear the interrupt condition and then clear the associated UxIF flag to clear the pending UART interrupt. In other words, the UxIF flag cannot be cleared by software until the UART Receive register is read. Table A-1 outlines the peripherals and associated interrupts that are implemented differently on PIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XX devices. In addition, on the SPI module, the IRQ numbers for the receive done interrupts were changed from 25 to 24 and the transfer done interrupts were changed from 24 to 25.
TABLE A-1:
Module
PIC32MX3XX/4XX vs. PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION DIFFERENCES
Interrupt Implementation
Input Capture SPI
To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits). Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits, respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF register to obtain the number of data to receive/transmit below the level specified by the SRXISEL<1:0> and STXISEL<1:0> bits. TX interrupt will be generated as soon as the UART module is enabled. Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits, respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or UxTXREG registers to obtain the number of data to receive/transmit below the level specified by the URXISEL<1:0> and UTXISEL<1:0> bits. All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source. To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT) register.
UART
ADC PMP
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APPENDIX B: REVISION HISTORY
Revision A (August 2009)
This is the initial revision of this document.
Revision B (November 2009)
The revision includes the following global update: * Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits Other major changes are referenced by their respective chapter/section in Table B-1.
TABLE B-1:
MAJOR SECTION UPDATES
Update Description
Section Name
"High-Performance, USB, CAN and Added the following devices: Ethernet 32-Bit Flash - PIC32MX575F256L Microcontrollers" - PIC32MX695F512L - PIC32MX695F512H
The 100-pin TQFP pin diagrams have been updated to reflect the current pin name locations (see the "Pin Diagrams" section). Added the 121-pin Ball Grid Array (XBGA) pin diagram. Updated Table 1: "PIC32MX Features" Added the following tables: - Table 2: "Pin Names: PIC32MX575F256L and PIC32MX575F512L Devices", - Table 3: "Pin Names: PIC32MX675F256L, PIC32MX675F512L and PIC32MX695F512L Devices" - Table 4: "Pin Names: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L and Devices" Updated the following pins as 5V tolerant: - 64-pin QFN: Pin 36 (D-/RG3) and Pin 37 (D+/RG2) - 64-pin TQFP: Pin 36 (D-/RG3) and Pin 37 (D+/RG2) - 100-pin TQFP: Pin 56 (D-/RG3) and Pin 57 (D+/RG2)
Section 2.0 "Guidelines for Getting Removed the last sentence of Section 2.3.1 "Internal Regulator Mode". Started with 32-Bit Removed Section 2.3.2 "External Regulator Mode" Microcontrollers"
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TABLE B-1: MAJOR SECTION UPDATES (CONTINUED)
Update Description Section Name Section 4.0 "Memory Organization"
Updated all register tables to include the Virtual Address and All Resets columns. Updated the title of Figure 4-1 to include the PIC32MX575F256L device. Updated the title of Figure 4-3 to include the PIC32MX695F512L and PIC32MX695F512H devices. Also changed PIC32MX795F512L to PIC32MX795F512H. Updated the title of Table 4-3 to include the PIC32MX695F512H device. Updated the title of Table 4-5 to include the PIC32MX575F5256L device. Updated the title of Table 4-6 to include the PIC32MX695F512L device. Reversed the order of Table 4-11 and Table 4-12. Reversed the order of Table 4-14 and Table 4-15. Updated the title of Table 4-15 to include the PIC32MX575F256L and PIC32MX695F512L devices. Updated the title of Table 4-45 to include the PIC32MX575F256L device. Updated the title of Table 4-47 to include the PIC32MX695F512H and PIC32MX695F512L devices.
Section 12.0 "I/O Ports" Section 22.0 "10-Bit Analog-toDigital Converter (ADC)" Section 28.0 "Special Features"
Updated the second paragraph of Section 12.1.2 "Digital Inputs" and removed Table 12-1. Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2). Removed references to the ENVREG pin in Section 28.3 "On-Chip Voltage Regulator". Updated the first sentence of Section 28.3.1 "On-Chip Regulator and POR" and Section 28.3.2 "On-Chip Regulator and BOR". Updated the Connections for the On-Chip Regulator (see Figure 28-2).
Section 31.0 "Electrical Characteristics"
Updated the Absolute Maximum Ratings and added Note 3. Added Thermal Packaging Characteristics for the 121-pin XBGA package (see Table 31-3). Updated the Operating Current (IDD) DC Characteristics (see Table 31-5). Updated the Idle Current (IIDLE) DC Characteristics (see Table 31-6). Updated the Power-Down Current (IPD) DC Characteristics (see Table 31-7). Removed Note 1 from the Program Flash Memory Wait State Characteristics (see Table 31-11). Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics, changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see Figure 31-13).
Section 32.0 "Packaging Information" "Product Identification System"
Added the 121-pin XBGA package marking information and package details. Added the definition for BG (121-lead 10x10x1.1 mm, XBGA). Added the definition for Speed.
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Revision C (February 2010)
The revision includes the following updates, as described in Table B-2:
TABLE B-2:
MAJOR SECTION UPDATES
Update Description
Section Name "High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers"
Added the following devices: * * * * * * * * * * PIC32MX675F256H PIC32MX775F256H PIC32MX775F512H PIC32MX675F256L PIC32MX775F256L PIC32MX775F512L EREFCLK ECRSDV AEREFCLK AECRSDV
Added the following pins:
Added the EREFCLK and ECRSDV pins to Table 3 and Table 4.
Section 1.0 "Device Overview"
Updated the pin number pinout I/O descriptions for the following pin names in Table 1-1: * SCL1A * SDA1A * SCL2 * SDA2 * SCL2A * SDA2A * SCL3A * SDA3A * TMS * TCK * TDI * TDO * RTCC * CVREF* CVREF+ * CVREFOUT * C1IN* C1IN+ * C1OUT * C2IN* C2IN+ * C2OUT * PMA0 * PMA1
Added the following pins to the Pinout I/O Descriptions table (Table 1-1): * * * * EREFCLK ECRSDV AEREFCLK AECRSDV
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TABLE B-2: MAJOR SECTION UPDATES (CONTINUED)
Update Description Section Name Section 4.0 "Memory Organization"
Added new devices and updated the virtual and physical memory map values in Figure 4-1. Added new devices to Figure 4-2. Added new devices to the following register maps: * * * * * * * * Table 4-3, Table 4-4, Table 4-6 and Table 4-7 (Interrupt Register Maps) Table 4-12 (I2C2 Register Map) Table 4-15 (SPI1 Register Map) Table 4-24 through Table 4-35 (PORTA-PORTG Register Maps) Table 4-36 and Table 4-37 (Change Notice and Pull-up Register Maps) Table 4-45 (CAN1 Register Map) Table 4-46 (CAN2 Register Map) Table 4-47 (Ethernet Controller Register Map)
Changed the bits named POSCMD to POSCMOD in Table 4-42 (Device Configuration Word Summary).
Section 28.0 "Special Features" Appendix A: "Migrating from PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX Devices"
Changed all references of POSCMD to POSCMOD in the Device Configuration Word 1 register (see Register 28-2). Added the new section A.3 "Pin Assignments".
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NOTES:
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INDEX
A
AC Characteristics ............................................................ 180 10-Bit Conversion Rate Parameters ......................... 204 A/D Conversion Requirements ................................. 205 ADC Specifications ................................................... 202 EJTAG Timing Requirements ................................... 212 Ethernet .................................................................... 201 Internal FRC Accuracy.............................................. 182 Internal RC Accuracy ................................................ 182 OTG Electrical Specifications ................................... 211 Parallel Master Port Read Requirements ................. 209 Parallel Master Port Write ......................................... 210 Parallel Master Port Write Requirements.................. 210 Parallel Slave Port Requirements ............................. 208 PLL Clock Timing...................................................... 182 Assembler MPASM Assembler................................................... 168
D
DC Characteristics............................................................ 172 I/O Pin Input Specifications ...................................... 176 I/O Pin Output Specifications.................................... 177 Idle Current (IIDLE) .................................................... 174 Operating Current (IDD) ............................................ 173 Power-Down Current (IPD)........................................ 175 Program Memory...................................................... 177 Temperature and Voltage Specifications.................. 172 Development Support ....................................................... 167 Direct Memory Access (DMA) Controller.......................... 117
E
Electrical Characteristics .................................................. 171 AC............................................................................. 180 Errata .................................................................................. 21 Ethernet Controller............................................................ 145 External Clock Timer1 Timing Requirements ................................... 186 Timer2, 3, 4, 5 Timing Requirements ....................... 187 Timing Requirements ............................................... 181
B
Block Diagrams A/D Module ............................................................... 141 Comparator I/O Operating Modes............................. 147 Comparator Voltage Reference ................................ 149 Connections for On-Chip Voltage Regulator............. 162 Core and Peripheral Modules ..................................... 23 DMA .......................................................................... 117 Ethernet Controller.................................................... 145 I2C Circuit ................................................................. 134 Input Capture ............................................................ 127 Interrupt Controller .................................................... 109 JTAG Programming, Debugging and Trace Ports ....................................................... 163 MCU............................................................................ 39 Output Compare Module........................................... 129 PIC32MX CAN Module ............................................. 143 PMP Pinout and Connections to External Devices ............................................................. 137 Prefetch Module........................................................ 115 Reset System............................................................ 107 RTCC ........................................................................ 139 SPI Module ............................................................... 131 Timer1....................................................................... 123 Timer2/3/4/5 (16-Bit) ................................................. 125 Typical Multiplexed Port Structure ............................ 121 UART ........................................................................ 135 WDT and Power-up Timer ........................................ 161 Brown-out Reset (BOR) and On-Chip Voltage Regulator................................ 162
F
Flash Program Memory .................................................... 105 RTSP Operation ....................................................... 105
I
I/O Ports ........................................................................... 121 Parallel I/O (PIO) ...................................................... 122 Instruction Set................................................................... 165 Inter-Integrated Circuit (I2C .............................................. 133 Internal Voltage Reference Specifications........................ 179 Interrupt Controller............................................................ 109 IRG, Vector and Bit Location .................................... 110
M
MCU Architecture Overview ................................................ 40 Coprocessor 0 Registers ............................................ 42 Core Exception Types ................................................ 43 EJTAG Debug Support............................................... 44 Power Management ................................................... 44 MCU Module....................................................................... 39 Memory Maps ............................................................... 46-48 Memory Organization ......................................................... 45 Layout......................................................................... 45 Migration PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX......... 227 MPLAB ASM30 Assembler, Linker, Librarian ................... 168 MPLAB Integrated Development Environment Software .............................................. 167 MPLAB PM3 Device Programmer .................................... 170 MPLAB REAL ICE In-Circuit Emulator System ................ 169 MPLINK Object Linker/MPLIB Object Librarian ................ 168
C
C Compilers MPLAB C18 .............................................................. 168 Clock Diagram .................................................................. 113 Comparator Specifications............................................................ 178 Comparator Module .......................................................... 147 Comparator Voltage Reference (CVREF ........................... 149 Configuration Bit ............................................................... 153 Controller Area Network (CAN)......................................... 143 CPU Module........................................................................ 35
O
Open-Drain Configuration................................................. 122 Oscillator Configuration .................................................... 113 Output Compare ............................................................... 129
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P
Packaging ......................................................................... 213 Details ....................................................................... 215 Marking ..................................................................... 213 Parallel Master Port (PMP) ............................................... 137 PIC32MX Family USB Interface Diagram ......................... 120 Pinout I/O Descriptions (table) ............................................ 24 Power-on Reset (POR) and On-Chip Voltage Regulator ................................ 162 Power-Saving Features..................................................... 151 CPU Halted Methods ................................................ 151 Operation .................................................................. 151 with CPU Running..................................................... 151 Prefetch Cache ................................................................. 115 Program Flash Memory Wait State Characteristics......................................... 178 Timing Requirements CLKO and I/O ........................................................... 183 Timing Specifications CAN I/O Requirements ............................................. 200 I2Cx Bus Data Requirements (Master Mode)........... 195 I2Cx Bus Data Requirements (Slave Mode)............. 198 Input Capture Requirements..................................... 187 Output Compare Requirements................................ 188 Simple OCx/PWM Mode Requirements ................... 188 SPIx Master Mode (CKE = 0) Requirements............ 189 SPIx Master Mode (CKE = 1) Requirements............ 190 SPIx Slave Mode (CKE = 1) Requirements.............. 192 SPIx Slave Mode Requirements (CKE = 0).............. 191
U
UART ................................................................................ 135 USB On-The-Go (OTG) .................................................... 119
R
Real-Time Clock and Calendar (RTCC)............................ 139 Register Maps ............................................................. 49-103 Registers DDPCON (Debug Data Port Control)........................ 164 DEVCFG0 (Device Configuration Word 0 ................. 153 DEVCFG1 (Device Configuration Word 1 ................. 155 DEVCFG2 (Device Configuration Word 2 ................. 157 DEVCFG3 (Device Configuration Word 3 ................. 159 DEVID (Device and Revision ID) .............................. 160 Resets ............................................................................... 107 Revision History ................................................................ 228
V
VCAP/VDDCORE pin............................................................ 162 Voltage Reference Specifications..................................... 179 Voltage Regulator (On-Chip) ............................................ 162
W
Watchdog Timer (WDT).................................................... 161 WWW, On-Line Support ..................................................... 21
S
Serial Peripheral Interface (SPI) ....................................... 131 Software Simulator (MPLAB SIM)..................................... 169 Special Features ............................................................... 153
T
Timer1 Module .................................................................. 123 Timer2/3, Timer4/5 Modules ............................................. 125 Timing Diagrams 10-Bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) .................................. 206 10-Bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001)........ 207 CAN I/O..................................................................... 200 EJTAG ...................................................................... 212 External Clock ........................................................... 180 I/O Characteristics .................................................... 183 I2Cx Bus Data (Master Mode) .................................. 194 I2Cx Bus Data (Slave Mode) .................................... 197 I2Cx Bus Start/Stop Bits (Master Mode) ................... 194 I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 197 Input Capture (CAPx)................................................ 187 OCx/PWM ................................................................. 188 Output Compare (OCx) ............................................. 188 Parallel Master Port Read ......................................... 209 Parallel Master Port Write ......................................... 210 Parallel Slave Port .................................................... 208 SPIx Master Mode (CKE = 0).................................... 189 SPIx Master Mode (CKE = 1).................................... 190 SPIx Slave Mode (CKE = 0)...................................... 191 SPIx Slave Mode (CKE = 1)...................................... 192 Timer1, 2, 3, 4, 5 External Clock............................... 186 UART Reception ....................................................... 136 UART Transmission (8-Bit or 9-Bit Data) .................. 136
DS61156C-page 234
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 5XX F 512 H T - 80 I / PT - XXX
Microchip Brand Architecture Product Groups Flash Memory Family Program Memory Size (KB) Pin Count Tape and Reel Flag (if applicable) Speed Temperature Range Package Pattern Example: PIC32MX575F256H-80I/PT: General purpose PIC32MX, 256 KB program memory, 64-pin, Industrial temperature, TQFP package.
Flash Memory Family
Architecture Product Groups MX = 32-bit RISC MCU core 5XX = General purpose microcontroller family 6XX = General purpose microcontroller family 7XX = General purpose microcontroller family F = Flash program memory
Flash Memory Family
Program Memory Size 256 = 256K 512 = 512K Pin Count H L 80 I PT PT PF MR BG = 64-pin = 100-pin = 80 MHz = -40C to +85C (Industrial) = = = = = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack) 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack) 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat) 121-Lead (10x10x1.1 mm) XBGA (Plastic Thin Profile Ball Grid Array)
Speed Temperature Range Package
Pattern
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 235
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/05/10
DS61156C-page 236
Preliminary
2010 Microchip Technology Inc.


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