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Data Sheet, Rev. 2.0, July 2009
TLE7189QK
P R O - S I L TM 3 - P h a s e B r i d g e D r i v e r I C
Automotive Power
TLE7189QK
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 2 3 3.1 3.2 4 4.1 4.2 4.3 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.3 5.3.1 6 6.1 7 8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Assignment TLE7189QK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Definitions and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Default State of Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation at Vs<12V - Integrated Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dead Time and Shoot Through Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Under Voltage Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ERR Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shunt Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 13 13 14 17 17 17 17 18 18 18 18 19 22 23
Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Layout Guide Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Data Sheet
2
Rev. 2.0, 2009-07-10
3-Phase Bridge Driver IC
TLE7189QK
1
Features * * * * * * * * * * * * * * * * * *
Overview
Compatible to very low ohmic normal level input N-channel MOSFETs PWM frequency up to 30kHz Fulfils specification down to 5.5V supply voltage Short circuit protection with adjustable detection level Three integrated current sense amplifiers 0 to 100% duty cycle Low EMC sensitivity and emission Control inputs with TTL characteristics Separate input for each MOSFET Separate source connection for each MOSFET Integrated minimum dead time Shoot through protection Disable function and sleep mode Detailed diagnosis Over temperature warning LQFP-64 package with exposed pad for excellent cooling Green Product (RoHS compliant) AEC (Automotive Electronics Council) qualified
PG-LQFP-64
SIL supporting features: * * * VCC check: Over- and under voltage check of 5V C supply Test functions for short circuit detection and VCC check High voltage rated inputs
Description The TLE7189QK is a driver IC dedicated to control the 6 to 12 external MOSFETs forming the converter for high current 3 phase motor drives in the automotive sector. It incorporates features like short circuit detection, diagnosis and high output performance and combines it with typical automotive specific requirements like full functionality even at low battery voltages. Its 3 high side and 3 low side output stages are powerful enough to drive MOSFETs with 400nC gate charge with approx. 150ns fall and rise times.
Type TLE7189QK Data Sheet
Package PG-LQFP-64 3
Marking TLE7189F Rev. 2.0, 2009-07-10
TLE7189QK
Block Diagram
2
Block Diagram
CL1 CH1 CB1 CL2 CH2 CB2
VS INH
Charge Pump 1 Under voltage det.
Charge Pump 2 Under voltage det. VDH
Floating HS driver Short circuit detection ERR1 ERR2 ENA SCDL Diagnostic logic Under voltage Over voltage Overtemperature Short circuit Reset VCC failure L E V E L S H I F T E R
GH1 SH1
Floating LS driver Short circuit detection
GL1 SL1
VCT VCC voltage check
Floating HS driver Short circuit detection
GH2 SH2
VS_OA
Floating LS driver Short circuit detection
GL2 SL2
IL1 IH1 IL2 IH2 IL3 IH3 VS_OA AGND ISP1 ISN1 ISP2 ISN2 ISP3 ISN3 Input control Shoot through protection dead time
Floating HS driver Short circuit detection
GH3 SH3
Floating LS driver Short circuit detection
GL3 SL3 GND GND GND AGND
3x Current sense OpAmp Bias reference buffer
VRI
VRO
VO1
VO2 VO3
Figure 1 Data Sheet
Block Diagram 4 Rev. 2.0, 2009-07-10
TLE7189QK
Pin Configuration
3
3.1
Pin Configuration
Pin Assignment TLE7189QK
AGND
AGND
SCDL
ISN3
ISP3
ENA
VCT
VO3
INH
IH2
IH1
IH3
NC
IL2
IL1
IL3
64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
ISP 2 NC ISN2 VO2 VRO VRI ISP 1 NC ISN1 VO1 VS _OA NC SL 3 NC NC GL 3
ERR1 ERR2 CH2 CH1 CL1 Vs CL2 GND CB1 VDH NC NC NC NC GL 1 SL1 PG-LQFP-64-6, -8, -11.vsd
18
SH1
19
GH1
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
NC
NC
CB2
GL2
SL2
GH2
SH2
NC
NC
NC
GH3
SH3
GND
Figure 2 Data Sheet
Pin Configuration 5 Rev. 2.0, 2009-07-10
TLE7189QK
Pin Configuration
3.2
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pin Definitions and Functions.
Symbol ERR1 ERR2 CH2 CH1 CL1 VS CL2 GND CB1 VDH NC NC NC NC GL1 SL1 GND SH1 GH1 NC NC CB2 GL2 SL2 GH2 SH2 NC NC NC GH3 SH3 GND GL3 NC NC SL3 NC VS_OA VO1 ISN1 Function Error signal 1 Error signal 2 + terminal for pump capacitor of charge pump 2 + terminal for pump capacitor of charge pump 1 - terminal for pump capacitor of charge pump 1 Voltage supply - terminal for pump capacitor of charge pump 2 Logic and power ground Buffer capacitor for charge pump 1 Connection to drain of high side switches for short circuit detection Not connected Not connected Not connected Not connected Output to gate low side switch 1 Connection to source low side switch 1 Logic and power ground Connection to source high side switch 1 Output to gate high side switch 1 Not connected Not connected Buffer capacitor for charge pump 2 Output to gate low side switch 2 Connection to source low side switch 2 Output to gate high side switch 2 Connection to source high side switch 2 Not connected Not connected Not connected Output to gate high side switch 3 Connection to source high side switch 3 Logic and power ground Output to gate low side switch 3 Not connected Not connected Connection to source low side switch 3 Not connected Voltage supply I-DC Link OpAmps and voltage reference buffer / input for VCC check Output of OpAmp 1 for shunt signal amplification - Input of OpAmp 1 for shunt signal amplification 6 Rev. 2.0, 2009-07-10
Data Sheet
TLE7189QK
Pin Configuration Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Cooling Tab Symbol NC ISP1 VRI VRO VO2 ISN2 NC ISP2 VO3 ISN3 NC ISP3 AGND AGND INH VCT SCDL ENA IL3 IH3 IL1 IH1 IL2 IH2 GND Function Not connected + Input of OpAmp 1 for shunt signal amplification Input of bias reference amplifier Output of bias reference amplifier Output of OpAmp 2 for shunt signal amplification - Input of OpAmp 2 for shunt signal amplification Not connected + Input of OpAmp 2 for shunt signal amplification Output of OpAmp 3 for shunt signal amplification - Input of OpAmp 3 for shunt signal amplification Not connected + Input of OpAmp 3 for shunt signal amplification Analog ground especially for the current sense OpAmps Analog ground especially for the current sense OpAmps Inhibit pin (active low) Input pin for VCC check test Input pin to adjust short circuit detection level Enable pin (active high) Input for low side switch 3 (active high) Input for high side switch 3 (active low) Input for low side switch 1 (active high) Input for high side switch 1 (active low) Input for low side switch 2 (active high) Input for high side switch 2 (active low) Should be connected to GND
All GND pins and Cooling Tab should be interconnected.
Data Sheet
7
Rev. 2.0, 2009-07-10
TLE7189QK
General Product Characteristics
4
4.1
General Product Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings 1) -40 C Tj 150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Voltages 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 4.1.11 4.1.12 4.1.13 4.1.14 4.1.15 4.1.16 4.1.17 4.1.18 4.1.19 4.1.20 4.1.21 Supply voltage Supply voltage Parameter Symbol Limit Values Min. Max. 45 45 47 18 6.0 18 18.0 18.0 18.0 7 45 18 55 15 55 55 55 20 28 35 28 V V V V V V V V V V V V V V V V V V V V V with 10 and 1F - tp<200ms - - with 10k2) with 1k2) - - - - - - - - Unit Conditions
VS1
-4.0 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -7 -7 -7 -7 -0.3 -0.3 -7.0 -9.0 -0.3 -0.3 -0.3 -5.0
VS2 Supply voltage VS3 Voltage range at IHx, ILx, ENA, VCT VDP1 Voltage range at ERRx, VOx, VRI, VRO, VDP2
SCDL Voltage range at ERRx, VRI, SCDL Voltage range at VOx Voltage range at INH Voltage range at VS_OA Voltage range at SLx Voltage range at SHx Voltage range at GLx Voltage range at GHx Voltage difference Gxx-Sxx Voltage range at VDH Voltage range at VDH Voltage range at VDH Voltage range at VDH Voltage range at VDH Voltage range at VDH Voltage range at VDH
VDP3
VVO VINH VVS_OA VSL VSH VGL VGH VGS VVDH1 VVDH2 VVDH3 VVDH4 VVDH5 VVDH6 VVDH7
RVDH=100; 200ms; 10x RVDH=100; 1ms; 10x VINH=low VINH=low;
5min; 3x
VINH=low; 400ms; 10x VINH=low; RVDH=100;
25C; 1min; 10x
4.1.22
Voltage range at VDH
VVDH8
-7.0
28
V
VINH=low; RVDH=100;
200ms; 10x
4.1.23
Voltage range at VDH
VVDH9
-9.0
28
V
VINH=low; RVDH=100;
1ms; 10x
Data Sheet
8
Rev. 2.0, 2009-07-10
TLE7189QK
General Product Characteristics Absolute Maximum Ratings (cont'd)1) -40 C Tj 150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 4.1.24 4.1.25 4.1.26 4.1.27 4.1.28 4.1.29 4.1.30 4.1.31 4.1.32 4.1.33 4.1.34 4.1.35 4.1.36 Parameter Voltage range at CL1 Symbol -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -2 -5 -10 2 -20 -31 Limit Values Min. Max. 25 25 25 25 55 60 25 +2 5 10 - 20 +31 V V V V V V V V V mA V V - - - - - Unit Conditions
VCL1 Voltage range at CH1, CB1 VCH1 Voltage difference CH1-CL1 VCP1 Voltage range at CL2 VCL2 Voltage range at CH2, CB2 VCH2 Voltage range at CB2 VCB2 Voltage difference CH2-CL2 VCP2 DC voltage difference between VDH and VVDHVS
VS
3)
tP<1s; f=50kHz
- - - - - -
Voltage range at ISPx, ISNx Output current range at VOx Gate resistor Min. Voltage rating of CB2 capacitor Min. Voltage rating of CB2 capacitor
VISI IVOx RG VCCB2a VCCB2b
External components
VS > 20V; VINH=low
- - - - -
Temperatures 4.1.37 4.1.38 4.1.39 4.1.40 4.1.41 4.1.42 4.1.43
1) 2) 3) 4) 5) 6)
Junction temperature Storage temperature Lead soldering temperature (1/16'' from body) Peak reflow soldering temperature4) Junction to case ESD Resistivity5) ESD Resistivity (charge device model)
6)
TJ Tstg Tsol Tref RthJC VESD VESD
-40 -55 - - - -2 -
150 150 260 260 5 2 750
C C C C K/W kV V
Thermal Resistance ESD Susceptibility
Not subject to production test, specified by design. after 50h the chip must be replaced; resistor in series High frequent transient ringing above 1MHz exceeding the +/-2V is allowed Reflow profile IPC/JEDEC J-STD-020C ESD susceptibility HBM according to EIA/JESD 22-A 114B ESD susceptibility CDM according to EIA/JESD 22-C 101
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation.
Data Sheet
9
Rev. 2.0, 2009-07-10
TLE7189QK
General Product Characteristics
4.2
Pos. 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7
Functional Range
Parameter Supply voltage Supply voltage Duty cycle
2) 1) 1)
Symbol Min.
VS1 VS2
Limit Values Max. 20 28 100 25 30 30 5.5 5.5 0 0 - -
Unit V % kHz A A
Conditions DC
TA=25C; t<1min
- Total gate charge 400nC
PWM frequency Quiescent current3) Quiescent current into VDH Supply current at Vs
D fPWM IQ IQ_VDH IVs
- -
110 110 90 90 60 40
mA
4.2.8
Supply current at Vs (device disabled by ENA)
IVs(o)
-
mA
4.2.9 4.2.10 4.2.11
Supply current at VS_OA Current flowing into VDH pin (device not in sleep mode) Current flowing into VDH pin (device not in sleep mode) Voltage difference CB2-VDH Junction temperature
IVs_OA IVDH1 IVDH2
- - 150
30 1.5 650
mA mA A
VS ,VVDH<20 V VVDH<20V; VS pin open fPWM=20kHz Qgate=170nC: VS = 5.5V VS = 14V VS= 18V VS = 20V VS=5.5V... 20V; VSHx=0V VS=20V... 28V; VSHx=0V VVS_OA=4.8 ... 5.2V VS=5.5V... 20V; VSHx=0V VS=5.5V... 20V; VS=VVDH=VSHx; VIHx=low
Operation mode
4.2.12 4.2.13
VCB2VDH TJ
-0.3 -40
20 150
V C
1) For proper start up minimum Vs=6.5V is required 2) Duty cycle is referred to the high side input command (IHx); The duty cycles can be driven continuously and fully operational 3) total current consumption from power net (Vs and VDH)
Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Note: If the voltage difference between CB2 and SHx is smaller than 2V during normal operation, there is a risk that the high side output can switch on and off without a corresponding input signal. As soon as this supply voltage recovers and the input signal changes, the output stage is automatically aligned to the input again.
Data Sheet
10
Rev. 2.0, 2009-07-10
TLE7189QK
General Product Characteristics
4.3
Table 1
Default State of Inputs
Default State of Inputs State Low High Low High Low Typ. 1.4V Zero ampere equivalent Remark Low side MOSFETs off High side MOSFETs off Device/outputs disabled Device/outputs disabled Sleep mode, IQ < 30 A - -
Characteristic Default state of ILx (if ILx left open -pull down) Default state of IHx (if IHx left open - pull up) Default state of ENA (if ENA left open - pull down) Default state of VCT (if VCT left open - pull up) Default state of INH (if INH left open - pull down) Default state of SCDL (if SCDL left open - internal voltage divider) Default State of sense amplifier output VOX (ISPx=ISNx=0V) Status of the Device and the Outputs when ENA=INH=high & VCT=low1)
1) No special start up procedure is required
Device active and outputs 5.5....28V; No VCC check functional failure
Note: The load condition "C=22nF; RLoad=1" in the paragraph "Electrical characteristics / Dynamic characteristic" means that RLoad is connected between the output Gxx and the positive terminal of the C. The negative terminal of the C is connected to GND and the corresponding Sxx. The voltage is measured at the positive terminal of the C. Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
Data Sheet
11
Rev. 2.0, 2009-07-10
TLE7189QK
Description and Electrical Characteristics
5
5.1 5.1.1
Description and Electrical Characteristics
MOSFET Driver Output Stages
The 3 low side and 3 high side powerful push-pull output stages of the TLE7189QK are all floating blocks, each with its own source pin. This allows the direct connection of the output stage to the source of each single MOSFET, allowing a perfect control of each gate-source voltage even when 200A are driven in the bridge with rise and fall times clearly below 1s. All 6 output stages have the same output power and thanks to the used charge pump principle they can be switched all up to 30kHz. Its output stages are powerful enough to drive MOSFETs with 400nC gate charge with approx. 150ns fall and rise times or even to run 12 MOSFETs with 200nC each with fall and rise times of approx. 150ns. Maximum allowed power dissipation, max. junction temperature and the capabilities of the charge pump limit the use for higher frequencies. Each output stage has its own short circuit detection block. For more details about short circuit detection see Chapter 5.2.1.
VS
INH
CL1 CH1
CB1 CL2 CH2
CB2
VDH CB2
100
To Vbat
Charge pump 1
Charge pump 2
SCD
UVLO
ERR1 +3.3V ERR2 ENA
Error logic Reset Power On Reset Under voltage Over voltage Over temperature Short circuit+disable
SCD
Under voltage lock out + V SCP Level shifter
GHx
R1 SCDL R2 IH1 IL1 IH2 IL2 IH3 IL3
lock / unlock
SCD
Floating HS driver 3x
SHx
SCD
CB1
SCD
short circuit filter + Input logic shoot through protection dead time
ON / OFF ON / OFF
V SCP Level shifter
GLx
Floating LS driver 3x
SLx Shuntx GND P-GND
Figure 3
Block Diagram of Driver Stages including Short Circuit Detection
Data Sheet
12
Rev. 2.0, 2009-07-10
TLE7189QK
Description and Electrical Characteristics
5.1.2
Operation at Vs<12V - Integrated Charge Pumps
The TLE7189QK provides a feature tailored to the requirements in 12V automotive applications. Often the operation of an application has to be assured even at 9V supply voltage or lower. Normally bridge driver ICs provide in such conditions clearly less than 9V to the gate of the external MOSFETs, increasing their RDSon and the associated power dissipation. The TLE7189QK has two charge pump circuitries for external capacitors. The operation of the charge pumps is independent upon the pulse pattern of the MOSFETs. The output of the charge pumps are regulated. The first charge pump doubles the supply voltage as long as it is below 8V. At 8V supply voltage and above, charge pump 1 regulates its output to 15V typically. Above 15V supply voltage, the output voltage of charge pump 1 will increase linearly. Yet, the output will not exceed 25V. Charge pump 2 is regulated as well but it is pumped to the voltage on Vs. Normally VDH and Vs are in the same voltage range. The driver is not designed to have significant different voltages at VDH compared to Vs. This would lead to reduced supply voltages for the high side output stages. Charge pump 1 supplies the low side MOSFETS and output stages for the low side MOSFETs with sufficient voltage to assure 10V at the MOSFETs gate even if the supply voltage is below 10V. Charge pump 2 supplies the output stages for the high side MOSFETs with sufficient voltage to assure 10V at the MOSFETs gate. In addition, the charge pump 1 supplies most of the internal circuits of the driver IC, including charge pump 2. Output of charge pump 1 is the buffer capacitor CB1 which is referenced to GND. Charge pump 2 supplies the high side MOSFETs and the output stages for the high side MOSFETs with sufficient voltage to assure 10V at the high side MOSFET gate. Output of charge pump 2 is buffer capacitor CB2 which is referenced to VDH. This concept allows to drive all external MOSFETs in the complete duty cycle range of 0 to 100% without taking care about recharging of any bootstrap capacitors. This simplifies the use in all applications especially in motor drives with block wise commutation. The charge pumps are only deactivated when the device is put into sleep mode via INH. The size of the charge pump capacitors (pump capacitors CPx as well as buffer capacitors CBx) can be varied between 1F and 4.7F. Yet, larger capacitor values result in higher charge pump voltages and less voltage ripple on the charge pump buffer capacitors CBx (which supply the internal circuits as well as the external MOSFETs, pls. see above). Besides the capacitance values the ESR of the buffer capacitors CBx determines the voltage ripple as well. It is recommended to use buffer capacitors CBx that have small ESR. Pls. see also Chapter 5.1.3 for capacitor selection.
5.1.3
Sleep Mode
When the INH pin is set to low, the driver will be set to sleep mode. The INH pin switches off the complete supply structure of the device and leads finally to an under voltage shut down of the complete driver. Enabling the device with the INH pin means to switch on the supply structure. The device will run through power on reset during wake up. It is recommended to perform a Reset by ENA after Wake up to remove possible ERR signals; Reset is performed by keeping ENA pin low until the charge pump voltages have ramped up. Enabling and disabling with the INH pin is not very fast. For fast enable / disable the ENA pin is recommended. When the TLE7189QK is in INH mode (INH is low) or when the supply voltage is not available on the Vs pin, then the driver IC is not supplied, the charge pumps are inactive and the charge pump capacitors are discharged. Pin CB2 (+ terminal of buffer capacitor 2) will decay to GND. When the battery voltage is still applied to VDH (- terminal of buffer capacitor 2) the buffer capacitor 2 will slowly charged to battery voltage, yet with reversed polarity compared to the polarity during regular operation. Hence, it is important to use a buffer capacitor 2 (CB2) that can withstand both, +25 V during operation mode and -VBAT during INH mode, e.g. a ceramic capacitor. In case of load dump during INH mode, the negative voltage across CB2 will be clamped to -31 V (CB2 referenced to VDH).
Data Sheet
13
Rev. 2.0, 2009-07-10
TLE7189QK
Description and Electrical Characteristics
5.1.4
Electrical Characteristics
Electrical Characteristics MOSFET drivers - DC Characteristics
VS = 5.5 to 20V, Tj = -40 to +150 C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 Parameter Low level output voltage High level output voltage Symbol Min. Limit Values Typ. - - - - - - Max. 0.2 13 13 13 1.0 0.2 V V V V V V - 9 7.5 6.5 - - Unit Conditions
VG_LL VG_HL1
High level output voltage, Low Side VG_HL2 High level output voltage, High Side VG_HL3 High level output voltage difference dVG_H Gate drive output voltage
VGS_D
ILoad=30mA VS=8... 20V; ILoad=-2mA VS=5.5... 8V; ILoad=-2mA VS=5.5... 8V; ILoad=-2mA ILoad=-100mA; VS=20V VENA=low or VVCT=high; ILoad=10mA UVLO; VS<=5.5V; ILoad=2mA
5.5V5.1.7
Gate drive output voltage Tj=-40C Tj=25C Tj=150C
VGS1
-
- 1.4 1.2 1.0
V
5.1.8
Gate drive output voltage high side VGS2 Tj=-40C Tj=25C Tj=150C Gate drive output voltage low side
-
- 1.4 1.2 1.0
V
Over voltage or VS=open or VINH=low; ILoad=2mA Over voltage;
5.1.9 5.1.10
VGS3
- -
- 1.7
0.2 -
V V
ILoad=2mA
SLx open;
Gate drive output voltage low side1) VGS3
VS=open; VINH=low; IGLx=10A
- 1.1 - V SLx open; VS=open; VINH=low; IGLx=3A - -
5.1.11
Gate drive output voltage low side1) VGS3
5.1.12 5.1.13 5.1.14 5.1.15 5.1.16 5.1.17 5.1.18 5.1.19 5.1.20 5.1.21
Low level input voltage of Ixx, ENA VI_LL High level input voltage of Ixx, ENA VI_HL Input hysteresis of IHx, ILx, ENA Input hysteresis of IHx, ILx, ENA Low level input voltage of INH High level input voltage of INH IHx pull up resistor ILx pull down resistor INH, ENA pull down resistor Quiescent current VDH
- 2.0 50 100 - 2.1 18 18 27 - 14
- - - 200 - - 30 30 45 5
1.0 - --0.75 - 42 42 70 -
V V mV mV V V k k k A
dVI1 dVI2 VI_LL VI_HL RIHx RILx RINEN IQVDH
VS=5.5... 8V VS=8... 20V
- -
VIHx<5.5V VILx<5.5V VINH; VENA<5.5V 25C; VINH=low
Rev. 2.0, 2009-07-10
Data Sheet
TLE7189QK
Description and Electrical Characteristics Electrical Characteristics MOSFET drivers - DC Characteristics
VS = 5.5 to 20V, Tj = -40 to +150 C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into
pin (unless otherwise specified) Pos. 5.1.22 5.1.23 Parameter Output bias current SHx Output bias current SLx Symbol Min. Limit Values Typ. -1.0 -1.0 Max. -0.3 -0.3 mA mA -1.6 -1.6 Unit Conditions
ISHx ISLx
VS=5.5...20V; VSHx=0...(VS+1) VS=5.5...20V; VSLx=0...7V
Electrical Characteristics MOSFET drivers - Dynamic Characteristics
VS = 5.5 to 20V, Tj = -40 to +150 C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. 5.1.24 5.1.25 Parameter Fixed internal dead time Turn on current, peak Symbol Min. Limit Values Typ. 400 1.5 Max. 600 - ns A - 220 - Unit Conditions
tDT IG(on)1
5.1.26
Turn on current, peak
IG(on)2
-
0.8
-
A
5.1.27
Turn off current, peak
IG(off)
-
1.5
-
A
5.1.28
Rise time (20-80%) Tj = -40C Tj = 25C Tj = 150C Fall time (20-80%) Tj = -40C Tj = 25C Tj = 150C Input propagation time (low on) Input propagation time (low off) Input propagation time (high on) Input propagation time (high off) Absolute input propagation time difference (all channels turn on) Absolute input propagation time difference (all channels turn off)
tG_rise
- 150 400 400 700
ns
VGxx-VSxx=0V; VS=8...20V; CLoad=22nF; RLoad=1 VGxx-VSxx=0V; VS=5.5...8V; CLoad=22nF; RLoad=1 VGxx-VSxx=10V; VS=8...20V; CLoad=22nF; RLoad=1 CLoad=22nF; RLoad=1
5.1.29
tG_fall
- 150 230 230 500 290 200 290 200 70 70
ns
CLoad=22nF; RLoad=1;
5.1.30 5.1.31 5.1.32 5.1.33 5.1.34 5.1.35
tP(ILN) tP(ILF) tP(IHN) tP(IHF) tP(an) tP(af)
90 0 90 0 - -
190 100 190 100 - -
ns ns ns ns ns ns
CLoad=22nF; RLoad=1
Data Sheet
15
Rev. 2.0, 2009-07-10
TLE7189QK
Description and Electrical Characteristics Electrical Characteristics MOSFET drivers - Dynamic Characteristics
VS = 5.5 to 20V, Tj = -40 to +150 C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into
pin (unless otherwise specified) Pos. 5.1.36 5.1.37 5.1.38 5.1.39 5.1.40 Parameter Symbol Min. Absolute input propagation time tP(1hfln) difference (1channel high off - low on) Absolute input propagation time tP(1lfhn) difference (1channel low off - high on) Absolute input propagation time tP(ahfln) difference (all channel high off - low on) Absolute input propagation time tP(alfhn) difference (all channel low off - high on) Wake up time; INH low to high 40 40 40 40 Limit Values Typ. - - - - - Max. 180 180 180 180 20 ns ns ns ns ms Driver fully functional; VS=6.5...8V; VENA=low; CCPx=CCBx=4.7F Driver fully functional; VS=8...20V; VENA=low; CCPx=CCBx=4,7F Driver fully functional; VS=6.5...8V; VENA=low; CCPx=CCBx=4,7F Driver fully functional; VS=8...20V; VENA=low; CCPx=CCBx=4,7F Unit Conditions
CLoad=22nF; RLoad=1
tINH_Pen1 -
5.1.41
Wake up time; INH low to high
tINH_Pen2 -
-
10
ms
5.1.42
Wake up time logic functions; INH low tINH_log to high
-
-
10
ms
5.1.43
Wake up time logic functions; INH low tINH_log to high
-
-
5
ms
5.1.44 5.1.45 5.1.46 5.1.47 5.1.48
INH propagation time to disable the output stages INH propagation time to disable the output stages INH propagation time to disable the entire driver IC Supply voltage Vs for Wake up Charge pump frequency
tINH_Pdi1 - tINH_Pdi2 - tINH_Pdi3 - VVsWU fCP
6.5 38
- - - - 55
10 8 300 - 72
s s s V kHz
VS=5.5...8V VS=8...20V
- diagnostic, OpAmp working -
Data Sheet
16
Rev. 2.0, 2009-07-10
TLE7189QK
5.2 5.2.1
Protection and Diagnostic Functions Short Circuit Protection
The TLE7189QK provides a short circuit protection for the external MOSFETs. It is a monitoring of the drainsource voltage of the external MOSFETs. As soon as this voltage is higher than the short circuit detection limit, a capacitor will be charged. The high side and the low side output stage of the same half bridge use the same capacitor (see Figure 3 ). This capacitor is discharged permanently with a current which is about 2 times smaller than the charging current. This charging and discharging ratio is specified with the help of duty cycle where a short is detected or not detected. After a delay of about 12s all external MOSFETs will be switched off until the driver is reset by the ENA pin. The error flag is set. The drain-source voltage monitoring of the short circuit detection for a certain external MOSFET is active as soon as the corresponding input is set to "on" and the dead time is expired. The short circuit detection level is adjustable in an analogue manner by the voltage setting at the SCDL pin. There is a 1:1 translation between the voltage applied to the SCDL pin and the drain-source voltage limit. E.g. to trigger the SCD circuit at 1V drain-source voltage, the SCDL pin must be set to 1V as well. The drain-source voltage limit can be chosen between 0.7 ... 2.5V. If the SCDL pin is left open, the short circuit detection level will be set internally to a specified value. In case SCDL is connected to GND the detection level is low. If SCDL is connected to 3.3V, the detection level is about 3.2V. In the TLE7189QK the short circuit detection functionality can be tested by setting the SCDL pin to voltages lower than 0.4V, switching off the low side MOSFETs and switching on one or more high side MOSFETs. In this test, a short circuit will be detected even without current in the external MOSFET (VDH-SHx > VTSCD1). This test function can be used as well to detect an open VDH pin. If VDH is open during this test, no SCD error will be reported. A setting of 5V at the SCDL pin will disable the short circuit protection function.
5.2.2
Dead Time and Shoot Through Protection
In bridge applications it has to be assured that the external high side and low side MOSFETs are not "on" at the same time, connecting directly the battery voltage to GND. The dead time generated in the TLE7189QK is fixed to a minimum value. This function assures a minimum dead time if the input signals coming from the C are faulty. The exact dead time of the bridge is usually controlled by the PWM generation unit of the C. In addition to this dead time, the TLE7189QK provides a locking mechanism, avoiding that both external MOSFETs of one half bridge can be switched on at the same time. This functionality is called shoot through protection. If the command to switch on both high and low side switches in the same half bridge is given at the input pins, the command will be ignored. The conflicting input signals will not generate an error message.
5.2.3
Under Voltage Shut Down
The TLE7189QK has an integrated under voltage shut down, to assure that the behavior of the device is predictable in all voltage ranges. If the voltage of a charge pump buffer capacitors CBx reaches the under voltage shut down level for a minimum specified filter time, the gate-source voltage of all external MOSFETs will be actively pulled to low. In this situation the short circuit detection of this output stage is deactivated to avoid a latching shut down of the driver. As soon as the charge pump buffer voltage recovers, the output stage condition will be aligned to the input patterns automatically.This allows to continue operation of the motor in case of under voltage shut down without a reset by the C.
Data Sheet
17
Rev. 2.0, 2009-07-10
TLE7189QK
Under voltage shut down will not occur when VS > 6V, QG < 250nC, fPWM < 25kHz, and the charge pump capacitors Cxx = 4.7 F.
5.2.4
Over Voltage Shut Down
The TLE7189QK has an integrated over voltage shut down to avoid destruction of the IC at high supply voltages.The voltage is measured at the Vs and the VDH pin. When one of them or all of them exceed the over voltage shut down level for more than the specified filter time then the external MOSFETs are switched off. In addition, over voltage will shut down the charge pumps and will discharge the charge pump capacitors. This results in an under voltage condition which will be indicated on the ERRx pins. During over voltage shut down the external MOSFETs and the charge pumps remain off until a reset is performed.
5.2.5
Over Temperature Warning
If the junction temperature is exceeding typ. 155C an error signal is given as warning. The driver IC will continue to operate in order not to disturb the application. The warning is removed automatically when the junction temperature is cooling down. It is in the responsibility of the user to protect the device against over temperature destruction.
5.2.6
VCC Check
To assure a high level of system safety, the TLE7189QK provides an VCC check. The 5.0V system supply connected to the VS_OA pin is checked by an internally monitoring for over- and under voltage. An internal filter time is integrated to avoid faulty triggering. The VCC check is active when the signal on the ENA pin is high and inactive when ENA signal is low (=driver IC disabled). In case of under- or over voltage at VS_OA, the VCC check will disable the driver IC and is latched. To restart the output stages, a reset has to be performed with the ENA pin. The VCT pin decides about the over voltage and under voltage detection level.
5.2.7
ERR Pins
The TLE7189QK has two status pins to provide diagnostic feedback to the C. The outputs of these pins are 5V push pull stages, they are either High or Low. Table 2 INH High High High High High Low Table 3 Overview of error conditions ENA High High High High Low X ERR1 Low Low High High High Low ERR2 Low High Low High High Low Driver conditions Under voltage or VCC check error Over temperature or over voltage Short circuit detection No errors observed No errors will be reported (except OT warning & undervoltage shutdown) ERR output tristate - low secured by pull down
Behavior at different error conditions restart behavior Auto restart Shuts down... All external Power -MOSFETs Latch, reset must be performed at ENA pin All external Power -MOSFETs Latch, reset must be performed at ENA pin All external Power -MOSFETs
Error condition Short circuit detection Under voltage Over voltage
Data Sheet
18
Rev. 2.0, 2009-07-10
TLE7189QK
Error condition VCC check
restart behavior
Shuts down... Nothing
Over temperature warning Self clearing
Latch, reset must be performed at ENA pin All external Power -MOSFETs
Note: All errors do NOT lead to sleep mode. Sleep mode is only initiated with the INH pin. The latch and restart behavior allows to distinguish between the different error types combined at the ERR signals. Table 4 Priority 1 2 3 4 5 Priorisation of Errors Error VCC check Short circuit detection Under voltage detection Over voltage detection Over temperature
Reset of ERROR registers and Disable The TLE7189QK can be reseted with the help of the enable pin ENA. If the ENA pin is pulled to low for a specified minimum time, the error registers are cleared and the external MOSFETs are switched off actively. During disable only the errors under voltage shut down and over temperature warning are shown. Other errors are not displayed.
5.2.8
Electrical Characteristics
Electrical Characteristics - Protection and diagnostic functions
VS = 5.5 to 20V, Tj = -40 to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Min. Over temperature 5.2.1 5.2.2 Over temperature warning Hysteresis for over temperature warning Limit Values Typ. 155 20 Max. 175 - C C - - Unit Conditions
Tj(OW) dTj(OW)
135 -
Short circuit detection 5.2.3 5.2.4 Filter time of short circuit protection tSCP(off) Maximum duty cycle for no SCD1) 8 - 12 - 16 30 s % Default
DSCDmax
fPWM=100kHz at IHx
or ILx and at static applied SC
5.2.5
minimum duty cycle for periodic SCD1) Voltage range on VSCD pin to adjust the Vds limit Short circuit detection level
DSCDmin
70
-
-
%
fPWM=100 kHz at IHx or ILx and at static applied SC
Short circuit detection is active Short circuit detection is active
5.2.6 5.2.7
VSCDLa1 VSCDLa2
0.7 2.64
- -
2.5 3.63
V V
VSCDL=3.3V
Data Sheet
19
Rev. 2.0, 2009-07-10
TLE7189QK
Electrical Characteristics - Protection and diagnostic functions (cont'd)
VS = 5.5 to 20V, Tj = -40 to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. 5.2.8 Parameter Short circuit disable voltage at VSCD pin Accuracy of SCD (VSCDL /VDS(off)) Accuracy of SCD (VSCDL /VDS(off)) SCDL pull up resistor SCDL pull down resistor SCDL default voltage SCDL voltage for SCD test activation Filter time for SCD test activation VDH-SHx voltage for SCD detection in SCD test mode VDH-SHx voltage with no SCD detection in SCD test mode High level output voltage of ERRx Low level output voltage of ERRx ERR pull down resistor Symbol Min. Limit Values Typ. - Max. 5.5 V Short circuit detection is disabled Unit Conditions
VSCDL(dis) 4.5
5.2.9 5.2.10 5.2.11 5.2.12 5.2.13 5.2.14 5.2.15 5.2.16 5.2.17
ASC(off)1 ASC(off)2 RSCDU RSCDD VSCDLop VSCDT tSCDT VTSCD1 VTSCD2
0.85 0.7 - - - - 0.5 -80 -
- - 400 160 1.4 - 2.5 - -
1.15 1.3 - - - 0.4 - - -350
- - k k V V s mV mV
VSCDL(off) set to 1...
2.5V
VSCDL(off) set to 0.7...
1V Not tested Not tested Open pin - -
Test of short circuit detection
ERR pins 5.2.18 5.2.19 5.2.20 5.2.21
VOHERR VOLERR RERR
4.0 -0.1 2.7 -
- - - -
5.2 0.4 112 200
V V k ns
ILoad= -0.2mA ILoad= 0.2mA VERR<5.5V; VINH=low
-
Propagation time difference ERR1 tPD(ERR) and ERR2 Over voltage shut down Over voltage shut down at VDH Over voltage filter time Under voltage shut down CB1 Under voltage shut down CB2 Hysteresis of under voltage shut down on CB1 and CB2 Under voltage filter time on CB1 and CB2 Reset time to clear ERR registers Low time of ENA signal without reset
Over- and under voltage 5.2.22 5.2.23 5.2.24 5.2.25 5.2.26 5.2.27 5.2.28
VOV(off) VOV(off) tOV VUV1 VUV2 VHUV1,2 tUV
28 28 30 7.4 4.6 - 3.5
- - - 8.2 - 1.0 5
33 32.7 60 9.0 6.8 - 7
V V s V V V s
- - - CB1 to GND CB2 to VDH - -
Enable and reset 5.2.29 5.2.30
tRes1 tRes0
3.0 -
- -
- 1.0
s s
- -
Data Sheet
20
Rev. 2.0, 2009-07-10
TLE7189QK
Electrical Characteristics - Protection and diagnostic functions (cont'd)
VS = 5.5 to 20V, Tj = -40 to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. 5.2.31 5.2.32 Parameter Symbol Min. ENA propagation time (for enable / tPENA disable) Return time to normal operation at tAR auto-restart - - Limit Values Typ. - - Max. 4.0 1.0 s s - - Unit Conditions
VCC Check 5.2.33 5.2.34 5.2.35 5.2.36 5.2.37 5.2.38 5.2.39 5.2.40
1)
VVCU Over voltage detection level VVCOl Over voltage detection level VVCOh Over- and under voltage filter time tVC Low level input voltage of VCT VVCT_LL High level input voltage of VCT VVCT_HL RVCT VCT pull up resistor tVCT Filter time for VCT test
Under voltage detection level
4.3 5.3 3.3 10 - 2.0 27 1.3
- - - - - - 45 2
4.7 5.8 4.3 25 1.0 - 70 3.0
V V V s V V k s
VVCT=low VVCT=low VVCT=high
- - -
VVCT<5.5V
-
Parameters describe the behavior of the internal SCD circuit. Therefore only internal delay times are considered. In application dead-/ delay times determined by application circuit (switching times of MOSFETs, adjusted dead time) have to be considered as well.
Data Sheet
21
Rev. 2.0, 2009-07-10
TLE7189QK
5.3
Shunt Signal Conditioning
The TLE7189QK incorporates three fast and precise operational amplifiers for conditioning and amplification of the shunt signals sensed in the three phases. Additionally, one reference bias buffer is integrated to provide an adjustable bias reference for the three OpAmps. The voltage divider on the VRI pin should be less than 50 k, the filtering capacitor less than 1.2 F - if needed at all. The gain of the OpAmps is adjustable by external resistors within a range of 5 to 15. When VISP = VISN, VO provides the reference voltage VVRO. VVRO is normally half of the regulated voltage provided from an external voltage regulator for the ADC used to read the current sense signal. The additional buffer allows bi-directional current sensing and permits the adaptation of the reference bias to different C I/O voltages. The reference buffer assures a stable reference voltage even in the high frequency range. The reference bias buffer is used for all of the OpAmps. The OpAmps of the TLE7189QK demonstrate low offset voltages and very little drift over temperature, thus allowing accurate phase current measurements.
3.3V CVRI < 1.2 F (if needed) RVRI < 50 kOhm VRI RVRI VRO CVRI RVRI
Adjustable bias reference
+ Bias
Reference
-
Rfb Rfb Rfb ISP1 I-DC Link OpAmp1 Rs
TLE7189
I-DC Link OpAmp2
I-DC Link OpAmp3
VO3 VO2
VO1
1k
1k
to ADCs
Figure 4
Shunt Signal Conditioning Block Diagram
Data Sheet
22
+
-
Dependent on customer specific requirements additional filtering can be necessary
+
+ -
Rs ISN1 Rfb Rs ISP2 Rs ISN2
Shunt
Rs ISP3 Rs ISN3
Rev. 2.0, 2009-07-10
TLE7189QK
5.3.1
Electrical Characteristics
Electrical Characteristics - Current sense signal conditioning
VS = 5.5 to 20V, VVSOA = 5V, Tj = -40 to +150 C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 Parameter Series resistors Resistor ratio (gain ratio) Resistor ratio (gain ratio) Input differential voltage (ISPx ISNx) Input voltage (Both Inputs - GND) (ISP - GND) or (ISN -GND) Input voltage (Both Inputs - GND) (ISP - GND) or (ISN -GND) Symbol Min. Limit Values Typ. 500 - - - - - - Max. 1000 20 20 800 2200 1500 1.28 - - mV mV mV mV - -
1k and 200pF at VOx
Unit
Conditions
RRS 100 RRfb/RRS1 5 RRfb/RRS2 3 VIDR VLL1 VLL2
-800 -800 -800 -1.58
-
VS=8 ... 20V
Input offset voltage of the I-DC link VIO1 OpAmp, including drift over temperature range Input offset voltage of reference buffer VRI input range Input bias current Input bias current of reference buffer High level output voltage of VOx Low level output voltage of VOx Output voltage of VOx
RRS=500; VCM=0V; VO=1.65V; VRI=1.65V
- -
5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 5.3.14
VIO2 VRI IIB IIBRB VOH VOL VOR ISC RRI ISC CMRR
-3 1.2 -300 0.6 4.0 -0.1 1.623
- - - 1.4 - - 1.65
2 2.6 -70 2.4 4.5 0.2 1.668
mV V A A V V V
VCM=0V; VO=open VRI=1.65V VRI=1.2 ... 2.6V; IOH=-3mA; VRI=1.2 ... 2.6V; IOH=3mA VIN(SS)=0V;
Gain=15; VRI=1.65V
5.3.15 5.3.16 5.3.17 5.3.18
Output short circuit current Differential input resistance
1) 1)
5 100 - 80
- - - -
- - 10 -
mA k pF db
- - 10kHz -
Common mode input capacitance Common mode rejection ratio at DC CMRR = 20*Log((Vout_diff/Vin_diff) * (Vin_CM/Vout_CM))
5.3.19
Common mode suppression2) with CMS CMS = 20*Log(Vout_CM/Vin_CM) Freq =100kHz Freq = 1MHz Freq = 10MHz
- 62 43 33
-
db
VIN=360mV*
sin(2**freq*t);
RRS=500; RRfb=7500; VVRI=1.65, 2.5V
Data Sheet
23
Rev. 2.0, 2009-07-10
TLE7189QK
Electrical Characteristics - Current sense signal conditioning (cont'd)
VS = 5.5 to 20V, VVSOA = 5V, Tj = -40 to +150 C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. 5.3.20 Parameter Slew rate Symbol Min. Limit Values Typ. 10 Max. - V/s Gain>= 5; RLoad=1.0k; CLoad=500pF - - Unit Conditions
ISC
5.3.21 5.3.22 5.3.23
Large signal open loop voltage gain AOL (DC) Unity gain bandwidth Phase margin1)
80 12 -
100 22 50
- - -
dB MHz
GBW
M
RLoad=1k; CLoad=100pF
Gain>= 5; RLoad=1k; CLoad=100pF
5.3.24 5.3.25
Gain margin1) Bandwidth
AM BWG
- 1.6
12 -
- -
db MHz
RLoad=1k; CLoad=100pF
Gain=15; RLoad=1k; CLoad=500pF; Rs=500 Gain=15; RLoad=1k; CLoad=500pF; 0.25.3.26 5.3.27 5.3.28
Output settle time to 98% Output rise time 10% to 90% Output fall time 90% to 10%
tset tIrise tIfall
- - -
1 - -
1.8 1 1
s s s
1) Not subject to production test; specified by design 2) Without considering any offsets such as input offset voltage, internal miss match and assuming no tolerance error in external resistors.
Data Sheet
24
Rev. 2.0, 2009-07-10
TLE7189QK
Application Description
6
Application Description
In the automotive sector there are more and more applications requiring high performance motor drives, such as electro-hydraulic or electric power steering. In these applications 3 phase motors, synchronous and asynchronous, are used, combining high output performance, low space requirements and high reliability.
Reverse polarity switch V S=12V R VS 10 *) C xxxx F P-GND
RVDH 100 V_Bridge VS_OA INH VS VDH
>2 SCDL VRI GH1 SH1 >2 GH2 CH2 C CP2 1F CL2 CCB2 1 F ceramic V_Bridge CCP1 1 F C and/or System ASIC CCB1 2.2F see 4.1.2: all pump capacitors 1F to 4.7F CH1 CB2 GH3 SH3 SH2 >2
TLE7189
CL1 CB1 GL1 SL1 GL2 ENA SL2 RERR *) RERR *) ERR1 ERR2 IL1 IH1 IL2 IH2 IL3 IH3 VCT VO3 VO2 VO1 RO *) GND ISN3 ISN2 ISN1 VRO ISP3 ISP2 ISP1 GL3 SL3
>2
>2
>2
Shunt
GND
capacitors for shunt signal conditioning only if additional filtering is desired
*) see max. Ratings
P-GND
Figure 5
Application Circuit - TLE7189QK
Note: This is a very simplified example of an application circuit. The function must be verified in the real application. Data Sheet 25 Rev. 2.0, 2009-07-10
TLE7189QK
Application Description
6.1
* * * *
Layout Guide Lines
Please refer also to the simplified application example. Three separated bulk capacitors CB should be used - one per half bridge Three separated ceramic capacitors CC should be used - one per half bridge Each of the 3 bulk capacitors CB and each of the 3 ceramic capacitors CC should be assigned to one of the half bridges and should be placed very close to it The components within one half bridge should be placed close to each other: high side MOSFET, low side MOSFET, bulk capacitor CB and ceramic capacitor CC (CB and CC are in parallel) and the shunt resistor form a loop that should be as small and tight as possible. The traces should be short and wide The three half bridges can be separated; yet, when there is one common GND referenced shunt resistor for the three half bridges the sources of the three low side MOSFETs should be close to each other and close to the common shunt resistor VDH is the sense pin used for short circuit detection; VDH should be routed (via Rvdh) to the common point of the drains of the high side MOSFETs to sense the voltage present on drain high side CB2 is the buffer capacitor of charge pump 2; its negative terminal should be routed to the common point of the drains of the high side MOSFETs as well - this connection should be low inductive / resistive Additional R-C snubber circuits (R and C in series) can be placed to attenuate/suppress oscillations during switching of the MOSFETs, there may be one or two snubber circuits per half bridge, R (several Ohm) and C (several nF) must be low inductive in terms of routing and packaging (ceramic capacitors) the exposed pad on the backside of the LQFP is recommended to connect to GND
*
* * *
*
Data Sheet
26
Rev. 2.0, 2009-07-10
TLE7189QK
Package Outlines
7
Package Outlines
0.10.05 STAND OFF 1.4 0.05 1.6 MAX.
+0.0 0.15 -0.0 5
H 0.6 0.15
6
0.5 7.5 0.2 -0.03
+0.07
0.08 C 64x C SEATING COPLANARITY PLANE 0.08 M A-B D C 64x
Bottom View
12 10
1)
0.2 A-B D 64x 0.2 A-B D H 4x
Ex (By) Ay Solder Area Exposed Diepad
D A B 10
1)
12
Ey
64 1
1
64
Index Marking Exposed Diepad Dimensions Package Leadframe PG-LQFP-64-17 C66065-A6866-C017 Ex 6 Ey 6
Index Marking Ay 5 0.1 (By) 5.7
0...7
1) Does not include plastic or metal protrusion of 0.25 max. per side
PG-LQFP-64-17-PO V02
GPS09181
Figure 6
PG-LQFP-64-17
Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Data Sheet 27
Dimensions in mm Rev. 2.0, 2009-07-10
TLE7189QK
Revision History
8
Version V2.0
Revision History
Date 2009-07 Changes -
Data Sheet
28
Rev. 2.0, 2009-07-10
Edition 2009-07-10 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer PRO-SILTM is a Registered Trademark of Infineon Technologies AG. The PRO-SILTM Trademark designates Infineon products which contain SIL Supporting Features.SIL Supporting Features are intended to support the overall System Design to reach the desired SIL (according to IEC61508) or A-SIL (according to ISO26262) level for the Safety System with high efficiency. SIL respectively A-SIL certification for such a System has to be reached on system level by the System Responsible at an accredited Certification Authority. SIL stands for Safety Integrity Level (according to IEC 61508) A-SIL stands for Automotive-Safety Integrity Level (according to ISO 26262) The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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