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PD - 96189
IRFB4310ZGPBF
HEXFET(R) Power MOSFET
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free l Halogen-Free
D
G S
VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited)
D
100V 4.8m: 6.0m: 127A 120A
c
G
D
S
TO-220AB IRFB4310ZGPBF G D S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V(Wire Bond Limited) Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
127 90 120 560 250 1.7 20 18 -55 to + 175 300 10lbxin (1.1Nxm) 130 See Fig. 14, 15, 22a, 22b,
Units
A
d
W W/C V V/ns
f
C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche CurrentA Repetitive Avalanche Energy
e
g
mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA Junction-to-Case Case-to-Sink, Flat Greased Surface Junction-to-Ambient
j
Parameter
Typ.
--- 0.50 ---
Max.
0.6 --- 62
Units
C/W
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1
10/15/08
IRFB4310ZGPBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
100 --- --- 2.0 --- --- --- --- --- --- 0.11 4.8 --- --- --- --- --- 0.7 --- --- 6.0 4.0 20 250 100 -100 --- nA V
Conditions
VGS = 0V, ID = 250A
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) IDSS IGSS RG Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 75A V A VDS = VGS, ID = 150A VDS = 100V, VGS = 0V VDS = 80V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V
g
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance
Min. Typ. Max. Units
150 --- --- --- --- --- --- --- --- --- --- --- 120 29 35 85 20 60 55 57 6860 490 220 570 920 --- --- --- --- --- --- --- --- --- --- pF ns --- 170 --- S nC ID = 75A VDS =50V VGS = 10V VDD = 65V ID = 75A RG = 2.7 VGS = 10V VGS = 0V VDS = 50V
Conditions
VDS = 50V, ID = 75A
ID = 75A, VDS =0V, VGS = 10V
g
g i, See Fig. 11 = 0V to 80V h
Conditions
D
Reverse Transfer Capacitance --- Coss eff. (ER) Effective Output Capacitance (Energy Related) --- Coss eff. (TR) Effective Output Capacitance (Time Related)h ---
= 1.0MHz, See Fig. 5 VGS = 0V, VDS
VGS = 0V, VDS = 0V to 80V
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Ad Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- --- 127 --- --- 40 49 58 89 2.5 --- A nC 560 1.3 A A V ns
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 75A, VGS = 0V VR = 85V, TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C
G
S
g g
IF = 75A di/dt = 100A/s
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 120A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.047mH RG = 25, IAS = 75A, VGS =10V. Part not recommended for use above the Eas value and test conditions. ISD 75A, di/dt 600A/s, VDD V(BR)DSS, TJ 175C.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniques refer to application note #AN-994. R is measured at TJ approximately 90C. Coss while VDS is rising from 0 to 80% VDSS.
2
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IRFB4310ZGPBF
1000
TOP
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
TOP
BOTTOM
VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
100
10
4.5V
4.5V 60s PULSE WIDTH Tj = 25C
1 0.1 1 10 100
60s PULSE WIDTH Tj = 175C
10 0.1 1 10 100
VDS , Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
2.5
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 75A
2.0
ID, Drain-to-Source Current()
VGS = 10V
100
TJ = 175C
10
1.5
TJ = 25C
1
1.0
VDS = 50V
0.1 2.0 3.0 4.0 5.0
60s PULSE WIDTH
6.0 7.0 8.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
12000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd 8000
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS, Gate-to-Source Voltage (V)
ID= 75A VDS = 80V VDS= 50V VDS= 20V
10000
16
C, Capacitance (pF)
Ciss
12
6000
8
4000
2000
Coss Crss
4
0 1 10 100
0 0 40 80 120 160 200 QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB4310ZGPBF
1000
10000
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
100
TJ = 175C
1000
OPERATION IN THIS AREA LIMITED BY R DS (on)
100
1msec
100sec
10
TJ = 25C
10
10msec
1
1
VGS = 0V
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Tc = 25C Tj = 175C Single Pulse 0.1 1
DC 10 100
0.1
VSD , Source-to-Drain Voltage (V)
VDS, Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
140 LIMITED BY PACKAGE 120
ID, Drain Current (A)
Fig 8. Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage
130
ID = 5mA
120
100 80 60 40 20 0 25 50 75 100 125 150 175 TC, Case Temperature (C)
110
100
90 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
EAS, Single Pulse Avalanche Energy (mJ)
3.0
Fig 10. Drain-to-Source Breakdown Voltage
600
2.5
500
ID 11A 19A BOTTOM 75A
TOP
2.0
400
Energy (J)
1.5
300
1.0
200
0.5
100
0.0 0 20 40 60 80 100
0 25 50 75 100 125 150 175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFB4310ZGPBF
1
D = 0.50
Thermal Response ( ZthJC )
0.1
0.20 0.10 0.05 0.02
J J 1 R1 R1 2 R2 R2 R3 R3 3 R4 R4 C 2 3 4 4
0.01
0.01 SINGLE PULSE ( THERMAL RESPONSE )
1
Ci= i/Ri Ci i/Ri
Ri (C/W) 0.018756 0.159425 0.320725 0.101282
(sec)
0.000373 0.000734 0.005665 0.115865
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.0001 0.001 0.01 0.1
0.001 1E-006 1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse 0.01
10
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
Avalanche Current (A)
0.05 0.10
1
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C.
0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
140 120 100 80 60 40 20 0 25 50 75 100 125 150 175
EAR , Avalanche Energy (mJ)
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 75A
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Starting TJ , Junction Temperature (C)
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB4310ZGPBF
4.5
24
VGS(th) Gate threshold Voltage (V)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75
ID = 1.0A ID = 1.0mA ID = 250A ID = 150A
IRRM - (A)
20
16
12
8
4
IF = 30A VR = 85V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
0
100 125 150 175
TJ , Temperature ( C )
dif / dt - (A / s)
Fig 16. Threshold Voltage Vs. Temperature
24
Fig. 17 - Typical Recovery Current vs. dif/dt
600
20
500
16
400
IRRM - (A)
QRR - (nC)
12
300
8
200
4
IF = 45A VR = 85V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
100
IF = 30A VR = 85V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
0
0
dif / dt - (A / s)
dif / dt - (A / s)
Fig. 18 - Typical Recovery Current vs. dif/dt
600
Fig. 19 - Typical Stored Charge vs. dif/dt
500
400
QRR - (nC)
300
200
100
IF = 45A VR = 85V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
0
dif / dt - (A / s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB4310ZGPBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
*
* * * *
dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
**
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* Use P-Channel Driver for P-Channel Measurements ** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
Fig 22b. Unclamped Inductive Waveforms
V DS VGS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
90%
D.U.T.
+
VDS
-VDD
10%
VGS
td(on) tr td(off) tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT
20K 1K
S
VCC
Vgs(th)
Qgodr
Qgd
Qgs2 Qgs1
Fig 24a. Gate Charge Test Circuit
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Fig 24b. Gate Charge Waveform
7
IRFB4310ZGPBF
Dimensions are shown in millimeters (inches)
TO-220AB Package Outline
TO-220AB Part Marking Information
@Y6HQG@) UCDTADTA6IADSA7#" BQ7A Ir)AABAAssvAvAhAirA vqvphrAAChytrAAArrA Ir)AAQAAvAhriyAyvrAvv vqvphrAAGrhqAAArrA DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G GPUA8P9@ Q6SUAIVH7@S 96U@A8P9@) 2G6TUA9DBDUAPA 86G@I96SA@6S XX2XPSFAX@@F Y2A68UPSA8P9@
TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 10/2008
8
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