View ISO1H812G_5019289.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Datasheet, Version 2.2, July 2009
ISOFACE
ISO1H812G
TM
Coreless Transformer Isolated Digital Output 8 Channel 0.625A High-Side Switch
Power Management & Drives
Never
stop
thinking.
ISO1H812G Revision History: Previous Version: 2.0 2.1 2.2 2009-07-01 V2.1 Version 2.2
Final Datasheet Data for parallel channels and UL approval added
Page 4, Figure 1 updated
Edition 2009-07-01 Published by Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany (c) Infineon Technologies AG 2009. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
ISOFACETM
ISO1H812G
Coreless Transformer Isolated Digital Output 8 Channel 0.625A High-Side Switch
Product Highlights
* * * * * * Coreless transformer isolated data interface Galvanic isolation 8 High-side output switches 0.625A C compatible 8-bit serial peripheral Isolated return path for DIAG signal UL508 compliant
Features
* * * * * * * * * * * * * * * * * * Interface CMOS 3.3/5V operation compatible Serial Interface High common mode transient immunity Short circuit protection Maximum current internally limited Overload protection Overvoltage protection (including load dump) Undervoltage shutdown with autorestart and hysteresis Switching inductive loads Common output disable pin Thermal shutdown with restart Thermal independence of seperate channels Common diagnostic output for overtemperature ESD protection Loss of GNDbb and loss of Vbb protection Very low standby current Reverse battery protection RoHS compliant
Typical Application
* * * * Isolated switch for industrial applications (PLC) All types of resistive, inductive and capacitive loads C compatible power switch for 24V DC applications Driver for solenoid, relays and resistive loads
Description
The ISO1H812G is a galvanically isolated 8 bit data interface in PG-DSO-36 package that provides 8 fully protected high-side power switches that are able to handle currents up to 625 mA. An serial C compatible interface allows to connect the IC directly to a C system. The input interface is designed to operate with 3.3/5V CMOS compatible levels. The data transfer from input to output side is realized by the integrated Coreless Transformer Technology.
Typical Application
VCC VCCP1.x AD0 WR VCC DIS CS SCLK DIAG Control & Protectio n Unit OUT1 Serial Interface Control Unit OUT0 CT Vbb Vbb
P0.0
SI
for daisy chain
SO DIAG
C (i.e C166)
GND
OUT7
ISO1H812G
GNDCC
GNDbb
Type ISO1H812G Datasheet
On-state Resistance 200m 3
Package PG-DSO-36 Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Pin Configuration and Functionality
1
1.1
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 TAB
Pin Configuration and Functionality
Pin Configuration
Symbol N.C. VCC DIS CS SCLK SI N.C. N.C. N.C. N.C. N.C. N.C. SO DIAG GNDCC N.C. N.C. N.C. GNDbb N.C OUT7 OUT7 OUT6 OUT6 OUT5 OUT5 OUT4 OUT4 OUT3 OUT3 OUT2 OUT2 OUT1 OUT1 OUT0 OUT0 Vbb Function Not connected Positive 3.3/5V logic supply Output disable Chip select Serial Clock Serial Data input Not connected Not connected Not connected Not connected Not connected Not connected Serial Data Output Common diagnostic output for overtemperature Input logic ground Not connected Not connected Not connected Output driver ground Not connected High-side output of channel 7 High-side output of channel 7 High-side output of channel 6 High-side output of channel 6 High-side output of channel 5 High-side output of channel 5 High-side output of channel 4 High-side output of channel 4 High-side output of channel 3 High-side output of channel 3 High-side output of channel 2 High-side output of channel 2 High-side output of channel 1 High-side output of channel 1 High-side output of channel 0 High-side output of channel 0 Positive driver power supply voltage Figure 1 .
Vbb N.C. VCC DIS CS SCLK SI N.C. N.C. N.C. N.C. N.C. N.C. SO DIAG GNDCC N.C. N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TAB 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 OUT5 OUT5 OUT6 OUT6 OUT7 OUT7 N.C. GNDbb
TAB Vbb
Power SO-36 (430mil)
Datasheet
4
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Pin Configuration and Functionality
1.2
Pin Functionality
GNDCC (Ground for VCC domain) This pin acts as the ground reference for the input interface that is supplied by VCC. GNDbb (Output driver ground domain) This pin acts as the ground reference for the output driver that is supplied by Vbb. OUT0 ... OUT7 (High side output channel 0 ... 7) The output high side channels are internally connected to Vbb and controlled by the corresponding data input. TAB (Vbb, Positive supply for output driver) The heatslug is connected to the positive supply port of the output interface.
VCC (Positive 3.3/5V logic supply) The VCC supplies the input interface that is galvanically isolated from the output driver stage. The input interface can be supplied with 5V. DIS (Output disable) The high-side outputs OUT0...OUT7 can be immediately switched off by means of the low active pin DIS that is an asynchronous signal. The input registers are also reset by the DIS signal. The output remains switched off after low-high transient of DIS, till new data is written into the input interface. Current Sink to GNDCC CS (Chip select) The system microcontroller selects the ISO1H812G by means of the low active pin CS to activate the interface. Current Source to VCC SCLK (Serial shift clock) SCLK (serial clock) is used to synchronize the data transfer between the master and the ISO1H802G. Data present at the SI pin are latched on the rising edge of the serial clock input, while data at the SO pin is updated after the falling edge of SCLK in serial mode. Current Source to VCC SI (Serial data input) This pin is used to transfer data into the device. Data is latched on the rising edge of the serial clock. Current Sink to GNDCC SO (Serial data output) This pin is used when the serial interface is activated. SO can be connected to a serial input of a further IC to built a daisy-chain configuration. It is only actvated if CS is in low state, otherwise this output is in high impedance state. DIAG (Common diagnostic output for overtemperature) The low active DIAG signal contains the OR-wired information of the separated overtemperature detection units for each channel.The output pin DIAG provides an open drain functionality that. A current source is also connected to the pin DIAG. In normal operation the signal DIAG is high. When overtemperature or Vbb below ON-Limit is detected the signal DIAG changes to low. Datasheet 5
Version 2.2, 2009-07-01
2
Figure 2
Vbb CT Logic GNDbb Voltage Source Overvoltage Protection Serial to Parallel Undervoltage Shutdown with Restart to Logic Channel 1 6 Gate Protection Limitation of Unclamped Inductive Load Current Limitation Overload Protection Temperature Sensor High-side Channel 0 OUT1 OUT2 OUT3 Channel 1 ... 6 OUT4 OUT5 OUT6 Vbb Common Diagnostic Output OUT0 Charge Pump Level shifter Rectifier
Galvanic Isolation
Datasheet
VCC
Undervoltage Shutdown with Restart
Blockdiagram
GNDCC
Blockdiagram
DIS
Logic
6
VCC 100A Logic Charge Pump Level Shifter Rectifier High-side Channel 7
CS
to Logic Channel 1 6
SCLK
SI
Serial Input Interface
from Temperature Sensor Channel 1 6
Gate Protection Limitation of Unclamped Inductive Load Current Limitation Overload Protection Temperature Sensor OUT7
SO
DIAG
Version 2.2, 2009-07-01
ISO1H812G
Blockdiagram
ISOFACETM ISO1H812G
ISOFACETM ISO1H812G
Functional Description
3
3.1
Functional Description
Introduction 3.3.2 Power Transistor Overvoltage Protection
The ISOface ISO1H812G includes 8 high-side power switches that are controlled by means of the integrated C compatible SPI interface. The outputs OUT0...OUT7 are controlled by the data of the serial input SI. The IC can replace 8 optocouplers and the 8 high-side switches in conventional I/O-Applications as a galvanic isolation is implemented by means of the integrated coreless transformer technology. The C compatible interfaces allow a direct connection to the ports of a microcontroller without the need for other components. Each of the 8 high-side power switches is protected against short to Vbb, overload, overtemperature and against overvoltage by an active zener clamp. The diagnostic logic on the power chip recognizes the overtemperature information of each power transistor The information is send via the internal coreless transformer to the pin DIAG at the input interface.
Each of the eight output stages has its own zener clamp that causes a voltage limitation at the power transistor when solenoid loads are switched off. VON is then clamped to 47V (min.).
Vbb Vz VON Vbb
OUTx GNDbb
Figure 3
Inductive and overvoltage output clamp (each channel)
3.2
Power Supply
The IC contains 2 galvanic isolated voltage domains that are independent from each other. The input interface is supplied at VCC and the output stage is supplied at Vbb. The different voltage domains can be switched on at different time. The output stage is only enabled once the input stage enters a stable state.
Energy is stored in the load inductance during an inductive load switch-off.
EL = 1 2 x L x IL
2
Ebb EAS Vbb Dx Vbb OUTx L GNDbb ZL ER RL EL ELoad
3.3
Output Stage
Each channel contains a high-side vertical power FET that is protected by embedded protection functions. The continuous current for each channel is 625mA (all channels ON).
3.3.1
Output Stage Control
Figure 4
Each output is independently controlled by an output latch and a common reset line via the pin DIS that disables all eight outputs and reset the latches. Serial data input (SI) is read on the rising edge of the serial clock SCLK. A logic high input data bit turns the respective output channel ON, a logic low data bit turns it OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition of CS transfers the serial data input bits to the output buffer.
Inductive load switch-off energy dissipation (each channel)
While demagnetizing the load inductance, the energy dissipation in the DMOS is
E AS = E bb + E L - E R = V ON ( CL ) x i L ( t )dt
with an approximate solution for RL > 0W:
IL x L IL x RL E AS = --------------- x ( V bb + V ON ( CL ) ) x ln 1 + ------------------------ 2 x RL V ON ( CL )
Datasheet
7
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Functional Description
3.3.3
Power Transistor Overcurrent Protection
IN
The outputs are provided with a current limitation that enters a repetitive switched mode after an initial peak current has been exceeded. The initial peak short circuit current limit is set to IL(SCp) at Tj = 125C. During the repetitive mode short circuit current limit is set to IL(SCr). If this operation leads to an overtemperature condition, a second protection level (Tj > 135C) will change the output into a low duty cycle PWM (selective thermal shutdown with restart) to prevent critical chip temperatures.
IN
VOUT Normal operation IL
t
Output short to GND t IL(SCp) IL(SCr) t
DIAG
t VOUT t
Figure 7
Short circuit in on-state, shut down down by overtemperature, restart by cooling
TJ
t
3.4
DIAG t
Common Diagnostic Output
t
The overtemperature detection information are ORwired in the common diagnostic output block. The information is send via the integrated coreless transformer to the input interface. The output stage at pin DIAG has an open drain functionality combined with a current source.
VCC Common Diagnostic Output
Figure 5
Overtemperature detection
The following figures show the timing for a turn on into short circuit and a short circuit in on-state. Heating up of the chip may require several milliseconds, depending on external conditions.
IN
100A DIAG
CT
VOUT Output short to GND IL
t
t IL(SCp) IL(SCr) t
Figure 8
Common diagnostic output
DIAG
t
Figure 6
Turn on into short circuit, shut down by overtemperature, restart by cooling
Datasheet
8
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Functional Description
3.5
Serial Interface
The ISO1H812G contains a serial interface that can be directly controlled by the microcontroller output ports.
SI - Serial input. Serial data bits are shifted in at this pin, the most significant bit first. SI information is read in on the rising edge of the SCLK. Input data is latched in the shift register and then transferred to the control buffer of the output stages. SO - Serial output. SO is in a high impedance state until the CS pin goes to a logic low state. The data of the internal shift register are shifted out serially at this pin. The most significant bit will appear at first. The further bits will appear following the falling edge of SCLK.
3.5.1
SPI Signal Description
CS - Chip select. The system microcontroller selects the ISO1H812G by means of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the C. CS High to low transition:
3.5.2
*Serial input data can be clocked in from then on *SO changes from high impendance state to logic high or low state corresponding to the SO bit-state CS Low to high transition:
SPI Bus Concepts Independent Individual Control
3.5.2.1
Each IC with a SPI is controlled individually and independently by an SPI master, as in a directional point-to-point communication.The port requirements for this topology are the greatest, because for each controlled IC an individual SPI at the C is needed (SCLK, CS, SI). All ICs can be addressed simultaneously with the full SPI bandwidth.
*Transfer of SI bits from shift register into output buffers, if number of clock signals was an integer multiple of 8 *SO changes from the SO bit-state to high impendance state
SPI 1
CLK Tx a1 Tx a2
SCLK CS SI SO SPI - Interface
Output lines
To avoid any false clocking the serial input pin SCLK should be logic high state during high-to-low transition of CS. When CS is in a logic high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. The integrated modulo counter that counts the number of clocks avoids the take over of invalid commands caused by a spike on the clock line or wrong number of clock cycles. A command is only taken over if after the low-to-high transition of the CS signal the number of counted clock cycles is an integer multiple of 8. SCLK - Serial clock. The system clock pin clocks the internal shift register of the ISO1H812G. The serial input (SI) accepts data into the input shift register on the rising edge of SCLK while the serial output (SO) shifts the output information out of the shift register on the falling edge of the serial clock. It is essential that the SCLK pin is in a logic high state whenever chip select CS makes any transition. The number of clock pulses will be counted during a chip select cycle. The received data will only be accepted, if exactly an integer multiple of 8 clock pulses were counted during CS is active.
IC 1
SPI n
CLK Tx n1 Tx n2
SCLK CS SI SO SPI - Interface
Output lines
C
IC n
Number of adressed ICs = n Number of necessary control and data ports = 3 n Individual ICs are adressed by the chip select
Figure 9
Individual independent control of each IC with SPI
3.5.2.2
Daisy-chain Configuration
The connection of different ICs and a C as shown in Fig. 11 is called a daisy-chain. For this type of bustopology only one SPI interface of the C for two or
Datasheet
9
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Functional Description more ICs is needed. All ICs share the same clock and chip select port of the SPI master. That is all ICs are active and addressed simultaneously. The data out of the C is connected to the SI of the first IC in the line. Each SO of an IC is connected to the SI of the next IC in the line.
CLK Tx a1 Tx a2 SCLK CS SI SO SPI - Interface IC1
wether the transmitted data is valid or not. If four times serial data coming from the internal registers is not accepted the output stages are switched off until the next valid data is received.
SPI 1
Output lines
SCLK CS SI SPI - Interface C ICn
Output lines
Number of adressed ICs = n Number of necessary control and data ports = 3 All ICs are adressed by the common chip select
Figure 10
SPI bus all ICs in a "daisy chain" configuration
The C feeds to data bits into the SI of IC1 (first IC in the chain). The bits coming from the SO of IC1 are directly shifted into the SI of the next IC. As long as the chip select is inactive (logic high) all the IC SPIs ignore the clock (SCLK) and input signals (SI) and all outputs (SO) are in tristate. As long as the chip select is active the SPI register works as a simple shift register. With each clock signal one input is shifted into the SPI register (SI), each bit in the shift register moves one position further within the register, and the last bit in the SPI shift register is shifted out of SO. This continous as long as the chip select is active (logic low) and clock signals are applied. The data is then only taken over to the output buffers of each IC when the CS signal changes to high from low and recognized as valid data by the internal modulo counter.
3.6
Transmission Failure Detection
There is a failure detection unit integrated to ensure also a stable functionality during the integrated coreless transformer transmission. This unit decides
Datasheet
10
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Functional Description
3.7
Serial Interface Timing
CS
Chipselect active
SCLK
SI
n+7
n+6
n+5
n+4
n+3
n+2
n+1
n
SO
Figure 11
n
n-1
n-2
n-3
n-4
n-5
n-6
n-7
Serial interface
CS
tCSS
tp(SCLK)
tCSH
SCLK
tSCLKL
tSCLKH tSU tHD MSB In
Serial input timing diagram
tSCLKF
tCSD
tSCLKR
SI
Figure 12
LSB In
CS
SCLK tVALID SO MSB Out
Serial output timing diagram
tSODIS
11
LSB Out
Figure 13
Datasheet
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Electrical Characteristics
4
Electrical Characteristics
Note: All voltages at pins 2to 14 are measured with respect to ground GNDCC (pin 15). All voltages at pin 20 to pin 36 and TAB are measured with respect to ground GNDbb (pin 19). The voltage levels are valid if other ratings are not violated. The two voltage domains VCC ,GNDCC and Vbb ,GNDbb are internally galvanic isolated.
4.1
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 2 (VCC) and TAB (Vbb) is discharged before assembling the application circuit. Supply voltages higher than Vbb(AZ) require an external current limit for the GNDbb pin, e.g. with a 15 resistor in GNDbb connection. Operating at absolute maximum ratings can lead to a reduced lifetime. Parameter at Tj = -40 ... 135C, unless otherwise specified Supply voltage input interface (VCC) Supply voltage output interface (Vbb) Continuos voltage at pin SI Continuos voltage at pin CS Continuos voltage at pin SCLK Continuos voltage at pin DIS Continuos voltage at pin SO Continuos voltage at pin DIAG Load current (short-circuit current) Reverse current through GNDbb1) Operating Temperature Storage Temperature Power Dissipation
2) 3)
Symbol VCC Vbb VDx VCS VWR VDIS VDx VDIAG IL IGNDbb Tj Tstg Ptot EAS
Limit Values min. -0.5 -1
1)
Unit 6.5 45 6.5 6.5 6.5 6.5 6.5 6.5 V
max.
-0.5 -0.5 -0.5 -0.5 -0.5 -0.5
---1.6 -25 -50
self limited
A
--internal limited C 150 3.3 W J
---
Inductive load switch-off energy dissipation single pulse, Tj = 125C, IL = 0.625A one channel active all channel simultaneously active (each channel) Load dump protection3) VloadDump4)=VA + VS VIN = low or high td = 400ms, RI = 2W, RL = 27W, VA = 13.5V td = 350ms, RI = 2W, RL = 57W, VA = 27V Electrostatic discharge voltage (Human Body Model) according to JESD22-A114-B Electrostatic discharge voltage (Charge Device Model) according to ESD STM5.3.1 - 1999 Continuos reverse drain current1)3), each channel 1) defined by Ptot
--VLoaddump ----VESD
10 1 V 90 117 kV 2 kV 1
VESD IS
---
4
A
2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm (one layer, 70m thick) copper area for drain connection. PCB is vertical without blown air. 3) not subject to production test, specified by design 4) VLoaddump is setup without the DUT connected to the generator per ISO7637-1 and DIN40839
Datasheet
12
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Electrical Characteristics
4.2
Thermal Characteristics
Limit Values min. typ. max. 1.5 50 38 K/W Unit Test Condition
Parameter Symbol at Tj = -25 ... 125C, Vbb=15...30V, VCC= 3.0...5.5V, unless otherwise specified Thermal resistance junction - case Thermal resistance @ min. footprint Thermal resistance @ 6cm cooling area
1)
RthJC Rth(JA) Rth(JA)
-------
-------
1) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm (one layer, 70m thick) copper area for drain connection. PCB is vertical without blown air.
4.3
Load Switching Capabilities and Characteristics
Limit Values min. typ. max. Unit Test Condition
Parameter Symbol at Tj = -25 ... 125C, Vbb=15...30V, VCC= 3.0...5.5V, unless otherwise specified On-state resistance, IL = 0.5A, each channel Tj = 25C Tj = 125C two parallel channels, Tj = 25C:1) four parallel channels, Tj = 25C:1) Nominal load current Device on PCB 38K/W, Ta = 85C, Tj < 125C one channel:1) two parallel channels:1) four parallel channels:1) Turn-on time to 90% VOUT2) RL = 47, VDx = 0 to 5V Turn-off time to 10% VOUT1) RL = 47, VDx = 5 to 0V Slew rate on 10 to 30% VOUT RL = 47, Vbb = 15V Slew rate off 70 to 40% VOUT RL = 47, Vbb = 15V
1) not subject to production test, specified by design
RON
-----
150 270 75 38
200 320 100 50
m
IL(NOM)
0.7 1.1 2.2
A
ton toff dV/dton -dV/dtoff
---------
64 89 1 1
120 170 2 2
s
V/s
2) The turn-on and turn-off time includes the switching time of the high-side switch and the transmission time via the coreless transformer in normal operating mode. During a failure on the coreless transformer transmission turn-on or turn-off time can increase by up to 50s.
Datasheet
13
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Electrical Characteristics
4.4
Operating Parameters
Symbol Limit Values min. dVISO/dt HIM Vbb Vbb(under) Vbb(u_rst) Vbb(under) Ibb(uvlo) IGNDL IL(off) -25 100 11 7 typ. max. 25 35 10.5 11 kV/s DVISO = 500V A/m IEC61000-4-8 V Unit Test Condition
Parameter at Tj = -25 ... 125C, Vbb=15...30V, VCC= 3.0...5.5V, unless otherwise specified Common mode transient immunity1) Magnetic field immunity1) Voltage domain Vbb (Output interface) Operating voltage Undervoltage shutdown Undervoltage restart Undervoltage hysteresis Undervoltage current Operating current Leakage output current (included in Ibb(off)) VDx = low, each channel Voltage domain VCC Operating voltage (Input interface) Undervoltage shutdown Undervoltage restart Undervoltage hysteresis Undervoltage current Operating current
1) not subject to production test
----------3.0 2.5
------0.5 1 10 5
--2.5 14 30 mA mA A Vbb < 7V All Channels ON - no load
VCC VCC(under) VCC(u_rst) VCC(under) ICC(uvlo) ICC(on)
---------
------0.1 1 4.5
5.5 2.9 3 --2 6
V
mA mA
Vcc < 2.5V
Datasheet
14
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Electrical Characteristics
4.5
Output Protection Functions
Limit Values min. typ. max. A Unit Test Condition
Parameter1) Symbol at Tj = -25 ... 125C, Vbb=15...30V, VCC=3.0...5.5V, unless otherwise specified
Initial peak short circuit current limit, each channel: IL(SCp) Tj = -25C, Vbb = 30V, tm = 700s ----1.9 Tj = 25C --1.4 --Tj = 125C 0.7 ----two parallel channels:3) twice the current of one channel four parallel channels:3) four times the current of one channel Repetitive short circuit current limit Tj = Tjt (see timing diagrams) each channel: IL(SCr) two parallel channels:3) four parallel channels:3) Repetitive short circuit current limit3) Tj = Tjt (see timing diagrams) Output clamp (inductive load switch off) at VOUT = Vbb - VON(CL) Overvoltage protection Thermal overload trip temperature Thermal hysteresis
3) 2) 3)
--1.1 1.1 1.1
---
IL(SCr) VON(CL) Vbb(AZ) Tjt Tjt
--47 47 135
1.1 53
--60 V
----10
---
-------
C K
1) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuos repetitive operation. 2) Higher operating temperature at normal function for each channel available 3) not subject to production test, specified by design
4.6
Diagnostic Characteristics at pin DIAG
Limit Values min. typ. max. 5 100 mA VDIAGON < 0.25 x VCC A Unit Test Condition
Parameter Symbol at Tj = -25 ... 125C, Vbb=15...30V, VCC=3.0...5.5V, unless otherwise specified Common diagnostic sink current (overtemperature of any channel) Tj = 135C Common diagnostic source current Idiagsink Idiagsource
Datasheet
15
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Electrical Characteristics
4.7
Input Interface
Limit Values min. -0.3 0.7 x VCC typ. max. 0.3 x VCC VCC+ 0.3 mV 0.25 x V VCC VCC+ 0.3 A CL < 50pF, RL > 10k V Unit Test Condition
Parameter Symbol at Tj = -25 ... 125C, Vbb=15...30V, VCC= 3.0...5.5V, unless otherwise specified Input low state voltage (SI, DIS, CS, SCLK) Input high state voltage (SI, DIS, CS, SCLK) Input voltage hysteresis (SI, DIS, CS, SCLK) Output low state voltage (SO) Output high state voltage (SO) Input pull down current (SI , DIS) Input pull up current (CS, SCLK) Output disable time (transition DIS to logic low)1)2) Normal operation Turn-off time to 10% VOUT RL = 47 Output disable time (transition DIS to logic low)1)2)3) Disturbed operation Turn-off time to 10% VOUT RL = 47 VIL VIH VIHys VOL VOH IIdown -IIup tDIS
----100
-0.3 0.75 x VCC
----100 100
---
85
170
s
tDIS
---
---
230
1) The time includes the turn-on/off time of the high-side switch and the transmission time via the coreless transformer. 2) If Pin DIS is set to low the outputs are set to low; after DIS set to high a new write cycle is necessary to set the output again. 3) The parameter is not subject to production test - verified by design/characterization
Datasheet
16
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Electrical Characteristics
4.8
SPI Timing
Limit Values min. DC 50 5 10 10 6 6 typ. max. 20 MHz ns Unit Test Condition
Parameter Symbol at Tj = -25 ... 125C, Vbb=15...30V, VCC= 3.0...5.5V, unless otherwise specified Serial clock frequency Serial clock period (1/fclk) CS Setup time (falling edge of CS to falling edge of SCLK) CS Hold time (rising edge of SCLK to rising edge of CS) CS Disable time (CS high time between two accesses) Data setup time (required time SI to rising edge of SCLK) Data hold time (falling edge of SCLK to SI) SO Output valid time CL = 50pF SO Output disable time fSCLK tp(SLCK) tCSS tCSH tCSD tSU tHD tVALID
-----------------
------------20 20
--tSODIS
4.9
Reverse Voltage
Limit Values min. typ. max. V Unit Test Condition
Parameter Symbol at Tj = -25 ... 125C, Vbb=15...30V, VCC= 3.0...5.5V, unless otherwise specified Reverse voltage1)2) RGND = 0 RGND = 150 Diode forward on voltage IF = 1.25A, VDx = low, each channel
1) defined by Ptot 2) not subject to production test, specified by design
-Vbb
-----VON
-------
1 45 1.2
---
Datasheet
17
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Electrical Characteristics
4.10
Parameter
Isolation and Safety-Related Specification
Value 500 1250 2.6 2.6 0.01 Unit VAC V mm mm mm Conditions 1 - minute duration1) 5s acc. DIN EN60664-1 shortest distance through air. shortest distance path along body. Insulation distance through insulation
Rated dielectric isolation voltage VISO Short term temporary overvoltage Minimum external air gap (clearance) Minimum external tracking (creepage) Minimum Internal Gap
1) not subject to production test, verified by characterization; Production Test with 1100V, 100ms duration
Approvals: UL508, CSA C22.2 NO.14 Certificate Number: 20090514-E329661
4.11
Reliability
For Qualification Report please contact your local Infineon Technologies office!
Datasheet
18
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Electrical Characteristics
Datasheet
19
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Electrical Characteristics
Datasheet
20
Version 2.2, 2009-07-01
ISOFACETM ISO1H812G
Package Outlines
5
Package Outlines
3.5 MAX.
3.25 0.1
11 0.15 1)
PG-DSO-36
0 +0.1
1.1 0.1
0.02
2.8
0.25 +0.07 -
(Plastic Dual Small Outline Package)
B
0.65
15.74 0.1 (Heatslug) 36x 0.25 M A B C
1.3
6.3 (Mold)
14.2 0.3
0.1 C
Heatslug 0.95 0.15 0.25 B
0.25 +0.13
Bottom View
3.2 0.1 (Metal)
36
19
19
36
Index Marking
1 x 45
1
18
10
15.9 0.1 1) (Mold)
1)
A
13.7 -0.2 (Metal)
1
Heatslug
Does not include plastic or metal protrusion of 0.15 max. per side
gps09181_1
Figure 14
PG-DSO-36
Datasheet
21
Version 2.2, 2009-07-01
5.9 0.1 (Metal)
5 3
Total Quality Management
Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Wir werden Sie uberzeugen. Quality takes on an all encompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced.
www.infineon.com
Published by Infineon Technologies AG

▲Up To Search▲

Price & Availability of ISO1H812G

	To Download ISO1H812G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .