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| MYSON TECHNOLOGY FEATURES * Horizontal SYNC input up to 150 KHz. * On-chip PLL circuitry or external pixel clock input up to 150 MHz. * Software control for CRT/LCD applications. * Programmable R,G,B input level for timing measurement among HFLB, VFLB, RIN, GIN and BIN for auto sizing. * Full screen self-test pattern generator. * Programmable Hor. resolutions up to 1524 dots per line. * Full-screen display consists of 15 (rows) by 30 (columns) * Two font size 12x16 or 12x18 dot matrix per character. * True totally 544 mask ROM fonts including 512 standard fonts and 32 multi-color fonts. * Character button boxes with programmable box length. * Double character height and/or width control. * Programmable positioning for display screen center. * Character bordering, shadowing and blinking effect. * Character (per row) and window intensity control. * Row to row spacing control to avoid expansion distortion. * 4 programmable windows with multi-level operation. * Shadowing on windows with programmable shadow width/height/color. * Programmable adaptive approach to handle H, V sync collision automatically by hardware. * Software clears bit for full-screen erasing. * Fade-in/fade-out or blending-in/blending-out effects. * Compatible with SPI bus or I2C interface with slave address 7AH/7BH (slave address is mask option). * 16-pin or 20-pin PDIP/SOP package. MTV038 (Revision 1.1) GENERAL DESCRIPTION MTV038 is designed for CRT/LCD monitor applications to display built-in characters or fonts onto monitor screens. The display operation occurs by transferring data and control information from the micro-controller to RAM through a serial data interface. It can execute full-screen display automatically, as well as specific functions such as character background, bordering, shadowing, blinking, double height and width, font by font color control, character button boxes, frame positioning, frame size control by character height and row-to-row spacing, horizontal display resolution, full-screen erasing, fade-in/fade-out effect, windowing effect, shadowing on window and full-screen selftest pattern generator. MTV038 provides 544 fonts including 512 standard fonts and 32 multi-color fonts and 2 font sizes, 12x16 or 12x18 for more efficacious applications. The full OSD menu is formed by 15 rows x 30 columns, which can be positioned anywhere on the monitor screen by changing vertical or horizontal delay. The auto sizing video measurement module measure the timing relationship among HFLB, VFLB, and R, G, BIN with 12-bit resolution at the speed related to the OSD pixel clock. And the R, G, BIN input level can be programming by software. MCU can get the measurement data, active video, front porth and back porth, through I2C bus read/ write operation to keep the appropriate display size and center. On-Screen Display Controller for CRT/LCD Monitor BLOCK DIAGRAM SSB 8 DATA SCK DATA 8 VDD LUMAR LUMAG LUMAB BLINK 8 CRADDR SERIAL DATA INTERFACE 9 ROW, COL ACK CWS CHS DISPLAY & ROW CONTROL REGISTERS VSS SDA DATA ARWDB HDREN VDREN NROW 8 5 5 RCADDR 9 DADDR 9 FONTADDR 5 WINADDR 5 PWMADDR VDDA CHARACTER ROM LUMINANCE & BORDGER GENERATOR LUMA VSSA BORDER ADDRESS BUS ADMINISTRATOR LPN CWS VCLKS VFLB VSP CH 7 CHS VERTD 8 VERTICAL DISPLAY CONTROL HORIZONTAL DISPLAY CONTROL PHASE LOCK LOOP 5 LPN NROW VDREN DATA 8 8 VERTD 8 HORD 7 CH WINDOWS & FRAME CONTROL WR WG WB FBKGC BLANK BSEN SHADOW OSDENB HSP VSP HFLB HSP RP VCO RIN GIN BIN HORD 8 ARWDB HDREN LUMAR LUMAG LUMAB BLINK VCLKX ROUT GOUT BOUT FBKG HTONE VCLKX COLOUR ENCODER AUTO SIZING MEASUREMENT PRB 8 DATA POWER ON RESET This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product. Revision 1.1 -1- 2001/8/21 MYSON TECHNOLOGY 1.0 PIN CONNECTION MTV038 (Revision 1.1) VSSA VCO/XIN RP/NC VDDA HFLB SSB SDA SCK 1 2 16 15 VSS ROUT GOUT BOUT FBKG INT VFLB VDD VSSA VCO/XIN RP/NC VDDA HFLB SSB SDA SCK RIN GIN 1 2 3 20 19 18 VSS ROUT GOUT BOUT FBKG INT VFLB VDD NC BIN 3 4 5 6 7 8 MTV038N-xx 14 13 12 11 10 9 4 5 6 7 8 9 10 MTV038N20-xx 17 16 15 14 13 12 11 2.0 PIN DESCRIPTIONS Name VSSA I/O Pin No. 16 20 Descriptions Analog ground. This ground pin is used to internal analog circuitry. Voltage Control Oscillator (bit LCD= 0). This pin is used to control the internal oscillator frequency by DC voltage input from external low pass filter. Pixel Clock Input (bit LCD= 1). This is a clock input pin. MTV038 can be driven by an external pixel clock source for all the logics inside. The frequency of XIN must be the integral time of pin HFLB. Bias Resistor (bit LCD= 0). The bias resistor is used to regulate the appropriate bias current for internal oscillator to resonate at specific dot frequency. No connection (bit LCD= 1). Analog power supply. Positive 5 V DC supply for internal analog circuitry. And a 0.1uF decoupling capacitor should be connected across to VDDA and VSSA. Horizontal input. This pin is used to input the horizontal synchronizing signal. It is a leading edge triggered and has an internal pull-up resistor. Serial interface enable. It is used to enable the serial data and is also used to select the operation of I2C or SPI bus. If this pin is left floating, I2C bus is enabled, otherwise the SPI bus is enabled. Serial data input. The external data transfer through this pin to internal display registers and control registers. It has an internal pull-up resistor. -22001/8/21 1 1 VCO/XIN I/O 2 2 RP/NC I/O 3 3 VDDA - 4 4 HFLB I 5 5 SSB I 6 6 SDA I 7 7 Revision 1.1 MYSON TECHNOLOGY Name SCK RIN GIN BIN NC VDD I/O I I I I Pin No. 16 20 MTV038 (Revision 1.1) Descriptions 8 9 8 9 10 11 12 13 Serial clock input. The clock-input pin is used to synchronize the data transfer. It has an internal pull-up resistor. Red video input. It is used for auto sizing measurement and this signal is came from video pre-amp red output. Green video input. It is used for auto sizing measurement and this signal is came from video pre-amp green output. Blue video input. It is used for auto sizing measurement and this signal is came from video pre-amp blue output. No connection. Digital power supply. Positive 5 V DC supply for internal digital circuitry and a 0.1uF decoupling capacitor should be connected across to VDD and VSS. Vertical input. This pin is used to input the vertical synchronizing signal. It is leading triggered and has an internal pull-up resistor. Intensity color output. 16-color selection is achievable by combining this intensity pin with R/G/B output pins. Fast Blanking output. It is used to cut off external R, G, B signals of VGA while this chip is displaying characters or windows. Blue color output. It is a blue color video signal output. Green color output. It is a green color video signal output. Red color output. It is a red color video signal output. Digital ground. This ground pin is used to internal digital circuitry. VFLB I 10 14 INT O 11 15 FBKG BOUT GOUT ROUT VSS O O O O - 12 13 14 15 16 16 17 18 19 20 3.0 FUNCTIONAL DESCRIPTIONS 3.1 SERIAL DATA INTERFACE The serial data interface receives data transmitted from an external controller. And there are 2 types of bus can be accessed through the serial data interface, one is SPI bus and other is I2C bus. 3.1.1 SPI bus While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission should be starting from pulling SSB to "low" level, enabling MTV038 to receiving mode, and retain "low" level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1. Revision 1.1 -3- 2001/8/21 MYSON TECHNOLOGY SSB SCK SDA MSB MTV038 (Revision 1.1) LSB First byte Last byte FIGURE 1. Data Transmission Protocol (SPI) There are three transmission formats shown as below: Format (a) R - C - D -> R - C - D -> R - C - D ..... Format (b) R - C - D -> C - D -> C - D -> C - D ..... Format (c) R - C - D -> D -> D -> D -> D -> D ..... Where R=Row address, C=Column address, D=Display data 3.1.2 I2C bus I2C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting from writing the slave address 7AH(write mode), or 7BH(read mode) to MTV038. The protocol is shown in Figure 2. And the auto sizing video measurement data (total 12 bytes) are read only registers and the others are write only registers. SCK SDA START B7 B6 First byte B0 ACK B7 Secondbyte B0 Last byte ACK STOP FIGURE 2. Data Transmission Protocol (I2C) There are three transmission formats for I2C write mode shown as below: Format (a) S - R - C - D -> R - C - D -> R - C - D ..... Format (b) S - R - C - D -> C - D -> C - D -> C - D ..... Format (c) S - R - C - D -> D -> D -> D -> D -> D ..... Where S=Slave address, R=Row address, C=Column address, D=Display data And there is one transmission formats for I2C read mode shown as below: Format (a) S -> D -> D -> D -> D -> D -> D -> D -> D -> D -> D -> D -> D -> D -> D -> dummy D ..... Where S=Slave address, D=Measurement data In the I2C read mode, 14 bytes of auto sizing video measurement data will be outputed directly from byte 0 to byte 9 and continues with dummy data until stop condition occurred when R/W bit is set to 1. Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with a different row address and column address. Format (b) is recommended for updating data that has the same row address but a different column address. Massive data updating or full screen data change should use format (c) to increase transmission efficiency. The row and column address will be incremented automatically when Revision 1.1 -42001/8/21 MYSON TECHNOLOGY Address Row Address Bytes of Display Reg. Columnab Columnc Data Row Attribute Bytes of Display Reg. Columnab Columnc Data b7 1 0 0 D7 1 0 0 D7 b6 0 0 1 D6 0 0 1 D6 b5 0 D8 D8 D5 1 x x D5 b4 R4 C4 C4 D4 R4 C4 C4 D4 b3 R3 C3 C3 D3 R3 C3 C3 D3 b2 R2 C2 C2 D2 R2 C2 C2 D2 b1 R1 C1 C1 D1 R1 C1 C1 D1 MTV038 (Revision 1.1) b0 R0 C0 C0 D0 R0 C0 C0 D0 Format a,b,c a,b c a,b,c a,b,c a,b c a,b,c the format (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy data. TABLE 1. The Configuration of Transmission Formats There are 2 types of data which should be accessed through the serial data interface, one is ADDRESS bytes of display registers, and the other is ATTRIBUTE bytes of display registers, the protocols are same for all except the bit5 of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and column addresses when transferring data from external controller. The bit6 of column address is used to differentiate the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". And at address bytes, bit5 of column address is the MSB (bit8) and data bytes are the 8 LSB (bit7~bit0) of display fonts address to save half MCU memory for true 512 fonts display. So each one of the 512 fonts can be displayed at the same time (see Table 1). And for format (c), since D8 is filled while program column address of address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until program column address of address bytes again. The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format (a) and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is configured as the state diagram shown in Figure 3. 0, X Initiate Input = b7, b6 1, X format (a) 1, X format (c) ROW 0, 0 format (b) 0, 0 0, 1 COL c X, X 0, 1 COL ab X, X 1, X X, X DA c DA ab FIGURE 3. Transmission State Diagram Revision 1.1 -5- 2001/8/21 MYSON TECHNOLOGY 3.2 Address bus administrator MTV038 (Revision 1.1) The administrator manages bus address arbitration of internal registers or user fonts RAM during external data write in. The external data write through serial data interface to registers must be synchronized by internal display timing. In addition, the administrator also provides automatic increment to address bus when external write using format (c). 3.3 Vertical display control The vertical display control can generates different vertical display sizes for most display standards in current monitors. The vertical display size is calculated with the information of double character height bit(CHS), vertical display height control register(CH6-CH0).The algorithm of repeating character line display are shown as Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines. The vertical display center for full screen display could be figured out according to the information of vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB, is calculated with the following equation: Vertical delay time = ( VERTD * 4 + 1 ) * H TABLE 2. Repeat Line Weight of Character CH6 - CH0 CH6,CH5=11 CH6,CH5=10 CH6,CH5=0x CH4=1 CH3=1 CH2=1 CH1=1 CH0=1 Repeat Line Weight +18*3 +18*2 +18 +16 +8 +4 +2 +1 Where H = one horizontal line display time TABLE 3. Repeat Line Number of Character Repeat Line # Repeat Line Weight 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +1 v +2 v v +4 v v v v +8 v v v v v v v v +16 v v v v v v v v v v v v v v v v +17 v v v v v v v v v v v v v v v v v +18 v v v v v v v v v v v v v v v v v v Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the character would not be repeated. 3.4 Horizontal display control The horizontal display control is used to generate control timing for horizontal display based on double character width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display charRevision 1.1 -62001/8/21 MYSON TECHNOLOGY For CRT: MTV038 (Revision 1.1) acters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calculated with the following equation, Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width Where P = One pixel display time = One horizontal line display time / (HORR*12) Horizontal delay time = ( HORD * 6 + 49) * P Where P = 1 XIN pixel display time For LCD: 3.5 Phase lock loop (PLL) On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution register (HORR). The frequency of VCLK is determined by the following equation: VCLK Freq = HFLB Freq * HORR * 12 The VCLK frequency ranges from 6MHz to 150MHz selected by (VCO1, VCO0). In addition, when HFLB input is not present to MTV038, the PLL will generate a specific system clock, approximately 2.5MHz, by a built-in oscillator to ensure data integrity. 3.6 Display & Row control registers The internal RAM contains display and row control registers. The display registers have 450 locations which are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4 and Figure 5. Each display register has its corresponding character address on ADDRESS byte, its corresponding background color, button box format, 1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at column 30 for row 0 to row 14 of attribute bytes, it is used to select background color or button box and set character size to each respective row. If double width character is chosen, only even column characters could be displayed on screen and the odd column characters will be hidden. ROW # 01 0 1 ROW ATTRIBUTE CRTL REG COLUMN # 28 29 30 31 R E S E R V E D CHARACTER ADDRESS BYTES of DISPLAY REGISTERS 13 14 FIGURE 4. Address Bytes of Display Registers Memory Map Revision 1.1 -7- 2001/8/21 MYSON TECHNOLOGY ROW # 01 0 1 COLUMN # 28 29 MTV038 (Revision 1.1) 30 31 CHARACTER ATTRIBUTE BYTES of DISPLAY REGISTERS RESERVED 13 14 COLUMN# 12 22 FRAME CRTL REG ROW 15 0 WINDOW1 ~ WINDOW4 11 23 RESERVED 31 ROW 16 COLUMN# 0 1 2 45 31 WINDOW SHADOW COLOR FRAME CRTL REG RESERVED FIGURE 5. Attribute Bytes of Display Registers Memory Map ADDRESS BYTES: Address registers, b8 b7 MSB b6 b5 b4 CRADDR b3 b2 b1 b0 LSB CRADDR - Define ROM character address from address 0 to 511. Row Control Registers, (Row 0 - 14) b7 b6 b5 COLN 30 - b4 BOX b3 b2 b1 CHS b0 CWS BGINT FGINT BOX - Select BGR, BGG, BGB or B2, B1, B0 of attributes bytes to the respective row. = 0 -> Background color bits BGR, BGG, BGB are selected. = 1 -> Button box bits B2, B1, B0 are selected. BGINT - The displayed character/symbol background color intensity control to the respective row. Setting this bit to 0 means low intensity in this row. 16 character background color is achievable by this bit. FGINT - The displayed character/symbol foreground color intensity control to the respective row. Setting this bit to 0 means low intensity in this row. 16 character foreground color is achievable by this bit. CHS - Define double height character to the respective row. CWS - Define double width character to the respective row. Revision 1.1 -8- 2001/8/21 MYSON TECHNOLOGY ATTRIBUTE BYTES: b7 b6 BGR/B2 b5 BGG/B1 b4 BGB/B0 b3 BLINK b2 R b1 G b0 B MTV038 (Revision 1.1) BGR, BGG, BGB - These three bits define the color of the background for its relative address character. If all three bits are clear, no background will be shown(transparent). Therefore, a total of 7 background colors can be selected. B2, B1, B0 - Select the character button boxes format of its relative address character. = 0, 0, 0 -> Button box is disabled. = 1, 0, 0 -> Start of depressed button box which is more than 1 character button box. = 1, 0, 1 -> Start of depressed button box which is only 1 character button box. = 1, 1, 0 -> Start of raised button box which is more than 1 character button box. = 1, 1, 1 -> Start of raised button box which is only 1 character button box. = 0, 1, 0 -> Middle of button box. = 0, 0, 1 -> End of button box. BLINK - Enable blinking effect while this bit is set to " 1 ". And the blinking is alternate per 32 vertical frames. R, G, B - These three bits are used to specify its relative address character color. 3.7 Character button box generator There are 4 character button box generators to generate 4 different types of button boxes including depressed button box with only 1 character, depressed button box with more than 1 character, raised button box with only 1 character, and raised button box with more than 1 character. The button boxes format is defined by (B2, B1, B0) bits of attribute bytes. And these bits are described as below: 1).(1, x, x) means the start of character button box, and then B1, B0 mean button boxes format. 2).(0, 1, 0) means the middle of character button box. 3).(0, 0, 1) means the end of character button box. The length of button box is also software control by (B2, B1, B0) bits. For example, if there is 1 raised button box which length is equal to 6 characters, these (B2, B1, B0) bits will be (1, 1, 0), (0, 1, 0), (0, 1, 0), (0, 1, 0), (0, 1, 0), (0, 0, 1). And if there is 1 depressed button box of which the length is equal to 4 characters, these (B2, B1, B0) bits will be (1, 0, 0), (0, 1, 0), (0, 1, 0), (0, 0, 1). That is, (0, 1, 0) command number define the button box length. And only one byte, the attribute byte of button box start character, should be modified when we want to change button box type to raised or depressed button. This is very easy and useful for software programming. Revision 1.1 -9- 2001/8/21 MYSON TECHNOLOGY MTV038 (Revision 1.1) B2~B0 = 1, 1, 1 1, 1, 0 0, 0, 1 1, 1, 0 0, 1, 0 0, 1, 0 0, 0, 1 Raised Button Boxes B2~B0 = 1, 0, 1 1, 0, 0 0, 0, 1 1, 0, 0 0, 1, 0 0, 1, 0 0, 0, 1 Depressed Button Boxes FIGURE 6. Character Button Boxes 3.8 Character ROM MTV038 character ROM contains 544 built-in characters and symbols including 512 standard fonts and 32 multi-color fonts. The 512 standard fonts are located from address 0 to 511. And the 32 multi-color fonts are located from address 480 to 511 while CFONT bits is set to 1. Each character and symbol consists of 12x18 dots matrix. 3.9 Multi-Color Font The color fonts comprises three different R, G, B fonts. When the code of color font is accessed, the separate R/G/B dot pattern is output to corresponding R/G/B output. See Figure 7 for the sample displayed color font. Note: No black color can defined in color font, black window underline the color font can make the dots become black in color. Revision 1.1 -10- 2001/8/21 MYSON TECHNOLOGY B G R MTV038 (Revision 1.1) Magenta Green Blue Cyan FIGURE 7. Example of Multi-Color Font TABLE 4. The Multi-Color Font Color Selection Background Color Blue Green Cyan Red Magenta Yellow White R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 3.10 Luminance & border generator There are 3 shift registers included in the design which can shift out of luminance and border dots to color encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character will be enveloped with blackedge on four sides. For shadowing effect, the character is enveloped with blackedge for right and bottom sides only. 3.11 Window and frame control The display frame position is completely controlled by the contents of VERTD and HORD. The window size and position control are specified in column 0 to 11 on row 15 of memory map, as shown in Figure 5. Window 1 has the highest priority, and window 4 is the least, when two windows are overlapping. More detailed information is described as follows: 1. Window control registers, ROW 15 b7 b6 b5 Column ROW START ADDR 0,3,6,OR 9 MSB b7 MSB b4 b3 b2 b1 ROW END ADDR b0 LSB LSB MSB b3 LSB b2 WEN b1 WINT Column 1,4,7,OR 10 b6 b5 b4 COL START ADDR b0 WSHD Revision 1.1 -11- 2001/8/21 MYSON TECHNOLOGY Column 2,5,8,OR 11 b7 MSB b6 b5 b4 COL END ADDR b3 LSB b2 R MTV038 (Revision 1.1) b1 G b0 B START(END) ADDR - These addresses are used to specify the window size. It should be noted that when the start address is greater than the end address, the window will be disabled. WEN - Enable the relative background window display. WINT - Specify the color intensity of the relative background window. Setting this bit to 0 means low intensity in this background window. WSHD - Enable shadowing on the relative window. R, G, B - Specify the color of the relative background window. 2. Frame control registers, ROW 15 b7 b6 Column 12 MSB b5 b4 b3 VERTD b2 b1 b0 LSB VERTD - Specify the starting position for vertical display. The total steps are 256, and the increment of each step is 4 Horizontal display lines. The initial value is 4 after power up. b7 Column 13 MSB b6 b5 b4 b3 HORD b2 b1 b0 LSB HORD - Define the starting position for horizontal display. The total steps are 256, and the increment of each step is 6 dots. The initial value is 15 after power up. Column 14 b7 b6 CH6 b5 CH5 b4 CH4 b3 CH3 b2 CH2 b1 CH1 b0 CH0 CH6-CH0 - Define the character vertical height, the height is programmable from 18 to 71 lines. The character vertical height is at least 18 lines if the contents of CH6-CH0 is less than 18. For example, when the contents is " 2 ", the character vertical height is regarded as equal to 20 lines. And if the contents of CH4-CH0 is greater than or equal to 18, it will be regarded as equal to 17. See Table 2 and Table 3 for detail description of this operation. b7 b6 b5 b4 b3 HORR b2 b1 b0 LSB Column 15 MSB (This byte is used only for CRT monitor application.) HORR - Specify the resolution of a horizontal display line, and the increment of each step is 12 dots. That is, the number of pixels per H line equal to HORR*12. It is recommended that HORR should be greater than or equal to 36 and smaller than 150M / (Hfreq*12). The initial value is 40 after power up. Revision 1.1 -12- 2001/8/21 MYSON TECHNOLOGY Column 16 b7 b6 b5 b4 MSB b3 b2 b1 RSPACE b0 MTV038 (Revision 1.1) LSB RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will be appended below each display row, and the maximum space is 31 lines. The initial value is 0 after power up. Column 17 b7 OSDEN b6 BSEN b5 SHADOW b4 FBEN b3 BLEND b2 WENCLR b1 RAMCLR b0 FBKGC OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up. BSEN - Enable the bordering and shadowing effect. SHADOW - Bordering and shadowing effect select bit. Activate the shadowing effect if this bit is set, otherwise the bordering is chosen. FBEN - Enable the fade-in/fade-out and blending-in/blending-out effect when OSD is turned on from off state or vice versa. BLEND - Fade-in/fade-out and blending-in/blending-out effect select bit. Activate the blendinf-in/blending-out function if this bit is set, otherwise the fade-in/fade-out function is chosen. These function roughly takes about 0.5 second to fully display the whole menu or to disappear completely. WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after power up. RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is set to "1". The initial value is 0 after power up. FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs high during the displaying of characters or windows, otherwise, it outputs high only during the displaying of character. B7 b6 b5 b4 b3 b2 TRIC FSS SELVCL/DWE HSP VSP (SELVCL, VCO1, VCO0 bits are used only for CRT monitor application.) (DWE bit is used only for LCD monitor application.) Column 18 b1 b0 VCO1/- VCO0/- TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is, while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are in high impedance state. The initial value is 0 after power up. FSS - Font size selection. = 1 -> 12x18 font size selected. = 0 -> 12x16 font size selected. SELVCL - Enable auto detection for horizontal and vertical syncs input edge distortion to avoid unstable Vsync leading mismatch with Hsync signal while the bit is set to "1". The initial value is 0 after power up. Revision 1.1 -13- 2001/8/21 MYSON TECHNOLOGY MTV038 (Revision 1.1) Fonts designed to be 12x18 display Output display if FSS=0; first and last lines omitted FIGURE 8. 12x18 and 12x16 Fonts DWE - Enable double width. When the bit is set to 1, the display of OSD menu can change to half resolution for double character width, and then the number of pixels of each line should be even. The initial value is 0 after power up. HSP = 1 -> Accept positive polarity Hsync input. = 0 -> Accept negative polarity Hsync input. = 1 -> Accept positive polarity Vsync input. = 0 -> Accept negative polarity Vsync input. VSP - VCO1, VCO0 - Select the appropriate curve partitions of VCO frequency to voltage based on HFLB input and horizontal resolution register (HORR). And there are different curve partitions based on different application resister value on pin 3 (pin RP) as below: (i)RRP = 5.6K ohm: = (0, 0) -> 6MHz < Pixel rate < 24MHz = (0, 1) -> 24MHz < Pixel rate < 48MHz = (1, 0) -> 48MHz < Pixel rate < 96MHz = (1, 1) -> 96MHz < Pixel rate < 128MHz (ii)2.2K ohm < RRP < 3.3K ohm: = (0, 0) -> 6MHz < Pixel rate < 28MHz = (0, 1) -> 28MHz < Pixel rate < 56MHz = (1, 0) -> 56MHz < Pixel rate < 112MHz = (1, 1) -> 112MHz < Pixel rate < 150MHz Where Pixel rate = VCLK Freq = HFLB Freq * HORR * 12 The initial value is (0, 0) after power up. Notes : 1. That is, if HORR is specified and RP resister = 3.3K ohm, then (VCO1, VCO0) = (0, 0) if 6000/(HORR * 12) < HFLB Freq (KHz) < 28000/(HORR * 12) = (0, 1) if 28000/(HORR * 12) < HFLB Freq (KHZ) < 56000/(HORR * 12) = (1, 0) if 56000/(HORR * 12) < HFLB Freq (KHZ) < 112000/(HORR * 12) = (1, 1) if 112000/(HORR * 12) < HFLB Freq (KHZ) < 150000/(HORR * 12) 2. It is necessary to wait for the PLL to become stable while (i) the HORR register is being changed; (ii) the (VCO1, VCO0) bits is changed; (iii) the horizontal signal (HFLB) is changed. 3. When PLL is unstable, don't write data in any address except Column 15,17,18 of Row 15. If data is written in any other address, a malfunction may occur. Column 19 B7 - b6 - b5 - b4 - b3 - b2 CSR b1 CSG b0 CSB Revision 1.1 -14- 2001/8/21 MYSON TECHNOLOGY MTV038 (Revision 1.1) CSR, CSG, CSB - Define the color of bordering or shadowing on characters. The initial value is (0, 0, 0) after power up. B7 FSW b6 b5 b4 b3 b2 FSR b1 FSG b0 FSB Column 20 FSW - Enable full screen self-test pattern and force the FBKG pin output to high to disable video RGB while this bit is set to 1. The color of the self-test pattern is determined by (FSR, FSG, FSB) bits. FSR, FSG, FSB - Define the color of full screen self-test pattern. B7 WW41 b6 WW40 b5 WW31 b4 WW30 b3 WW21 b2 WW20 b1 WW11 b0 WW10 Column 21 WW41, WW40 - Determines the shadow width of the window 4 when WSHD bit of the window 4 is enabled. Please refer to the Table 5 for more details. TABLE 5. Shadow Width Setting (WW41, WW40) Shadow Width (unit in Pixel) (0, 0) 2 (0, 1) 4 (1, 0) 6 (1, 1) 8 WW31, WW30 - Determines the shadow width of the window 3 when WSHD bit of the window 3 is enabled. WW21, WW20 - Determines the shadow width of the window 2 when WSHD bit of the window 2 is enabled. WW11, WW10 - Determines the shadow width of the window 1 when WSHD bit of the window 1 is enabled. B7 WH41 b6 WH40 b5 WH31 b4 WH30 b3 WH21 b2 WH20 b1 WH11 b0 WH10 Column 22 WH41, WH40 - Determines the shadow height of the window 4 when WSHD bit of the window 4 is enabled. Please refer to the Table 6 for more details. TABLE 6. Shadow Height Setting (WH41, WH40) Shadow Height (unit in Line) (0, 0) 2 (0, 1) 4 (1, 0) 6 (1, 1) 8 WH31, WH30 - Determines the shadow height of the window 3 when WSHD bit of the window 3 is enabled. WH21, WH20 - Determines the shadow height of the window 2 when WSHD bit of the window 2 is enabled. WH11, WH10 - Determines the shadow height of the window 1 when WSHD bit of the window 1 is enabled. 3.12 Color encoder The encoder generates the video output to ROUT, GOUT and BOUT by integrating window color, border blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs. Revision 1.1 -15- 2001/8/21 MYSON TECHNOLOGY MTV038 (Revision 1.1) M Pixels N Horizontal lines WINDOW AREA Note: M and N are defined by the registers of row 15, column 21 and 22. N Horizontal lines Bordering Shadowing M Pixels FIGURE 9. Character Bordering and Shadowing and Shadowing on Window Column 23 ~ column 31 : Reserved. Notes : The register located at column 31 of row 15 is reserved for the testing. Don' program this byte t anytime in normal operation. ROW 16 Column 0 B7 b6 R1 b5 G1 b4 B1 b3 b2 R2 b1 G2 b0 B2 R1, G1, B1 - Define the shadow color of window 1. The initial value is (0, 0, 0) after power up. R2, G2, B2 - Define the shadow color of window 2. The initial value is (0, 0, 0) after power up. B7 b6 R3 b5 G3 b4 B3 b3 b2 R4 b1 G4 b0 B4 Column 1 R3, G3, B3 - Define the shadow color of window 3. The initial value is (0, 0, 0) after power up. R4, G4, B4 - Define the shadow color of window 4. The initial value is (0, 0, 0) after power up. B7 b6 b5 b4 (This byte is used only for LCD monitor application.) Column 2 b3 b2 D2 b1 D1 b0 D0 D2-D0 - These 3 bits define the propagation delay of R, G, B, FBKG and INT output pins to XIN pin. Please refer to Figure 13 and Table 7. The initial value is (0, 0, 0) after power up. TABLE 7. Output timing to Pixel Clock Symbol (D2, D1, D0) 0 1 2 3 4 5 6 7 Min. 2 3 4 5 6 7 8 9 Typ. -16Max. 4 5 6 7 8 9 10 11 Unit ns ns ns ns ns ns ns ns 2001/8/21 tpd Revision 1.1 MYSON TECHNOLOGY Column 3 B7 b6 b5 b4 - MTV038 (Revision 1.1) b3 b2 b1 b0 CFONT3 CFONT2 CFONT1 CFONT0 CFONT0 - Enable 1st 8 multi-color fonts. = 0 -> Character addresses 480 to 487 are connected to standard ROM fonts. = 1 -> Character addresses 480 to 487 are connected to multi-color ROM fonts. CFONT1 - Enable 2nd 8 multi-color fonts. = 0 -> Character addresses 488 to 495 are connected to standard ROM fonts. = 1 -> Character addresses 488 to 495 are connected to multi-color ROM fonts. CFONT2 - Enable 3rd 8 multi-color fonts. = 0 -> Character addresses 496 to 503 are connected to standard ROM fonts. = 1 -> Character addresses 496 to 503 are connected to multi-color ROM fonts. CFONT3 - Enable 4th 8 multi-color fonts. = 0 -> Character addresses 504 to 511 are connected to standard ROM fonts. = 1 -> Character addresses 504 to 511 are connected to multi-color ROM fonts. The initial value is (0, 0, 0, 0) after power up. B7 LCD b6 b5 ID5 b4 ID4 b3 ID3 b2 ID2 b1 ID1 b0 ID0 Column 4 LCD - OSD application selection. = 1 -> LCD monitor application selected. The 2nd and 3rd pins will be XIN, NC. = 0 -> CRT monitor application selected. The 2nd and 3rd pins will be VCO, RP. After this bit is changed, the whole chip circuit will be reset to default value except this byte. So this bit also can work as software reset bit. The initial value is 0 after power up. ID5-ID0 - LCD bit identify bits. LCD bit can be updated to 1 only when ID5-ID0 = (0, 1, 0, 1, 0, 1). And LCD bit can be updated to 0 only when ID5-ID0 = (1, 0, 1, 0, 1, 0). B7 VMEN b6 b5 b4 b3 b2 T2 b1 T1 b0 T0 Column 5 VMEN - Auto sizing video measurement enable bit. All video measurements commence at the following VFLB pulse after the VMEN bit is set, complete the measurement after one vertical frame. This bit will be self-clear after the video measurement of one vertical frame is completed. T2-T0 - These 3 bits define the trigger level of RIN, GIN, BIN auto-sizing input pins. The initial value is (0, 0, 0) after power up. = 0, 0, 0 -> 2.00 +/- 0.1 V = 0, 0, 1 -> 2.15 +/- 0.1 V = 0, 1, 0 -> 2.30 +/- 0.1 V = 0, 1, 1 -> 2.45 +/- 0.1 V = 1, 0, 0 -> 2.60 +/- 0.1 V = 1, 0, 1 -> 2.75 +/- 0.1 V = 1, 1, 0 -> 2.90 +/- 0.1 V = 1, 1, 1 -> 3.00 +/- 0.1 V Revision 1.1 -17- 2001/8/21 MYSON TECHNOLOGY Column 6 ~ column 31 : Reserved. MTV038 (Revision 1.1) 3.13 Auto sizing video measurement The auto sizing video measurement module monitors horizontal and vertical flyback pulses and their relationship to video content. In horizontal measurement, the HFLB is the reference signal. As PLL clock is the certain multiple of HFLB frequency, the measurements for HFLB and R,G,BIN are all based on the PLL clock. In vertical measurement, the VFLB pulse is reference signal and the HFLB is the counting clock. HFLB and VFLB have an exact timing relationship to the active raster display on the monitor. When the HFLB, VFLB sync signals and the R,G,BIN video signals (taken from the output of pre-amplifier) are compared, it will feedback to MCU a lot of information about the display size and centering. If back porch is much smaller than front porch, then the video information is too much to the left (or up in the vertical direction). If both front porth and back porth percentage of the total display period is too large, then the display size is too small. MCU can change the display size and center until front and back porches are equal and the porches to active video ratio is correct. Please note that due to the deviation of analog circuits, building a ratio table of correct porches to video for different operating frequencies is needed. And it is recommend that video contrast is set to maximum first for the correct capture of video information. All these measurements commence at the following VFLB pulse after enabling VMEN bit, complete the measurement after one vertical frame, and then FINISH bit will be set to 1 by hardware, so after FINISH bit is set to 1 or minimum delay 2 vertical frame time after enabling VMEN bit is needed to read out the measurement data. The horizontal measurement for R,G,BIN will store the minimum start location and the maximum ending location in one vertical frame into registers. All of the input signals for timing measurement are polarity programmable, so the different phase measurement can be obtained. Note: (HSP, VSP) bits should be filled in the opposite value of the polarity of HFLB and VFLB input when auto sizing function is work. Auto sizing video measurement data bytes : read only registers Byte 0 B7 FINISH b6 b5 b4 b3 MSB FINISH : = 1 -> The auto sizing video measurement is finished after enabling VMEN bit. = 0 -> The auto sizing video measurement is not finished. b2 b1 HSTART b0 b3 ~ b0 : The most significant 4 bits of HSTART which represents the distance between the first active edge of R,G,BIN input and reference HFLB trailing edge. See Figure 10. B7 Byte 1 b6 b5 b4 b3 HSTART b2 b1 b0 LSB b7 ~ b0 : The least significant 8 bits of HSTART which represents the distance between the first active edge of R,G,BIN input and reference HFLB trailing edge. See Figure 10. B7 b6 b5 b4 b3 MSB b3 ~ b0 : The most significant 4 bits of HEND which represents the distance between the last active edge of R,G,BIN input and reference HFLB trailing edge. See Figure 10. b2 HEND b1 b0 Byte 2 Revision 1.1 -18- 2001/8/21 MYSON TECHNOLOGY B7 Byte 3 b6 b5 b4 HEND b3 b2 MTV038 (Revision 1.1) b1 b0 LSB b7 ~ b0 : The least significant 8 bits of HEND which represents the distance between the last active edge of R,G,BIN input and reference HFLB trailing edge. See Figure 10. B7 b6 b5 b4 b3 MSB b3 ~ b0 : The most significant 4 bits of HACTIVE which represents the HFLB dot distance between 2 reference HFLB sync pulse. See Figure 10. B7 Byte 5 b6 b5 b4 b3 HACTIVE b2 b1 b0 LSB b7 ~ b0 : The least significant 8 bits of HACTIVE which represents the HFLB dot distance between 2 reference HFLB sync pulse. See Figure 10. B7 b6 b5 b4 b3 MSB b3 ~ b0 : The most significant 4 bits of HPULSE which represents the HFLB pulse dot distance. See Figure 10. B7 Byte 7 b6 b5 b4 b3 HPULSE b2 b1 b0 LSB b7 ~ b0 : The least significant 8 bits of HPULSE which represents the HFLB pulse dot distance. See Figure 10. B7 b6 b5 b4 b3 MSB b3 ~ b0 : The most significant 4 bits of VSTART which represents the H line distance between the first active line of R,G,BIN input and reference VFLB leading edge. See Figure 10. B7 Byte 9 b6 b5 b4 b3 VSTART b2 b1 b0 LSB b7 ~ b0 : The least significant 8 bits of VSTART which represents the H line distance between the first active line of R,G,BIN input and reference VFLB leading edge. See Figure 10. b2 b1 VSTART b0 b2 b1 HPULSE b0 b2 b1 HACTIVE b0 Byte 4 Byte 6 Byte 8 Revision 1.1 -19- 2001/8/21 MYSON TECHNOLOGY Byte 10 B7 b6 b5 b4 b3 MSB b2 VEND MTV038 (Revision 1.1) b1 b0 b3 ~ b0 : The most significant 4 bits of VEND which represents the H line distance between the last active line of R,G,BIN input and reference VFLB leading edge. See Figure 10. B7 Byte 11 b6 b5 b4 VEND LSB b7 ~ b0 : The least significant 8 bits of VEND which represents the H line distance between the last active line of R,G,BIN input and reference VFLB leading edge. See Figure 10. B7 b6 b5 b4 OVER b3 MSB OVER = 1 -> The line number counter is overflow. = 0 -> Not overflow. b2 b1 VACTIVE b0 b3 b2 b1 b0 Byte 12 b3 ~ b0 : The most significant 4 bits of VACTIVE which represents the total H line count between two consecutive VFLB pulses. See Figure 10. B7 Byte 13 b6 b5 b4 b3 VACTIVE b2 b1 b0 LSB b7 ~ b0 : The least significant 8 bits of VACTIVE which represents the total H line count between two consecutive VFLB pulses. See Figure 10. Revision 1.1 -20- 2001/8/21 MYSON TECHNOLOGY HPULSE HACTIVE MTV038 (Revision 1.1) HFLB R,G,BIN HSTART HEND VACTIVE VFLB R,G,BIN VSTART VEND FIGURE 10. Timing Diagram of Auto Sizing Video Measurement 4.0 ABSOLUTE MAXIMUM RATINGS DC Supply Voltage(VDD,VDDA) Voltage with respect to Ground Storage Temperature Ambient Operating Temperature -0.3 to +7 V -0.3 to VDD+0.3 V -65 to +150 oC 0 to +70 oC 5.0 OPERATING CONDITIONS DC Supply Voltage(VDD,VDDA) Operating Temperature +4.75 to +5.25 V 0 to +70 oC Revision 1.1 -21- 2001/8/21 MYSON TECHNOLOGY Symbol VIH Parameter Input High Voltage (pin hflb, vflb, sda, sck, ssb) Input High Voltage (pin rin, gin, bin) Input Low Voltage (pin hflb, vflb, sda, sck) Input Low Voltage (pin ssb) Input Low Voltage (pin rin, gin, bin) Output High Voltage Output Low Voltage Conditions (Notes) IOH > -5 mA IOL < 5mA MTV038 (Revision 1.1) Min. 0.7 * VDD TBD VSS-0.3 VSS-0.3 VSS-0.3 VDD-0.8 5 Max. VDD+0.3 VDD+0.3 0.3 * VDD 0.2 * VDD TBD 0.5 9 Units V V V V V V V V 6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions) VIL VOH VOL VODH VODL ICC ISB Open Drain Output High Volt- (For all OD pins, and pulled age up by external 5 to 9V power supply) 5 mA > IDOL Open Drain Output Low Voltage ( For all OD pins ) Pixel rate=150MHz Operating Current Iload = 0uA Standby Current Vin = VDD, Iload = 0uA - 0.5 25 12 V mA mA 7.0 SWITCHING CHARACTERISTIC (Under Operating Conditions) Symbol fHFLB fVFLB Tr Tf tBCSU tBCH tDCSU tDCH tSCKH tSCKL tSU:STA tHD:STA tSU:STO tHD:STO Parameter HFLB input frequency VFLB input frequency Output rise time Output fall time SSB to SCK set up time SSB to SCK hold time SDA to SCK set up time SDA to SCK hold time SCK high time SCK low time START condition setup time START condition hold time STOP condition setup time STOP condition hold time Min. 15 200 100 200 100 500 500 500 500 500 500 Typ. 3 3 Max. 150 200 Units KHz Hz ns ns ns ns ns ns ns ns ns ns ns ns Revision 1.1 -22- 2001/8/21 MYSON TECHNOLOGY 8.0 TIMING DIAGRAMS tSCKH MTV038 (Revision 1.1) SCK tSCKL SSB tBCSU tBCH SDA tDCSU tDCH FIGURE 11. Data Interface Timing(SPI) tSCKH SCK tSU:STA tSCKL tHD:STO SDA tHD:STA tDCSU tDCH tSU:STO FIGURE 12. Data Interface Timing(I2C) PlXin R,G,B, FBKG INT tpd tpd:: Propagation Delay and INT outputs to R,G,B, FBKG HFLB t SETUP t HOLD FIGURE 13. Output and HFLB Timing to Pixel Clock Revision 1.1 -23- 2001/8/21 MYSON TECHNOLOGY 9.0 PACKAGE DIMENSION 9.1 16 Pin PDIP 300mil MTV038 (Revision 1.1) 312 +/-12 55 +/-20 R40 250 +/-4 R10Max (4X ) 90 +/-20 350 +/-20 75 +/-20 90 +/-20 750 +/-10 15 Max 7 Typ 65 +/-4 55 +/-4 310Max 10 35 +/-5 115 Min 15 Min 100Ty p 18 +/2Typ 60 +/5Typ 9.2 20 Pin PDIP 300mil 312 +/-12 55 +/-20 R40 250 +/-4 R10Max (4X ) 90 +/-20 350 +/-20 75 +/-20 90 +/-20 1020 +/-10 15 Max 7 Typ 65 +/-4 55 +/-4 310Max 10 35 +/-5 115 Min 15 Min 100Typ 18 +/-2Typ 60 +/-5Typ Revision 1.1 -24- 2001/8/21 MYSON TECHNOLOGY 9.3 16 Pin SOP 300mil MTV038 (Revision 1.1) 0.406 +/-0.013 0.295 +/-0.004 0.406 +/-0.008 (4x) 0.015x45o 7o(4x) 0.091 0.098 +/-0.006 0.016 +/-0.004 0.050 0.028 +0.022 /-0.013 9.4 20 Pin SOP 300 mil 0.502+/-0.006inch 20 11 0.406+/-0.012inch 0.295+/-0.004inch 0.020x45 1 0.016typ. 10 0.050typ. Revision 1.1 -25- 2001/8/21 |
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