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SY69753L
3.3V, 125Mbps, 155Mbps Clock and Data Recovery Use lower-power SY69753AL for new designs
General Description
The SY69753L is a complete Clock Recovery and Data Retiming integrated circuit for OC-3/STS-3 applications at 155Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY69753L also includes a link fault detection circuit. Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.
Features
* 3.3V power supply * SONET/SDH/ATM compatible * Clock and data recovery for 125Mbps/155Mbps NRZ data stream * Two on-chip PLLs: one for clock generation and another for clock recovery * Selectable reference frequencies * Differential PECL high-speed serial I/O * Line receiver input: no external buffering needed * Link fault indication * 100k ECL compatible I/O * Industrial temperature range (-40C to +85C) * Complies with Bellcore, ITU/CCITT and ANSI specifications for OC-3 applications * Available in 32-pin EPAD-TQFP
Applications
* Ethernet media converter(m) * SONET/SDH/ATM OC-3 * Proprietary architecture at 135Mbps to 180Mbps
Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
December 2007
M9999-120307-F hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY69753L
Ordering Information(1)
Part Number SY69753LHI SY69753LHITR SY69753LHG
(3) (2)
Package Type H32-1 H32-1 H32-1
(2, 3)
Operating Range Industrial Industrial Industrial Industrial
Package Marking SY69753LHI SY69753LHI SY69753LHG with Pb-Free bar-line indicator SY69753LHG with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb NiPdAu Pb-Free NiPdAu Pb-Free
SY69753LHGTR
Notes: 1. 2. 3.
H32-1
Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. Tape and Reel. Recommended for new designs.
Pin Configuration
32-Pin EPAD-TQFP (H32-1)
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Micrel, Inc.
SY69753L
Pin Description
Inputs
Pin Number 2 3 5 Pin Name RDINP RDINN REFCLK Type Differential PECL TTL Input Pin Name Serial Data Input: These built-in line receiver inputs are connected to the differential receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. Reference Clock: This input is used as the reference for the internal frequency synthesizer and the "training" frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN inputs. Carrier Detect: This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH, the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to look onto the clock frequency generated from REFCLK. Divider Select: These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the "Reference Frequency Selection" table. Clock Select: This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. Pin Name Link Fault Indicator: This output indicates the status of the input data stream RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (1000ppm) and will be alternating if not. LFIN is an asynchronous output. Receive Data Output: These ECL 100K outputs represent the recovered data from the input data stream (RDIN). This recovered data is specified against the rising edge of RCLK. Clock Output: These ECL 100K outputs represent the recovered clock used to sample the recovered data (RDOUT). Clock Output: These ECL 100K outputs represent either the recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL = LOW). Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL. Clock Recovery PLL Loop Filter: External loop filter pins for the receiver PLL.
26
CD
PECL Input
32 25 16
DIVSEL1 DIVSEL2 CLKSEL
TTL Input
TTL Input
Outputs
Pin Number 31 Pin Name LFIN Type TTL Output
23 24 20 21 18 17 9 10 14 15 Pin Number 27, 28 29, 30 19, 22 12, 13 1, 4, 6, 7, 8 11
RDOUTN RDOUTP RCLKN RCLKP TCLKP TCLKN PLLSP PLLSN PLLRN PLLRP Pin Name VCC VCCA VCCO GND NC GNDA
Differential PECL Differential PECL Differential PECL
Power and Ground
Type Pin Name Power Supply.
(1) (1)
Analog Power Supply Voltage. Output Supply Voltage. Ground. No connect. Analog Ground.
(1)
Note: 1. VCC, VCCA, VCCO must be the same value.
December 2007
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Micrel, Inc.
SY69753L
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ......................................-0.5V to +5.0V Input Voltage (VIN) ..............................................-0.5V to VCC Output Current (IOUT) Continuous ...........................................................50mA Surge..................................................................100mA Lead Temperature (soldering, 20sec.) ..................... +260C Storage Temperature (Ts) .......................... -65C to +150C
Operating Ratings(2)
Input Voltage (VCC) .............................. +3.15V to +3.45V Ambient Temperature (TA) ..................... -40C to +85C Junction Temperature (TJ)....................................+125C (3) Package Thermal Resistance EPAD-TQFP (JA) Still-air....................................................... 28C/W 500lfpm..................................................... 20C/W EPAD-TQFP (JC) ............................................. 4C/W
DC Electrical Characteristics
TA = -40C to +85C, unless otherwise noted.
Symbol VCC ICC Parameter Power Supply Voltage Power Supply Current Condition Min 3.15 Typ 3.3 170 Max 3.45 230 Units V mA
PECL 100K DC Electrical Characteristics
VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to +85C, unless otherwise noted.
Symbol VIH VIL VOH VOL IIL Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input LOW Current 50 to VCC-2V 50 to VCC-2V VIN = VIL (Min) Condition Min VCC-1.165 VCC-1.810 VCC-1.075 VCC-1.860 0.5 Typ Max VCC-0.880 VCC-1.475 VCC-0.830 VCC-1.570 Units V V V V A
TTL DC Electrical Characteristics
VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to +85C, unless otherwise noted.
Symbol VIH VIL VOH VOL IIH IIL IOS
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Numbers valid with proper thermal design of PCB and exposed pad soldered to island on PCB. Refer to Figure on page 13.
Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input LOW Voltage Output Short Circuit Current
Condition
Min 2.0
Typ
Max VCC 0.8
Units V V V V A A A mA
IOH = -0.4mA IOL = 4mA VIN = 2.7V, VCC = Max. VIN = VCC, VCC = Max. VIN = 0.5V, VCC = Max. VOUT = 0V, (max., 1 sec.)
2.0 0.5 -125 +100 -300 -15 -100
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SY69753L
AC Electrical Characteristics
VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to +85C, unless otherwise noted.
Symbol fVCO fVCO tACQ tCPWH tCPWL tDV tDH tir tODC tRSKEW tr, tf Parameter VCO Center Frequency VCO Center Frequency Tolerance Acquisition Lock Time REFCLK Pulse Width HIGH REFCLK Pulse Width LOW Data Valid Data Hold REFCLK Input Rise Time Output Duty Cycle (RCLK/TCLK) Recovered Clock Skew ECL Output Rise/Fall Time (20% to 80%) 50 to VCC-2 45 -200 100 Condition fREFCLK x Byte Rate Nominal 50 to VCC-2V 50 to VCC-2V VIN = VIL (Min) 4 4 1/(2xfRCLK) -200 1/(2xfRCLK) -200 0.5 2 55 +200 400 Min 800 5 15 Typ Max 1250 Units MHz % s ns ns ps ps ns % of UI ps ps
Timing Waveforms
December 2007
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SY69753L
Functional Block
Functional Description
Clock Recovery Clock Recovery, as shown in the block diagram, generates a clock that is at the same frequency as the incoming data bit rate at the Serial Data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. Output pulses from the detector indicate the required direction of phase correction. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability, without incoming data, is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the Frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the PLL will be declared out of lock, and the PLL will lock to the reference clock. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. This transfer function yields a 30s data stream of continuous 1's or 0's for random incoming NRZ data. December 2007 6
The total loop dynamic of the clock recovery PLL provides jitter tolerance which is better than the specified tolerance in GR-253-CORE. Lock Detect The SY69753L contains a link fault indication circuit, which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, then the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by more than approximately 1000ppm, the PLL will be declared out of lock. The lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within approximately 1000ppm, the PLL will be declared in lock and the lock detect output will go active. Performance The SY69753L PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used with differential inputs and outputs.
M9999-120307-F hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc. Input Jitter Tolerance Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1dB optical/electrical power penalty. SONET input jitter tolerance requirement condition is the input jitter amplitude that causes an equivalent of 1dB power penalty.
Jitter Transfer
SY69753L
Jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 2. Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed .01 U.I. rms when a serial data input with no jitter is presented to the serial data inputs.
OC/STS-N Level 3
f0 (Hz) 10
f1 (Hz) 30
f2 (Hz) 300
f3 (Hz) 6.5
ft (Hz) 65
OC/STS-N Level 3
fc (kHz) 130
P (dB) 0.1
Figure 1. Input Jitter Tolerance
Figure 2. Jitter Transfer
December 2007
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Micrel, Inc.
SY69753L
Loop Filter Components(1)
R1 = 350 C1 = 1.5F (X7R Dielectric)
Note: 1. Suggested values. Values may vary for different applications.
R2 = 680 C2 = 1.0F (X7R Dielectric)
Reference Frequency Selection
DIVSEL1 0 0 1 1 DIVSEL2 0 1 0 1 fRCLK/fREFCLK 8 10 16 20
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SY69753L
Application Example
Note: C3, C4 are optional.
C1 = 1.5F C2 = 1.0F R1 = 350 R2 = 680 R3 through R10 = 5k R12 = 12k R13 = 130
December 2007
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SY69753L
Bill of Materials
Item C1 C2 C3, C4 C5 C6 C7, C8, C9, C10 C19 C11, C13 C15, C17 C20 C12, C14 C16, C18 C21 D1 D2 J1, J2, J3, J4, J5, J6, J7, J8, J9, J10, J11, J12 L1, L2, L3 Q1 R1 R2 R3, R4, R5, R6, R7, R8, R9, R10 R11 R12 R13 SW1
Notes: 1. 2. 3. 4. 5. Panasonic: www.panasonic.com. Johnson Components: www.johnson-components.com. Murata: www.murata.com. NTE: www.nte.com. CTS: www.cts.com.
Part Number ECU-V1H104KBW ECU-V1H104KBW ECU-V1H104KBW ECS-T1ED226R ECU-V1H104KBW ECS-T1EC685R ECJ-3YB1E105K ECU-V1H104KBW ECU-V1H104KBW ECU-V1H104KBW ECU-V1H103KBW ECU-V1H103KBW ECU-V1H103KBW 1N4148 P300-ND/P301-ND 142-0701-851
Manufacturer Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic
(1)
Description 1.5F Ceramic Capacitor, Size 1206, X7R Dielectric, Loop Filter, Critical 1.0F Ceramic Capacitor, Size 1206, X7R Dielectric, Loop Filter, Critical 0.47F Ceramic Capacitor, Size 1206, X7R Dielectric, Loop Filter, Optional 22F Tantalum Electrolytic Capacitor, Size D 0.1F Ceramic Capacitor, Size 1206, X7R Dielectric Power Supply Decoupling 6.8F Tantalum Electrolytic Capacitor, Size C 0.1F Ceramic Capacitor, Size 1206, X7R Dielectric VEEA Decoupling 0.1F Ceramic Capacitor, Size 1206, X7R Dielectric VCCO/VCC Decoupling 0.1F Ceramic Capacitor, Size 1206, X7R Dielectric VCCA/VEEA Decoupling 0.1F Ceramic Capacitor, Size 1206, X7R Dielectric VEEA Decoupling 0.01F Ceramic Capacitor, Size 1206, X7R Dielectric VCCO/VCC Decoupling 0.01F Ceramic Capacitor, Size 1206, X7R Dielectric VCCA/VEEA Decoupling 0.01F Ceramic Capacitor, Size 1206, X7R Dielectric VEEA Decoupling Diode T-1 3/4, Red LED Gold Plated, Jack, SMA, PCB Mount
Qty. 1 1 2 1 1 4 1 1 1 1 1 1 1 1 1 12
(1)
(1)
(1) (1)
(1) (1)
(1)
(1)
(1)
(1)
(1)
(1)
Panasonic
(1)
Johnson (2) Components Murata NTE
(3)
BLM21A102F NTE123A
Ferrite Beads, Power Noise Suppression 2N2222A Buffer/Driver Transistor, NPN 350 Resistor, 2%, Size 1206, Loop Filter Component, Critical 680 Resistor, 2%, Size 1206, Loop Filter Component, Critical 5k Pull-up Resistor, 2%, Size 1206 1k Pull-down Resistor, 2%, Size 1206 12k Resistor, 2%, Size 1206 130 Pull-up Resistor, 2%, Size 1206
3 1 1 1 8 1 1 1 1
(4)
206-7
CTS
(5)
SPST, Gold Finish, Sealed Dip Switch
December 2007
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SY69753L
6. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals. Higher speed operation may require use of fundamental-tone (third-overtone typically has more jitter) crystal-based oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter. All unused outputs require termination. To conserve power, unused PECL outputs can be terminated with a 1k resistor to VEE.
Appendix A
Layout and General Suggestions 1. 2. 3. 4. Establish controlled impedance stripline, microstrip, or coplanar construction techniques. Signal paths should have approximately the same width as the device pads. All differential paths are critical timing paths, where skew should be matched to within 10ps. Signal trace impedance should not vary more than 5%. If in doubt, perform TDR analysis of all high-speed signal traces. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to reduce stray capacitance. Be careful of crosstalk coupling into the filter network.
7.
8.
5.
December 2007
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SY69753L
Package Information
32-Pin EPAD-TQFP (H32-1)
December 2007
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Micrel, Inc.
SY69753L
PCB Thermal Consideration for 32-Pin EPAD-TQFP Package
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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