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Datasheet
AS5050
Low Power 10-Bit Magnetic Rotary Encoder
1 General Description
The AS5050 is a single-chip magnetic rotary encoder IC with low voltage and low power features. It includes 4 integrated Hall elements, a high resolution ADC and a smart power management controller. The angle position, alarm bits and magnetic field information are transmitted over a standard 3-wire or 4-wire SPI interface to the host processor. The AS5050 is available in a small QFN 16-pin 4x4x0.85mm package and specified over an operating temperature of -40C to 80C.
2 Key Features
10-bit resolution Standard SPI interface, 3 or 4 wire 3.0 to 3.6 V core voltage, 1.8 to 3.6 V peripheral supply voltage Automatic wakeup over SPI interface Interrupt output for conversion complete indication Low power mode: - < 8mA (avg) @ 620s readout interval - < 5mA (avg) @ 1ms readout interval - < 500A (avg) @ 10ms readout interval - < 53A (avg) @ 100ms readout interval Small size 16-pin QFN (4x4x0.85mm)
3 Applications
The device is ideal for Servo motor control, Input device for battery operated portable devices, and Robotics.
Figure 1. AS5050 Block Diagram
AS5050
ADC Hall Sensors Power Management SPI Interface Cordic
EN_INT/ INT/
VDDp
VDD
VSS
Wire MOSI MISO SCK mode
SS/
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AS5050
Datasheet - C o n t e n t s
Contents
1 General Description .................................................................................................................................................................. 2 Key Features............................................................................................................................................................................. 3 Applications............................................................................................................................................................................... 4 Pin Assignments .......................................................................................................................................................................
4.1 Pin Descriptions....................................................................................................................................................................................
1 1 1 3
3
5 Absolute Maximum Ratings ...................................................................................................................................................... 6 Electrical Characteristics...........................................................................................................................................................
6.1 Operating Conditions............................................................................................................................................................................ 6.2 System Parameters .............................................................................................................................................................................. 6.3 DC/AC Characteristics..........................................................................................................................................................................
4 5
5 5 5
7 Detailed Description..................................................................................................................................................................
7.1 Operating Modes .................................................................................................................................................................................. 7.1.1 7.1.2 7.1.3 7.1.4 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Power Supply Filter...................................................................................................................................................................... Reading an Angle ........................................................................................................................................................................ Low Power Mode ......................................................................................................................................................................... Interrupt Chaining ........................................................................................................................................................................
6
6 6 7 7 7 8
7.2 SPI Communication..............................................................................................................................................................................
Command Package ..................................................................................................................................................................... 8 Read Package (Value Read from AS5050) ................................................................................................................................. 8 Write Data Package (Value Written to AS5050) .......................................................................................................................... 9 Register Block.............................................................................................................................................................................. 9 SPI Interface Commands........................................................................................................................................................... 10
8 Application Information ...........................................................................................................................................................
8.1 SPI Interface.......................................................................................................................................................................................
14
14
8.1.1 SPI Interface Signals (4-Wire Mode, Wire_mode = 1)............................................................................................................... 14 8.1.2 SPI Timing ................................................................................................................................................................................. 15 8.1.3 SPI Connection to the Host C ................................................................................................................................................. 16 8.2 Placement of the Magnet.................................................................................................................................................................... 17
9 Package Drawings and Markings ........................................................................................................................................... 10 Ordering Information.............................................................................................................................................................
19 21
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Datasheet - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
Wire_mode
Test
16
VSS
INT/
15
14
13 12 11
MOSI MISO SCK SS/
1 2
VDD VDDp
Epad
3 4 5 6 7 8 10 En_INT/ 9
Test_coil
tb0
tb1
tb3
tb2
4.1 Pin Descriptions
Table 1. Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Epad Pin Name MOSI MISO SCK SS/ tb0 tb1 tb2 tb3 Test coil En_INT/ VDDp VDD VSS Wire_mode INT/ Test Digital I/O Supply Supply Digital input Test pin, connect to VSS Enable / disable Interrupt Peripheral power supply, 1.8V ~ VDD Analog and digital power supply, 3.0 ~ 3.6 V Supply ground 0: 3-wire mode 1: 4-wire mode Test pin, leave unconnected Center pad not connected Analog I/O Test pin, leave unconnected Pin Type Digital input SPI bus data input Digital output, tri-state buffer SPI bus data output Digital input Schmitt trigger SPI Clock Schmitt trigger Digital input SPI Slave Select, active LOW Description
Digital output, tri-state buffer Interrupt output. Active LOW, when conversion is finished Digital I/O -
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Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Symbol Electrical Parameters VDD VDDp Vin Iscr ESD Theta_JA Electrostatic Discharge Electrostatic discharge Package thermal resistance 1 33.5 kV C/W Norm: MIL 883 E method 3015 Velocity=0, Multi Layer PCB; Jedec Standard Testboard DC supply voltage Peripheral supply voltage Input pin voltage Input current (latchup immunity) -0.3 -0.3 -0.3 -100 5.0 VDD+0.3 5.0 100 V V V mA Norm: Jedec 78 Value of these process dependent parameters are according to Process Parameter document, current version Parameter Min Max Units Comments
Continuous Power Dissipation Pt Tstrg Total power dissipation Storage temperature -55 36 125 mW C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020 "Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". The lead finish for Pb-free leaded packages is matte tin (100% Sn). Represents a maximum floor life time of 168h Temperature Ranges and Storage Conditions
Tbody
Package body temperature
260
C
Humidity non-condensing MSL Moisture Sensitive Level
5 3
85
%
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Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
6.1 Operating Conditions
Table 3. Operating Conditions Parameter DC supply voltage Peripheral supply voltage Input pin voltage Ambient operating temperature External component Power supply filter, pin VDD (refer to Power Supply Filter on page 6) Ceramic capacitor, pin VDDp to VSS 1. VDDp must not exceed VDD (protection diode between VDDp and VDD)
1
Conditions VDD VDDp Vin
Min 3.0 1.8 -0.3 -40 2.2 15 100
Typ
Max 3.6 VDD VDDp +0.3 80 4.7 33
Units V V V C F nF
6.2 System Parameters
Table 4. System Parameters Symbol I_10 I_100 I_max Parameter Operating current Operating current Operating current Readout rate Power down current Rd BZ Lateral displacement range Magnetic field strength Serial interface Resolution; angle INL IC package 1. Without the time for the SPI interface Best-fit line - over supply, displacement and temperature - but without quantization -1.41 QFN 4x4x0.85 Conditions Average current @ 10 ms readout rate Maximum readout rate Time between READ ANGLE command and INTERRUPT Power down current Centre of the magnet to the centre of the die 30 10 1.41 320
1
Min
Typ
Max 0.5 53 8.5 430 3 0.5 80
Units mA A mA s A mm mT bit degree
Average current @ 100 ms readout rate
SPI mode 0 (CPOL = 0 / CPHA =0)
6.3 DC/AC Characteristics
Digital pads: MISO, MOSI, SCK, SS/, EN_INT/, INT/, Wire_mode Table 5. DC/AC Characteristics Symbol VIH VIL VIL ILEAK VOH VOL CL Parameter High level input voltage Low level input voltage Low level input voltage Input leakage current High level output voltage Low level output voltage Capacitive load Revision 1.12 VDDp - 0.5 VSS + 0.4 35 VDDp > 2.7V VDDp < 2.7V Conditions Min 0.7 * VDDp 0.3 * VDDp 0.25 * VDDp 1 Typ Max Units V V V A V V pF 5 - 22
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AS5050
Datasheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
User Programming.
The AS5050 does not require any programming by the user. A dedicated on-chip zero position programming is not implemented. If a zero position programming is required, it is recommended to store the zero position offset in the host controller.
7.1 Operating Modes
Typical Application.
The AS5050 requires only a few external components in order to operate immediately when connected to the host microcontroller. Only 6 wires are needed for a simple application using a single power supply: two wires for power and four wires for the SPI communication. A seventh connection can be added in order to send an interrupt to the host CPU to inform that a new valid angle can be read. Figure 3. Typical Application Using SPI 4-Wire Mode and INT/ Output
47
15 ohm
VDD
DC 3. 0 ~ 3.6V
AS5050
ADC Hall Sensors Power Management
VSS
VDD
Supply: peripherals
Cordic
INT/
Interrupt
EN_INT/
DC 1.8 ~3.6V
SPI Interface
VDDp
100n
C
VDDp
Test_coil VDDp
Wire mode
MOSI
MISO
SCK
SS/
SPI Interface
Upon power-up, the AS5050 performs a full power-up sequence including one angle measurement. The completion of this cycle is indicated at the INT/ output pin and the angle value is stored in an internal register. Once this output is set, the AS5050 suspends to sleep mode.
7.1.1
Power Supply Filter
Due to the sequential internal sampling of the Hall sensors, fluctuations on the analog power supply (pin#12: VDD) may cause additional jitter of the measured angle. This jitter can be avoided by providing a stable VDD supply. The easiest way to achieve that is to add a RC filter: 15 + 4.7F in the power supply line as shown in Figure 3. Alternatively, a filter: 33 + 2.2F may be used. However with this configuration, the minimum supply voltage is 3.15V.
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Datasheet - D e t a i l e d D e s c r i p t i o n
7.1.2
Reading an Angle
The external microcontroller can respond to the INT request by reading the angle value from the AS5050 over the SPI interface. Once the angle value is read, the INT output is cleared again. Sending a "read angle" command by the SPI interface also automatically powers up the chip and starts another angle measurement. As soon ad the microcontroller has completed reading of the angle value, the INT output is cleared and a new result is stored in the angle register. The completion of the angle measurement is again indicated by setting the INT output and a corresponding flag in the status register.
Reducing the Angle Jitter. Due to the measurement principle of the chip, only a single angle measurement is performed in very short time
(~600s) after each power-up sequence. As soon as the measurement of one angle is completed, the chip suspends to power-down state. An on-chip filtering of the angle value by digital averaging is not implemented, as this would require more than one angle measurement and consequently, a longer power- up time which is not desired in low-power applications. The angle jitter can be reduced by averaging of several angle samples in the external microcontroller. For example, an averaging of 4 samples reduces the jitter by 6dB (50%).
7.1.3
Low Power Mode
After completing the readout of an angle value, the device is in very low power condition. The AS5050 remains in sleep mode until it receives another angle reading request over the SPI interface. The average power consumption therefore depends on the interval, at which the external controller reads an angle over the SPI Interface. The timing ratio between active and sleep phase: (EQ 1)
I avg =
Where: ton = Minimum on-time for power-up and angle measurement
ton I on + toff I off ton + toff
600s 8mA avg. 3A
toff = Pause interval between measurements, determined by the polling rate of the external microcontroller Ion = Current consumption in active mode Ioff = Current consumption in sleep mode Examples: 3000 measurements per second (continuous mode) 1000 measurements per second 100 measurements per second 10 measurements per second I = 8mA Iavg = 5mA Iavg = 500A Iavg = 53A
Note: Even in low power mode, the power supply must be capable of supporting the active current at least for the time Ton, until the AS5050 is suspended to sleep mode.
7.1.4
Interrupt Chaining
Every chip contains a configurable gate to combine its own internally generated interrupt signal with a signal applied externally over the XENINTpin. The INT-mode register is preset via an OTP register can be overwritten by the SPI interface.
Case A.
Device A is set to mode 0 Device B is set to mode 0 The micro controller recognizes an interrupt if both devices signalize that the computation is finished.
Case B.
Device A is set to mode 0 Device B is set to mode 1 The micro controller recognizes an interrupt if one of the two devices signalize that the computation is finished.
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AS5050
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 4. Interrupt Chaining
XENINT
=1
XINT 0
MUX
XENINT
=1
XINT 0 1
MUX
XINT
&
1 x_interrupt
& INT mode
x_interrupt
INT mode
otp
otp
AS5050 (Device A)
AS5050 (Device B)
Micro controller
7.2 SPI Communication
The transmitted data consists of 14-bit data, an Error-Flag and a Parity bit. When writing data to the chip, the Error-Flag is not applicable. The Parity is generated from the upper 15-bit and forms an even parity over the whole frame. The Error-Flag indicates that a failure occurred in a previous transmission.
7.2.1
Command Package
Every command sent to the AS5050 is represented with the following layout. Table 6. Command Package Bit MSB RWn Bit RWn Address PAR Description Indicates read or write command 14-bit address code Parity bit (EVEN) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB PAR Address <13:0>
7.2.2
Read Package (Value Read from AS5050)
The read frame always contains two alarm bits, the error and parity flags and the addressed data of the previous read command. Table 7. Read Package Bit MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 EF LSB PAR Data <13:0> Bit Data EF PAR Description 14-bit addressed data Error flag indicating a transmission error in a previous host transmission Parity bit (EVEN)
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Datasheet - D e t a i l e d D e s c r i p t i o n
7.2.3
Write Data Package (Value Written to AS5050)
The write frame is compatible to the read frame and contains two additional bits, the don't care and parity flag. If the previous command was a write command a second package has to be transmitted. Table 8. Write Package Bit MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Don't care LSB PAR Data <13:0> Bit Data PAR Description 14-bit data to write to former selected address Parity bit (EVEN)
7.2.4
Register Block
Register Bit Mode Reset Value Bit Description The POR cell is deactivated when the value 0x5A is written to this register (30A reduction of current consumption) Refer to SOFTWARE RESET Command on page 12 Refer to CLEAR ERROR FLAG Command on page 11 Refer to NOP Command on page 13 Automatic gain control: low values = strong magnetic field high values = weak magnetic field Measured angular value, 10-bit Alarm bit indicating a too low magnetic field, active HIGH HIGH
1
Table 9. Register Block Power ON Reset (POR) Register - [0x3F22] POR_OFF 8 R/W 0x00 <7:0>
Software Reset Register - [0x3C00] software_reset clr_error_flag NOP 14 14 14 W R w 0x0 0x0 0x0 <13:0> <13:0> <13:0> Clear Error Flag Register - [0x3380] No Operation Register - [0x0000] Automatic Gain Control (AGC) Register - [0x03FF8] AGC Angular Data - [0x3FFF] Angle Value Alarm LO Alarm HI break_offset_loop interrupt_mode 10 1 1 1 1 R R R R/W R/W 0x000 0 0 0 0 <9:0> <12> <13> <1> <0> 6 R/W 0x20 <5:0>
Alarm bit indicating a too high magnetic field, active
1
Breaks the offset compensation loop to use the offset registers in a static mode Interrupt gate mode 0 = mode 0 1 = mode1
1. Both bits High: Alarm LO = Alarm Hi = 1 indicate a major system error (DAC overflow, CORDIC overflow or Hall current error).
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Datasheet - D e t a i l e d D e s c r i p t i o n
7.2.5
SPI Interface Commands
READ Command. For a single READ command two transmission sequences are necessary. The first package written to the AS5050 contains the READ command (MSB high) and the address the chip has to access, the second package transmitted to the AS5050 device can be any command the chip has to process next. The content of the desired register is available in the MISO register of the master device at the end of the second transmission cycle.
Figure 5. READ Command
T COM
MSB LSB READ MSB Next command LSB
MOSI
MISO
MSB
Response - 1 LSB MSB
Response on READ command LSB
Transmission N
Transmission N + 1
WRITE Command. A single WRITE command takes two transmission cycles. With a NOP command after the WRITE command you can verify the sent data with three transmission cycles because the data will be send back during the NOP command.
Figure 6. WRITE Command
TCOM
MSB LSB WRITE command MSB DATA LSB MSB Next command LSB
MOSI
MISO
MSB
Response -1 LSB MSB
Old register content LSB MSB
New register content LSB
Transmission N
Transmission N + 1
Transmission N + 2
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Datasheet - D e t a i l e d D e s c r i p t i o n
CLEAR ERROR FLAG Command. The CLEAR ERROR FLAG command is implemented as READ command. This command clears the
ERROR FLAG which is contained in every READ frame. The READ data are 0x0000, which indicates a successful clear command. Figure 7. CLEAR ERROR FLAG Command
TCOM
MSB LSB CLEAR ERROR FLAG MSB Next command LSB
MOSI
MISO
MSB
Response-1 LSB MSB
0x 0000 LSB
Transmission N
Transmission N + 1
The package necessary to perform a CLEAR ERROR FLAG is built up as follows. Table 10. CLEAR ERROR FLAG Command Bit MSB 1 14 1 13 1 12 0 11 0 10 1 9 1 8 1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 LSB PAR PAR
CLEAR ERROR FLAG command Possible conditions which force the ERROR FLAG to be set: Wrong parity Wrong command Wrong number of clocks (no full transmission cycle or too many clocks)
Note: If the error flag is set to high because of a communication problem the flag remains set until it will be cleared by an external command.
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Datasheet - D e t a i l e d D e s c r i p t i o n
SOFTWARE RESET Command. The SOFTWARE RESET command is implemented as WRITE command. The bit `RES SPI' of the DATA
package indicates if the SPI registers should be reset as well. The soft reset resets the digital part (`RES SPI' is set to one) as well as the PPTRIM. A new PPTRIM auto-load is initiated and the reset values stored in the PPTRIM are loaded into the configuration registers. The command following the SOFTWARE RESET command can be any of the commands specified in this chapter. After the data package is sent, the soft reset is generated. The fuses of the PPTRIM are loaded into the registers and a new conversion cycle will be started. If the device is in sleep mode the oscillator will be started first. Figure 8. SOFTWARE RESET Command
TCOM
MSB LSB SOFTWARE RESET command MSB DATA LSB MSB Next command LSB
MOSI
MISO
MSB
Response -1 LSB MSB
0x 0000 LSB MSB
0x 0000 LSB
Transmission N
Transmission N + 1
Transmission N + 2
In order to invoke a software reset on the AS5050 the following bit pattern has to be sent. Table 11. SOFTWARE RESET Command Bit MSB 0 14 1 13 1 12 1 11 1 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 LSB PAR PAR
SOFTWARE RESET command Table 12. Data Package Bit MSB 14 13 12 11 10 9 Don't care Bit RES SPI PAR Description If set to one, SPI registers are reset as well Parity bit (EVEN)
1
8
7
6
5
4
3
2
1
LSB PAR
RES SPI Don't care
1. After a power on reset, the OTP will be read and hence OTP related registers are changed independent on the RES SPI flag.
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AS5050
Datasheet - D e t a i l e d D e s c r i p t i o n
NOP Command. The NOP command represents a dummy write to the AS5050.
Figure 9. NOP Command
TCOM
MSB LSB NOP MSB NOP LSB MSB Next command LSB
MOSI
MISO
MSB
Response -1 LSB MSB
0x0000 LSB MSB
0x0000 LSB
Transmission N
Transmission N + 1
Transmission N + 2
The NOP command frame looks like follows. Table 13. NOP Command Bit MSB 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 LSB
NOP command (0x0000) The chip's response on this command is 0x0000 - if no error happens.
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AS5050
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8 Application Information
The benefits of the AS5050 device are as follows: Complete system-on-chip Low power consumption Low operating voltage Easy to use SPI interface
8.1 SPI Interface
The 16-bit SPI Interface enables read / write access to the register blocks and is compatible to a standard micro controller interface. The SPI module is active as soon as /SS pin is pulled low. The AS5050 then reads the digital value on the MOSI (master out slave in) input with every falling edge of SCK and writes on its MISO (master in slave out) output with the rising edge. After 16 clock cycles /SS has to be set back to a high status in order to reset some parts of the interface core. The SPI Interface can be set into two different modes - 3-wire mode or 4-wire mode. Note: The wire mode selection is read during the POWER-UP state and can be changed with a power on reset or a software reset command. The SPI Interface can be set into two different modes: 3-wire mode or 4-wire mode. Table 14. Wire Mode Selection Wire Mode Selection (pad 14) wire_mode = LO wire_mode = HI 3-wire mode 4-wire mode
8.1.1
SPI Interface Signals (4-Wire Mode, Wire_mode = 1)
The AS5050 only supports slave operation mode. Therefore SCK for the communication as well as the /SS signal has to be provided by the test equipment. The following picture shows a basic interconnection diagram with one master and an AS5050 device and a principle schematic of the interface core. Figure 10. SPI Interface Connection
SPI_CLK SPI_SSN MOSI
SCK SS/ MOSI RXSR Interface Core RXSPI TXSPI TXSR
Master Device
(Tester)
MISO
MISO
AS5050
Because the interface has to decode the sent command before it can react and provide data the response of the chip to a specific command applied at a time T can be accessed in the next transmission cycle ending at T + TCOM. The data are sent and read with MSB first. Every time the chip is accessed it is sending and receiving data.
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AS5050
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 11. SPI Command / Response Data Flow
TCOM
MSB LSB Command 1 MSB Command 2 LSB MSB Command N - 1 LSB MSB Command N LSB
MOSI
MISO
MSB
0x 00 LSB MSB
Response 1 LSB MSB
Response 2 LSB MSB
Response N - 1 LSB
Transmission 1
Transmission 2
Transmission N - 1
Transmission N
8.1.2
SPI Timing
Figure 12. SPI Timing Diagram
t XSSH
SS / ( Input )
tL t sck t sckL t sckH tH
SCK ( Input )
t MISO t OZ
data[ 15] data[ 14] data[0]
MISO ( Output ) MOSI ( Input )
t MOSI
t OZ
data[ 14] data[0]
data[ 15]
Table 15. SPI Timing Characteristics Parameter tL tL tSCK tSCKL tSCKH tH tXSSH tXSSH tMOSI tMISO Description Time between SS/ falling edge and SCK rising edge Time between SS/ falling edge and SCK rising edge Serial clock period Low period of serial clock High period of serial clock Time between last falling edge of SCK and rising edge of SS/ High time of SS/ between two transmissions High time of SS/ between two transmissions Data input valid to clock edge SCK edge to data output valid Min 10
1 2
Max
Unit ns ns ns ns ns ns ns ns ns
350
100 50 50 tSCK / 2 10
1 2
350 20
20
ns
1. No synchronization needed because the internal clock is inactive 2. Synchronization with the internal clock 2 * tCLK_SYS + 10 ns (e.g. at 8 MHz 253 ns)
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AS5050
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.1.3
SPI Connection to the Host C
Single Slave Mode.
Figure 13. Single Slave Mode
0xFFFF Write CMD MOSI Read angle 1 0xFFFF 0xFFFF Write CMD Write CMD Read angle 2 Read angle 3 Angle 1 Angle 2 0xFFFF 0xFFFF 0xFFFF Write CMD Write CMD Write CMD Read angle 4 Read angle 5 Read angle 6 Angle 3 Angle 4 Angle 5
MOSI MISO
MOSI MISO SCK SS/
1
Write CMD NOP Angle 6
...
UC
SCK SS/
AS5050
MISO SS/
Wire_Mode
4-wire mode
1
MOSI MISO SCK SS/
MISO
MISO
...
Angle 1
Angle 2
Angle 3
Angle 4
Angle 5
Angle 6
Angle 7
UC
SCK SS/
1
AS5050
SS/
Wire_Mode
3-wire mode(Read only )
0xFFFF Write CMD SISO Read angle 1 0xFFFF Write CMD Read angle 2 0xFFFF Write CMD Read angle 3 0xFFFF Write CMD Read angle 4
SISO
MISO MOSI SCK SS/
0
Angle 1
Angle 2
Angle 3
Angle 4
UC
SCK SS/
AS5050
SS/
Wire_Mode
3-wire mode( Bi - dir)
Note: 3-Wire Mode (read only): If the ERROR FLAG is set the device must be externally reset.
Multiple Slave, n+3 Wire (Separate ChipSelect).
Figure 14. Multiple Slave, n+3 Wire (Separate ChipSelect)
MOSI MISO
MOSI MISO SCK SS/ 1
UC MOSI
Write CMD SW reset ...
0xFFFF Write CMD Read angle 1
xx Angle 1
0xFFFF Write CMD Read angle 2
xx Angle 2
0xFFFF Write CMD Read angle3
0xFFFF xx Angle 3 Write CMD NOP
UC
SCK SS1/ SS2/ SS3/
AS5050 I
UC MISO
SS1/ SS2/ SS2/
Wire_ Mode
MOSI MISO SCK SS/ 1
AS5050 II
Wire_ Mode
MOSI MISO SCK SS / 1
AS5050 III
Wire_ Mode
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Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Daisy Chain, 4 Wire.
Figure 15. Daisy Chain, 4-Wire
MOSI MISO
MOSI MISO SCK SS/ 1
CMD UC MOSI Writereset SW
Write CMD SW reset
Write CMD SW reset
UC
SCK SS/
AS5050 UC MISO I SS/
...
Wire_Mode
0xFFFF MOSI MISO SCK SS/ 1
0 xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF ... Angle 3 ... Angle 2 ... Angle1
UC MOSI Read angle3 Read angle2 Read angle1 Read angle3 Read angle2 Read angle1
AS5050 UC MISO II SS/
Angle 3
Angle 2
Angle 1
Wire_Mode
MOSI MISO SCK SS/ 1
AS5050 III
Wire_Mode
8.2 Placement of the Magnet
Non-Linearity Error over Displacement.
As shown in Figure 17, the recommended horizontal position of the magnet axis is over the diagonal center of the IC. Figure 16 shows a typical error curve at a vertical magnet distance of 1.0mm, measured with a NdFeB N35H magnet with 6mm diameter and 2.5mm height. The X- and Y- axis of the graph indicate the lateral displacement of the magnet center with respect to the IC center. At X = Y = 0, the magnet is perfectly centered over the IC. The total displacement plotted on the graph is for 1mm in both directions. The Z-axis displays the worst case INL error over a full turn at each given X-and Y- displacement. The error includes the quantization error of 1/2 LSB. At the sample shown in Figure 16, the accuracy for a centered magnet is better than 0.5. Within a radius of 0.5mm, the accuracy is about 1.0 (spec = 1.41 over temperature).
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Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 16. Integral Non-linearity Over Displacement of the Magnet
Non-Linearity @ z=1mm
4 3.5 3 2.5 2 INL [] 1.5 1 0.5 0 -1.0 -0.7 -0.4 -0.1 0.2 -0.7 0.5 0.8 -1.0
3.5-4
0.8 0.5 0.2 -0.1 -0.4
Y-displacement [mm]
3-3.5 2.5-3 2-2.5 1.5-2 1-1.5 0.5-1 0-0.5
X-displacement [mm]
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AS5050
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
9 Package Drawings and Markings
The device is available in a 16-pin QFN (4x4x0.85mm) package. Figure 17. Package Drawing and Hall Sensor Location
D
Dx Dz
A 1 /2 A1
Dy
TOP VIEW
center of die
YYWWXZZ AS5050
E
r
D1
Hall sensor array
A Pin 1 indicator
13 12 E1
BOTTOM VIEW
16 1 L L1 4 e
9 8
L
b
e
Symbol A A1 b D E D1 E1
Min 0.80 0.00 0.25
Nom 0.85 0.30 4.00 BSC 4.00 BSC 2.60 2.60
Max 0.90 0.05 0.35
2.50 2.50
2.70 2.70
Symbol Min Nom Max Notes e 0.65 BSC L 0.40 0.45 0.50 L1 0.10 Dx 1.85 2.00 2.15 1 Dy 1.85 2.00 2.15 2 Dz 0.323 0.383 0.443 3 r 1.00 4
Notes: 1. 2. 3. 4. Center of die to package edge Center of die to package edge Surface of die to package surface Radius of Hall array
Marking: YYWWXZZ.
YY Year (i.e. 04 for 2004) WW Week X Assembly plant identifier ZZ Assembly traceability code
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AS5050
Datasheet - R e v i s i o n H i s t o r y
Revision History
Revision 1.12 Date 17 Feb, 2011 Owner mub Description Latest draft
Note: Typos may not be explicitly mentioned under revision history.
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AS5050
Datasheet - O r d e r i n g I n f o r m a t i o n
10 Ordering Information
The devices are available as the standard products shown in Table 16. Table 16. Ordering Information Ordering Code AS5050-EQFT Description 10-bit low power magnetic rotary encoder Delivery Form Tape & Reel Package 16-pin QFN (4x4x0.85mm)
Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Technical Support is available at http://www.austriamicrosystems.com/Technical-Support For further information and requests, please contact us mailto: sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor
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AS5050
Datasheet - C o p y r i g h t s
Copyrights
Copyright (c) 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact
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