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 PD - 97345B
IRF6717MPBF IRF6717MTRPbF
l RoHs Compliant and Halgen Free l Low Profile (<0.7 mm) l Dual Sided Cooling Compatible l Ultra Low Package Inductance l Optimized for High Frequency Switching l Ideal for CPU Core DC-DC Converters l Optimized for Sync. FET socket of Sync. Buck Converter l Low Conduction and Switching Losses l Compatible with existing Surface Mount Techniques l100% Rg tested
Typical values (unless otherwise specified)
DirectFET Power MOSFET RDS(on) Qgs2
6.6nC
VDSS Qg
tot
VGS Qgd
14nC
RDS(on) Qoss
35nC
25V max 20V max 0.95m@ 10V 1.6m@ 4.5V
Qrr
31nC
Vgs(th)
1.8V
46nC
MX
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
DirectFET ISOMETRIC
SQ
SX
ST
MQ
MX
MT
MP
Description
The IRF6717MPBF combines the latest HEXFET(R) Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the lowest on-state resistance in a package that has the footprint of a SO-8 and only 0.7 mm profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%. The IRF6717MPBF balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of processors operating at higher frequencies. The IRF6717MPBF has been optimized for parameters that are critical in synchronous buck including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The IRF6717MPBF offers particularly low Rds(on) and high Cdv/dt immunity for synchronous FET applications.
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TA = 25C ID @ TA = 70C ID @ TC = 25C IDM EAS IAR
6
Typical RDS(on) (m)
Max.
Units
V
Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Single Pulse Avalanche Energy Avalanche CurrentAg
g
e e f
h
25 20 38 30 220 300 290 30
VGS, Gate-to-Source Voltage (V)
A
mJ A
14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 0 20 40 60 80 100 120 QG Total Gate Charge (nC) ID= 30A VDS= 20V VDS= 13V
5 4 3 2 1 0 2 TJ = 25C 4 6 8 10 12 14 T J = 125C
ID = 30A
16
18
20
VGS, Gate -to -Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage Notes: Click on this section to link to the appropriate technical paper. Click on this section to link to the DirectFET Website. Surface mounted on 1 in. square Cu board, steady state.
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage
TC measured with thermocouple mounted to top (Drain) of part. Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 0.64mH, RG = 25, IAS = 30A.
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1
11/19/10
IRF6717MPBF
Static @ TJ = 25C (unless otherwise specified)
Parameter
BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th)/TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss RG td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min.
25 --- --- --- 1.35 --- --- --- --- --- 140 --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. Max. Units
--- 18 0.95 1.6 1.8 -6.7 --- --- --- --- --- 46 14 6.6 14 11 20.6 35 1.3 25 37 19 15 6750 1700 730 --- ---
Conditions
V VGS = 0V, ID = 250A mV/C Reference to 25C, ID = 1mA 1.25 m VGS = 10V, ID = 38A VGS = 4.5V, ID = 30A 2.1 2.35 V VDS = VGS, ID = 150A
i i
--- 1.0 150 100 -100 --- 69 --- --- --- --- --- --- 2.2 --- --- --- --- --- --- ---
mV/C A nA S VDS = 20V, VGS = 0V VDS = 20V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V VDS = 13V, ID =30A VDS = 13V nC VGS = 4.5V ID = 30A See Fig. 15 nC
VDS = 16V, VGS = 0V VDD = 13V, VGS = 4.5VAi ID = 30A
ns
RG= 1.8 VGS = 0V VDS = 13V = 1.0MHz
pF
Diode Characteristics
Parameter
IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Ag Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
Min.
--- --- --- --- ---
Typ. Max. Units
--- --- --- 27 31 120 A 300 1.0 41 47 V ns nC
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 30A, VGS = 0V TJ = 25C, IF =30A di/dt = 175A/s
i
i
Notes:
Repetitive rating; pulse width limited by max. junction temperature. Pulse width 400s; duty cycle 2%.
2
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IRF6717MPBF
Absolute Maximum Ratings
PD @TA = 25C PD @TA = 70C PD @TC = 25C TP TJ TSTG Power Dissipation Power Dissipation Power Dissipation Peak Soldering Temperature Operating Junction and Storage Temperature Range
e e f
Parameter
Max.
2.8 1.8 96 270 -40 to + 150
Units
W
C
Thermal Resistance
RJA RJA RJA RJC RJ-PCB Junction-to-Ambient Junction-to-Ambient Junction-to-Ambient Junction-to-Case Junction-to-PCB Mounted Linear Derating Factor
100 D = 0.50 0.20 0.10 0.05 0.02 0.01
J J 1 1
el jl kl fl
Parameter
Typ.
--- 12.5 20 --- 1.0 0.022
Max.
45 --- --- 1.3 ---
Units
C/W
eA
W/C
Thermal Response ( Z thJA )
10
Ri (C/W)
0.0116 0.0289 0.2249
R1 R1 R2 R2 R3 R3 R4 R4 R5 R5 R6 R6 R7 R7 R8 R8 A 2 2 3 3 4 4 5 5 6 6 7 7 A
i (sec)
0.000007 3.55E-06 0.000076 0.006892 0.001645 0.009995 38.19138
1
0.3032 0.7515 2.7510 17.682
0.1
Ci= i/Ri Ci= i/Ri
0.01 SINGLE PULSE ( THERMAL RESPONSE )
23.053 1.05185 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Tc
0.001 1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
1000
t1 , Rectangular Pulse Duration (sec)
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Used double sided cooling, mounting pad with large heatsink. Mounted on minimum footprint full size board with metalized
back and with small clip heatsink. Notes:
R is measured at TJ of approximately 90C.
Surface mounted on 1 in. square Cu (still air).
Mounted to a PCB with small clip heatsink (still air)
Mounted on minimum footprint full size board with metalized back and with small clip heatsink (still air)
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3
IRF6717MPBF
1000 1000
60s PULSE WIDTH
Tj = 25C
TOP
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
VGS 10V 5.0V 4.5V 3.5V 3.3V 3.0V 2.8V 2.5V
60s PULSE WIDTH
Tj = 150C
TOP
100
BOTTOM
VGS 10V 5.0V 4.5V 3.5V 3.3V 3.0V 2.8V 2.5V
10
10 2.5V
1 0.1 1
2.5V 10 100
1 0.1 1 10 100 V DS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 4. Typical Output Characteristics
1000 VDS = 15V 60s PULSE WIDTH 100 TJ = 150C TJ = 25C TJ = -40C
Typical RDS(on) (Normalized)
Fig 5. Typical Output Characteristics
2.0 ID = 38A V GS = 10V 1.5 V GS = 4.5V
ID, Drain-to-Source Current (A)
10
1.0
1
0.1 1 2 3 4 5
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 T J , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 6. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd
Fig 7. Normalized On-Resistance vs. Temperature
6 5 Vgs = 3.5V Vgs = 4.0V Vgs = 4.5V Vgs = 5.0V Vgs = 10V T J = 25C
Typical RDS(on) ( m)
C oss = C ds + C gd
C, Capacitance(pF)
10000
Ciss Coss
4 3 2 1
1000
Crss
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0 0 50 100 150 200
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage
Fig 9. Typical On-Resistance vs. Drain Current and Gate Voltage
ID, Drain Current (A)
4
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IRF6717MPBF
1000 10000 OPERATION IN THIS AREA LIMITED BY R DS(on)
ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A)
100
1000
100 DC 10 10msec
1msec
100sec
10
1
T J = 150C T J = 25C T J = -40C VGS = 0V
1
T C = 25C
T J = 150C 0.1
Single Pulse 2.5 0 1 10 100
0 0.0 0.5 1.0 1.5 2.0 VSD, Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 10. Typical Source-Drain Diode Forward Voltage
240 200
ID, Drain Current (A) VGS(th) , Gate Threshold Voltage (V)
Fig11. Maximum Safe Operating Area
2.5
2.0
160 120 80 40 0 25 50 75 100 125 150 T C , Case Temperature (C)
1.5
ID = 150A
1.0
0.5 -75 -50 -25 0 25 50 75 100 125 150 T J , Temperature ( C )
Fig 12. Maximum Drain Current vs. Case Temperature
1200
EAS , Single Pulse Avalanche Energy (mJ)
Fig 13. Typical Threshold Voltage vs. Junction Temperature
ID 19A 24A BOTTOM 30A TOP
1000 800 600 400 200 0 25 50 75
100
125
150
Starting T J , Junction Temperature (C)
Fig 14. Maximum Avalanche Energy vs. Drain Current
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5
IRF6717MPBF
Id Vds Vgs
L
0
DUT 1K
VCC
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 15a. Gate Charge Test Circuit
Fig 15b. Gate Charge Waveform
V(BR)DSS
15V
tp
DRIVER
VDS
L
VGS G R
D.U.T
IAS tp
+ - VDD
A
20V
0.01
I AS
Fig 16b. Unclamped Inductive Waveforms
Fig 16a. Unclamped Inductive Test Circuit
VDS VGS RG
RD
90%
D.U.T.
+
VDS
- VDD
10%
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
VGS
td(on) tr td(off) tf
Fig 17a. Switching Time Test Circuit
Fig 17b. Switching Time Waveforms
6
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IRF6717MPBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * di/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 18. Diode Reverse Recovery Test Circuit for N-Channel HEXFET(R) Power MOSFETs
DirectFET Board Footprint, MX Outline (Medium Size Can, X-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs.
G = GATE D = DRAIN S = SOURCE
D S G S D
D
D
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7
IRF6717MPBF
DirectFET Outline Dimension, MX Outline (Medium Size Can, X-Designation).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
DIMENSIONS
CODE A B C D E F G H J K L M N P METRIC MIN MAX 6.25 6.35 4.80 5.05 3.85 3.95 0.35 0.45 0.68 0.72 0.68 0.72 1.38 1.42 0.80 0.84 0.38 0.42 0.88 1.02 2.28 2.42 0.59 0.70 0.03 0.08 0.08 0.17 IMPERIAL MIN MAX 0.246 0.250 0.189 0.201 0.152 0.156 0.014 0.018 0.027 0.028 0.027 0.028 0.054 0.056 0.031 0.033 0.015 0.017 0.035 0.040 0.090 0.095 0.023 0.028 0.001 0.003 0.003 0.007
DirectFET Part Marking
GATE MARKING LOGO PART NUMBER BATCH NUMBER DATE CODE
Line above the last character of the date code indicates "Lead-Free"
Note: For the most current drawing please refer to IR website at http://www.irf.com/package 8 www.irf.com
IRF6717MPBF
DirectFET Tape & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm Std reel quantity is 4800 parts. (ordered as IRF6717MTRPBF). For 1000 parts on 7" reel, order IRF6717MTR1PBF REEL DIMENSIONS TR1 OPTION (QTY 1000) STANDARD OPTION (QTY 4800) METRIC METRIC IMPERIAL IMPERIAL MAX MIN MIN CODE MAX MAX MAX MIN MIN N.C 6.9 12.992 A N.C 177.77 330.0 N.C N.C 0.75 0.795 B N.C N.C 19.06 20.2 N.C N.C 0.53 0.504 C 0.50 0.520 13.5 12.8 13.2 12.8 0.059 0.059 D N.C 1.5 1.5 N.C N.C N.C 2.31 3.937 E N.C 58.72 100.0 N.C N.C N.C F 0.53 N.C N.C N.C N.C 18.4 0.724 13.50 G N.C 0.47 0.488 0.567 11.9 12.4 14.4 12.01 H 0.47 0.469 N.C 0.606 11.9 11.9 15.4 12.01
LOADED TAPE FEED DIRECTION
NOTE: CONTROLLING DIMENSIONS IN MM
CODE A B C D E F G H
DIMENSIONS IMPERIAL METRIC MIN MAX MIN MAX 0.311 0.319 7.90 8.10 0.154 0.161 3.90 4.10 0.469 0.484 11.90 12.30 0.215 0.219 5.45 5.55 0.201 0.209 5.10 5.30 0.256 0.264 6.50 6.70 0.059 N.C 1.50 N.C 0.059 0.063 1.50 1.60
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.11/2010
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