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| Type IPD105N04L G OptiMOS(R)3 Power-Transistor Features * Fast switching MOSFET for SMPS * Optimized technology for DC/DC converters * Qualified according to JEDEC for target applications * N-channel, logic level * Excellent gate charge x R DS(on) product (FOM) * Very low on-resistance R DS(on) * 100% Avalanche tested * Pb-free plating; RoHS compliant IPD105N04L G Type * Pb-free plating; RoHS compliant 1) Product Summary V DS R DS(on),max ID 40 10.5 40 V m A Package Marking PG-TO252-3 105N04L Maximum ratings, at T j=25 C, unless otherwise specified Parameter Continuous drain current Symbol Conditions ID V GS=10 V, T C=25 C V GS=10 V, T C=100 C V GS=4.5 V, T C=25 C V GS=4.5 V, T C=100 C Pulsed drain current2) Avalanche current, single pulse 3) Avalanche energy, single pulse Gate source voltage 1) Value 40 34 40 29 280 40 10 20 Unit A I D,pulse I AS E AS V GS T C=25 C T C=25 C I D=40 A, R GS=25 mJ V J-STD20 and JESD22 Rev. 1.0 page 1 2007-12-06 IPD105N04L G Maximum ratings, at T j=25 C, unless otherwise specified Parameter Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 Symbol Conditions P tot T j, T stg T C=25 C Value 42 -55 ... 175 55/175/56 Unit W C Parameter Symbol Conditions min. Values typ. max. Unit Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm cooling area 4) Electrical characteristics, at T j=25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=14 A V DS=40 V, V GS=0 V, T j=25 C V DS=40 V, V GS=0 V, T j=125 C Gate-source leakage current Drain-source on-state resistance I GSS R DS(on) V GS=20 V, V DS=0 V V GS=4.5 V, I D=25 A V GS=10 V, I D=40 A Gate resistance Transconductance 2) 3) 4) - - 3.6 75 50 K/W 40 1.2 - 0.1 2 1 V A - 10 10 12.0 8.8 1.1 62 100 100 15 10.5 S nA m RG g fs |V DS|>2|I D|R DS(on)max, I D=40 A 31 See figure 3 for more detailed information See figure 13 for more detailed information Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.0 page 2 2007-12-06 IPD105N04L G Parameter Symbol Conditions min. Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics 5) Gate to source charge Gate charge at threshold Gate to drain charge Switching charge Gate charge total Gate plateau voltage Gate charge total Q gs Q g(th) Q gd Q sw Qg V plateau Qg V DD=20 V, I D=30 A, V GS=0 to 4.5 V V DS=0.1 V, V GS=0 to 10 V V DD=20 V, V GS=0 V V DD=20 V, I D=30 A, V GS=0 to 10 V 4.8 2.2 1.9 4.6 18 3.5 8 23 11 V nC nC C iss C oss Crss t d(on) tr t d(off) tf V DD=20 V, V GS=10 V, I D=30 A, R G=1.6 V GS=0 V, V DS=20 V, f =1 MHz 1400 330 16 3.7 2.4 16 2.8 1900 440 ns pF Values typ. max. Unit Gate charge total, sync. FET Output charge Reverse Diode Diode continuous forward current Diode pulse current Diode forward voltage Q g(sync) Q oss - 16.4 13 - IS I S,pulse V SD T C=25 C V GS=0 V, I F=40 A, T j=25 C V R=20 V, I F=I S, di F/dt =400 A/s - 0.94 35 280 1.2 A V Reverse recovery charge Q rr - 16 - nC 5) See figure 16 for gate charge parameter definition Rev. 1.0 page 3 2007-12-06 IPD105N04L G 1 Power dissipation P tot=f(T C) 2 Drain current I D=f(T C); V GS10 V 45 40 35 30 45 40 35 30 25 20 15 10 5 0 0 50 100 150 200 0 50 100 150 200 P tot [W] 20 15 10 5 0 T C [C] I D [A] 25 T C [C] 3 Safe operating area I D=f(V DS); T C=25 C; D =0 parameter: t p 103 limited by on-state resistance 1 s 4 Max. transient thermal impedance Z thJC=f(t p) parameter: D =t p/T 10 102 10 s 0.5 1 0.2 0.1 0.05 0.02 I D [A] DC 10 1 1 ms 10 ms Z thJC [K/W] 100 s 0.1 0.01 single pulse 100 10-1 10-1 100 101 102 0.01 0 0 0 0 0 0 1 10-6 10-5 10-4 10-3 10-2 10-1 100 V DS [V] t p [s] Rev. 1.0 page 4 2007-12-06 IPD105N04L G 5 Typ. output characteristics I D=f(V DS); T j=25 C parameter: V GS 160 10 V 5V 6 Typ. drain-source on resistance R DS(on)=f(I D); T j=25 C parameter: V GS 25 3.5 V 20 120 4V 80 4V R DS(on) [m] 4.5 V 15 4.5 V I D [A] 5V 10 10 V 40 5 3.5 V 3.2 V 3V 2.8 V 0 0 1 2 0 3 0 20 40 60 80 100 V DS [V] I D [A] 7 Typ. transfer characteristics I D=f(V GS); |V DS|>2|I D|R DS(on)max parameter: T j 120 8 Typ. forward transconductance g fs=f(I D); T j=25 C 100 100 80 80 60 60 g fs [S] 40 20 175 C 25 C I D [A] 40 20 0 0 1 2 3 4 5 0 0 20 40 60 80 100 V GS [V] I D [A] Rev. 1.0 page 5 2007-12-06 IPD105N04L G 9 Drain-source on-state resistance R DS(on)=f(T j); I D=40 A; V GS=10 V 10 Typ. gate threshold voltage V GS(th)=f(T j); V GS=V DS; I D=250 A 20 2.5 16 2 R DS(on) [m] 12 typ 8 V GS(th) [V] 100 140 180 98 % 1.5 1 4 0.5 0 -60 -20 20 60 0 -60 -20 20 60 100 140 180 T j [C] T j [C] 11 Typ. capacitances C =f(V DS); V GS=0 V; f =1 MHz 12 Forward characteristics of reverse diode I F=f(V SD) parameter: T j 104 1000 25 C 103 Ciss Coss 100 25 C, 98% 175 C, 98% C [pF] 102 I F [A] 175 C Crss 10 101 100 0 10 20 30 40 1 0.0 0.5 1.0 1.5 2.0 V DS [V] V SD [V] Rev. 1.0 page 6 2007-12-06 IPD105N04L G 13 Avalanche characteristics I AS=f(t AV); R GS=25 parameter: T j(start) 100 14 Typ. gate charge V GS=f(Q gate); I D=30 A pulsed parameter: V DD 12 10 20 V 8V 32 V 25 C 8 10 V GS [V] 102 103 I AV [A] 100 C 6 150 C 4 2 1 10-1 100 101 0 0 4 8 12 16 20 t AV [s] Q gate [nC] 15 Drain-source breakdown voltage V BR(DSS)=f(T j); I D=1 mA 16 Gate charge waveforms 45 V GS Qg 40 V BR(DSS) [V] 35 30 V g s(th) 25 Q g(th) Q gs -60 -20 20 60 100 140 180 Q sw Q gd Q g ate 20 T j [C] Rev. 1.0 page 7 2007-12-06 IPD105N04L G Package Outline PG-TO252-3 Footprint: Packaging: Rev. 1.0 page 8 2007-12-06 IPD105N04L G Published by Infineon Technologies AG 81726 Munich, Germany (c) 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.0 page 9 2007-12-06 |
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