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IXA531
500mA 3-Phase Bridge Driver
Preliminary Data Sheet
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Features * Fully operational to +650V
* * * * * Tolerant of negative transient voltages dV/dt immune (50V/ns) Latch-up protected over entire operating range Fault-current shutdown for all drive outputs User selectable delay or latching function for clearing of the FAULT signal, independent user controlled clearing of the FAULT signal is also available UVLO protection for all drive outputs Enable signal capable of disabling all driver outputs 3 half-bridge driver pairs (independent) 3.3V logic compatible Cross-conduction prevention logic, 220 ns - 360ns Phase leg deadtime Peak output current: 600mA Pull-up/Source, 600mA Pull-down/Sink Wide operating supply voltage range: 8.0V to 35V Capacitive load drive capability: 1250pF in < 100ns Matched, low propagation delay times Low supply current Monolithic construction ___ Fault monitoring is accompanied by a FLT signal indication, with programmable reset or user selectable latched protection Target package power dissipation capability is 2.0W. Full level of function available from -55C to + 125C Available in 48-Lead 7mm x 7mm MLP Quad package and 44-Lead PLCC package
General Description
The IXA531 is a monolithic, 3-phase, MOSFET/IGBT gate driver consisting of three independent, high and low side output channels. In addition to the six inputs, which are CMOS/TTL Compatible, for the three corresponding high side and three low side outputs, there are dedicated lines for FAULT, ENABLE and RESET. Overload/Short Circuit protection is implemented by sensing a voltage across a shunt or low value resistor which carries load current. Upon Overload/Short Circuit detection, all outputs are disabled. Likewise ENABLE (EN) pin, when LOW under abnormal operating conditions, affords soft shut down of outputs. FAULT(FLT) signal`s status indicates that shut down has occurred either due to Overload/Short Circuit in driven MOSFET/IGBT or Under Voltage on VCL. Clearing of FAULT (FLT) signal and restoration of normal operation ensue automatically after a programmed delay using an RC Network wired at RST (RESET) pin. Matched propagation delays ensure proper operation even at very high switching frequencies. Absence of cross conduction in output stages removes possibility of shoot through in driven power MOSFETs or IGBTs.
* * * * * * * * * * * *
* *
Applications
* * * * * * Driving MOSFETs and IGBTs in half-bridge circuits High voltage, high side and low side drivers Motor Controls Switch Mode Power Supplies (SMPS) DC to DC Converters Class D Switching Amplifiers
*
Ordering Information Part
IXA531S10 IXA531L4
Package
48L - SSLGA 44L - PLCC
Warning: The IXA531 is ESD sensitive.
DS99187A(12/05) 1
Copyright (c) IXYS CORPORATION 2005
First Release
IXA531
Fig. 1. Single Phase Application
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up to + 650 V
VCL HIN1 LIN1 FLT EN
VCL HIN1 LIN1 FLT EN
VCH1
HGO1 HS1 IXA531
To Load
RST ITRP DG
UVSEL LGO1 LS
HG03
LGO3 LIN2 HG02 LGO2 LIN3 HS3 VCH3
HIN2 VCH2 HS2 HIN3
Pin Description And Configuration
SYMBOL
_______ HIN1,2,3 _______ LIN1,2,3 EN DG VCH1,2,3 HGO1,2,3 HS1,2,3 VCL LGO1,2,3 LS ___ FLT ITRP RST
FUNCTION
HS Input LS Input Enable Ground Supply Voltage Output Return Supply Voltage
DESCRIPTION
High side Input signal, TTL or CMOS compatible; HGO1,2,3 out of phase Low side Input signal, TTL or CMOS compatible; LGO1,2,3 out of phase Chip enable. When driven high, both outputs go low. Logic Reference Ground High Side Power Supply High side driver output High side voltage return Low side and Logic fixed power supply. This power supply provides power for all outputs. Voltage range is from 8.0 to 35V.
Output Low side return Fault Trip Delay after trip
Low side driver output Low side driver return Indicates Low-Side under voltage or Over Current Trip Input for over current shutdown Externally connected RC network decide FAULT CLEAR delay.
2
up to + 650 V
VCL VCH2 HIN2 LIN2 PH1 To Load HS2 PH2 To Load LIN2 HGO2 LIN3 HIN2 HIN3 HIN3 LIN3
VCL
VCH1
VCH3 HGO3 HS3 PH3 To Load
HIN1
HIN1
LIN1 HS1
LIN1
HGO1
FLT EN
FLT EN
3
LGO2 LS
RST
UVSEL LGO3
ITRP
LGO1
DG
IXA531S10
GND
Fig. 2. 3-Phase Application for the IXA531.
IXA531
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IXA531
Absolute Maximum Ratings
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Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to LS. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions Symbol Definition VCH VHS VHGO VCL VDG VLGO VIN VFLT dV/dt PD RthJA TJ TS TL High side floating supply voltage , (VCH1,2,3) High side floating supply offset voltage , (VHS1,2,3) High side floating output voltage , (VHGO1,2,3) Low side and logic fixed supply voltage Logic Supply offset voltage Low side output voltage _______ _______ Input voltage HIN1,2,3, LIN1,2,3, ITRP, RST , EN FAULT output voltage Allowable offset voltage slew ratelew rate Package power dissipation@ TA +25OC Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) -55 Min. -200 VCH1,2,3 - 35 VHS1,2,3- 0.3 8.0 VLS - 0.7 - 0.3 VDG - 0.3 VDG - 0.3 Max. 650 VCH1,2,3 + 0.3 VCH1,2,3 + 0.3 35 VLS + 0.7 VCL + 0.3 Lower of (VDG + 35) or (VCL + 0.3) VCL + 0.3 50 2.0 63 125 150 300 Units V V V V V V V V V/ns W K/W
O O O
C C C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute values referenced to LS. The VHS offset rating is tested with all supplies baised at 15V differential. Symbol VCH1,2,3 VHS1,2,3 VHGO1,2,3 VLGO1,2,3 VCL VDG VFLT VRST VITRP VIN TA Definition High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side output voltage Low side and logic fixed supply voltage Logic Supply offset voltage FAULT output voltage RST input voltage ITRP input voltage _______ _______ Logic input voltage HIN1,2,3, LIN1,2,3, EN Ambient temperature Min. VHS1,2,3 + 12 - 200 VHS1,2,3 0 12 VLS - 0.3 VDG VDG VDG VDG or VLS -40 Max. VHS1,2,3 + 35 650 VCH1,2,3 VCL 35 VLS + 0.3 VCL VCL VCL VCL 125 Units V V V V V V V V V V
O
C
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IXA531
Static Electrical Characteristics
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VBIAS (VCL, VCH1,2,3) = 15V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to DG and are applicable to all six channels . The VO and IO parameters are referenced to LS and V and are applicable to the HS1,2,3 respective output leads: H and LGO1,2,3.
GO1,2,3
Symbol VINL VINH VEN,TH+ VEN,TH VITRP, TH+ VITRP, HYS VRST,TH+ VRST, HYS VOH1,2,3 VOL1,2,3 VCLUV+ VCHUV+ VCLUVVCHUVVCLUVH VCHUVH ILK IQVCH IQVCL VIN ILIN+or IIN+ ILIN-or IINIHIN+or IIN+ IHIN-or IINIITRP+ IITRPIEN+ IENIRST IGO+ IGORON, RST RON, FLT
Definition Logic "0" input voltage HIN1,2,3; LIN1,2,3 Logic "1" input voltage HIN1,2,3; LIN1,2,3 EN positve going threshold EN negative going threshold ITRP positve going threshold ITRP input hysteresis RST positive going threshold RST input hysteresis High level output voltage, VCH - VHGO or VCL- VLGO Low level output voltage, VHGO or VLGO VCL supply under-voltage positive going threshold VCH supply under-voltage positive going threshold VCL supply under-voltage negaitive going threshold VCH supply under-voltage negaitive going threshold VCL supply under-voltage lockout hysteresis VCH supply under-voltage lockout hysteresis Offset supply leakage current Quiescent VCH supply current Quiescent VCL supply current Input clamp voltage (HIN,LIN,ITRP,EN) Logic "1" Input bias current for LIN1,2,3 Logic "0" Input bias current for LIN1,2,3 Logic "1" Input bias current for HIN1,2,3 Logic "0" Input bias current for HIN1,2,3 "high" ITRP input bias current "low" ITRP input bias current "high" ENABLE input bias current "low" ENABLE input bias current RST input bias current Output high short circuit pulsed current Output low short circuit pulsed current RST low on resistance FLT low on resistance
Min.
Typ. Max. Units 0.8 V V 3.0 V V 0.46 0.55 V .07 8 3 0.9 0.4 1.4 0.6 V V V V V
Test Conditions
3.0
0.8 0.37
I0=20mA I0=20mA
10.6 10.6 10.4 10.4
11.1 11.6 V 11.1 11.6 V 10.9 11.4 V 10.9 11.4 V 0.2 0.2 50 70 1.6 4.9 200 100 200 100 30 0 30 0 0 600 600 50 50 100 100 300 220 300 220 100 1 100 1 1 120 2.3 V V A A mA V A A A A A A A A A mA mA VCH1,2,3= VHS1,2,3=600 V VIN=0V or 5V VIN=0V or 5V IIN = 100A VLIN = 5V VLIN = 0V VHIN = 5V VHIN = 0V VITRP = 5V VITRP = 0V VEN = 5V VEN = 0V VRST = 0Vor 15V V0=0V,PW <10 s V0=15V,PW<10s
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IXA531
Dynamic Electrical Characteristics
VCL = VCH = VBIAS = 15V, VHS1,2,3 = VDG = VLS, TA = 25C and CL = 1000pF unless otherwise specified.
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Symbol
ton toff tr tf tEN tITRP tbl tFLT tFILIN tFLCLR DT MT MDT PM
Definition
Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-on fall time ENABLE low to output shutdown propagation delay ITRP to output shutdown propagation delay ITRP blanking time ITRP to FAULT propagation delay Input filter time (HIN, LIN, EN) FAULT clear time RST=2meg, C=1nF Dead time Matching delay ON and OFF Matching delay, max (ton , toff) - min (ton , toff) (ton,toff are applicable to all 3 channels) Output pulse width matching, PWMIN-PWMOUT
Min.
300 250
Typ.
425 400 125 50 450 750 150 600 200 1.65 290 40 25 40
Max.
550 550 190 75 600 1000
Units
nS nS nS nS nS nS nS
Test Conds.
VIN=0V & 5V VIN=0V & 5V ------VIN , VEN = 0 V or 5 V VITRP=5V VIN=0V or 5V VITRP = 5V V IN = 0V or 5V VITRP = 5V VIN = 0V & 5V VIN = 0V or 5V VITRP=0V VIN = 0V & 5V External Dead Time
300 500 100 400 100 1.3 220
800
nS nS
2 360 75 70 75
mS nS nS nS nS
>400nsec
VCL
VCH
X
ITRP
X 0V 0V
ENABLE
X 15V 15V 15V 0V
FAULT
0(note 1) high imp high imp 0 (note 2) high imp
LGO1,2,3
0 LIN1,2,3 LIN1,2,3 0 0
HGO1,2,3
0 0 HIN1,2,3 0 0
15V 15V 15V
>VITRP
0V
Notes: A Cross Conduction logic prevents LGO1,2,3 and HGO1,2,3 for each channel from turning on simultaneously. 1. UVCL is not latched, when VCL>UVCL, FAULT returns to high impedance. 2. When ITRP < VITRP, FAULT returns to high-impedance after RST pin becomes greater then 8V (@VCL= 15V).
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IXA531
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HIN1,2,3
HIN1,2,3 LIN1,2,3 EN
ITRP FLT
RST
HO1,2,3
LO1,2,3
Fig. 3. (5) Timing Diagram Fig. Timing Diagram
EN
50%
t EN
LO1,2,3 HO1,2,3
90%
Fig. 4. ENABLE Timing Waveforms Fig. (6) Enable Timing Waveforms
LIN1,2,3
50% 50%
HIN1,2,3
PWMIN
LIN1,2,3 HIN1,2,3
50% 50%
ton tr
90% PWMOUT
toff
tf
90%
HO1,2,3 LO1,2,3
10%
10%
Fig. 5. Switching Time Definitions
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IXA531
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LIN1,2,3
50% 50%
HIN1,2,3 LIN1,2,3 HIN1,2,3
50% 50%
LO1,2,3 HO1,2,3 DT DT
Fig.Fig. (8) Deadtime Waveforms 6. Deadtime Waveforms
RST
50%
VRST,th+
50%
50%
ITRP FLT
50%
t FLT t FLCLR OUTPUT t ITRP
90%
50%
Fig.Fig. (9) ITRP /Waveforms 7. ITRP / RST RST Waveforms
t FILIN
t FILIN
on HIN / LIN
off
on
off
on
off
HO / LO
high low
Fig. 8. ENABLE Timing Waveforms Fig. (10) Input Filter Diagram
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IXA531
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VCL 750K
VCL
VCL
VCH
VCH1
600mA Gate Driver
HIN1
VCL 750K
Low to
hin1 5V LOGIC to VCL CMOS en1 Level Shift , & Anti-Cross Conduction Logic h01
High
Out Rst In
In Isolation
HGO1
iO1
UVCC Detect HS Isolated High Side
LIN1
lin1
HS1
VCL 750K
VCL
VCL
VCH
VCH2
600mA Gate Driver
Low to
High
HIN2
VCL 750K
hin2 en2
5V LOGIC to VCL CMOS Level Shift , & Anti-Cross Conduction Logic
Out Rst In
h02
In Isolation
HGO2
iO2
UVCC Detect HS Isolated High Side
LIN2
lin2
HS2
VCL 750K
VCL
VCL
VCH
VCH3
600mA Gate Driver
Low to
High
HIN3
VCL 750K
hin3 en3
5V LOGIC to VCL CMOS Level Shift , & Anti-Cross Conduction Logic
h03
In Isolation
Out Rst In
HGO3
iO3
UVCC Detect HS Isolated High Side
LIN3
lin3
HS3
VCL
VCL
VCL
UVCL
EN
50K
VCL
In
OUT Detect
Low to High Delay Equalizer
Out
600mA Gate Driver
LGO1
ITRP
50K + 0.5 V VCL
+ S R Set Dominant Latch QB In Low to High Delay Equalizer Out 600mA Gate Driver
LGO2
RST
N In Low to High Delay Equalizer Out 600mA Gate Driver
LGO3 LS
FLT
N
1
DG
Fig. (9) IXA531 Block Diagram
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IXA531
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Fig. 10. Pin Diagram for the IXA531S10 48-Lead MLP Quad Package
0.2760.002 [7.000.05] 0.0390.002 [1.000.05]
0.2760.002 [7.000.05]
0.0150.001 [0.380.03] 0.0090.001 [0.230.03] 0.0300.001 [0.750.03] 0.020 [0.50]
Fig. 11. Pin Diagram for the IXA531L4 44-Lead PLCC package
HIN3 HIN2 HIN1 VCH1 HGO1 VCL HS1 41 NC NC NC NC 40
6
5
4
3
2
1
44
43
42
NC LS LIN1 LIN2 LIN3 NC FLT NC ITRP NC EN RST
7 8 9 10 11 12 13 14 15 16 17
39 38 37
NC NC VCH2 HGO2 HS2 NC NC NC VCH3 HGO3 HS3
IXA531L4
36 35
IXA531S10
34 33 32 31 30 29
18
19
20
21
22
23 LGO3
24 LGO2
25 LGO1
26
27
28
NC
DG
NC
NC
NC
LS
10
NC
NC
IXA531
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Fig. 12. 44-Lead PLCC Outline Diagram
IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 e-mail: sales@ixys.net www.ixys.com
IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: marcom@ixys.de
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