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M29F102BB
1 Mbit (64Kb x16, Boot Block) Single Supply Flash Memory
FEATURES SUMMARY

SINGLE 5V10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 35ns PROGRAMMING TIME - 8s per Word typical 5 MEMORY BLOCKS - 1 Boot Block (Bottom Location) - 2 Parameter and 2 Main Blocks PROGRAM/ERASE CONTROLLER - Embedded Word Program algorithm - Embedded Multi-Block/Chip Erase algorithm - Status Register Polling and Toggle Bits ERASE SUSPEND and RESUME MODES - Read and Program another Block during Erase Suspend UNLOCK BYPASS PROGRAM COMMAND - Faster Production/Batch Programming TEMPORARY BLOCK UNPROTECTION MODE LOW POWER CONSUMPTION - Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per BLOCK M28F102 COMPATIBLE - Pin-out and Read Mode 20 YEARS DATA RETENTION - Defectivity below 1 ppm/year ELECTRONIC SIGNATURE - Manufacturer Code: 0020h - Bottom Device Code M29F102BB: 0097h PACKAGES - Compliant with Lead-Free Soldering Processes - Lead-Free Versions
Figure 1. Package
PLCC44 (K)
TSOP40 (N) 10 x 14mm
November 2004
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M29F102BB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Table 2. Figure 3. Figure 4. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Bottom Boot Block Addresses, M29F102BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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M29F102BB
Table 5. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70C). . . . . . 10 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 7. Absolute Maximum Ratings (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. AC Testing Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. AC Testing Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Capacitance (TA = 25 C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 10. DC Characteristics (TA = 0 to 70C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 11. Read AC Characteristics (TA = 0 to 70C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 12. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 C) . . . . . . . . . . . . . . . 17 Figure 10.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 13. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70 C) . . . . . . . . . . . . . . . 18 Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 14. Reset/Block Temporary Unprotect AC Characteristics (TA = 0 to 70C) . . . . . . . . . . . . . 19 Figure 12.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 13.PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline . . . . . . . . . . . . . . . . . 20 Table 15. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data . . . . . . . . . . 20 Figure 14.TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Outline . . . . . . . . . 21 Table 16. PTSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Mechanical Data 21 ORDERING INFORMATION SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 18. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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M29F102BB
SUMMARY DESCRIPTION
The M29F102BB is a 1 Mbit (64Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically arranged, see Table 2., Bottom Boot Block Addresses, M29F102BB. The first 32 Kwords have been divided into four additional blocks. The 8 Kword Boot Block can be used for small initialization code to start the microprocessor, the two 4 Kword Parameter Blocks can be used for parameter storage and the remaining 16 Kwords are a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in PLCC44 and TSOP40 (10 x 14mm) packages. In addition to the standard version, the packages are also available in Leadfree version, in compliance with JEDEC Std JSTD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. The memory is supplied with all the bits erased (set to '1'). Figure 2. Logic Diagram
VCC
16 A0-A15 W E G RP M29F102BB
16 DQ0-DQ15
VSS
AI02130C
Table 1. Signal Names
A0-A15 DQ0-DQ15 E G W RP VCC VSS NC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Supply Voltage Ground Not Connected Internally
Table 2. Bottom Boot Block Addresses, M29F102BB
# 4 3 2 1 0 Size (KWords) 32 16 4 4 8 Address Range 8000h-FFFFh 4000h-7FFFh 3000h-3FFFh 2000h-2FFFh 0000h-1FFFh
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M29F102BB
Figure 3. PLCC Connections Figure 4. TSOP Connections
1 44 DQ12 DQ11 DQ10 DQ9 DQ8 VSS NC DQ7 DQ6 DQ5 DQ4 A13 A12 A11 A10 A9 VSS NC A8 A7 A6 A5
12
M29F102BB
34
23
DQ3 DQ2 DQ1 DQ0 G NC A0 A1 A2 A3 A4
AI02131C
A9 A10 A11 A12 A13 A14 A15 NC W VCC RP E DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8
1
40
10 11
M29F102BB
31 30
20
21
AI02132C
VSS A8 A7 A6 A5 A4 A3 A2 A1 A0 G DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS
DQ13 DQ14 DQ15 E RP NC VCC W NC A15 A14
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M29F102BB
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A15). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ15). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations DQ0-DQ7 represent the commands sent to the Command Interface of the internal state machine; the Command Interface does not use DQ8-DQ15 to decode the commands. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tPLYH, whichever occurs last. See Table 13., Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70 C) and Figure 12., Reset/ Block Temporary Unprotect AC Waveforms. Holding RP at VID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Reset/Block Temporary Unprotect can be left unconnected. A weak internal pull-up resistor ensures that the memory always operates correctly. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1F capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3. Vss Ground. The VSS Ground is the reference for all voltage measurements.
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M29F102BB
BUS OPERATIONS
There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 3., Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 9., Read Mode AC Waveforms, and Table 11., Read AC Characteristics (TA = 0 to 70C), for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 10 and 11, Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Table 3. Bus Operations
Operation Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code
Note: 1. X = VIL or VIH.
Standby Supply Current, ICC2, Chip Enable should be held within VCC 0.2V. For the Standby current level see Table 10., DC Characteristics (TA = 0 to 70C). During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 3., Bus Operations. Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.
E VIL VIL X VIH VIL VIL
G VIL VIH VIH X VIL VIL
W VIH VIL VIH X VIH VIH
Address Inputs Cell Address Command Address X X A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH
Data Inputs/Outputs Data Output Data Input Hi-Z Hi-Z 0020h 0097h
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M29F102BB
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The commands are summarized in Table 4., Commands. Refer to Table 4. in conjunction with the text descriptions below. Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take up to 10s to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29F102BB is 0097h. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A15 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 5.. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior. Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command.
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Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 5.. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to '1'. All previous data is lost. Block Erase Command. The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50s after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50s of the last block. The 50s timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands. Typical block erase times are given in Table 5.. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to '1'. All previous data in the selected blocks is lost. Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within 15s of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It will not be possible to select any further blocks for erasure after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. Reading from blocks that are being erased will output the Status Register. It is also possible to enter the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until a Read/Reset command returns the memory to Erase Suspend mode. Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.
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Table 4. Commands
Length Bus Write Operations 1st Addr X 555 555 555 555 X X 555 555 X X Data F0 AA AA AA AA A0 90 AA AA B0 30 2AA 2AA 2AA 2AA PA X 2AA 2AA 55 55 55 55 PD 00 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 BA 10 30 X 555 555 555 F0 90 A0 20 PA PD 2nd Addr Data 3rd Addr Data 4th Addr Data 5th Addr Data 6th Addr Data Command
1 Read/Reset 3 Auto Select Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Erase Suspend Erase Resume 3 4 3 2 2 6 6+ 1 1
Note: 1. X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. 2. All values in the table are in hexadecimal. 3. The Command Interface only uses address bits A0-A10 and DQ0-DQ7 to verify the commands, the upper address bits and the upper data bits are Don't Care. 4. Read/Reset. 5. After a Read/Reset command, read the memory as normal until another command is issued. 6. Auto Select. 7. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. 8. Program, Unlock Bypass Program, Chip Erase, Block Erase. 9. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations until the Timeout Bit is set. 10. Unlock Bypass. 11. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. 12. Unlock Bypass Reset. 13. After the Unlock Bypass Reset command read the memory as normal until another command is issued. 14. Erase Suspend. 15. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on nonerasing blocks as normal. 16. Erase Resume. 17. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.
Table 5. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70C)
Parameter Chip Erase (All bits in the memory set to `0') Chip Erase Block Erase (32 KWords) Program Chip Program Program/Erase Cycles (per Block)
Note: 1. TA = 25C, VCC = 5V.
Min
Typ(1) 0.6 1.3 0.6 8 0.6
Typical after 100k W/E Cycles(1) 0.6 1.3 0.6 8 0.6
Max
Unit s
6 4 150 2.5
s s s s cycles
100,000
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M29F102BB
STATUS REGISTER
Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 6., Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a '1' during a Bus Read operation within a block being erased. The Data Polling Bit will change from a '0' to a '1' when the Program/Erase Controller has suspended the Erase operation. Figure 5., Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. Figure 6., Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to '1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set at '0' back to '1' and attempting to do so may or may not set DQ5 at `1'. In both cases, a successive Bus Read operation will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to '1'. Before the Program/Erase Controller starts the Erase Timer Bit is set to '0' and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations from addresses within the blocks being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly.
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Table 6. Status Register Bits
Operation Program Program During Erase Suspend Program Error Chip Erase Block Erase before timeout Non-Erasing Block Erasing Block Block Erase Non-Erasing Block Erasing Block Erase Suspend Non-Erasing Block Good Block Address Erase Error Faulty Block Address
Note: 1. Unspecified data bits should be ignored.
Address Any Address Any Address Any Address Any Address Erasing Block
DQ7 DQ7 DQ7 DQ7 0 0 0 0 0 1
DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle
DQ5 0 0 1 0 0 0 0 0 0
DQ3 - - - 1 0 0 1 1 -
DQ2 - - - Toggle Toggle No Toggle Toggle No Toggle Toggle
Data read as normal 0 0 Toggle Toggle 1 1 1 1 No Toggle Toggle
Figure 5. Data Polling Flowchart
Figure 6. Data Toggle Flowchart
START
START READ DQ5 & DQ6
READ DQ5 & DQ7 at VALID ADDRESS
READ DQ6
DQ7 = DATA NO NO
YES
DQ6 = TOGGLE YES NO
DQ5 =1 YES
NO
DQ5 =1 YES READ DQ6 TWICE
READ DQ7 at VALID ADDRESS
DQ7 = DATA NO FAIL
YES
DQ6 = TOGGLE YES NO
PASS
FAIL
AI03598
PASS
AI01370B
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M29F102BB
MAXIMUM RATINGS
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at Table 7. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG TLEAD VIO (2) VCC VID Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Lead Temperature during Soldering Input or Output Voltage Supply Voltage Identification Voltage Value 0 to 70 -50 to 125 -65 to 150
(3)
these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Unit C C C
-0.6 to 6 -0.6 to 6 -0.6 to 13.5
V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in Table 7., Absolute Maximum Ratings (1) may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions. 3. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
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DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 9, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 8. Operating and AC Measurement Conditions
M29F102BB Parameter Min Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 1.5 30 10 3 Max pF ns V V Unit
Figure 7. AC Testing Input Output Waveform
Figure 8. AC Testing Load Circuit
1.3V
3V 1.5V 0V
AI01417
1N914
3.3k DEVICE UNDER TEST CL = 30pF
OUT
CL includes JIG capacitance
AI02979
Table 9. Capacitance (TA = 25 C, f = 1 MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: Sampled only, not 100% tested.
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Table 10. DC Characteristics (TA = 0 to 70C)
Symbol ILI(1) ILR1 ILR2 ILO ICC1 ICC2 ICC3 (2) VIL VIH VOL VOH VID IID VLKO (2) Parameter Input Leakage Current RP Leakage Current High RP Leakage Current Low Output Leakage Current Supply Current (Read) Supply Current (Standby) Supply Current (Program/ Erase) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Identification Voltage Identification Current Program/Erase Lockout Supply Voltage A9 = VID 3.2 IOL = 5.8mA IOH = -100A VCC -0.4 11.5 12.5 100 4.2 Test Condition 0V VIN VCC RP = VCC RP = VSS 0V VOUT VCC E = VIL, G = VIH, f = 6MHz E = VCC 0.2V, RP = VCC 0.2V Program/Erase Controller active -0.5 2 6 30 -0.2 Min Typ (3) Max 1 1 -10 1 20 100 20 0.8 VCC +0.5 0.45 Unit A A A A mA A mA V V V V V A V
Note: 1. Excluding the RP input. 2. Sampled only, not 100% tested. 3. TA = 25C, VCC = 5V
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Table 11. Read AC Characteristics (TA = 0 to 70C)
M29F102BB Symbol tAVAV (1) tAVQV (1) tELQX (2) tELQV (1) tGLQX (2) tGLQV (1) tEHQZ (2) tGHQZ (2) tEHQX tGHQX tAXQX Alt Parameter Address Valid to Next Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output HiZ Chip Enable, Output Enable or Address Transition to Output Transition Test Condition 35 tRC tACC tLZ tCE tOLZ tOE tHZ tDF E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL Min Max Min Max Min Max Max Max 35 35 0 35 0 20 15 15 45 45 45 0 45 0 20 15 15 50 / 55 50 50 0 50 0 20 18 18 70 70 70 0 70 0 30 20 20 ns ns ns ns ns ns ns ns Unit
tOH
Min
0
0
0
0
ns
Note: 1. This timing refers to a Load Capacitance (CL) of 30pF. If CL is higher, add 1.5ns for each extra 10pF. 2. Sampled only, not 100% tested.
Figure 9. Read Mode AC Waveforms
tAVAV A0-A15 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ15 tGHQX tGHQZ VALID
AI02980
VALID tAXQX
tEHQX tEHQZ
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Table 12. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 C)
M29F102BB Symbol tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tVCHEL tOEH tVCS Alt tWC tCS tWP tDS tDH tCH tWPH tAS tAH Parameter 35 Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low Write Enable High to Output Enable Low VCC High to Chip Enable Low Min Min Min Min Min Min Min Min Min Min Min Min 35 0 35 20 0 0 20 0 35 0 0 50 45 45 0 40 25 0 0 20 0 40 0 0 50 50 / 55 50 0 40 25 0 0 20 0 40 0 0 50 70 70 0 45 30 0 0 20 0 45 0 0 50 ns ns ns ns ns ns ns ns ns ns ns s Unit
Figure 10. Write AC Waveforms, Write Enable Controlled
tAVAV A0-A15 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ15 VALID tWHDX tWLWH tWHGL tWHEH
VCC tVCHEL
AI02119
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Table 13. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70 C)
M29F102BB Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tEHGL tVCHWL tOEH tVCS Alt tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter 35 Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low Chip Enable High to Output Enable Low VCC High to Write Enable Low Min Min Min Min Min Min Min Min Min Min Min Min 35 0 35 20 0 0 20 0 35 0 0 50 45 45 0 40 25 0 0 20 0 40 0 0 50 50 / 55 50 0 40 25 0 0 20 0 40 0 0 50 70 70 0 45 30 0 0 20 0 45 0 0 50 ns ns ns ns ns ns ns ns ns ns ns s Unit
Figure 11. Write AC Waveforms, Chip Enable Controlled
tAVAV A0-A15 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ15 VALID tEHDX tELEH tEHGL tEHWH
VCC tVCHWL
AI02120
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Table 14. Reset/Block Temporary Unprotect AC Characteristics (TA = 0 to 70C)
M29F102BB Symbol tPHWL (1) tPHEL tPHGL (1) tPLPX tPLYH (1) tPHPHH (1) Alt Parameter 50 RP High to Write Enable Low, Chip Enable Low, Output Enable Low RP Pulse Width RP Low to Read Mode RP Rise Time to VID 70 90 Unit
tRH
Min
50
50
50
ns
tRP tREADY tVIDR
Min Max Min
500 10 500
500 10 500
500 10 500
ns s ns
Note: 1. Sampled only, not 100% tested.
Figure 12. Reset/Block Temporary Unprotect AC Waveforms
W, E, G tPHWL, tPHEL, tPHGL RP tPLPX tPHPHH tPLYH
AI02943
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PACKAGE MECHANICAL
Figure 13. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline
D D1
1N
A1 c
B1
E3
E1 E
E2 B
e
D3
A2 A CP
PLCC-B
D2
Note: Drawing is not to scale.
Table 15. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B B1 CP c D D1 D2 D3 E E1 E2 E3 e N 12.700 1.270 44 12.700 0.510 17.400 16.510 14.990 - 17.400 16.510 14.990 - - 17.650 16.662 16.000 - 17.650 16.660 16.000 - - 0.5000 0.0500 44 0.5000 Min 4.200 2.290 3.650 0.331 0.661 Max 4.570 3.040 3.700 0.533 0.812 0.101 0.0201 0.6850 0.6500 0.5902 - 0.6850 0.6500 0.5902 - - 0.6949 0.6560 0.6299 - 0.6949 0.6559 0.6299 - - Typ Min 0.1654 0.0902 0.1437 0.0130 0.0260 Max 0.1799 0.1197 0.1457 0.0210 0.0320 0.0040 inches
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Figure 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
L
Table 16. PTSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 13.80 12.30 9.90 - 0.50 0 40 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 14.20 12.50 10.10 - 0.70 5 0.0197 0.0020 0.0374 0.0067 0.0039 0.5433 0.4843 0.3898 - 0.0197 0 40 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.5591 0.4921 0.3976 - 0.0276 5 inches
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ORDERING INFORMATION SCHEME
Table 17. Ordering Information Scheme
Example: Device Type M29 Operating Voltage F = VCC = 5V 10% Device Function 102BB = 1 Mbit (64Kb x16), Bottom Boot Block Speed 35 = 35ns 45 = 45 ns 50 = 50 ns 55 = 55 ns 70 = 70 ns Package K = PLCC44 N = TSOP40:10 x 14mm Temperature Range 1 = 0 to 70 C Option T = Tape & Reel Packing F = Lead-free and RoHS Package, Tape & Reel Packing M29F102BB 50 N 1 T
Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content bits erased to `1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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REVISION HISTORY
Table 18. Revision History
Date July 1999 Version 1.0 First Issue New document template Status Register bit DQ5 clarification Data Polling Flowchart diagram change (Figure 5.) Data Toggle Flowchart diagram change ( Figure 6.) Document restructured. PLCC44 and TSOP40 Lead-free options added: SUMMARY DESCRIPTION, SIGNAL DESCRIPTIONS updated with Lead-free packages, TLEAD parameter added in Table 7., Absolute Maximum Ratings (1) and Lead-free option added in Table 17., Ordering Information Scheme. Revision Details
28-Jul-00
2.0
30-Nov-2004
3.0
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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