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Preliminary P521-39 Low Phase Noise LVDS VCXO (65MHz to 130MHz) FEATURES * 65MHz to 130MHz Fundamental Mode Crystal. * Output range: 65MHz - 130MHz. * Complementary LVDS outputs. * Selectable OE Logic (enable high or enable low). * Integrated variable capacitors. * High pull linearity: < 5%. * +/- 125 ppm pull range www..com * Supports 2.5V or 3.3V-Power Supply. * Available in die form. * Thickness 10 mil. DIE CONFIGURATION 57.5 mil VDDOSC OSCOFF OESEL V N/C N/C (1460,1435) GNDOSC VCON XIN 18 17 16 15 14 13 12 VDDANA VDDBUF VDDBUF PECLBAR PECL GNDBUF 19 11 20 10 9 8 56.5 mil XOUT OE 21 7 22 1 2 3 4 5 6 GNDOSC GNDANA GNDANA VCON GNDBUF Y (0,0) DESCRIPTIONS P521-39 is a VCXO IC specifically designed to pull high frequency fundamental crystals. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. The chip provides a low phase noise, low jitter LVDS differential clock output. X DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Thickness Value 56.5 x 57.5 mil GND 80 micron x 80 micron 10 mil BLOCK DIAGRAM OE VCON Oscillator X+ XQ Q OUTPUT ENABLE LOGIC SELECTION OESEL (Pad #14) 0 (Default) OECTRL (Pad #22) 0 1 (Default) 0 (Default) 1 State Tri-state Output enabled Output enabled Tri-state Amplifier w/ integrated varicaps P521-39 1 Pad #14, 22: Bond to GND to set to "0", bond to VDD to set to "1" No connection results to "default" setting through internal pull-up/-down. Pad #22: Logical states defined by CMOS VIH and VIL levels. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 GNDBUF Rev 3/02/04 Page 1 Preliminary P521-39 Low Phase Noise LVDS VCXO (65MHz to 130MHz) PAD ASSIGNMENT AND DESCRIPTION Pad # 1 2 3 4 www..com Name VCON GNDOSC GNDANA GNDANA GNDBUF GNDBUF GNDBUF (optional) LVDS LVDSBAR VDDBUF (optional) X ( m) 329.6 498.3 696.2 825.0 973.6 1150.0 1183.6 1183.6 1183.6 1182.4 Y ( m) 110.1 110.0 110.0 110.0 110.0 109.1 302.2 452.3 613.5 745.9 Description Control Voltage input. Use this pin to change the output frequency by varying the applied Control Voltage. GND connection for oscillator circuitry. GND connection for analog circuitry. GND connection for analog circuitry. GND connection for output buffer circuitry. GND connection for output buffer circuitry. GND connection for output buffer circuitry. PECL output PECL complementary output. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. VDD connection for analog circuitry. VDDANA should be separately decoupled from other VDDs whenever possible. Selector input to choose the OE control logic. See table on page 1. VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. Oscillator Off Selection input pad. When low, turns off the oscillator when output is disabled. When high (default), oscillator running when output is disabled. Internal pull-up GND connection for oscillator circuitry. Control Voltage input. Use this pin to change the output frequency by varying the applied Control Voltage (internally connected to pad 1). Crystal oscillator input pad. Crystal oscillator output pad. OE input pad. See table on page 1. 5 6 7 8 9 10 11 VDDBUF 1252.4 903.6 12 13 14 15 16 17 18 19 20 21 22 VDDANA Not used OESEL VDDOSC Not used OSCOFF GNDOSC (optional) VCON XIN XOUT OECTRL 1252.4 1058.5 864.5 624.0 467.1 271.1 109.4 108.9 109.0 108.6 108.6 1081.3 1221.6 1221.6 1222.7 1222.6 1222.6 1222.9 1062.1 865.8 358.4 146.5 Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 3/02/04 Page 2 Preliminary P521-39 Low Phase Noise LVDS VCXO (65MHz to 130MHz) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc www..com SYMBOL VDD VI VO TS TA TJ MIN. VSS-0.5 VSS-0.5 -65 0 MAX. 7 VDD+0.5 VDD+0.5 150 70 125 260 2 UNITS V V V C C C C kV Storage Temperature Ambient Operating Temperature Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Crystal Pullability Recommended ESR SYMBOL FXIN CL (xtal) C0 C0/C1 (xtal) RE AT cut AT cut CONDITIONS Parallel Fundamental Mode Die at VCON = 1.65V MIN. 65 TYP. MAX. 130 UNITS MHz pF 7.5 3.5 250 30 pF 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW 0V VCON 3.3V, -3dB 25 SYMBOL TVCXOSTB CONDITIONS From power valid XTAL C0/C1 < 250 0V VCON 3.3V at room temperature VCON = 0 to 3.3V MIN. 250* TYP. 10 MAX. UNITS ms ppm 80* 4 - 18* 4* 65 60 5* ppm pF % ppm/V k kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 3/02/04 Page 3 Preliminary P521-39 Low Phase Noise LVDS VCXO (65MHz to 130MHz) 4. General Electrical Specifications PARAMETERS Supply Current (Loaded Outputs) Output valid after OE enabled Operating Voltage www..com SYMBOL IDD CONDITIONS at 3.3V @ 77.76MHz Oscillator off Oscillator on MIN. TYP. 10 MAX. 40 UNITS mA ms V % mA 1 2.25 3.63 50 50 55 VDD @ 1.25V (LVDS) Output Clock Duty Cycle Short Circuit Current 45 5. Jitter specifications PARAMETERS Period jitter RMS at 77.76MHz Period jitter peak-to-peak at 77.76MHz Accumulated jitter RMS at 77.76MHz Accumulated jitter peak-to-peak at 77.76MHz Random Jitter Integrated jitter RMS at 77.76MHz Measured on Wavecrest SIA 3000 CONDITIONS At 77.76MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 77.76MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. "RJ" measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz MIN. TYP. 2.5 18.5 2.5 24 2.5 0.5 MAX. 20 UNITS ps 27 ps ps 0.7 ps 6. Phase noise specifications PARAMETERS Phase Noise relative to carrier FREQUENCY 77.76MHz 10Hz -75 100Hz -100 1kHz -125 10kHz -140 100kHz -145 1MHz -150 UNITS dBc/Hz Note: Phase Noise measured at VCON = 0V 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 3/02/04 Page 4 Preliminary P521-39 Low Phase Noise LVDS VCXO (65MHz to 130MHz) 7. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage www..com Offset Voltage SYMBOL VOD VOD VOH VOL VOS VOS IOXD IOSD CONDITIONS MIN. 247 -50 TYP. 355 MAX. 454 50 UNITS mV mV V V V mV uA mA RL = 100 (see figure) 1.4 0.9 1.125 0 1.1 1.2 3 1 -5.7 1.6 1.375 25 10 -8 Offset Magnitude Change Power-off Leakage Output Short Circuit Current Vout = VDD or GND VDD = 0V 8. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time LVDS Levels Test Circuit OUT SYMBOL tr tf CONDITIONS RL = 100 CL = 10 pF (see figure) MIN. 0.2 0.2 TYP. 0.7 0.7 MAX. 1.0 1.0 UNITS ns ns LVDS Switching Test Circuit OUT 50 CL = 10pF VOD VOS VDIFF RL = 100 50 CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 20% 0V 80% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 3/02/04 Page 5 Preliminary P521-39 Low Phase Noise LVDS VCXO (65MHz to 130MHz) ORDERING INFORMATION www..com The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PART NUMBER P521-39 PART NUMBER DC TEMPERATURE C=COMMERCIAL D=DIE PACKAGE TYPE Order Number P521-39DC Marking P521-39DC Package Option Die - Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 3/02/04 Page 6 |
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