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CM2030 HDMI Transmitter Port Protection and Interface Device
Features
* * * * * * * * * * * HDMI 1.3 compliant Supports thin dielectric and 2-layer boards Minimizes TMDS skew with 0.05pF matching Long HDMI cable support with integrated I2C accelerator Active termination and slew rate limiting for CEC Supports direct connection to CEC microcontroller Integrated I2C level shifting to CMOS level includ ing low logic level voltages Integrated 8kV ESD protection and backdrive pro tection on all external I/O lines Integrated overcurrent output protection per HDMI 1.3 Multiport I2C support eliminates need for analog mux on DDC lines Simplified layout with matched 0.5mm trace spac ing
Product Description
The CM2030 HDMI Transmitter Port Protection and Interface Device is specifically designed for next gener ation HDMI Host interface protection. An integrated package provides all ESD, slew rate lim iting on CEC line, level shifting/isolation, overcurrent output protection and backdrive protection for an HDMI port in a single 38-Pin TSSOP package. The CM2030 part is specifically designed to provide the designer with the most reliable path to HDMI 1.3 CTS compliance. The CM2030 also incorporates a silicon overcurrent protection device for +5V supply voltage output to the connector.
Applications
* * PC and consumer electronics Set top box, DVD RW, PC, graphics cards
Electrical Schematic
5V_SUPPLY TMDS_D2+ TMDS_GND TMDS_D2 TMDS_D1+ TMDS_GND TMDS_D1 TMDS_D0+ TMDS_GND TMDS_D0 TMDS_CK+ TMDS_GND TMDS_CK
5V_SUPPLY LV_SUPPLY LV_SUPPLY
5V_SUPPLY
DYNAMIC PULLUP DDC_CLK_OUT
DDC_DAT_IN
DYNAMIC PULLUP DDC_DAT_OUT
DDC_CLK_IN
CMOS/I2C LEVEL SHIFT
CMOS/I2C LEVEL SHIFT
CE_SUPPLY
LV_SUPPLY IS
CE_SUPPLY
ACTIVE SLEW RATE LIMITING CE_REMOTE_OUT
HOTPLUG_DET_IN
3IS
HOTPLUG_DET_OUT
CE_REMOTE_IN
5V_SUPPLY
55mA OVERCURRENT SWITCH
5V_OUT
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CM2030
PACKAGE / PINOUT DIAGRAM
TOP VIEW
5V_SUPPLY LV_SUPPLY GND TMDS_D2+ TMDS_GND TMDS_D2- TMDS_D1+ TMDS_GND TMDS_D1- TMDS_D0+ TMDS_GND TMDS_D0- TMDS_CK+ TMDS_GND TMDS_CK- CE_REMOTE_IN DDC_CLK_IN DDC_DAT_IN HOTPLUG_DET_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 5V_OUT CE_SUPPLY GND TMDS_D2+ TMDS_GND TMDS_D2- TMDS_D1+ TMDS_GND TMDS_D1- TMDS_D0+ TMDS_GND TMDS_D0- TMDS_CK+ TMDS_GND TMDS_CK- CE_REMOTE_OUT DDC_CLK_OUT DDC_DAT_OUT HOTPLUG_DET_OUT
Note: This drawing is not to scale.
38-PIN TSSOP PACKAGE
PIN DESCRIPTIONS
PINS 4, 35 6, 33 7, 32 9, 30 10, 29 12, 27 13, 26 15, 24 16 23 17 22 18 21 19 20 2 37 1 NAME TMDS_D2+ TMDS_D2- TMDS_D1+ TMDS_D1- TMDS_D0+ TMDS_D0- TMDS_CK+ TMDS_CK- CE_REMOTE_IN CE_REMOTE_OUT DDC_CLK_IN DDC_CLK_OUT DDC_DAT_IN DDC_DAT_OUT HOTPLUG_DET_IN HOTPLUG_DET_OUT LV_SUPPLY CE_SUPPLY 5V_SUPPLY ESD Level 8kV 8kV
3
DESCRIPTION TMDS 0.9pF ESD protection.1 TMDS 0.9pF ESD protection.1 TMDS 0.9pF ESD protection.1 TMDS 0.9pF ESD protection.1 TMDS 0.9pF ESD protection.1 TMDS 0.9pF ESD protection.1 TMDS 0.9pF ESD protection.1 TMDS 0.9pF ESD protection.1 CE_SUPPLY referenced logic level in. 5V_SUPPLY referenced logic level out plus 10pF ESD.6 LV_SUPPLY referenced logic level in. 5V_SUPPLY referenced logic level out plus 10pF ESD.6 LV_SUPPLY referenced logic level in. 5V_SUPPLY referenced logic level out plus 10pF ESD.6 LV_SUPPLY referenced logic level in. 5V_SUPPLY referenced logic level out plus 10pF ESD. A 0.1F bypass ceramic capacitor is recommended on this pin.2 Bias for CE / DDC / HOTPLUG level shifters. CEC bias voltage. Previously CM2020 ESD_BYP pin. Current source for 5V_OUT, VREF for DDC I2C voltage references, and bias for 8kV ESD pins.
8kV3
3
8kV3 8kV3 8kV3 8kV3 8kV3 2kV4 8kV3 2kV4 8kV3 2kV4 8kV3 2kV4 8kV3 2kV4 2kV4,2 2kV4
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CM2030
PIN DESCRIPTIONS (CONTINUED)
38 3, 5, 8, 11, 14, 25, 28, 31, 34, 36 5V_OUT GND / TMDS_GND 8kV3 N/A 55mA minimum overcurrent protected 5V output. This output must be bypassed with a 0.1F ceramic capacitor. GND reference.
Note 1: These 2 pins need to be connected together in-line on the PCB. See recommended layout diagram. Note 2: This output can be connected to an external 0.1F ceramic capacitor/pads to maintain backward compatibility with the CM2020. Note 3: Standard IEC 61000-4-2, CDISCHARGE=150pF, RDISCHARGE=330, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1F ceramic capacitor connected to GND. Note 4: Human Body Model per MIL-STD-883, Method 3015, CDISCHARGE=100pF, RDISCHARGE=1.5k, 5V_SUPPLYand LV_SUPPLY within recommended operating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1F ceramic capacitor connected to GND. Note 5: These pins should be routed directly to the associated GND pins on the HDMI connector with single point ground vias at the connector. Note 6: The slew-rate control and active acceleration circuitry dynamically offsets the system capacitive load on these pins.
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CM2030
Backdrive Protection and Isolation
Backdrive current is defined as the undesirable current flow through an I/O pin when that I/O pin's voltage exceeds the related local supply voltage for that cir cuitry. This is a potentially common occurrence in mul timedia entertainment systems with multiple components and several power plane domains in each system. For example, if a DVD player is switched off and an HDMI connected TV is powered on, there is a possibil ity of reverse current flow back into the main power supply rail of the DVD player from pull-ups in the TV. As little as a few milliamps of backdrive current flowing back into the power rail can charge the DVD player's bulk bypass capacitance on the power rail to some intermediate level. If this level rises above the poweron-reset (POR) voltage level of some of the integrated circuits in the DVD player, then these devices may not reset properly when the DVD player is turned back on. If any SOC devices are incorporated in the design which have built-in level shifter and/or ESD protection structures, there can be a risk of permanent damage due to backdrive. In this case, backdrive current can forward bias the on-chip ESD protection structure. If the current flow is high enough, even as little as a few milliamps, it could destroy one of the SOC chip's inter nal DRC diodes, as they are not designed for passing DC. To avoid either of these situations, the CM2030 was designed to block backdrive current, guaranteeing less than 5A into any I/O pin when the I/O pin voltage exceeds its related operating CM2030 supply voltage.
LV_SUPPLY =OFF
+5V
+5V LV_SUPPLY =OFF
LOW VOLTAGE HDMI ASIC
ASIC
LOW VOLTAGE HDMI ASIC
ASIC
HDMI SOURCE
HDMI SINK
HDMI SOURCE
HDMI SINK
Figure 1. Backdrive Protection Diagram.
Display Data Channel (DDC) lines
The DDC interface is based on the I2C serial bus proto col for EDID configuration. DYNAMIC PULLUPS Based on the HDMI specification, the maximum capac itance of the DDC line can approach 800pF (50pF from source, 50pF from sink, and 700pF from cable). At the upper range of capacitance values (i.e. long cables), it becomes impossible for the DDC lines to meet the I2C timing specifications with the minimum pull-up resistor of 1.5k. For this reason, the CM2030 was designed with an internal I2C accelerator to meet the AC timing specifi cation even with very long and non-compliant cables. The internal accelerator increases the positive slew rate of the DDC_CLK_OUT and DDC_DAT_OUT lines whenever the sensed voltage level exceeds 0.3*5V_SUPPLY (approximately 1.5V). This provides faster overall risetime in heavily loaded situations with out overloading the multi-drop open drain I2C outputs elsewhere.
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CM2030
DYNAMIC PULLUPS (CONT'D)
Figure 2. Dynamic DDC Pullups (Discrete - Top, CM2030 - Bottom; 3.3V ASIC - Left, 5V Cable - Right.) Figure 2 demonstrates the "worst case" operation of the dynamic CM2030 DDC level shifting circuitry (bot tom) against a discrete NFET common-gate level shifter circuit with a typical 1.5k pullup at the source (top.) Both are shown driving an off-spec, but unfortu nately readily available 31m HDMI cable which exceeds the 700pF HDMI specification. Some widely available HDMI cables have been measured at over 4nF. When the standard I/OD cell releases the NFET dis crete shifter, the risetime is limited by the pullup and the parasitics of the cable, source and sink. For long cables, this can extend the risetime and reduce the margin for reading a valid "high" level on the data line. In this case, an HDMI source may not be able to read uncorrupted data and will not be able to initiate a link. With the CM2030's dynamic pullups, when the ASIC driver releases its DDC line and the "OUT" line reaches at least 0.3*VDD (of 5V_SUPPLY), then the "OUT" active pullups are enabled and the CM2030 takes over driving the cable until the "OUT" voltage approaches the 5V_SUPPLY rail. The internal pass element and the dynamic pullups also work together to damp reflections on the longer cables and keep them from glitching the local ASIC. I2C LOW LEVEL SHIFTING In addition to the Dynamic Pullups described in the previous section, the CM2030 also incorporates improved I2C low-level shifting on the DDC_CLK_IN and DDC_DAT_IN lines for enhanced compatibility. Typical discrete NFET level shifters can advertise specifications for low RDS[on], but usually state rela tively high V[GS] test parameters, requiring a 'switch' signal (gate voltage) as high as 10V or more. At a sink current of 4mA for the ASIC on DDC_XX_IN, the CM2030 guarantees no more than 140mV increase to DDC_XX_OUT, even with a switching control of 2.5V on LV_SUPPLY. When I2C devices are driving the external cable, an internal pulldown on DDC_XX_IN guarantees that the VOL seen by the ASIC on DDC_XX_IN is equal to or lower than DDC_XX_OUT. Multiport DDC Multiplexing By switching LV_SUPPLY, the DDC/HPD blocks can be independently disabled by engaging their inherent "backdrive" protection. This allows N:1 multiplexing of the low-speed HDMI signals without any additional FET switches.
Consumer Electronics Control (CEC)
The Consumer Electronics Control (CEC) line is a high level command and control protocol, based on a single wire multidrop open drain communication bus running at approximately 1kHz (See Figure 3). While the HDMI link provides only a single point-to-point connection, up
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CM2030
to ten (10) CEC devices may reside on the bus, and they may be daisy chained out through other physical connectors including other HDMI ports or other dedi cated CEC links. The high level protocol of CEC can be implemented in a simple microcontroller or other inter face with any I/OD (input/open-drain) GPIO. levels and HDMI slew-rate and isolation specifications (See Figure 5).
CEC CEC RX TX I/OD GPIO CEC I/F P
CM2030
Figure 3. Typical C I/OD Driver To limit possible EMI and ringing in this potentially complex connection topology, the rise- and fall-time of this line are limited by the specification. However, meeting the slew-rate limiting requirements with addi tional discrete circuitry in this bi-directional block is not trivial without an additional RX/TX control line to limit the output slew-rate without affecting the input sensing (See Figure 4).
Figure 5. Integrated CM2030 Solution The CM2030 also includes an internal backdrive pro tected static pullup 120A current source from the CE_SUPPLY rail in addition to the dynamic slew rate control circuitry. Figure 6 shows a typical shaped CM2030 CEC output (bottom) against a ringing uncontrolled discrete solu tion (top).
CEC RX TX TX_EN Slew Rate Limited 3-State Buffer
Figure 4. Three-Pin External Buffer Control Simple CMOS buffers cannot be used in this applica tion since the load can vary so much (total pullup of 27k to less than 2k, and up to 7.3nF total capaci tance.) The CM2030 targets an output drive slew-rate of less than 100mV/s regardless of static load for the CEC line. Additionally, the same internal circuitry will perform active termination, thus reducing ringing and overshoot in entertainment systems connected to leg acy or poorly designed CEC nodes. The CM2030's bi-directional slew rate limiting is inte grated into the CEC level-shifter functionality thus allowing the designer to directly interface a simple low voltage CMOS GPIO directly to the CEC bus and simultaneously guarantee meeting all CEC output logic
Figure 6. CM2030 CEC Output
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CM2030
Hotplug Detect Logic
The CM2030 ensures that the local ASIC will properly detect an HDMI compliant Sink. The current sink main tains a local logic "low" when no system is connected.
CM2030
5V_SUPPLY
A valid pullup on the HDMI connector pin will overdrive the internal pulldown and deliver a logic "high" to the local ASIC.
LV_SUPPLY IS
HP_IN
3IS
HP_OUT
19
HDMI CONN
Figure 7. Hotplug Detect Circuit
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CM2030
Ordering Information
PART NUMBERING INFORMATION
Lead-free Finish Pins 38 Package TSSOP-38 Ordering Part Number1 CM2030-A0TR Part Marking CM2030-A0TR
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER VCC5, VCCLV DC Voltage at any Channel Input Storage Temperature Range RATING 6.0 [GND - 0.5] to [VCC + 0.5] -65 to +150 UNITS V V C
STANDARD (RECOMMENDED) OPERATING CONDITIONS
SYMBOL 5V_SUPPLY LV_SUPPLY CE_SUPPLY PARAMETER Operating Supply Voltage Bias Supply Voltage Bias Supply Voltage Operating Temperature Range 1 3 -40 MIN TYP 5 3.3 3.3 MAX 5.5 5.5 3.6 85 UNITS V V V C
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL ICC5 PARAMETER Operating Supply Current CONDITIONS 5V_SUPPLY = 5.0V, CEC_OUT = 3.3V, LV_SUPPLY= CE_SUPPLY= 3.3V, DDC=5V; Note 7 LV_SUPPLY=3.3V; Note 7 CE_SUPPLY=3.3V, CEC_OUT=0V; Note 7 5V_SUPPLY=5.0V, IOUT=55mA 5V_SUPPLY=5.0V, 5V_OUT=GND LV_SUPPLY=0V; Note 2 CE-REMOTE_IN = CE_SUPPLY < CE_REMOTE_OUT All Supplies = 0V; TMDS_[2:0]+/-, TMDS_CK+/- = 4V 90 MIN TYP 300 MAX 350 UNITS A
ICCLV ICCCE VDROP ISC IOFF IBACKDRIVECEC
Bias Supply Current Bias Supply Current 5V_OUT Overcurrent Out put Drop 5V_OUT Short Circuit Cur rent Limit OFF state leakage current, level shifting NFET Current through CE-REMOTE_OUT when powered down Current through TMDS pins when powered down
60 60 65 135 0.1 0.1
150 150 100 175 5 1.8
A A mV mA A A
IBACKDRIVETMDS
0.1
5
A
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CM2030
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
IBACKDRIVE5V_OUT Current through 5V_OUT when powered down Current through DDC_DAT/CLK_OUT when powered down Current through HOTPLUG_DET_OUT when powered down CEC Slew Limit CEC Rise Time All Supplies = 0V; 5V_OUT_PIN = 5V All Supplies = 0V; DDC_DAT/CLK_OUT = 5V; DDC_DAT/CLK_IN = 0V All Supplies = 0V; HOTPLUG_DET_OUT = 5V; HOTPLUG_IN = 0V Measured from 10-90% or 90-10% Measured from 10-90% Assumes a signal swing from 0 3.3V Measured from 90-10% Assumes a signal swing from 0 3.3V Voltage is 0.3 10% X 5V_Supply; Note 2 LV_SUPPLY=3.3V, 3mA Sink at DDCIN, DDCOUT < VACC DDC_OUT=0.4V, LV_SUPPLY=3.3V, 1.5k pullup on DDC_OUT to 5.0V; Note 2 DDC_IN floating, LV_SUPPLY=3.3V, 1.5k pullup on DDC_OUT to 5.0V, Bus Capacitance = 1500pF IF = 8mA, TA = 25C; Note 2 0.6 0.6 Pins 4, 7, 10, 13, 20, 21, 22, 23, 24, 27, 30, 33, TA = 25C; Notes 2 and 3 Pins 1, 2, 16, 17, 18, 19, 37, 38, TA = 25C; Note 2 TA=25C, IPP = 1A, tP = 8/20S; Notes 2 & 6 TA=25C, IPP = 1A, tP = 8/20S Any I/O pin to Ground; Note 6 TA = 25C; Note 2 5V_SUPPLY=5.0V, Measured at 1MHz, VBIAS=2.5V; Note 2 0.85 0.85 0.95 0.95 V V kV 26.4 0.1 5 A
IBACKDRIVEDDC
0.1
5
A
IBACKDRIVEHOTPLUG
0.1
5
A
CECSL CECRT
0.26
0.65 250
V/s s
CECFT
CEC Fall Time
4
50
s
VACC VON(DDC_OUT) VOL(DDC_IN)
Turn On Threshold of I2C/ DDC Accelerator Voltage drop across DDC level shifter Logic Level (ASIC side) when I2C/DDC Logic Low Applied;
(I2C pass-through compatibility)
1.35
1.5 150 0.3
1.65 225 0.4
V mV V
tr(DDC)
DDC_OUT Line Risetime, VACC < VDDC_OUT < (5V_Supply-0.5V) Diode Forward Voltage Top Diode Bottom Diode ESD Withstand Voltage (IEC) ESD Withstand Voltage (HBM) Channel Clamp Voltage Positive Transients Negative Transients Dynamic Resistance Positive Transients Negative Transients TMDS Channel Leakage Current TMDS Channel Input Capacitance
1
s
VF
VESD
8 2
11.0 -2.0 1.4 0.9 0.01 0.9 1 1.2
VESD VCL
kV
V V A pF
RDYN
ILEAK CIN, TMDS
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CM2030
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) CIN, TMDS
CMUTUAL TMDS Channel Input Capacitance Matching 5V_SUPPLY=5.0V, Measured at 1MHz, VBIAS=2.5V; Notes 2 and 5 0.05 0.07 pF pF
Mutual Capacitance 5V_SUPPLY=0V, Measured at between signal pin and adja 1MHz, VBIAS=2.5V; Note 2 cent signal pin Level Shifting Input Capaci tance, Capacitance to GND 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=2.5V; Note 2 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=1.65V; Note 2 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=2.5V; Note 2
CIN, DDCOUT
10
pF
CIN, CECOUT
Level Shifting Input Capaci tance, Capacitance to GND
10
pF
CIN, HPOUT
Level Shifting Input Capaci tance, Capacitance to GND
10
pF
Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. Note 2: This parameter is guaranteed by design and verified by device characterization. Note 3: Standard IEC61000-4-2, CDISCHARGE=150pF, RDISCHARGE=330, 5V_SUPPLY=5V, 3.3V_SUPPLY=3.3V, LV_SUPPLY=3.3V, GND=0V. Note 4: Human Body Model per MIL-STD-883, Method 3015, CDISCHARGE=100pF, RDISCHARGE=1.5k, 5V_SUPPLY=5V, 3.3V_SUPPLY=3.3V, LV_SUPPLY=3.3V, GND=0V. Note 5: Intra-pair matching, each TMDS pair (i.e. D+, D-) Note 6: These measurements performed with no external capacitor on VP (VP floating) Note 7: These static measurements do not include AC activity on controlled I/O lines
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CM2030
Performance Information
Typical Filter Performance (TA=25C, DC Bias=0V, 50 Ohm Environment)
Figure 8. Insertion Loss vs. Frequency (TMDS_D1- to GND)
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CM2030
Application Information
ROPT(See NOTE 4) 5V_OUT
5V_SUPPLY LV_SUPPLY
CM2020/2030
1 2 3 4
TMDS_D2+ TMDS_D2-
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
VCEC CBYP
100nF
TMDS_D2+ TMDS_GND TMDS_D2- TMDS_D1+ TMDS_GND TMDS_D1- TMDS_D0+ TMDS_GND TMDS_D0- TMDS_CK+ TMDS_GND TMDS_CK- CE_REMOTE N/C DDC_CLK DDC_DAT
NOTE 1
{
5 6 7
TMDS_D1+ TMDS_D1-
8 9 10
TMDS_D0+ TMDS_D0-
11 12 13
TMDS_CK+ TMDS_CK- ASIC_CEC2 ASIC_SCL2 ASIC_SDA2
14 15 16 17 18 19
HOTPLUG_DETECT2
NOTE 3
GND +5V OUT HOTPLUG_DET
DCEC
HDMI Connector
RCEC
EEPROM_CLK
VCEC
EEPROM_DAT
27k
CEC
RDAT
2k
RSCL
2k
RPD CHP 15k 100nF
CVOUT
100nF
Figure 9. Typical Application for CM2030 LAYOUT NOTES
1
Differential TMDS Pairs should be designed as normal 100 HDMI Microstrip. Single Ended (decoupled) TMDS traces underneath MediaGuardTM, and traces between MediaGuardTM and Connector should be tuned to match chip/connec tor IBIS parasitics. (See MediaGuardTM Layout Application Notes.)
avoid placing any silk-screen printing over TMDS traces. CM2020/CM2030 footprint compatibility. For the CM2030, Pin 37 becomes the VCEC power supply pin for the slew-rate limiting circuitry. This can be supplied by a 0 jumper to VCEC which should be depopulated to uti lize the CM2020. The 100nF CBYP is recommended for all applications.
4
Level Shifter signals should be biased with a weak pullup to the desired local LV_SUPPLY. If the local ASIC includes sufficient pullups to register a logic high, then external pullups may not be needed.
2 3
Place MediaGuardTM as close to the connector as pos sible, and as with any controlled impedance line always
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CM2030
Application Information
Design Considerations
1. 5V out (pin 38)
Maximum overcurrent protection output drop at 55mA on 5V_OUT is 100mV. To meet HDMI output require ments of 4.8-5.3V, an input of greater than 4.9V should be used (i.e. 5.1V 4%)
figurations can be forward biased when their VDD rail is lower than the I/O pin bias, thereby exhibiting extremely high apparent capacitance measurements, for example. The MediaGuard backdrive isolation circuitry limits this current to less than 5A, and will help ensure HDMI compliance.
2. DUT On vs. DUT Off
Many HDMI CTS tests require a power off condition on the System Under Test. Many discrete ESD diode con
Please review all of the current HDMI design guidelines available at:
http://www.calmicro.com/applications/customer/downloads/current-cmd-mediaguard-design-guidelines.zip
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CM2030
Mechanical Details
TSSOP-38 Mechanical Specifications CM2030 devices are supplied in 38-pin TSSOP pack ages. Dimensions are presented below. Mechanical Package Diagrams
PACKAGE DIMENSIONS
Package JEDEC No. Pins Dimensions A A1 b c D E E1 e L # per tape and reel Millimeters Min -- 0.05 0.17 0.09 9.60 4.30 0.45 Max 1.20 0.15 0.27 0.20 9.80 4.50 0.75 Min -- 0.002 0.007 0.004 0.378 0.169 0.018 TSSOP MO-153 (Variation BD-1) 38 Inches Max 0.047 0.006 0.011 0.008 0.386 0.177 0.030
A
SEATING PLANE SIDE VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 TOP VIEW
D
33 32 31 30 29 28 27 26 25 24 23 22 21 20
E
Pin 1 Marking
E1
6.40 BSC 0.50 BSC
0.252 BSC
A1 b e
0.020 BSC 2500 pieces
END VIEW
Controlling dimension: millimeters
c
L
Package Dimensions for TSSOP-38
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14
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214 Issue A - 11/16/07
Fax: 408.263.7846
www.cmd.com

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Price & Availability of CM2030

	To Download CM2030 Datasheet File
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