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PRODUCT SPECIFICATION
1
Z90102/103/104
40-PIN LOW-COST DIGITAL TELEVISION CONTROLLER
FEATURES 8-Bit CMOS Microcontroller for Consumer Television, Cable and Satellite Receiver Applications.
Device Z90102 Z90103 Z90104 ROM (KB) 4 6 8 RAM* (Bytes) 236 236 236 I/O 24 24 24
s s
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Clock Speed up to 4 MHz On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC or External Clock Drive Permanently Enabled Watch-Dog/Power-On Reset Timer 3K x 6-Bit Character Generator ROM 120 x 7-Bit Video RAM Mask Programmable 96-Character Set Display. The 90102 and 90103 6-Row x 20 Column Format, 12x15 Pixel Character Cell. The 90104 8-Row x 20 Column Format 12x15 Pixel Character Cell. The 90102, 90103 90104 Capable of supporting English, Korean, Thai, Chinese and Japanese High Resolution Characters. Fully Programmable Color Attributes Including Row Character, Row Background/Fringes, Frame Background/Position, Bar Graph Color Change, and Character Size. Programmable Display Position and Character Size Control One Pulse Width Modulator (14-Bit Resolution) for Voltage Synthesis Tuner Control. Three Pulse Width Modulator (8-Bit Resolution) for Picture Control Three Pulse Width Modulators (6-Bit Resolution) for Audio Control
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s s s
Note: *General-Purpose s s s s s s
Lowest Cost DTC Family Member Low Power Consumption Fast Instruction Pointer - 1.5 ms @ 4 MHz Two Standby Modes - STOP and HALT Low Voltage Detection/Voltage Sensitive Reset Port 2 (8-Bit Programmable I/O) and Port 3 (2-Bit Input, 3-Bit Output) Register Mapped Ports Port 6 (6-Bit Input and Tristate Comparator AFC Input) Memory Mapped I/O Ports All Digital CMOS Levels Schmitt-Triggered Two Programmable 8-Bit Counter/Timers each with 6Bit Programmable Prescaler. Six Vectored, Priority Interrupts from Six Different Sources
s s
s
s
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GENERAL DESCRIPTION
The Z90102/3/4 40-pin Low-Cost Digital Television Controller are members of the Z8(R)STOP Mode MCU singlechip family with 4, 6, and 8 KB of ROM and 236 bytes of RAM. The device is offered in a 40-pin package and is DS97TEL1902 CMOS compatible. The DTC offers mask programmed ROM which enables the Z8(R) MCU to be used in a high volume production application device embedded with a custom program (customer supplied program) and combines 1
Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
Zilog
GENERAL DESCRIPTION (Continued)
together with the Z86C27 and Z86127 to provide support for mid range and low end TV applications. Zilog's DTC offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The device provides an ideal performance and reliability solution for consumer and industrial television applications. The Z90102/3/4 architecture is characterized by utilizing Zilog's advanced SuperintegrationTM design methodology. The device has an 8-bit internal data path controlled by a Z8 microcontroller and On Screen Display (OSD) logic circuits and Pulse Width Modulators (PWM). On-chip peripherals include two register mapped I/O ports (Ports 2 and 3), interrupt control logic (one software, two external and three internal interrupts) and a standby mode recovery input port (Port 3, P30). The OSD control circuits support 6 rows x 20 columns of characters. The character color is specified by row. One of the six rows is assigned to show two kinds of colors for bar type displays such as volume control. The OSD is capable of displaying either low resolution (5 x 7 dot pattern) or high resolution (11 x 15 dot pattern) characters. A 14-bit PWM port provides enough voltage resolution for a voltage synthesizer tuning system. Three 6-bit PWM ports are used for controlling audio signal levels. Three 8bit PWM ports used to vary picture levels. For DTC applications demanding powerful I/O capabilities, the Z90102/3/4 fulfills this with 24 I/O pins dedicated to input and output. These lines are grouped into three ports, and are configurable under software control to provide timing, status signals, parallel I/O and an address/data bus for interfacing to external memory. There are three basic address spaces available to support this wide range of configurations: Program Memory, Video RAM, and Register File. The Register File is composed of 236 bytes of general-purpose registers, two I/O Port registers, 15 control and status registers and three reserved registers. To unburden the program from coping with the real-time problems such as counting/timing and data communication, the DTC offers two on-chip counter/timers with a large number of user selectable modes (Figure 1). Notes: All signals with a preceding front slash, "/", are active Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
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DS97TEL1902
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
XTAL1 XTAL2 /RESET
RESET Oscillator WDT Counter Timer Counter Timer
4, 6 or 8 KB Program ROM Port 2 Z8 CPU Core
P30 P31 P34 P35 P36 P60 P61 P62 P63 P64 P65 AFCIN
P27 P26 P25 P24 P23 P22 P21 P20
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Port 3/ Interrupt 256 Byte Register File PWM 1 14 -bit PWM 1
Port 6 Port 0 A8-15 Port 1 AD0-7
PWM 6 to PWM 8 6-bit
PWM 6 PWM 7 PWM 8
PWM 9 to PWM 11 8-bit
PWM 9 PWM 10 PWM 11
120 Byte Character RAM
On-Screen Display
3 Kbyte Character ROM
OSCIN OSCOUT HSYNC VSYNC VRED VGREEN VBLUE VBLANK
Figure 1. Functional Block Diagram
DS97TEL1902
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
Zilog
PIN DESCRIPTION
PWM1 P35 P36 P34 P31 P30 XTAL1 XTAL2 /RESET P60 GND P61 P62 VCC P63 P64 P65 AFCIN OSCIN OSCOUT
1
21
Z90102 Z90103 Z90104 40-Pin DIP
20
40
PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 P27 P26 P25 P24 P23 P22 P21 P20 VBLANK VBLUE VGREEN VRED VSYNC HSYNC
Figure 2. 40-Pin Mask-ROM Plastic DIP
Table 1. 40-Pin Mask-ROM Plastic DIP 40-Pin 1 2, 3 4 5 6 7 8 9 10 11 12 13 14 15, 16, 17 18 19 20 21 22 23 Name PWM1 P35-36 P34 P31 P30 XTAL1 XTAL2 /RESET P60 GND P61 P62 VCC P63-65 AFCIN OSCIN OSCOUT HSYNC VSYNC Vred Function Pulse Width Modulator 1 Port 3, Pins 5, 6 Port 3, Pin 4 Port 3, Pin 1 Port 3, Pin 0 Crystal Oscillator Crystal Oscillator System Reset Port 6, Pin 0 Ground Port 6, Pin 1 Port 6, Pin 2 Power Supply Port 6, Pins 3, 4, 5 AFC Voltage Level Video Dot Clock Osc Video Dot Clock Osc Horizontal Sync Vertical Sync Video Red Direction Output Output Output Input Input Input Output Input Input Input Input Input Input Input Input Input Output Input Input Output
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller Table 1. 40-Pin Mask-ROM Plastic DIP
40-Pin 24 25 26 27-34 35 36 37 38 39 40
Name Vgreen Vblue Vblank P20-27 PWM11 PWM10 PWM9 PWM8 PWM7 PWM6
Function Video Green Video Blue Video Blank Port 2, Pins 0,1,2,3,4,5,6,7 Pulse Width Modulator 11 Pulse Width Modulator 10 Pulse Width Modulator 9 Pulse Width Modulator 8 Pulse Width Modulator 7 Pulse Width Modulator 6
Direction Output Output Output In/Output Output Output Output Output Output Output
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
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PIN DESCRIPTION
XTAL1, XTAL2. (time-based input, output, respectively). These pins connect to the internal parallel-resonant clock crystal (4 MHz max) oscillator circuit with two capacitors to GND. XTAL1 is also used as an external clock input. SCLK System Clock. SCLK is the internal system clock. It can be used to clock external glue logic. HSYNC (input, Schmitt triggered, CMOS level). Horizontal Sync is an input pin that accepts an externally generated Horizontal Sync signal of either negative or positive polarity. VSYNC (input,Schmitt-triggered, CMOS level). Vertical Sync is an input pin that accepts an externally generated Vertical Sync signal of either negative or positive polarity. OSCIN, OSCOUT (Video Oscillator input, output, respectively). Oscillator input and output pins for on-screen display circuits. These pins connect to an inductor and two capacitors to generate the character dot clock (typically around 6 MHz). The dot clock frequency determines the character pixel width and phase synchronized to HSYNC. Vblank Video Blank (output). CMOS output, programmable polarity. Used as a superimpose control port to display characters from video RAM. The signal controls Y signal output of the CRT and turns off the incoming video display while the characters in video RAM are superimposed on the screen. The red, green, and blue outputs drive the three electron guns on the CRT directly, while the blank output turns off the Y signal. Vblue Video Blue (output). CMOS Output of the Blue video signal (B-Y) and is programmable for either polarity. Vgreen Video Green (output). CMOS Output of the Green video signal (G-Y) and is programmable for either polarity. Vred Video Red (output). CMOS Output of the Red video signal (R-Y) and is programmable for either polarity. Port 2 (P27-P20). Port 2 is an 8-bit port, CMOS-compatible, bit programmable for either input or output. Input buffers are Schmitt triggered. Bits programmed as outputs may be globally programmed as either push pull or opendrain (Figure 9). Port 3 (P30, P31, P34-P36). Port 3, P30 input, is read directly. If appropriately enabled, a negative edge event is latched in IRQ3 to initiate an IRQ3 vectored interrupt. An application could place the device in STOP Mode when P30 goes Low (in the IRQ3 interrupt routine). P30 initiates a STOP Mode recovery when it subsequently goes to a High. Port 3, P31 are read directly. If appropriately enabled, a negative edge event is latched in IRQ2 to initiate an IRQ2 vectored interrupt. P31 High is signified as the TIN signal to Timer1. Port 3, P34 and P35 are general-purpose output lines. Port 3, P36 can be used as a generalpurpose output or as an output for TOUT (from Timer1 or Timer2) or SCLK (Figure 10). Port 6 (P65-P60). Port 6 is a 6-bit, Schmitt triggered CMOS compatible, input port. The outputs of the AFC comparators internally feed into the Port 6, bit 6 and bit 7 inputs (Figure 11). AFCIN (Comparator input port, memory mapped). The input signal is supplied to two comparators with VTH1=2/5 VCC and VTH2=3/5 VCC typical threshold voltage. The comparator outputs are internally connected to Port 6, bit 6 and bit 7. AFCIN is typically used to detect AFC voltage level to accommodate digital automatic fine tuning functions (Figure 12). Pulse Width Modulator 1 (PWM). PWM1 is typically used as the D/A converter for Voltage Synthesis Tuning systems. It is a push-pull output with 14-bit resolution. Pulse Width Modulator 6-8 (PWM). PWM8-PWM6 are Pulse Width Modulators with 6-bit resolution. Pulse Width Modulator 9, 10, 11 (PWM). Pulse Width Modulator circuits with 8-bit resolution. These PWMs are 12 volt, open-drain outputs. Pulse Width Modulator 1, 6, 7, 8 (PWM). Can be programmed as general-purpose outputs. PWM 1 is 5 VOH push-pull, and PWMs 6, 7, 8 are 12 volt open-drain outputs. /RESET System Reset. Code is executed from memory address 000CH after the /RESET pin is set to a high level. The reset function is also carried out by detecting a VCC transition state (automatic Power-On Reset) so that the external reset pin can be permanently tied to VCC. A low level on /RESET forces a restart of the device.
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational secSymbol VCC VI VI VO IOH IOH IOL IOL TA TSTG Parameters Power Supply Voltage* Input Voltage Input Voltage Output Voltage Output Current High Output Current High Output Current Low Output Current Low Operating Temperature Storage Temperature -65 +150 C Min -0.3 -0.3 -0.3 -0.3 tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Max +7 VCC +0.3 VCC +0.3 13.2 -10 -100 20 200
Units V V V V mA mA mA mA
Notes
1 2, 3 1 pin All total 1 pin All total
Notes: 1. Port 2 open-drain 2. PWM open-drain outputs 3. Absolute maximum operating voltage 13.2V. Absolute maximum momentary (non-operating) voltage is 16.0V. * Voltage on all pins with respect to GND. See Ordering Information
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 3).
VDD
RLL
From Output Under Test
150 pF
RLH
Figure 3. Test Load Diagram
DS97TEL1902
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
Zilog
CAPACITANCE TA = 25C; VCC = GND = 0V; Freq =1.0 MHz; unmeasured pins to GND.
Parameter Input capacitance Output capacitance I/O capacitance AFCIN input capacitance Max 10 20 25 10 Units pF pF pF pF
DC CHARACTERISTICS TA = 0C to +70C; VCC = +4.5V to +5.5V; FOSC = 4 MHz
TA = 0C to +70C Sym VIL VILC VIH VIHC VHY VPU VOL V00-01 V01-11 VOH IIR IIL IOL ICC ICC1 ICC2 Parameter Input Voltage Low Input XTAL/Osc In Low Input Voltage High Input XTAL/Osc In High Schmitt Hysteresis Maximum Pull-Up Voltage Output Voltage Low AFC Level 01 In AFC Level 11 In Output Voltage High Reset Input Current Input Leakage Tristate Leakage Supply Current -3.0 -3.0 0.5 VCC VCC -0.4 -80 3.0 3.0 20 6 10 0.7 VCC 0.8 VCC 0.1 VCC 13.2 0.4 0.4 0.45 VCC 0.75 VCC 0.16 0.19 1.9 3.12 4.75 -46 0.01 0.02 13.2 3.2 2.0 Min 0 Max 0.2 VCC 0.07 VCC VCC VCC Typical @ 25C 1.48 0.98 3.0 3.2 0.8 Units V V V V V V V V V V V mA mA mA mA mA mA IOH=-0.75 mA VRL=0V 0V, VCC 0V, VCC All inputs at rail & outputs floating 1, 2 IOL=1.00 mA IOL=0.75 mA 1 External Clock Generator Driven External Clock Generator Driven Conditions
Notes: 1. PWM open-drain 2. Recommended operating voltage 12V with maximum positive tolerance 10%, i.e., 13.2V.
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
AC CHARACTERISTICS Timing Diagrams
1 3
1
XTAL1
3 2
2
Figure 4. External Clock
7
5
TIN
4 6
Figure 5. Counter Timer
IRQN
8
9
Figure 6. Interrupt Request
DS97TEL1902
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
Zilog
VCC
10
11
Internal /RESET
12
External /RESET
Figure 7. Power-On Reset
HSYNC
13
14
OSC2
Figure 8. On-Screen Display
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DS97TEL1902
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
AC CHARACTERISTICS TA = 0 C to +70 C; VCC = +4.5V to +5.5V; FOSC = 4 MHz
No 1 2 3 4 5 6 7 8a 8b 9 10 11 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH TdPOR TdLVIRES Parameter Input Clock Period Clock Input Rise and Fall Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Int Req Input Low Int Request Input High Power On Reset Delay Low Voltage Detect to Internal RESET Condition Reset Minimum Width HSYNC Start to VOSC Stop HSYNC End to VOSC Start WDT Refresh Time Min 250 125 70 3TpC 8TpC 100 70 3TpC 3TpC 25 200 Max 1000 15 Unit ns ns ns ns
1
ns ns
100
ms ns
12 13 14 15
TwRES TdHsOI TdHsOh TdWDT
5TpC 2TpV
3TpV 1TpV 12 ms
Notes: Refer to DC Characteristics for details on switching levels.
DS97TEL1902
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
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FUNCTIONAL DESCRIPTION
The Z8 DTCincorporates special functions to enhance the Z8's versatility in consumer, industrial and television control applications. Pulse Width Modulator (PWM). The has seven PWM channels (Figure 9). There are three types of PWM circuits: PWM1 (one channel of 14-bit resolution) typically used for Voltage Synthesis Tuning, PWM8-PWM6 (three channels of 6-bit resolution) typically used for audio level control, and PWM9, 10, 11 (three channels of 8-bit resolution) typically used for picture level control. The PWM control registers are mapped into external memory and are accessed through LDE and LDEI instructions. PWM1. It is a push-pull output. PWMs 6 through 11. They have their maximum values (on times) when all 1s are loaded in their PWM Value registers (and minimum value for all 0s). PWM1 has a maximum value for all 0s and minimum value for all 1s. On-Screen Display (OSD). The OSD has a capability of displaying 6 rows x 20 columns of 96 kinds of characters for high resolution (11 x 15 dots) patterns (Figures 10 and 11).
/RESET AD7-0 AD7-0
XTAL
14-Bit Binary Down Counter
13-0 Upper 7-Bit 6-0 13-7 13-7 Lower 7-Bit 6-0
PWM Output Port Reg FC11h 7-0
PWM Mod Reg FC10h 7-0
AD7-0
14-Bit PWM1 Reg
FC12-3h
7-Bit Comparator
RS & DFF
0 PWM1 push-pull output
Pulse Distributor
5-0
AD7-0
6-Bit PWM6 Reg
FC18h FC19h FC1Ah
5-0
5-0
RSFF
MPX
PWM6 (open-drain) PWM7 (open-drain)
6-Bit Comparator
RSFF
PWM8 (open-drain) RSFF
7-0
AD7-0
8-Bit PWM9 Reg
FC1Bh FC1Ch FC1Dh
7-0
7-0
8-Bit Comparator
RSFF
PWM9 (open-drain)
RSFF
PWM10 (open-drain)
RSFF
PWM11 (open-drain)
Figure 9. Pulse Width Modulator Block Diagram
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DS97TEL1902
AD7-0 Bar Line Control Register
FC06-7H
AD7-0
Horizontal Position Register
FC02H
5-0 Comparator AD7-0 Data Bus MPX Comparator
AD7-0 1/4 6-Bit Column Address Counter
Reset
OSCIN OSCOUT Horizontal Size Counter 5-Bit
OSC
Reset
HSYNC
HS VS
8-Bit
Video RAM
(20 x 6 x 7)
VSYNC IRQ
ADDR BUS MPX
7-Bit
Character Generator ROM
(96 x 32 x 6)
6-Bit
Main DOT Shift Reg
Sub DOT Shift Reg
VSYNC Vertical Size Counter Row Address Counter
Enable
Polarity Control Reset
3-Bit
1/4 4-Bit
Address INC/DEC/PASS Control Row ATTR Reg
VBLANK RED GREEN Character DOT & Smoothing & Fringe Generator
Figure 10. On-Screen Display Block Diagram
Retrace Timer Comparator 5-0 Vertical Position Register
FC01H
Comparator 4-0 Row Space Control Register
Comparator 3-0 Fade Position Register Display Attribute Register
BLUE
4-5 OSD Control Register
FC00H
2-0
6 AD7-0 AD7-0
FC04H
FC05H
FC03H
AD7-0
AD7-0
AD7-0
Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
The OSD features are as follows:
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characters. LDE or LDEI instructions are required to access the Video RAM (Figure 11).
Character Color: Seven kinds of color are specified on a row basis. Character Pixel Size: Four character pixel sizes are selected for a high resolution (1HL, 2HL, 3HL, and 4HL) Horizontal Line (HL). Polarity Selections: Can select active low or high for horizontal/vertical sync input and RGB outputs. Display Position: Can display 64 vertical positions by 4HL units and 64 horizontal positions by a 4-dot clock. Inter Row Spacing: Inter row vertical line spacing is set from 2HL to 17HL. Fade In/Out Control: Fade position can be determined in vertical direction. Bar Line Type Display: One of the rows is selected to display an analog bar line every half column by setting second color with proper character set. Fringe Function: Fringe off/on and the color selected. Background Color: Eight kinds of color including black background color. ON/OFF Control: Character display, backgrounds are turned on and off. Number of Display Characters: 6 rows x 20 columns. Character Set: 96 (11 x 15 dots).
Hex Address FD00 FD01 FD02 FD13 FD14 FD20 FD21 FD22 FD33 FD34 FD40 FD54 FD60 FD74 FD80 FD94 FDA0 FDB4 Row 6 Video RAM Buffer MSB (7 Bits Wide) LSB Row 1 Attribute (ROW1_ATTR) Row 1 Column 1 Character Data Row 1 Column 2 Through Column 19 Character Data Row 1 Column 20 Character Data Row 2 Attribute (ROW2_ATTR) Row 2 Column 1 Character Data Row 2 Column 2 Through Column 19 Character Data Row 2 Column 20 Character Data Row 3 Video RAM Buffer
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s
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Row 4 Video RAM Buffer
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Row 5 Video RAM Buffer
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Character Generator ROM. The character generator ROM is organized as 3 KB of six bits. The ROM defines either 11 x 15 dot (high resolution) Video RAM. The Video RAM is organized as 8-row arrays (21 x 7 bits each, Figure 11). The first location of each row array contains the attribute for that row. Row attributes include programmable character color, row background color and control for background off/on. The next 20 bytes contain row character data. Each character byte contains the ASCII code in order to select one of the 96 displayable
Figure 11. Video RAM Configuration
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
( 7 Bits Wide) Row 1 Attribute
ROW1 FD00H
ROW2 FD20H
ROW3 FD40H
ROW4 FD60H
ROW5 FD80H
ROW6 FDA0H
1
Row 1 Column 1 Character Row 1 Column 2 Character Row 1 Column 3 Character Row 1 Column 4 Character Row 1 Column 5 Character Row 1 Column 6 Character Row 1 Column 7 Character Row 1 Column 8 Character Row 1 Column 9 Character Row 1 Column 10 Character Row 1 Column 11 Character Row 1 Column 12 Character Row 1 Column 13 Character Row 1 Column 14 Character Row 1 Column 15 Character Row 1 Column 16 Character Row 1 Column 17 Character Row 1 Column 18 Character Row 1 Column 19 Character Row 1 Column 20 Character MSB
FD01H FD02H FD03H FD04H FD05H FD06H FD07H FD08H FD09H FD0AH FD0BH FD0CH FD0DH FD0EH FD0FH FD10H FD11H FD12H FD13H FD14H
FD21H FD22H FD23H FD24H FD25H FD26H FD27H FD28H FD29H FD2AH FD2BH FD2CH FD2DH FD2EH FD2FH FD30H FD31H FD32H FD33H FD34H
FD41H FD42H FD43H FD44H FD45H FD46H FD47H FD48H FD49H FD4AH FD4BH FD4CH FD4DH FD4EH FD4FH FD50H FD51H FD52H FD53H FD54H
FD61H FD62H FD63H FD64H FD65H FD66H FD67H FD68H FD69H FD6AH FD6BH FD6CH FD6DH FD6EH FD6FH FD70H FD71H FD72H FD73H FD74H
FD81H FD82H FD83H FD84H FD85H FD86H FD87H FD88H FD89H FD8AH FD8BH FD8CH FD8DH FD8EH FD8FH FD90H FD91H FD92H FD93H FD94H
FDA1H FDA2H FDA3H FDA4H FDA5H FDA6H FDA7H FDA8H FDA9H FDAAH FDABH FDACH FDADH FDAEH FDAFH FDB0H FDB1H FDB2H FDB3H FDB4H
LSB
Figure 12. Video RAM Map (Write/Read Registers)
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
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FUNCTIONAL DESCRIPTION (Continued)
Hex Address 00 0 01 0 02 0 03 1 04 0 05 0 06 0 07 0 08 1 09 0 0A 1 0B 0 0C 0 0D 0 0E 1 0F 1 10 0 11 0 12 0 13 1 14 1 15 1 16 0 17 1 18 1 19 0 1A 0 1B 1 1C 0 1D 1 1E 1 1F 1 20 3F
Must be 00H at each pattern
0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0
0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0
0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 1 1 1 0 1 1 0 0 1 0 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Left Half
Right Half
High Resolution Character Pattern
FC0 High Resolution Character Pattern FDF FE0 High Resolution Character Pattern FFF MSB LSB (6 Bits Wide)
Figure 13. High Resolution Character ROM Configuration
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Zilog Program Memory. The program ROM size is 6 KB (Figure 14). The IRQ vector table is located in the lower address space. The vector address is fetched after the corresponding interrupt and program control is passed to the specified
Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller vector address. IRQ1 vector is fixed to VSYNC interrupt request and occurs at the leading edge of the filtered VSYNC input. Program memory start at address 000CH after reset.
1
Hex Address 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 17FF 1800 FBFF FC00 FC32 FC33 FCFF FD00 FDB4 FDB5 FFFF Reserved Reserved Reserved Port 6 Input Port (PORT6) Video Refresh RAM Reserved Memory Mapped I/O PWM6 6-Bit Register (PWM6) PWM7 6-Bit Register (PWM7) PWM8 6-Bit Register (PWM8) PWM9 8-Bit Register (PWM9) PWM10 8-Bit Register (PWM10) PWM11 8-Bit Register (PWM11) Reserved Reserved IRQ0 (High Byte) IRQ0 (Low Byte) VSYNC IRQ1 (High Byte) VSYNC IRQ1 (Low Byte) P31 IRQ2 (High Byte) P31 IRQ2 (Low Byte) P30 IRQ3 (High Byte) P30 IRQ3 (Low Byte) T0 IRQ4 (High Byte) T0 IRQ4 (Low Byte) T1 IRQ5 (High Byte) T1 IRQ5 (Low Byte) Reset Start Address On-Chip Program ROM (6 KByte) PWM Mode (PWM_MODE) PWM Output Port (PWM_OUT) PWM1 High 6-Bit (PWM1_HI) PWM1 Low 8-Bit (PWM_LO) OSD Control (OSD_CNTRL) Vertical Position (VERT_POS) Horizontal Position (HOR_POS) Display Attribute (DISP_ATTR) Row Space (ROW_SPACE) Fade Position (FADE_POS) Bar Line Control (BAR_CNTRL) Bar Position (BAR_POS)
Hex Address FC00 FC01 FC02 FC03 FC04 FC05 FC06 FC07
FC10 FC11 FC12 FC13 FC14
Reserved
FC15 FC16 FC17 FC18 FC19 FC1A FC1B FC1C FC1D FC1E FC1F Write Only
FC30 FC31 FC32
Figure 14. Program Memory
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Memory Mapped Register. All control registers and I/O ports (except Port 2 and Port 3) are assigned to program memory space. Address space FC00H contains OSD control registers, PWM output registers and Port 6 I/O registers. Two bits of the decoded AFCIN port are assigned to Port 6 input port. LDE and LDEI instructions are required to transfer data between the Register File and the Memory Mapped Registers. Register File. A total of 253 byte registers are implemented in the Z8 core. Address 00H, 01H and FOH are reserved. The register file consists of two I/O Port registers, 236 general-purpose registers and 15 control and status registers (Figure 19). The instructions can access registers directly or indirectly with an 8-bit address field. This also allows short 4-bit register addressing using the Register Pointer. In the 4-bit mode, the register file is divided into sixteen working-register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working-register group (Figure 15). Note: Register Bank E0-EF is only accessed through a working register and indirect addressing modes.
r7 r6 r5 r4
r3 r2 r1 r0
R253 (Register Pointer)
The upper nibble of the register file address provided by the register pointer specifies the active working-register group.
FF
Register Group F
F0
R15 to R0
* * * * * * * *
Hex Address
* * * * * *
2F
Specified Working Register Group
The lower nibble of the register file address provided by the instruction points to the specified register.
02 03 04
Port 2 (P2) Port 3 (P3)
20 1F
Register Group 1
10 0F
R15 to R0 R15 to R4 R3 to R0
General-Purpose Registers
00
Register Group 0 I/O Ports
EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Reserved Timer Mode (TMR) Timer/Counter1(T1) T1 Prescaler (PRE1) Timer/Counter0 (T0) T0 Prescaler (PRE0) Port 2 Mode (P2M) Port 3 Mode (P3M) Port 0-1 Mode (P01M) Interrupt Priority Reg (IPR) Interrupt Request Reg (IRQ) Interrupt Mask Reg (IMR) Condition Flag (FLAGS) Register Pointer (RP) Stack Pointer High (SPH) Stack Pointer Low (SPL)
Figure 16. Register Pointer
Figure 15. Register File Configuration 18 DS97TEL1902
Zilog
Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
Z8 STANDARD CONTROL REGISTERS
RESET CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
1
U U U U U 0 U 1 0 1 U U U U 0 U U U U U 0 U 0 0 1 U U 0 U 0 U U U U U 0 U 1 0 1 0 U 0 U 0
REGISTER POINTER
7 6 5 4 0 0 0 0
REGISTER
% FF % FE % FD SPL 6P RP FLAGS IMR IRQ IPR Reserved P3M P2M PRE0 T0 PRE1 T1 TMR Reserved U U U U 0 0 U 0 0 1 U U U U 0 U U U U U 0 U 1 0 1 U U U U 0 U U U U U 0 U 1 0 1 U U U U 0 U U U U U 0 U 0 0 1 U U U U 0 U U U U U 0 U 1 0 1 U U U U 0
Working Register Group Pointer
Must be "0"
% FC % FB % FA % F9 % F8 % F7 % F6 % F5 % F4
Z8 Reg. File
%FF %FO
% F3 % F2 % F1 % F0
%7F
Reserved
%0F %00
EXPANDED REG. GROUP (0)
REGISTER
Legend: % (0) 03 U = Unknown % (0) 02 % (0) 01 % (0) 00 P3 P2 Reserved Reserved U U 1 U 1 U 1 U U U U U U U U U
RESET CONDITION
Note: All General-Purpose registers, PWM Registers, and Video RAM registers, Port 4, 5, and 6 registers are undefined after reset.
Figure 17. Z90102/3/4 Register File Reset Condition
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
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FUNCTIONAL DESCRIPTION (Continued)
Stack. Either the internal register file or the external data memory is used for the stack. An 8-bit Stack Pointer is used for the internal stack that resides within the 236 general-purpose registers. Counter/Timers. There are two 8-bit programmable counter/timers (T0-T1), each driven by its own 6-bit programmable prescaler (PRE0 and PRE1). The T1 prescaler can be driven by internal or external clock sources; however, the T0 prescaler is driven by the internal clock only (Figure 18). The counter, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user definable and is the internal microprocessor clock (XTAL clock/4), or an external signal input through Port 3, P31. The counter/timers are programmably cascaded by connecting the T0 output to the input of T1.
Internal Data Bus Write Write Read
PRE0 Initial Value Register OSC 6-Bit Down Counter
T0 Initial Value Register
T0 Current Value Register
4 Internal Clock
8-Bit Down Counter
IRQ4 Serial I/O Clock
External Clock Clock Logic 4 6-Bit Down Counter 8-Bit Down Counter
2
TOUT P36
IRQ5
Internal Clock Gated Clock Triggered Clock
PRE1 Initial Value Register
T1 Initial Value Register
T1 Current Value Register
TIN
P31 Write Write Internal Data Bus Read
Figure 18. Counter/Timer Block Diagram
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Zilog Interrupts. The DTC has six different interrupts from six different sources. These interrupts are maskable and prioritized (Figure 19). The six sources are divided as follows:
Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller two sources are claimed by Port 3 (P30, P31), one by VSYNC, two by the counter/timers, and one is software triggered only.
1
IRQ
IRQ
IMR
Global Interrupt Enable
6 IPR
Interrupt Request
Priority Logic
Vector Select
Figure 19. Interrupt Block Diagram
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
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FUNCTIONAL DESCRIPTION (Continued)
HALT Mode. The Z90102/3/4 is driven by two internal clocks, TCLK and SCLK. They both oscillate at the crystal frequency. TCLK provides the clock signal for the countertimers and the interrupt block. SCLK provides the clock signal for all other CPU blocks. HALT Mode turns off the internal CPU clock (SCLK), but not the XTAL oscillation. The counter/timers and external interrupts remain active. The device may be recovered by interrupts, either externally or internally generated. An interrupt request may be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP Mode. The STOP instruction stops crystal oscillation, thereby stopping both SCLK and TCLK. The device ceases to operate. The STOP Mode can be released by two methods. The first method is to reset the device. A high input condition on Port 3 P30 is the second method. After releasing the STOP Mode by using either one of the two methods, program execution begins at location 000CH. To complete an instruction prior to entering the standby modes, a NOP instruction has to be placed before the HALT or STOP instructions. This is required because of instruction pipelining, i.e.: FF NOP 6F STOP FF NOP 7F HALT ; clear the pipeline ; enter STOP Mode or ; clear the pipeline ; enter HALT Mode
Notes: In STOP Mode, XTAL2 pin has an internal pull-up on it and OSCOUT has an internal pull-down. Clock. The Z90102/3/4 on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal is an AT cut, parallel resonant, 4 MHz max with a series resistance (RS) less than or equal to 100 Ohms. The crystal source is connected across XTAL1 and XTAL2 using the crystal manufacturer's recommended capacitors (10 pF < CL < 300 pF, where C1=C2=CL) from each pin to device ground (Figure 20).
XTAL1 C1 * VSS XTAL2 C2 * VSS
XTAL1
XTAL2
External Clock Ceramic Resonator or Crystal
XTAL1
27mH
6.8kW
XTAL2 33pF * VSS * VSS LC Oscillator Circuits * Must be connected to VSS pin and not system ground. 33pF MPU
Figure 20. Oscillator Configuration 22 DS97TEL1902
Zilog Watch-Dog Timer (WDT). The Z90102/3/4 is equipped with a permanently enabled Watch-Dog Timer which must be refreshed every 12 ms. Failure to refresh the timer results in a reset of the device. The WDT is permanently enabled and is initially reset upon POR. Every subsequent WDT instruction resets the timer. The Watch-Dog Timer may or may not be enabled during the STOP Mode. The instruction WDT 4F (HEX) enables the timer during HALT.
Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller If the WDH instruction is used, and if the HALT Mode is not released and the Watch-Dog Timer is not retriggered (by the WDT instruction) within 12 ms, a device reset occurs. The WDT instruction affects the Z (Zero) S (Sign), and V (Overflow) flags. WDT does not run during STOP Mode. VCC Voltage Sensitive Reset (VSR). Reset is globally driven if VCC is below the specified voltage (Figure 21).
1
VBO
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40 -60 -40 -20 +0 20 40 60 80 100 120 140 Temperature (C)
Figure 21. Voltage Sensitive Reset vs Temperature
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
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STANDARD CHARACTER SETS
24
DS97TEL1902
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
SUMMARY Input/Output Circuits
VCC
OEN P PAD VCC
1
20 Ohm PAD
IN
OUT N 20 Ohm
IN
Figure 22. Input Only (Pad Type 1)
Figure 25. Input/Output Tristate (Pad Type 4)
VCC
VCC OD OEN P PAD
20 Ohm IN
PAD
OUT
N
20 Ohm
IN
Figure 23. Input Only, Schmitt-Triggered (Pad Type 2)
Figure 26. Input/Output, Tristate, Open-Drain
VCC
VCC
P PAD
OEN P PAD
OUT
N
OUT
N
Figure 24. Output Only (Pad Type 3)
Figure 27. Output Only, Tristate
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
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SUMMARY (Continued)
VCC
VCC
PAD N VCC N
STOP P
2R
OUT
N N
P67 + 1R 20 Ohm
VCC
PAD
P66 + 2R
Figure 28. Output Only, 12-Volt Open-Drain (Pad Type 7) Figure 30. AFC Input Circuit (Pad Type 9) Table 2. Mapping of Symbolic Pad Types to Pin Functions Pin Name
20 Ohm RESET PAD
VCC
RPU
Pad Type 1 * 8 5 2 3 2 9 2 3 3 3 7
N
Figure 29. Reset Input Circuit (Pad Type 8)
XTAL1, OSCIN XTAL2, OSCOUT /RESET P20-P27 P30-P31 P34-P36 P60-P65 AFCIN HSYNC, VSYNC VRED, VBLUE, VGREEN, VBLANK PWM1 PWM [6 -11]
Note: *High gain start, low gain run amplifier circuit.
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
DTC CONTROL REGISTER DIAGRAMS Port Registers
1
P2 02H
P3 03H
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 P30 Input Port Stop-Mode Recovery Input P31 Input/T1 (input)
Input/Output Port 0 Logic Level 0 1 Logic Level 1
P34 Output Port P35 Output Port P36 Output/T1, T0 (output) Reserved
Figure 31. Port 2 Register (Read/Write) Figure 33. Port 3 Register (P30, P31 Read Only) (P34, P35, P36 Write Only)
F6H Input/Output Mode 0 Output Mode 1 Input Mode
P2M
D7 D6 D5 D4 D3 D2 D1 D0
P6
FC32H D0
D7 D6 D5 D4 D3 D2 D1
Figure 32. Port 2 Mode Register (Write Only)
Port 6 Input 0 Logic Level 0 1 Logic Level 1 Port 6 Comparator Input 00 GND thru V1 0 1 V1 thru V2 11 V2 thru VCC
Figure 34. Port 6 Register (Read Only)
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
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DTC CONTROL REGISTER DIAGRAMS PWM Registers
PWM1 UPPER FC12H
PWM8 VAL FC1AH
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
PWM1 High Byte Reserved (Must be 0)
PWM8 Value Reserved (Must be 0)
Figure 35. PWM 1 High Value (Write Only)
Figure 39. PWM 8 Value (Write Only)
PWM1 LOWER
FC13H
PWM9 VAL
FC1BH
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
PWM1 Low Byte
PWM9 Value
Figure 36. PWM 1 Low Value (Write Only)
Figure 40. PWM 9 Value (Write Only)
PWM6 VAL
FC18H
D7 D6 D5 D4 D3 D2 D1 D0
PWM10 VAL
FC1CH
D7 D6 D5 D4 D3 D2 D1 D0
PWM6 Value Reserved (Must be 0)
PWM10 Value
Figure 37. PWM 6 Value (Write Only)
Figure 41. PWM 10 Value (Write Only)
PWM7 VAL
FC19H
D7 D6 D5 D4 D3 D2 D1 D0
PWM11 VAL
FC1DH
D7 D6 D5 D4 D3 D2 D1 D0
PWM7 Value Reserved (Must be 0)
PWM11 Value
Figure 38. PWM 7 Value (Write Only)
Figure 42. PWM 11 Value (Write Only)
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
PWM MODE
FC10H Mode Control 0 PWM 1 Output Port Reserved (Must be 0)
PWM OUT
FC11H Output Control 0 = Logic Level 1 1 = Logic Level 0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
Reserved (Must be 0)
Figure 43. PWM Mode Register (Write Only)
Figure 44. PWM Port Output Register (Write Only)
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
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Z8 REGISTER DIAGRAMS
OSDC CNTRL FC00H
DISP ATTR
FC03H
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Retrace Blanking High Resolution Must be 1 X4HL Pixel Size 00 x 1 01 x 2 10 x 3 11 x 4 Sync Polarity 0 Positive 1 Negative Reserved (Must be 0)
Blue Background Green Background Red Background RGB Polarity 0 - Positive 1 - Negative Reserved (Must be 0) Fringe On-Off 0 - Off 1 - On Background On-Off 0 - Off 1 - On Display On-Off 0 - Off 1 - On
Figure 45. OSD Control Register (Write Only)
Figure 48. OSD Display Attribute Register (Write Only)
VERT POS FC01H FC04H D7 D6 D5 D4 D3 D2 D1 D0 ROW SPACE D7 D6 D5 D4 D3 D2 D1 D0 Vertical Position Control x 4 Horizontal Lines Reserved (Must be 0) Inter Row Space Reserved (Must be 0)
Figure 46. OSD Vertical Position Register (Write Only)
Fade Direction 0 - Fade After 1 - Fade Before Fade On-Off 0 - Off 1 - On
HOR POS
FC02H
D7 D6 D5 D4 D3 D2 D1 D0
Figure 49. OSD Row Space Register (Write Only)
Horizontal Position Control x 4 DOT Clocks Reserved (Must be 0)
FADE POS
FC05H
D7 D6 D5 D4 D3 D2 D1 D0
Figure 47. OSD Horizontal Position Register (Write Only)
Vertical Index Reserved (Must be 0)
Figure 50. OSD Fade Position Register (Write Only)
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
BAR CNTRL
FC06H
ROW_ ATTR
FD00H,FD20H,FD40H, FD60H,FD80H,FDA0H
D7 D6 D5 D4 D3 D2 D1 D0 Row Address Reserved (Must be 0) Red Bar Color Green Bar Color Blue Bar Color Bar Color Enable
D7 D6 D5 D4 D3 D2 D1 D0
1
Row Background Color Red Green Blue Row Background On-Off 0 Off 1 On Character Color Red Green Blue Reserved (Must be 0)
Figure 51. OSD Bar Control Register (Write Only)
BAR POS
FC07H
D7 D6 D5 D4 D3 D2 D1 D0
Figure 54. ROW_ATTR Register (Write Only)
Bar Column Position Reserved (Must be 0) R242 T1 F2H D7 D6 D5 D4 D3 D2 D1 D0
Figure 52. OSD Bar Position Register (Write Only)
T1 Initial Value (When Written) (Range: 1-256 Decimal 01-00 Hex) T1 Current Value (When Read)
R241 TMR
F1H
D7 D6 D5 D4 D3 D2 D1 D0
0 - No Function 1 - Load T0 0 -Disable T0 Count 1 -Enable T0 Count 0 - No Function 1 - Load T1 0 - Disable T1 Count 1 - Enable T1 Count TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) TOUT Modes 00 Not Used 01 T0 Out 10 T1 Out 11 Internal Clock Out
Figure 55. Counter Timer 1 Register (F1H: Read/Write)
R243 PRE1
F3H
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode 0 T1 Single Pass* 1 T1 Modulo N Clock Source 1 T1 Internal 0 T1 External Timing Input* (TIN) Mode Prescaler Modulo (Range: 1-64 Decimal 01-00 Hex) * Default After Reset
Figure 53. Timer Mode Register (F1H: Read/Write)
Figure 56. Prescaler 1 Register (F3H: Write Only)
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
Zilog
Z8 REGISTER DIAGRAMS (Continued)
R247 P3M F7H
R244 T0
F4H
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0 - Port 2 Open-Drain 1 - Port 2 Push-Pull Reserved (Must be 0) 0 P32 - Input (Must be 0) P35 - Output
T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 Hex) T0 Current Value (When Read)
00 P33 - Input P34 - Output (Must be 0) 11 Reserved 0 P31 - Input (TIN) P36 - Output (TOUT) 0 P30 - Input
Figure 57. Counter/Timer 0 Register (F4H: Read/Write)
Reserved (Must be 0)
R245 PRE0
F5H
Figure 60. Port 3 Mode Register (F6H; Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
R249 IPR F9H
Count Mode 0 T0 Single Pass* 1 T0 Modulo-N Reserved (Must be 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 Hex) * Default After Reset
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B > C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ1, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0)
Figure 58. Prescaler 0 Register (F5H: Write Only)
R246 P2M
F6H
D7 D6 D5 D4 D3 D2 D1 D0
P27 - P20 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input
Figure 61. Interrupt Priority Register (F9H: Write Only)
Figure 59. Port 2 Mode Register (F6H: Write Only)
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
R250 IRQ
FAH
R253 RP
FDH
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
Reserved (Must be 0) Register Pointer
IRQ - Software only IRQ1 - VSYNC IRQ2 - P31 Input IRQ3 - P30 Input IRQ4 - T0 IRQ5 - T1 Reserved (Must be 0) Reset Condition = 00H
Reset Condition = 00H
Figure 65. Register Pointer (FDH: Read/Write)
Figure 62. Interrupt Request Register (FAH: Read/Write)
R254 GP
FEH
D7 D6 D5 D4 D3 D2 D1 D0
R251 IMR FBH
D7 D6 D5 D4 D3 D2 D1 D0
0 = Level 0 1 = Level 1
1 - Enables IRQ5 - IR0 (D0 - IRQ0) Reserved (Must be 0) 1 - Enables Interrupts 0* Disable Interrupts
Reset Condition = Undefined
Figure 66. General-Purpose (FEH: Read/Write)
* Default after Reset
Figure 63. Interrupt Mask Register (FBH: Read/Write)
R255 SPL
FFH
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Upper Byte (SP7-SP0)
R252 FLAGS
FCH
D7 D6 D5 D4 D3 D2 D1 D0
Figure 67. Stack Pointer (FFH: Read/Write)
User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure 64. Flag Register (FCH: Read/Write)
DS97TEL1902
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
Zilog
PACKAGE INFORMATION
Figure 68. 40-Pin DIP Package Diagram
34
DS97TEL1902
Zilog
Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
ORDERING INFORMATION Z90102, Z90103, Z90104
4 MHz 40-pin DIP Z90102/3/404PSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
1
CODE
Package P = Plastic DIP Temperature S = 0C to +70C Speed 04 = 4 MHz Environmental C = Plastic Standard
Example: Z 890103 04 P S C
is an 86227, 4 MHz, DIP 0C to +70C, Plastic Standard Flow , Environmental Flow T emperature Package Speed Product Number Zilog Prefix
DS97TEL1902
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Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller
Zilog
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DS97TEL1902

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