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EK7606C PRELIMINARY DATA SHEET
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Eureka Microelectronics, Inc.
EK7606C
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240- Output TFT LCD Analog Source Driver
6F, NO.12, INNOVATION 1 . RD., SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU CITY, TAIWAN, R.O.C. http://www.eureka.com.tw
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Table of Contents
EK7606C
Page 1.GENERAL DESCRIPTION........................................................................3 2.FEATURES...........................................................................................3 3.BLOCK DIAGRAM..................................................................................4 4.PIN CONFIGURATION...........................................................................5 5.PIN FUNCTION DESCRIPTIONS............................................................6 6.FUNCTION OPERATIONS........................................................................8 6.1 Operation timing 6.2 Sampling modes 6.3 Color mode selection 6.4 Relationship between OE and output waveform 7.ABSOLUTE MAXIMUM RATINGS...........................................................18 7.1 Absolute maximum ratings 7.2 Recommended operating conditions .com 8.ELECTRICAL CHARACTERISTICS..........................................................19 8.1 DC characteristics 8.2 AC characteristics 8.3 Timing chart 9.RECOMMANDED SOLDERING CONDITIONS............................................22 10.DEFINITIONS.......................................................................................22 10.1 Data sheet status and application information 10.2 Life support application
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240- Output TFT LCD Analog Source Driver
EK7606C
1. GENERAL DESCRIPTION The EK7606C is an analog, fully color, source driver for TFT LCD panels designed for camera, TV etc. Analog R, G and B signal are applied directly on the chip. For each of the 240 outputs, the voltage is sampled and buffered to the panel. With a double sample and hold circuit a new voltage can be sample whereas the previous sample voltage is applied to the panel. According to different modes, the 3 input voltages (VA, VB, VC) can be applied on different output to support various pixel array types. The 3 input voltages (VA, VB, VC) can be sampled simultaneously or sequentially to have a better flexibility with the input voltage. Using enable signal (STHx), several chips can be cascaded for large panel.
2. FEATURES
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LCD outputs: 240 Bi-directional shift ( L/R )
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Simultaneous or Sequential RGB acquisition mode X1 or X3 clock mode High frequency Sampling 10MHz (x1) Automatic low power consumption mode after data capture (gated clock) RGB color selection (automatic or manual) Logic power supply voltage VDD: 2.7V - 5.25V LCD power supply voltage AVDD: 4.5V - 5.5V Output dynamic range AVSS+0.2V to AVDD-0.2V Applicable to COF/COG
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3. BLOCK DIAGRAM
QA1
INH
EK7606C
QB1 QC1 QA2 QA80 QB80 QC80
+
+
+
+
+
+
+
-
-
-
-
-
-
Line Control
AMUX
AMUX
AMUX
AMUX
AMUX
AMUX
MUX
Q1H Q2H VA (R) VB (G) VC (B) TEST2
AMUX
SHA SHB
SHA SHB
SHA SHB
SHA SHB
SHA SHB
SHA SHB
SHA SHB
MUX
MUX
MUX
MUX
MUX
L/R STH1 CPH1 Clock MUX SR SR SR SR SR SR SR STH2
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CPH3 MODE
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Fig. 1 Block diagram
MUX
AMUX
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Clock MUX
Selects if the sampling is simultaneous or sequential. Also gates the clock.
3 x 80-bit bi-directional shift register
Generates enable signals for sequential sampling 134/160 groups of 3 input colors.
Line control
Select sample circuit SHA or SHB and the high impedance output state
SH control MUX
Select which sample and hold circuit samples the analog input value.
AMUX
According to the controls signals, selects which input color goes to which group of outputs.
Sample and hold Circuit (SHA, SHB)
Sample the input voltage when the enable signal of the shift register is generated and hold this value until it is stored on the panel.
Buffers
Drive the sample grayscale voltage on the panel.
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4. Pin Configuration
COM COM COM COM COM RESET MODE INH STH1 CPH3 CPH2 CPH1 VDD AVDD NC TEST2 AVSS VC VB VA VSS STH2 Q2H Q1H L/R COM COM COM COM COM
EK7606C
COM COM COM COM COM Qa1 Qb1 Qc1
Copper Foil Surface
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Qa80 Qb80 Qc80 COM COM COM COM COM
Fig. 2 Pin Arrangement (COF package)
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5. PIN FUNCTION DESCRIPTION
EK7606C
Table 1. Pin function description Signal Name Pin Type Function Liquid-crystal application voltages Qa1 to Qa80 Output Each QaX, QbX or QcX correspond to one of the analog Qb1 to Qb80 sample input signal VA, VB or VC. Qc1 to Qc80
VA VB VC L/R Input Video input signal Analog video input signal that is sampled internally and applied to the panel. Controls the display data shift direction L/R = H : STH1 input, Qa1 Qc80, STH2 output. STH1 Bidir L/R = L : STH2 input, Qc80 Qa1, STH1 output. Right shift start pulse L/R = H : Becomes the start pulse input pin. STH2 Bidir L/R = L : Becomes the start pulse output pin. Left shift start pulse L/R = H : Becomes the start pulse output pin. CPH1 CPH2 CPH3 Input (Pull-down CPH2 & CPH3 @ TEST2 = L And MODE=H) L/R = L : Becomes the start pulse input pin. Sampling clock input Refers to the analog data-sampling clock. The sampling starts at the first rising edge of CPH1 when STH1 ( L/R =H) is activated. CPH1 can be internally divided (x3 mode) to generate internal .com clock signal CPH1'. The sampling can be simultaneous or sequential. In simultaneous mode, the sampling is made during CPH1 (CPH1') period for all output. In sequential mode, the sampling is made according the table below : CPH1 (CPH1') control the sampling for Qa1 Qa80 CPH2 (CPH2') control the sampling for Qb1 Qb80 CPH3 (CPH3)' control the sampling for Qc1 Qc80 When clock mode x1 and sequential is selected, the three inputs CPH1, CPH2 and CPH3 must have an input clock signal applied. Otherwise only CPH1 must have input clock applied. Load line The sampled voltages are connecting to the panel at the rising edge of INH . The outputs of SHA(B) that was in sample mode are applied to the panel, whereas the SHB(A) becomes ready to sample new values. During INH = L, output level is HiZ state and this signal initialise the internal circuits.
Input
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INH
Input
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TEST2
Input (Pull-up) Input signal color rotation mode selector
EK7606C
TEST2 = L: No data rotation mode. Input voltage of each output QaX, QbX and QcX are selected from VA, VB and VC according to the control signal Q1H and Q2H. Simultaneous or sequential clock mode is selected by MODE. TEST2 = H or open: Automatic rotation mode. Input voltage of each output QaX, QbX and QcX are selected automatically from VA, VB and VC according to the filter arrays, selected by the control signal Q1H and Q2H. Simultaneous or sequential clock mode is selected by Q1H, Q2H. Sampling mode selection MODE = L or open: Sequentially sampling MODE = H: Simultaneous sampling This signal is only usable when TEST2 = L. Color selection input When TEST2 = L: Q1H and Q2H select which input voltage (VA, VB, VC) correspond to QaX, QbX, QcX outputs. When TEST2 =H: Q1H and Q2H select the filters array colors sequence. Q1H and Q2H select also simultaneous/sequential mode according to the equation below. Q1H = Q2H = 0: Simultaneous sampling .com Q1H =1 OR Q2H = 1: Sequential sampling Automatic color selection Initialisation Reset the system of the automatic rotation mode. To initialise the module a pulse on INH must be applied after reset. This function is only usable when TEST2 =H. When not used should be L or open. Logic part power supply Logic part ground Analog part power supply Analog part ground
MODE
Input (Pull-down @ TEST2 = L)
Q1H Q2H
Input (Pull-down @ TEST2 = L)
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RESET Input (Pull-down @ TEST2 = L)
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VDD VSS AVDD AVSS
Power Power Power Power
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6. FUNCTIONAL DESCRIPTION 6.1 Operation Timing
Line
EK7606C
CPH1
1 2 3 4 78 79 80 81 82 319 320 321 1
2
STH1 VA VB VC
A1 A2 A3 A78 A79 A80 A81 A319 A320 A1
B1
B2
B3
B78
B79
B80
B81
B319
B320
B1
C1
C2
C3
C78
C79
C80
C81
C319
C320
C1
INH STH2
1 Chip
st
STH2
Last Chip
Sample circuits Buffers Ouputs Drivers Outputs High Z L/R = H shift from left to right Clock mode : x1 simultaneous
SHA Line n Line n-1 Line n-1 No rotation mode Ax, Bx, Cx correspond to the .com sample values for the VA -> QAx outputs QAx, QBx, QCx. VB -> QBx VC -> QCx
SHB Line n+1 Line n High Z Line n
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Fig. 3 Operation timing diagram
The start condition is initiated by applying a start pulse to the enable input pin (STH1 when L/R =VDD) at the beginning of each line on the first chip. During the next 80 CPH1 rising edges, this source driver sample 80 times 3 display input voltage (3 RGB dot x 80 pixels). After sampling the 80th group of input voltages, it activates the enable output signal (STH2 when L/R =VDD) to enable the following chip. As soon as the loading of the input voltage is achieved for a complete line, the controller activates the INH signal to force the 240 output buffers in a high impedance state. Then the outputs of SHA(B) that were in sample mode are applied to the output buffers , whereas the SHB(A) becomes ready to sample new values. Finally, at the rising edge of INH , the 240 output buffers drive the sample voltages to the panel.
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6.2 Sampling Modes
EK7606C
Simultaneous/Sequential and x1/x3 sampling modes provide 4 different ways to sample input voltages. Simultaneous/Sequential selection mode is described on the table below.
Table 2.
Simultaneous Sequential selection table When TEST2 =L Mode=H Mode=L When TEST2 =H Q1H=Q2H=L Q1H=H OR Q2H =H Sampling Mode Simultaneous Sequential
Table 3.
x1 x3 clock selection table Sampling Mode CPH1 Simultaneous Sequential Simultaneous Sequential Clock IN Clock IN Clock IN Clock IN
CPH2 L Clock IN L L
CPH3 L Clock IN H H
Clock division x1 x3
All diagram below describe the 4 clock modes, voltage correspondence are: VA -> QAX, VB -> QBX, VC -> QCX.
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Ax, Bx, Cx correspond to the sample values for the outputs QAx, QBx, QCx. .com
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CPH1 CPH2 CPH3 STH1 VA VB VC STH2
1
2
3
4
78
79
80
81
A1
A2
A3
A78
A79
A80
B1
B2
B3
B78
B79
B80
C1
C2
C3
C78
C79
C80
L/R = H shift from left to right CPH2 = CPH3 = L
MODE = H when TEST2 = L OR Q1H = Q2H = L when TEST2 = H
Fig. 4 x1 simultaneous sampling mode
Each input is sampled simultaneously synchronised with CPH1 rising edge.
th
Output enable signal is generated at the falling edge of the 80 period of CPH1 since the start pulse.
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CPH1 CPH2 CPH3 STH1 VA VB VC STH2 L/R = H shift from left to right CPH2, CPH3 : clock input MODE = L when TEST2 = L OR Q1H = H or Q2H = H when TEST2 = H
A1 A2 A3 A78 A79 A80 1 2 3 4 78 79 80 81
EK7606C
1
2
3
4
78
79
80
81
1
2
3
4
78
79
80
81
B1
B2
B3
B78
B79
B80
C1
C2
C3
C78
C79
C80
Fig. 5 x1 sequential sampling mode
Each input is sampled sequentially synchronised with the associated rising edge of the corresponding
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clock. CPH1 controls the sample for QAx outputs, CPH2 controls the sample for QBx outputs and CPH3 .com controls the sample for QCx outputs. Output enable signal is generated at the falling edge of the 80 period of CPH1 since the start pulse.
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CPH1
1 2 3 4 5 6 7 8 9 10 11
EK7606C
234 235 236 237 238 239 240 241 242 243 244 245
CPH2 CPH3 STH1 CPH1 VA VB VC
1 A1 2 A2 3 A3 4 78 A78 79 A79 80 A80 81
B1
B2
B3
B78
B79
B80
C1
C2
C3
C78
C79
C80
STH2 L/R = H shift from left to right CPH2 = L CPH3 = H
MODE = H when TEST2 = L OR Q1H = Q2H = L when TEST2 = H
Fig. 6 x3 simultaneous sampling mode
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Each input is sampled simultaneously synchronised with CPH1' rising edge. CPH1' is generated from .com CPH1 (Frequency divided by 3). Output enable signal is generated at the falling edge of the 80th period of CPH1' since the start pulse.
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CPH1
1 2 3 4 5 6 7 8 9 10 11
EK7606C
234 235 236 237 238 239 240 241 242 243 244 245
CPH2 CPH3 STH1 CPH1 CPH2 CPH3 VA VB VC
A1 1 2 3 4 78 79 80 81
1
2
3
4
78
79
80
81
1
2
3
4
78
79
80
81
A2
A3
A78
A79
A80
B1
B2
B3
B78
B79
B80
C1
C2
C3
C78
C79
C80
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STH2 L/R = H shift from left to right CPH2 = L CPH3 = H
.com MODE = L when TEST2 = L OR Q1H = H or Q2H = H when TEST2 = H
Fig. 7 x3 sequential sampling mode
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Each input is sampled sequentially synchronised with the associated rising edge of the corresponding clock. CPH1' controls the sample for QAx outputs, CPH2' controls the sample for QBx outputs and CPH3' controls the sample for QCx outputs. CPH1', CPH2' and CPH3' are generated from CPH1 (Frequency divided by 3). The three clocks have one CPH1 period phase shift between them. Output enable signal is generated at the falling edge of the 80th period of CPH1' since the start pulse.
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6.3 Color mode selection
EK7606C
According to the signal description table, the color mode selection is separated in two modes. No rotation mode and automatics rotation mode.
No rotation mode
This mode is selected by TEST2 = L. When no rotation mode is selected, Q1H and Q2H control the color selection in order to the table below.
Table 4.
No rotation mode color selection table Q1H L L H Q2H L H X QA VA VC VB QB VB VA VC QC VC VB VA
The sample circuit SHA(B) get the value according to the table above. For example, when Q1H = Q2H = L, the sample circuit SHA(B) for the outputs Qax sample VA and the next INH pulse this sample voltage is put to the panel.
Automatic rotation mode
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This mode is selected by TEST2 = H. It allows the chip to select automatically the color in function of the .com panel color filter and the chips location on the panel (single bank or dual bank). Single bank mean that all the source drivers are on one side of the panel. Dual bank means that one group of source drivers is in the top of the panel and one at the bottom of the panel and they drive columns alternatively.
Table 5.
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Automatic rotation mode panel selection table Q1H Q2H Color array L L Vertical Stripe L H Delta H X Delta
Chip location Single bank Single bank Dual bank
In this mode, the color selection has a cycle of two lines. A pulse on RESET and after an activation of INH initialises this sequence (figure below).
RESET INH Sample QA1 to QC80 1st line sampling 2nd line sampling 1st line (Odd) 2nd line (Even)
Fig. 8 Automatic rotation mode initialisation sequence
In automatic rotation mode, the color is selected automatically for Odd and Even line.
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Vertical stripe array
EK7606C
This mode is selected by Q1H = Q2H = L and TEST2 =H. The characteristics of this panel configuration are: Each column is associated with one color. One bank of source driver.
Q1H = L Q2H = L VA = R VB = B VC = G QA1
st
EK7606C
QB2 B B B B QC2 G G G G QC79 QA80 QB80 QC80 G G G G R R R R B B B B G G G G
QB1
QC1
QA2 R R R R
1 line R(VA) B(VB) G(VC) nd 2 line R(VA) B(VB) G(VC) rd 3 line R B G th 4 line R B G
Fig. 9 Vertical stripe array panel configuration
The figure shows, for this mode, that there is only one case of color:
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Table 6. Vertical stripe array color selection table Line QA QB .com Odd VA VB Even VA VB
QC VC VC
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Single bank delta array
EK7606C
This mode is selected by Q1H = L, Q2H = H and TEST2 = H. The characteristics of this panel configuration are: Each column is share between two colors. One bank of source driver.
Q1H = L Q2H = H VA = R VB = B VC = G QA1
st
EK7606C
QB2 B G R B G R G R QC2 G R G B QC79 QA80 QB80 QC80 G B R G R G B R B R G G
QB1
QC1
QA2 R R
1 line R(VA) B(VB) G(VC) nd 2 line B(VB) G(VC) R(VA) B rd 3 line R B G th 4 line B G R B
Fig. 10 Single bank delta array panel configuration
The colors are switched between Odd and Even line:
Table 7. Single bank delta array color selection table
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Line Odd Even
.com QA QB VA VB VB VC
QC VC VA
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Dual bank delta array
EK7606C
This mode is selected by Q1H = H, Q2H = H and TEST2 = H. The characteristics of this panel configuration are: Each column is share between two colors. Two bank of source driver (top and bottom of the panel).
Q1H = H Q2H = H L/R = H VA = B VB = R VC = G QA1 1 line nd 2 line rd 3 line th 4 line
st
EK7606C
QA80 R B R B G G B R B R G B QB80 G B R G R G B R QC80 B R G G
QB1
QC1
R (VB) B(VC) G(VC) R (VB) B(VA) G(VA) B(VA) G(VA) R(VB) B(VC) G(VC) R(VB) R G R B G B B R B G R G
last-3 line last-2 line last-1 line last line
R B R B G G
B R B R
G B G B
R G R G
B R B R
G G
R R G G B B B B R R G G R (VB) B(VC) G(VC) R (VB) B(VA) G(VA) B(VA) G(VA) R(VB) B(VC) G(VC) R(VB) QC1 QB1 QA1
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QC80
QB80
QA80 .com
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EK7606C
Q1H = H Q2H = H L/R = L VA = G VB = R VC = B
Fig. 11 Dual bank delta array panel configuration
The colors are switched between Odd and Even line and depend also on L/R :
Table 8. Dual bank delta array color selection table
L/R H L
Line Odd Even Odd Even
QA VB VA VA VB
QB VC VB VB VC
QC VA VC VC VA
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Colors selection resuming
EK7606C
The table below resume 3 different color cases:
Table 9. RGB Color selection case Case 1 2 3
QA VA VC VB
QB VB VA VC
QC VC VB VA
The table below resume all color selection modes:
Table 10. Colors selection resuming table
Q1H L L H H
Q2H L H H H
LR X X L H
When TEST2 =L 1 2 3 3
When TEST2 =H Odd line Even line 1 1 1 3 1 3 3 1
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6.4 Relationship between INH and output waveform .com
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At INH rising edge, the sample voltages are output on the panel. As long as INH is active, the 240 output buffers are forced in a high impedance state.
INH
QA1 to QC80
Hi-Z Hi-Z Hi-Z Hi-Z
Fig. 12 INH timing diagram
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7. ABSOLUTE MAXIMUM RATINGS 7.1 Absolute maximum ratings Table 11. Absolute maximum rating (VSS = AVSS = 0 V)
EK7606C
Parameter
Logic Part Supply Voltage Analog Part Supply Voltage Logic Part Input Voltage Video Input Voltage Logic Part Output Voltage Driver Part Output Voltage Storage Temperature
Symbol
VDD AVDD VI1 VI2 VO1 VO2 TSTG
Rating
-0.5 to +7.0V -0.5 to +7.0V -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -55 to +125
Unit
V V V V V V C
Caution: If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum rating, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum rating.
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7.2 Recommended operating range Table 12. Recommended operating range (VSS = AVSS = 0 V)
Parameter
Logic Part Supply Voltage Analog Part Supply Voltage Video Input Voltage Operating Ambient Temperature Maximum Clock Frequency
Symbol
VDD AVDD VVIDEO TA
Conditions
MIN
2.7 4.5 AVSS + 0.2 -30
TYP
MAX
5.25 5.5 AVDD - 0.2 75 10 25
Unit
V V V C MHz MHz s
X1 Mode FCPH X3 Mode INH period TINH 64
200
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8. ELECTRICAL CHARACTERISTICS 8.1 DC characteristics Table 13. DC characteristics
EK7606C
(TA= -30 to +75C, VDD= 2.7V to 5.25V, AVDD= 4.5V to 5.5V, VSS=AVSS=0V) Parameter
Logic High-level Input Voltage Logic Low-level Input Voltage Logic Input Leakage Current Video Input Leakage Current Logic High-level Output Voltage Logic Low-level Output Voltage Output Voltage Range Output Voltage Deviation Logic Part Dynamic Current Consumption Driver Part Dynamic Current Consumption
Symbol
VDIH VDIL ILIL IVIL VOH VOL V0 V0 IDD IADD
Condition
MIN.
0.7*VDD 0.0
TYP.
MAX.
VDD 0.3*VDD 1.0 1.0
Unit
V V A A V
STH1(STH2), IOH=0mA STH1(STH2), IOL=0mA
VDD - 0.1 0.1 0.2 AVDD - 0.2 20 0.8 3.0
V V mV mA mA
Note 1 Note 2 Note 3
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Note 1: Deviation between input voltage and output value. Voltage on the output pin 30us after the rinsing edge of INH . VVIDEO= 0.2V to AVDD-0.2V. Note 2: FCPH=10MHz, X1 Simultaneous Clock Mode, TINH=63 s, TIWL = 5us, No load. Note 3: Video input = AVDD/2, No Load.
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8.2 AC characteristics Table 14. AC characteristics
EK7606C
(TA= -30 to +75C, VDD= 2.7V to 5.25V, VSS=AVSS=0V) Parameter
Clock Period
Symbol
TCP
Condition
x1 Mode x3 Mode x1 Mode
MIN.
100 40 40 15 40 15 15 10 10 100
TYP.
MAX.
Unit
ns ns ns ns ns ns
Clock high-level width
TCWH x3 Mode x1 Mode
Clock low-level width
TCWL x3 Mode
Delay time Between Clocks STH Setup Time STH Hold Time RESET Pulse Width
TC12, TC23 TSS TSH TWR TRST-INH TIWH TIWL TINH-STH TSD TDD
x1 Sequential Mode
1/2*TCP
ns ns ns ns ns s ns ns
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RESET- INH Timing INH high-level width INH low-level width INH -STH Timing STH Pulse Delay Time Driver Output Delay Time
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100 30 100 TBD
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CL =20pF CL =25pF, RL=25k 12
20 20
ns s
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8.3 Timing chart
EK7606C
Unless otherwise specified, the input level is defined to VIH = 0.7 VDD, VIL = 0.3 VDD
x1 Mode
TCWH TCWL
79
TCP
80 81
TR
TF
CPH1 CPH2 CPH3
1
2
TC12
2
1
TC23
2
79
80
81
1
79
80
81
TSS TSH
TSS
STH input STH Output
TSD
TSD
x3 Mode
TCWH TCWL TCP TR TF
CPH1
1 2 3 4 5 234 235 236 237 238 239 240 241 242 243 244 245 243 244
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STH input CPH1
TSS TSH TSS
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DataShee
1
2
78
79
80
81
TSD
TSD
STH Output
RESET
TWR TRST-INH
STH input INH
TIWL
TINH-STH
TIWH
QA1 to QC80
Target voltage + 20mV
High-Z
TDD
Fig. 13 AC characteristics waveform July 2003
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Preliminary Rev. 0.1
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DataSheet 4 U .com
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EUREKA
9. RECOMMANDED SOLDERING CONDITIONS
EK7606C
The following conditions must be met for soldering conditions of the EK7606C. Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions.
EK7606C : (COF Package)
Mounting Condition Thermocompression
Mounting Method Soldering
Condition Heating tool 300 to 350C : heating for 2 to 3 Seconds : pressure 100g (per solder)
ACF (Anisotropic Conductive Film)
Temporary bonding 70 to 100C : pressure 3 to 8 kg/cm2 : time 3 to 5 seconds. Real bonding 165 to 180C : pressure 25 to 45 Kg/cm2 : time 30 to 40 seconds.
10. DEFINITIONS 10.1 Date sheet status and application information
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Data sheet status Preliminary specification
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This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Product specification Application information Where application information is given, it is advisory and does not form part of the specification.
10.2 Life support application
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Eureka customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Eureka for any damages resulting from such improper use or sale.
July 2003
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Preliminary Rev. 0.1
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DataSheet 4 U .com

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