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| CY8C201A0 CapSense ExpressTM - 10 Configurable IOs with Slider Features Overview The CapSense ExpressTM controller allows the control of 10 IOs configurable as one capacitive sensing slider (5 or 10 segments)[1] and the rest as buttons or GPIOs for driving LEDs or interrupt signals based on various button conditions. The GPIOs are also configurable for waking up the device from sleep based on an interrupt input. The user has the ability to configure slider, buttons, outputs, and parameters, through specific commands sent to the I2C port. The IOs have the flexibility of mapping to capacitive buttons and as standard GPIO functions such as interrupt output or input, LED drive, and digital mapping of input to output using simple logical operations. This enables easy PCB trace routing and reduces the PCB size and stack up. CapSense Express products are designed for easy integration into complex products. 10 configurable IOs supporting CapSenseTM slider LED drive Interrupt outputs WAKE on interrupt input User defined input or output 2.4V to 2.9V, 3.10V to 3.6V, and 4.75V to 5.25V operating voltage Industrial temperature range: -40C to +85C I2C slave interface for configuration Selectable to 50 kHz, 100 kHz, and 400 kHz. Reduce BOM cost Internal oscillator - no external oscillators or crystal Free development tool - no external tuning components Low operating current Active current: 1.5 mA Deep Sleep current: 2.6 uA Available in 16-pin COL and 16-pin SOIC packages Architecture The logic block diagram shows the internal architecture of CY8C201A0. The user can configure registers with parameters needed to adjust the operation and sensitivity of the CapSense system. CY8C201A0 supports a standard I2C serial communication interface that allows the host to configure the device and to read sensor information in real time through easy register access. The CapSense Express Core The CapSense Express core has a powerful configuration and control block. It encompasses SRAM for data storage, an interrupt controller, and sleep and watchdog timers. System resources provide additional capability, such as a configurable I2C slave communication interface and various system resets. The Analog System contains the CapSense PSoC(R) block, which supports capacitive sensing of up to 10 inputs. Note 1. This part should be selected only if the design requires a slider. This part cannot be configured to work without a slider. For 10 IO requirement use CY8C20110. Cypress Semiconductor Corporation Document Number: 001-17349 Rev. *F * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised January 28, 2009 [+] Feedback CY8C201A0 Logic Block Diagram External VCC 2.40V to 2.90V, 3.10V to 3.60V, 4.75V to 5.25V CapSense ExpressTM Core SYSTEM BUS 10 Configurable IOs with Slider 512B SRAM 2 KB Flash Interrupt Controller Configuration and Control Engine Sleep and Watchdog Clock Sources (Internal Main Oscillator) SYSTEM BUS CapSense Block I2C Slave Voltage & Current Reference System Reset POR/LVD Document Number: 001-17349 Rev. *F Page 2 of 16 [+] Feedback CY8C201A0 Pinouts Figure 1. Pin Diagram - 16 COL COL (TOP VIEW) Table 1. Pin Definitions - 16 COL Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I Name GP0[0] GP0[1] 2C Description Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C clock I2C data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Active HIGH external reset with internal pull down Configurable as CapSense or GPIO Supply voltage Configurable as CapSense or GPIO Integrating Input. The external capacitor is required only if 5:1 SNR cannot be achieved. Typical range is 10 nF to 100 nF Configurable as CapSense or GPIO SCL I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD GP0[3] CSInt GP0[4] Document Number: 001-17349 Rev. *F Page 3 of 16 [+] Feedback CY8C201A0 Figure 2. Pin Diagram - 16 SOIC GP0[3] CSInt GP0[4] GP0[0] GP0[1] I2CSCL I2CSDA GP1[0] 1 2 3 4 5 6 7 8 16 15 14 VDD GP0[2] XRES GP1[4] GP1[3] GP1[2] VSS GP1[1] SOIC (Top View) 13 12 11 10 9 Table 2. Pin Definitions - 16 SOIC Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I Name GP0[3] CSInt GP0[4] GP0[0] GP0[1] 2C Description Configurable as CapSense or GPIO Integrating Input. The external capacitor is required only if 5:1 SNR cannot be achieved. Typical range is 10 nF to 100 nF Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C clock I2C data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Active HIGH external reset with internal pull down Configurable as CapSense or GPIO Supply voltage SCL I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD Document Number: 001-17349 Rev. *F Page 4 of 16 [+] Feedback CY8C201A0 The CapSense Analog System The CapSense analog system contains the capacitive sensing hardware which supports the CapSense Successive Approximation (CSA) algorithm. This hardware performs capacitive sensing and scanning without external components. Capacitive sensing is configurable on each pin. I2C Interface The two modes of operation for the I2C interface are: Device register configuration and status read or write for controller Command execution Additional System Resources System resources provide additional capability useful to complete systems. Additional resources are low voltage detection and power on reset. Brief statements describing the merits of each system resource are: The I2C address is programmable during configuration. It can be locked to prevent accidental change by setting a flag in a configuration register. I2C Device Addressing I2C device address is contained in the upper seven bits of the first byte of a read or write transaction. The first byte of the transaction is used by the I2C master to address the slave. The LSB of the byte contains the R/W bit. If this bit is 0, the master performs write operation to the addressed slave. If this bit is 1, the master performs read operation from the addressed slave. The LSB(B0) is eliminated when fixing the device address. For example, if the slave address is 02h, then the required address is 0000010 (7 bit) excluding LSB. If write operation is performed, the LSB is 0 and the address is 00000100(04h). If read operation is performed, the LSB is 1 and the address is 00000101(05h). Table 3 provides examples of I2C addressing. The slave provides 50, 100, or 400 kHz communication over two wires. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels and the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. I2C An internal 1.8V reference provides a stable internal reference so that capacitive sensing functionality is not affected by minor VDD changes. Table 3. Examples of I2C Addressing Slave Address Defined 0 0 1 1 10 10 75 75 127 127 B7 0 0 0 0 0 0 1 1 1 1 B6 0 0 0 0 0 0 0 0 1 1 B5 0 0 0 0 0 0 0 0 1 1 B4 0 0 0 0 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 B2 0 0 0 0 1 1 1 1 1 1 B1 0 0 1 1 0 0 1 1 1 1 B0 0(W) 1(R) 0(W) 1(R) 0(W) 1(R) 0(W) 1(R) 0(W) 1(R) Address to be sent (in Hex) by Master 00 01 02 03 14 15 96 97 FE FF CapSense Express Software Tool An easy to use software tool integrated with PSoC Express is available for configuring and tuning CapSense Express devices. Refer to the application note "CapSenseTM Express Software Tool - AN42137" for details of the software tool. CapSense Express Register Map CapSense Express supports user configurable registers through which the device functionality and parameters are configured. For details, refer to the CY8C201xx Register Reference Guide. Document Number: 001-17349 Rev. *F Page 5 of 16 [+] Feedback CY8C201A0 Modes of Operation CapSense Express devices are configured to operate in any of the following three modes to meet different power consumption requirements: Deep Sleep Mode Deep sleep mode provides the lowest power consumption because there is no operation running. In this mode, the device is woken up only using an external GPIO interrupt. A sleep timer interrupt cannot wake up a device from deep sleep mode. This can be treated as a continuous sleep mode without periodic wakeups. Refer to the application note "CapSense Express Power and Sleep Considerations - AN44209" for details on different sleep modes. Active Mode Sleep Mode Deep Sleep Mode Active Mode In the active mode, all the device blocks including the CapSense sub system are powered. Typical active current consumption of the device across the operating voltage range is 1.5 mA Bi-Directional Sleep Control Pin The CY8C201A0 requires a dedicated sleep control pin to allow reliable I2C communication in case any sleep mode is enabled. This is achieved by pulling the sleep control pin LOW to wake up the device and start I2C communication. The sleep control pin can be configured on any of the GPIO. If sleep control feature is enabled, the device has one less GPIO available for CapSense and GPIO functions. The sleep control pin can also be configured as interrupt output pin from CY8C201A0 to the host to acknowledge finger press on any button. To enable bi-directional feature, user must use I2C-USB bridge program. Sleep Mode Sleep mode provides an intermediate power operation mode. It is enabled by configuring the corresponding device register. When enabled, the device enters sleep mode and wakes up after a specified sleep interval. It scans the capacitive sensors before going back to sleep again. The device can also wake up from sleep mode with a GPIO interrupt. The following sleep intervals are supported in CapSense Express. The sleep interval is configured through registers. 1.95 ms (512 Hz) 15.6 ms (64 Hz) 125 ms (8 Hz) 1s (1 Hz) Document Number: 001-17349 Rev. *F Page 6 of 16 [+] Feedback CY8C201A0 Electrical Specifications Absolute Maximum Ratings Parameter TSTG Description Storage temperature Min -55 Typ 25 Max +100 Unit C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25C 25C (0C to 50C). Extended duration storage temperatures above 65C degrade reliability TA VDD VIO VIOZ IMIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any GPIO pin Electro static discharge voltage Latch up current -40 -0.5 VSS - 0.5 VSS - 0.5 -25 2000 - - - - - - - - +85 +6.0 VDD + 0.5 VDD + 0.5 +50 - 200 C V V V mA V mA Human body model ESD Operating Temperature Parameter TA TJ Description Ambient temperature Junction temperature Min -40 -40 Typ - - Max +85 +100 Unit C C Notes Document Number: 001-17349 Rev. *F Page 7 of 16 [+] Feedback CY8C201A0 DC Electrical Characteristics DC Chip Level Specifications Parameter VDD IDD ISB Description Supply voltage Supply current Deep sleep mode current with POR and LVD active. Mid temperature range Deep sleep mode current with POR and LVD active Deep sleep mode current with POR and LVD active Min 2.40 - - Typ - 1.5 2.6 Max 5.25 2.5 4 Unit V mA A Conditions are VDD = 3.10V, TA = 25C VDD = 2.55V, 0C < TA < 40C Notes ISB ISB - - 2.8 5.2 5 6.4 A A VDD = 3.3V, -40C < TA < 85C VDD = 5.25V, -40C < TA < 85C 5V and 3.3V DC General Purpose IO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40C VIL VIH VIL VIH VH IIL CIN COUT Input low voltage Input high voltage Input low voltage Input high voltage Input hysteresis voltage Input leakage Capacitive load on pins as input Capacitive load on pins as output 1.6 - 2.0 - - 0.5 0.5 - - 140 1 1.7 1.7 .75 0.8 - - - 5 5 V V V V mV nA pF pF Document Number: 001-17349 Rev. *F Page 8 of 16 [+] Feedback CY8C201A0 2.7 DC General Purpose IO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 2.90V and -40C Low output voltage port 1 pins - - 0.4 V VIL VIH VIH1 VIH2 VH IIL CIN COUT Input low voltage Input high voltage Input high voltage Input high voltage Input hysteresis voltage Input leakage Capacitive load on pins as input Capacitive load on pins as output - 1.6 1.4 1.6 - - 0.5 0.5 - - - - 60 1 1.7 1.7 0.75 - - - - - 5 5 V V V V mV nA pF pF 2.7V DC Spec for I2C Line with 1.8V External Pull-Up This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 2.9V and 3.10V to 3.60V, and -40C Input low voltage Input high voltage Capacitive load on pins as input Capacitive load on pins as output - 1.4 0.5 0.5 - - 1.7 1.7 0.75 - 5 5 V V pF pF Document Number: 001-17349 Rev. *F Page 9 of 16 [+] Feedback CY8C201A0 DC POR and LVD Specifications Parameter VPPOR0 VPPOR1 Description VDD Value for PPOR Trip VDD= 2.7V VDD= 3.3V,5V VDD Value for LVD Trip VDD= 2.7V VDD= 3.3V VDD= 5V Min - - Typ 2.36 2.60 Max 2.40 2.65 Unit V V Notes VDD must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from watchdog. VLVD0 VLVD2 VLVD6 2.39 2.75 3.98 2.45 2.92 4.05 2.51 2.99 4.12 V V V DC Programming Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C Document Number: 001-17349 Rev. *F Page 10 of 16 [+] Feedback CY8C201A0 CapSense Electrical Characteristics Max (V) 3.6 3.10 Typical (V) 3.3 2.7 Min (V) 3.10 2.45 Conditions for Supply Voltage <2.9V <2.45V Result The device automatically reconfigures itself to work in 2.7V mode of operation. The scanning for CapSense parameters shuts down until the voltage returns to over 2.45V. The device goes into reset. The device automatically reconfigures itself to work in 3.3V mode of operation. The scanning for CapSense parameters shuts down until the voltage returns to over 4.73V. This range is not supported by CapSense Express. The device will work, but CapSense scanning is not enabled until the voltage goes above 4.73V. This range is not supported by CapSense Express. <2.4V 3.6 5.25 3.3 5.0 3.10 4.75 >3.10V <4.73V 3.6 to 4.75V 2.9 to 3.1V AC Electrical Characteristics 5V and 3.3V AC General Purpose IO Specifications Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload = 50 pF, Port 0 Rise time, strong mode, Cload = 50 pF, Port 1 Fall time, strong mode, Cload = 50 pF, all ports Min 15 10 10 Max 80 50 50 Unit ns ns ns Notes VDD = 3.10V to 3.6V and 4.75V to 5.25V, 10% - 90% VDD = 3.10V to 3.6V, 10% - 90% VDD = 3.10V to 3.6V and 4.75V to 5.25V, 10% - 90% 2.7V AC General Purpose IO Specifications Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload = 50 pF, Port 0 Rise time, strong mode, Cload = 50 pF, Port 1 Fall time, strong mode, Cload = 50 pF, all ports Min 15 10 10 Max 100 70 70 Unit ns ns ns Notes VDD = 2.4V to 2.90V, 10% - 90% VDD = 2.4V to 2.90V, 10% - 90% VDD = 2.4V to 2.90V, 10% - 90% Document Number: 001-17349 Rev. *F Page 11 of 16 [+] Feedback CY8C201A0 AC I2C Specifications Parameter FSCLI2C Description SCL clock frequency Standard Mode Min 0 4.0 Max 100 - Fast Mode Min 0 0.6 Max 400 - kbps s Fast mode not supported for VDD < 3.0V Units Notes THDSTAI2C Hold time (repeated) START condition. After this period, the first clock pulse is generated TLOWI2C THIGHI2C LOW period of the SCL clock HIGH period of the SCL clock 4.7 4.0 4.7 0 250 4.0 4.7 - - - - - - - - - 1.3 0.6 0.6 0 100 0.6 1.3 0 - - - - - - - 50 s s s s ns s s ns TSUSTAI2C Setup time for a repeated START condition THDDATI2C Data hold time TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Data setup time Setup time for STOP condition BUS free time between a STOP and START condition Pulse width of spikes suppressed by the input filter Figure 3. Definition of Timing for Fast/Standard Mode on the I2C Bus ~ ~ ~ ~ ~ ~ SDA tf tSUDATI2C tf ~ ~ tLOWI2C tr tHDSTAI2C tSPI2C tr tBUFI2C SCL ~ ~ ~ ~ S tHDSTAI2C tHDDATI2C tHIGHI2C tSUSTAI2C Sr tSUSTOI2C P S Document Number: 001-17349 Rev. *F Page 12 of 16 [+] Feedback CY8C201A0 Ordering Information Ordering Code CY8C201A0-LDX2I CY8C201A0-SX2I Package Diagram 001-09116 51-85068 16 Package Type COL[5] 16 SOIC Operating Temperature Industrial Industrial Thermal Impedances by Package Package 16 COL [5] Typical JA[3] 46 C 79.96 C 16 SOIC Solder Reflow Peak Temperature Package 16 COL[5] 16 SOIC Minimum Peak Temperature[4] 240 C 240 C Maximum Peak Temperature 260 C 260 C Notes 3. TJ = TA + Power x JA. 4. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5C with Sn-Pb or 245 5C with Sn-Ag-Cu paste Refer to the solder manufacturer specifications. 5. Earlier termed as QFN package. Document Number: 001-17349 Rev. *F Page 13 of 16 [+] Feedback CY8C201A0 Package Diagrams Figure 4. 16L Chip On Lead 3 X 3 mm Package Outline (SAWN) - 001-09116 - (Pb-Free) 001-09116 *D Figure 5. 16-Pin (150-Mil) SOIC (51-85068) 51-85068-*B Document Number: 001-17349 Rev. *F Page 14 of 16 [+] Feedback CY8C201A0 Document History Page Document Title: CY8C201A0 CapSense ExpressTM - 10 Configurable IOs with Slider Document Number: 001-17349 Rev. ** *A ECN No. 1494145 1773608 Orig. of Change TUP/AESA TUP/AESA Submission Date See ECN See ECN New data sheet Removed table - 3V DC General Purpose IO Specifications Updated Logic Block Diagram Updated table - DC POR and LVD Specifications Updated table - DC Chip Level Specifications Updated table - 5V and 3.3V DC General Purpose IO Specifications Updated table - 2.7V DC General Purpose IO Specifications Updated table - AC GPIO Specifications and split into 2 tables for 5V/3.3V and 2.7V Added section on CapSense ExpressTM Software tool Updated 16-QFN Package Diagram Updated tables-DC Chip Level Specifications Updated table-Pin Definitions 16 pin COL Updated table-Pin Definitions 16 pin SOIC Updated table-5V and 3.3V DC General Purpose IO Specifications Updated table - 2.7V DC General Purpose IO Specifications Changed definition for Timing for Fast/Standard Mode on the I2C Bus diagram Updated Logic Block Diagram and Features Added DC Programming Specifications Table Added CapSense Electrical Specifications Table Corrected typo in device name in ordering information (CY8C20140 to CY8C201A0) Different sleep modes explained Bi-Directional Sleep Control Pin defined Table added on "2.7V DC Spec for I2C Line with 1.8V External Pull up Included section on I2C Device Addressing Updated CapSense Electrical Specifications table Deleted VOH5, VOH6, VOH7, and VOH8 parameters Description of Change *B 2091026 DZU/MOHD /AESA See ECN *C 2404731 DZU/MOHD/ PYRS GUK/PYRS ZSK/AESA See ECN *D *E 2506321 2544918 See ECN See ECN *F 2648811 DZU/PYRS 01/28/09 Document Number: 001-17349 Rev. *F Page 15 of 16 [+] Feedback CY8C201A0 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-17349 Rev. *F Revised January 28, 2009 Page 16 of 16 CapSenseTM, CapSense ExpressTM, PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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