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| OneNANDTM256 / OneNANDTM512 FLASH MEMORY www..com OneNANDTMMCP SPECIFICATION NAND Density 256Mb NAND T.B.D KEF00F0000CM-EG00 KEF00F0000CM-SG00 512Mb NAND KEC00C00CM-EGG0 KEC00C00CM-SGG0 T.B.D 2.6V(2.4V~2.8V) 2.6V(2.4V~2.8V) 1.8V(1.7V~1.95V) 1.8V(1.7V~1.95V) Part No. VCC_core 1.8V(1.7V~1.95V) 2.6V(2.4V~2.8V) VCC_IO 1.8V(1.7V~1.95V) 2.6V(2.4V~2.8V) T.B.D 63FBGA(LF) 63FBGA 63FBGA(LF) 63FBGA T.B.D PKG Version: Ver. 0.0 Date: April 4, 2003 1 OneNANDTM256 / OneNANDTM512 1. FEATURES * Design Technology: 0.25m www..com * Voltage Supply - Main: 1.8V device(1.7V~1.95V) 2.6V device(2.4V~2.8V) - Host Interface & NAND Flash Interface: 1.8V device(1.7V~1.95V) 2.6V device(2.4V~2.8V) * Organization - Host Interface:16bit * Internal BufferRAM - BootRAM at booting, Cache-like at normal operation FLASH MEMORY Architecture Performance * Host Interface type - Synchronous Random Read : Clock Frequency: up to 45MHz @30pF - Synchronous Burst Read : Clock Frequency: up to 45MHz @30pF : Burst Length: 4 words/ 8 words/ 16 words/ 32 words/ Continuous Linear Burst(2K words) - Asynchronous Random Read - Asynchronous Page Read: 4words - Asynchronous Random Write * Programmable Read latency * 2Bit EDC / 1Bit ECC * Multiple Reset - Cold Reset / Warm Reset / Hot Reset * Internal Bootloader * Itelligent Data Protection * Unique ID - Detail information can be obtained by contact with Samsung Software * Handshaking Feature * Interface Chip ID Read - Detailed chip information by additional controller ID register * Package - 63ball, 9.5mm x 12mm x max 1.4mmt FBGA Packaging 2 OneNANDTM256 / OneNANDTM512 2. GENERAL DESCRIPTION FLASH MEMORY OneNANDTM (MCP of NAND Flash Interface chip and NAND Flash) allows standard NAND Flash chips to interface with OneNANDTM bus without performance penalty. This device is 1.8V/2.6V operation and comprised of about 10,000 gates and 4KB internal Bufferwww..com RAM. This 4KB BufferRAM is used as bootRAM during cold reset, and is used as cache RAM after cold reset. The operating clock frequency is up to 45MHz. This device is X16 interface with Host and X8 interface with NAND Flash. (Notice, in this specification, address is expressed by the byte order) Also this device has the speed of ~40ns random access time. Actually, it is accessible with minimum 3clock latency(host-driven clock for synchronous read), but this device adopts the appropriate wait cycles by programmable read latency. OneNANDTM provides the multiple page read operation by assigming the number of pages to be read in the page counter register. The device is offered in the single type of package; 63ball, 9.5mm x 12mm x max 1.4mmt FBGA. The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. 3 OneNANDTM256 / OneNANDTM512 3. PIN DESCRIPTION Pin Name Host Interface www..com A11~A0 I Type Nameand Description FLASH MEMORY Address Inputs - Inputs for addresses during read operation, which are for addressing BufferRAM & Register. Interrupt Notifyin Host when a command has completed. CMOS type driver output. Data Inputs/Outputs - Inputs data during program and commands during all operations, outputs data during memory array/ register read cycles. Data pins float to high-impedance when the chip is deselected or outputs aredisabled. Clock CLK synchronizes the device to the system bus frequency in synchronous read mode. The first rising edge of CLK in conjunction with AVD low latches address input. Write Enable WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse' rising edge s Address Valid Detect Indicates valid address presence on address inputs. During asynchronous read operation, all addresses are transparent during AVD' low, and during synchronous read operation, all addresses are s latched on CLK' rising edge while AVD is held low for one clock cycle. s >Low: for asynchronous mode, indicates valid address: for vurst mode, causes starting address to ve latched on rising edge on CLK >High: device ignores address inputs Reset Pin t When low, RP resets internal operation of OneNANDTM. RP status is don' care during power-up and bootloading. Chip Enable CE-low activates internal controll logic, and CE-high deselects the device, places it in standby state, and places A/DQ in Hi-Z Output Enable OE-low enables the device' output data buffers during a read cycle. s UID The device is set to access Unique ID from NAND when this is high. This should be low in normal operation. INT O DQ15~DQ0 I/O CLK I WE I AVD I RP I CE I OE I UID Power Supply VCC VSS-Core etc RFU DNU NC Power Ground Reserved for future use RFU1 reserved for A12. RFU2 is reserved for A15. RFU3 is reserved for A14. RFU4 is reserved for A13. Do Not Use Leave it disconnected. These pins are used for testing. No Connection Lead is not internally connected. NOTE: Do not leave power supply(VCC, VSS) disconnected. 4 OneNANDTM256 / OneNANDTM512 4. PIN CONFIGURATION www..com FLASH MEMORY NC NC NC NC NC NC NC WE RP DQ14 VSS VSS DQ13 DQ12 DQ8 DQ1 OE DQ9 VCC DQ7 DQ4 DQ11 DQ10 DQ3 VCC DQ15 RFU1 DQ0 RFU2 DQ5 DQ6 12mm fls CLK CE DQ2 NC UID A9 RFU3 RFU4 AVD A7 A11 A8 INT A0 A1 NC A10 A6 NC A4 A5 A2 A3 NC NC NC NC NC NC NC NC NC 9.5mm (TOP VIEW, Balls Facing Down) 63ball FBGA OneNANDTM Chip 9.5mm x 12mm x max. 1.4mmt, Ball Pitch: 0.8mm 5 OneNANDTM256 / OneNANDTM512 5. BLOCK DIAGRAM For OneNANDTMMCP www..com Bootloader FLASH MEMORY A0~A11 DQ0~DQ15 CLK CE OE WE RP BufferRAM (4K Bytes) 1) fCLE StateMachine Standard NAND Flashn Interface fALE fCE NAND Flash Host Interface Error Correction Internal Registers Logic (Address/Command/Configuration /Status Registers) fRE fWE fWP AVD INT fR/B I/O0~I/O7 - Host interface - 4KB BufferRAM - Command and status registers - State Machine (Bootloader is included) - Error Correction Logic - Standard NAND flash Interface - NAND Flash NOTE: 1) At cold reset, bootloader copies boot code(4K byte size) from NAND Flash BufferRAM. and except cold reset host can use BufferRAM like cacheRAM. 6 OneNANDTM256 / OneNANDTM512 6. ACCESS TIMINGS for OneNANDTM MCP Operation Standby www..com Warm Reset Asynchronous Write CE H X L OE X X H WE X X L A0~15 X X Add. In DQ0~15 High-Z High-Z Data In FLASH MEMORY RP H L H CLK X X X AVD X X Asynchronous Read L L H Add. In Data Out H L or Load Initial Burst Address L H H Add. In X H Burst Read L L H X Burst Dout H or Terminate Burst Read Cycle Terminate Burst Read Cycle Terminate Current Burst Read Cycle and Srart New Burst Read Cycle H X X X H X X X High-Z High-Z H L X X X X H H Add In High-Z H X=Don' Care t 7 OneNANDTM256 / OneNANDTM512 < BUS OPERATION > www..com Async. Write HOST FLASH MEMORY OneNANDTM Async. Random Read Async. Page Read Sync. Read < ACCESS TYPES > Figure 1. Asynchronous Read Mode * Please notice, tAES is Address delay from CE & AVD' low, and tAES should not be over 10ns. s tCE CE tAES* WE tAE CLK tOE OE RP Ai Valid Address tACC DQi Valid Data tOH 8 OneNANDTM256 / OneNANDTM512 Figure 2. Latched Asynchronous Read Mode www..com FLASH MEMORY tCE CE tAES* AVD WE tASA tAE CLK tOE OE RP Ai Valid Address tACC DQi Valid Data tOH 9 OneNANDTM256 / OneNANDTM512 Figure 3. Asynchronous Page Read Mode FLASH MEMORY * Please notice, tAES is Address delay from CE & AVD' low, and tAES should not be over 10ns. s www..com tCE CE tAES* tAE AVD tASA tOH WE CLK ' L' tOE OE RP A11~2 Valid Address A1~0 Valid Address Valid Address Valid Address Valid Address tAPA DQi tACC Data0 Data1 Data2 Data3 10 OneNANDTM256 / OneNANDTM512 Figure 4. Synchronous Burst Read Mode www..com FLASH MEMORY tCES CE tAVDS tAVDH AVD tOH WE CLK tBACC tBDH OE tOH RP tACS Ai Valid Address tIACC DQi Data0 Data1 Data2 tACH INT Read latency: 7clock(default), 3clock(min) 11 OneNANDTM256 / OneNANDTM512 Figure 5. Asynchronous Write Mode(No AVD pin case) www..com FLASH MEMORY tCS CE tWPL WE tWC CLK tWPH tCH OE RP WP tAWES Ai Valid Address tDS DQi tDH Valid Data Valid Address Valid Data INT 12 OneNANDTM256 / OneNANDTM512 Figure 6. Latched Asynchronous Write Mode www..com FLASH MEMORY tCS CE tAVDP AVD tWPL WE tWC CLK tWPH tCH OE RP WP tAAVDS Ai Valid Address tAWES DQi tDS tAAVDH Valid Address tDH Valid Data Valid Data INT 13 OneNANDTM256 / OneNANDTM512 Timing Diagram for OneNANDTM FLASH MEMORY The read cycle is initiated by first applying address to the address bus. The address latch is transparent while CE is low. The random access time is measured from a stable address, falling edge of CE. The clock should remain "0" during asynchronous access. www..com time(tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time(tCE) is the Address access delay from the stable addresses and stable CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of OE to valid data at the output. CE must toggle in asynchromous read operation. Figure 7. Asynchronous Read Mode tCE CE tAE OE tACC Ai tAES DQi Valid Data Valid Address tOE 14 OneNANDTM256 / OneNANDTM512 Lathced Asynchronous Read Operation FLASH MEMORY The read cycle is initiated by first applying address to the address bus. The address latch is transparent while AVD is low. The random access time is measured from a stable address, falling edge of AVD or falling edge of CE which ever occurs last. The clock www..com "0" during asynchronous access. Address access time(tACC) is equal to the delay from stable addresses to valid outshould remain put data. The chip enable access time(tCE) is the delay from the stable addresses and stable CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of OE to valid data at the output. CE and AVD must toggle in asynchromous read operation. Figure 8. Asynchronous Read Mode tCE CE AVD tAE OE tACC Ai tAES DQi Valid Data Valid Address tOE 15 OneNANDTM256 / OneNANDTM512 Asynchronous Page Read Operation FLASH MEMORY Asynchronous page read mode is the default state and provides a high data transfer rate for non clocked memory subsystems. The page size is four words, and A1~0 addresses one of the four words. The read cycle is initiated by first applying address to the www..com The address latch is transparent while AVD is low. The address is latched by internal address latch circuit. The random address bus. access time is measured from a stable address, falling edge of AVD or falling edge of CE which ever occurs last. The clock should remain "1" during asynchronous access. Address access time(tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time(tCE) is the delay from the stable addresses and stable CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of OE to valid data at the output. CE and AVD must toggle in asynchromous read operation. Figure 9. Asynchronous Page Read Mode tCE CE tOH tAE AVD tAES CLK ' L' tASA tOE OE A11~2 Valid Address A1~0 Valid Address tACC Valid Address Valid Address Valid Address tAPA Data0 Data1 Data2 Data3 DQi 16 OneNANDTM256 / OneNANDTM512 Synchronous Burst Read Operation FLASH MEMORY When the device is powered up, it defaults to asynchronous read operation. Burst mode is selected by System Configuration register bit 15. The burst mode is used to improve the data transfer between the memory and the system processor. The burst mode is used www..com only for read operations. Burst length is available on 4words/ 8words/ 16words/ 32words/ Continuous length, and is set by BL of System configuration reguster. The Bus Controller in the system will insert required read latency to meet host random access time. The first access time in the burst is equal to the random access time. In the burst access, the address is latched at the rising edge of the clock pulse when AVD is low. The first data in the burst access is available after the random access time. The Bus Controller reads s s data at the first rising edge of the clock after read latency. There is no conflict between AVD' low and OE' low. The output buffers need to settle before the first data is available. Due to this, the shortest random access is at least one clock cycles from the rising edge of the clock when AVD is low. This is defined as random access without any wait state. As the random access is allowed to be much longer than one clock cycles, the flash device has to support wait state insertion in order to synchronize the start of the burst access. Figure 10. Synchronous Burst Read Mode(3clock read latency case) CE AVD tBACC tBDH CLK OE Ai Valid Address tIACC DQi Data0 Data1 Data2 Data3 17 OneNANDTM256 / OneNANDTM512 Programmable Read Latency FLASH MEMORY The programmable read latency value indicates to the device the number of additional clock cycles that must elapse after AVD is driven active before data will be available. www..com read latency that should be programmed into the device is directly related to the clock frequency. Upon Power up, the The number of device defaults to seven cycles. The total number of the read latency is programmable from zero to seven cycles. A hardware reset will set read latency to seven cycles after power-up. The minimum read latency for this device is three cycle assuming 40MHz system clock. Figure 11. Example of 3clock Read Latency Insertion Ai Valid Address DQi Data 0 Data 1 Data 2 Data 3 Data 4 AVD tBACC OE tIACC CLK 0 1 2 3 Rising edge of the clock cycle following last read latency triggers next burst data tBDH Number of clock cycles programmed 18 OneNANDTM256 / OneNANDTM512 Asynchronous Write Operation FLASH MEMORY Write is allowed only in the asynchronous mode. The address is latched at the rising edge of the CE signal. The random access time is measured from a stable address, falling edge of CE. Write operations are asynchronous. Therefore, CLK is ignored during write www..com operation. There is no conflict between CE' low and OE' low. s s Figure 12 Asynchronous Write Mode CE WE Ai Valid Address tDS tDH DQi Valid Data 19 OneNANDTM256 / OneNANDTM512 Latched Asynchronous Write Operation FLASH MEMORY At Latched Asynchronous Write operation, the address is latched at the rising edge of the AVD signal. Because Write operations are asynchronous operation, CLK is ignored during write operation. There is no conflict between AVD' low and OE' low. s s www..com Figure 13. Latched Asynchronous Write Mode tCH CE AVD Address Latch WE Ai Valid Address tDS tDH DQi Valid Data 20 OneNANDTM256 / OneNANDTM512 7. Electrical Specifications 7-1. Absolute Maximum Ratings www..com Voltage on any pin relative to VSS Latch-up current Storage temperature Parameter VCC All other pins Symbol VCC VIN Ilatch TSTG FLASH MEMORY Rating 3.6 3.6 200 -65 to 150 Unit V mA C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 7-2 Recommended Operating Ratings 7-2-1. Supply Voltage(Voltage reference to GND) Parameter Supply Voltage Symbol Min VCC VSS 1.7 0 1.8V Part Typ. 1.8 0 Max 1.95 0 Min 2.4 0 2.6V Part Typ. 2.6 0 Max 2.8 0 V Unit 7-2-2. Temperature Parameter Commercial temperature Industrial temperature Symbol TA(Commercial temp.) TA(Industrial temp.) Rating 0 to 70 -25 to 85 Unit C 21 OneNANDTM256 / OneNANDTM512 7-3. DC Characteristics Parameter www..com Input leakage current Output leakage current Standby current Symbol Test Condition Min ILI ILO VIN=VSS to VCC VCC=VCC(max) VOUT=VSS to VCC VCC=VCC(max) VCC=VCC(max) CE=RP=VIH INT=floating VIN=VIH or VIL CE=VIL OE=VIH CE=VIL OE=VIH Continuous Burst CLK=45Mhz Program in Progress Erase in Progress IOH=-100uA VCC=VCC(min) IOH=-100uA VCC=VCC(min) Any input and Bi-directional buffers Any output buffers -7 -7 1.8V Part Typ. Max 7 7 FLASH MEMORY 2.6V Part Min -10 -10 Typ. Max 10 10 Unit uA ICCS - 22 85 22 85 Active Async. Read Current ICCR1 - 10 20 10 25 Active Sync. Read Current Active Program Current Active Erase Current Input High voltage Input Low voltage High level output voltage Low level output voltage Input capacitance1) Output capacitance1) NOTE: 1. This value excludes package parasitic ICCR2 - 11 20 11 25 mA ICCW ICCE VIH VIL VOH VOL CIN COUT VCC -0.4 -0.5 VCC0.2 - 12 12 - 20 20 VCC+ 0.4 0.4 0.2 10 10 VCC0.4 -0.5 VCC0.2 - 12 12 - 25 25 VCC+ 0.4 0.4 V 0.2 10 pF 10 22 OneNANDTM256 / OneNANDTM512 7-4. AC Test Condition Parameter FLASH MEMORY Value 0V to VCC 5ns VCC/2 CL=30pF www..com Input Palse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VCC VCC/2 0V Input Pulse and Test Point Input & Output Test Point VCC/2 Device Under Test CL=30pF Output Load 23 OneNANDTM256 / OneNANDTM512 7-5. AC Characteristics Asynchronous www..com Parameter tCE tOE tACC tAE tOH tAPA tASA tAES tCA FLASH MEMORY Read AC Parameters Description Min 1.8V Part Typ. Max 55 23 55 55 4 40 7 0 10 7 0 Min 0 2.6V Part Typ. Max 55 23 55 55 4 40 10 ns ns ns ns ns ns ns ns ns Unit Access time from CE Low Output Enable to Output Valid Asynchronous Access Time Random Access AVD-Data Valid Output hold from CE or OE change, whichever occurs first Page address access time Address setup to AVD high CE & AVD setup to Valid Address CE setup to AVD falling edge 0 Asynchronous Read AC Parameters Parameter tCES tIACC tBACC tBDH tAVDS tAVDH tACS tACH tOH tOE tCLKH tCLKL tCA Description Min CE setup time to CLK Initial Access Time @45Mhz Burst Access Time Valid clock to output delay Data hold time from next clock cycle AVD setup time to CLK AVD hold time to CLK Address setup time to CLK Address hold time to CLK Output hold from CE or OE change, whichever occurs first Output Enable ot Output Valid FlsCLK high time FlsCLK low time CE setup to AVD falling edge 10 10 0 5 4 5 7 5 7 4 23 10 10 0 1.8V Part Typ. Max 85.6 19 4 5 8 5 7 4 Min 5 2.6V Part Typ. 23 Max 84.6 17 ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 24 OneNANDTM256 / OneNANDTM512 Write AC Parameters Parameter www..com tAVDP tAAVDS tAWES tAAVDH tDS tDH tWC tWPL tWPH tCS tCH tAWES tVLWH AVD Low time Asynchronous Address setup time Asynchronous Address setup to new low Asynchronous Address hold time Data Setup Time Data Hold Time Write Cycle Time Write Pulse Width Low Write Pulse Width High CE setup time CE Hold Time Address setup to WE low AVD rising edge to WE rising edge Description Min 12 7 5 7 5 4 80 20 50 0 4 5 10 1.8V Part Typ. Max - FLASH MEMORY 2.6V Part Min 12 7 5 7 5 4 80 20 50 0 4 5 10 Typ. Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns 25 OneNANDTM256 / OneNANDTM512 FLASH MEMORY www..com *AVD connected case Host CE AVD ADD<12> ADD<3> ADD<2> ADD<1> ADD<0> GND or VDD OneNANDTM CE AVD ADD<11> ADD<2> ADD<1> ADD<0> > If host uses byte-order typed address, ADD<0> can be used as byte/word selection pin. *AVD disconnected case Host CE GND OneNANDTM CE AVD ADD<11> ADD<2> ADD<1> ADD<0> > If host uses byte-order typed address, ADD<0> can be used as byte/word selection pin. > In AVD disconnected case, AVD can be tIed to CE or GND. ADD<12> ADD<3> ADD<2> ADD<1> ADD<0> GND or VDD 26 |
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