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1 M x 1-Bit Dynamic RAM Low Power 1 M x 1-Bit Dynamic RAM
HYB 511000BJ-50/-60/-70 HYB 511000BJL-50/-60/-70
Advanced Information 1 048 576 words by 1-bit organization Fast access and cycle time 50 ns access time 95 ns cycle time (-50 version) 60 ns access time 130 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) * Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) 45 ns (-70 version) * Low power dissipation max. 495 mW active (-50 version) max. 440 mW active (-60 version) max. 385 mW active (-70 version) max. 5.5 mW standby max. 1.1 mW standby for L-version
* * * * * *
* *
*
Single + 5 V ( 10 %) supply with a built-in VBB generator Output unlatched at cycle end allows twodimensional chip selection Common I/O capability using "early write" operation Read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh, fast page mode capability and test mode capability All inputs, outputs and clocks TTL-compatible 512 refresh cycles/8 ms 512 refresh cycles/64 ms for L-version only Plastic Packages: P-SOJ-26/20-1
Ordering Information Type HYB 511000BJ-50 HYB 511000BJ-60 HYB 511000BJ-70 HYB 511000BJL-50 HYB 511000BJL-60 HYB 511000BJL-70 Ordering Code Q67100-Q1056 Q67100-Q518 Q67100-Q519 on request Q67100-Q526 Q67100-Q527 Package P-SOJ-26/20-1 P-SOJ-26/20-1 P-SOJ-26/20-1 P-SOJ-26/20-1 P-SOJ-26/20-1 P-SOJ-26/20-1 Description DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns)
Semiconductor Group
33
01.95
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
The HYB 511000BJ/BJL is the new generation dynamic RAM organized as 1 048 576 words by 1-bit. The HYB 511000BJ/BJL utilizes CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 511000BJ/BJL to be packaged in a standard plastic P-SOJ-26/20. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V ( 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. "Test Mode" function is implemented. The HYB 511000BJL are specially selected for low power battery backup applications. Pin Definitions and Functions Pin No. A0-A9 RAS DI DO CAS WE Function Address Inputs Row Address Strobe Data In Data Out Column Address Strobe Read/Write Input Power Supply (+ 5 V) Ground (0 V) Test Function No Connection
VCC VSS
TF N.C.
Semiconductor Group
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HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
Pin Configuration (top view)
SOJ-26/20-1
Semiconductor Group
35
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
Block Diagram Semiconductor Group 36
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
Absolute Maximum Ratings Operating temperature range .........................................................................................0 to + 70 C Storage temperature range......................................................................................- 55 to + 150 C Soldering temperature ............................................................................................................260 C Soldering time .............................................................................................................................10 s Input/output voltage ........................................................................................................ - 1 to + 7 V Test Function Input voltage ....................................................................................... - 1 to + 10.5 V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation..................................................................................................................... 0.6 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 % Parameter Input high voltage Input low voltage Test enable input high voltage Test disable input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current, any input except TF (0 V VIN 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V VOUT 5.5 V) Average VCC supply current: -50 version -60 version -70 version (RAS, CAS, address cycling: tRC = tRC min.) Symbol Limit Values min. max. 6.5 0.8 2.4 - 1.0 - 1.0 2.4 - - 10 - 10 Unit Test Condition V V V V V A A
1) 1) 1) 1) 1) 1) 1)
VIH VIL VIH(TF) VIL(TF) VOH VOL II(L) IO(L) ICC1
VCC + 4.5 10.5
- 0.4 10 10
VCC + 1.0 V
1)
- - - -
90 80 70 2
mA mA mA mA
2) 3) 2) 3) 2) 3)
Standby VCC supply current (RAS = CAS = VIH) ICC2
-
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HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
DC Characteristics (cont'd) TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 % Parameter Average VCC supply current during RAS only refresh cycles: -50 version -60 version -70 version (RAS cycling: CAS = VIH : tRC = tRC min.) Average VCC supply current during fast page modes: -50 version -60 version -70 version (RAS = VIL , CAS, address cycling: tPC = tPC min.) Standby VCC supply current L-Version (RAS = CAS = VCC - 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode: -50 version -60 version -70 version (RAS, CAS, address cycling: tRC = tRC min.) Symbol Limit Values min. max. 90 80 70 Unit Test Condition mA mA mA
2) 2) 2)
ICC3
- - -
ICC4
- - - 70 60 50 mA mA mA
2) 3) 2) 3) 2) 3)
ICC5
- -
1 200
mA A
1) 1)
ICC6
- - - 90 80 70 mA mA mA
2) 2) 2)
For L-version only: Battery backup current: average power supply current, battery backup mode: (CAS = CAS before RAS cycling or 0.2 V, WE = VCC - 0.2 V or 0.2 V, A0 to A9 = VCC - 0.2 V or 0.2 V, DI = VCC - 0.2 V or 0.2 V open, tRC = 125 s, tRAS = tRAS min. ~ 1 s) Input leakage current (only TF) (0 V VIN (TF) VCC + 0.5 V) All other pins not under test = 0 V
Test function input current (VCC + 4.5 VIN (TF) 10.5 V)
ICC7
-
300
A
2)
IITF(L)
- 10
+ 10
A
1)
ITF
-
1
mA
1)
Semiconductor Group
38
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
AC Characteristics 4) 13) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol -50 min. Random read or write cycle time Read-write cycle time Fast page mode cycle time Fast page mode readwrite cycle time Access time from RAS Access time from CAS
6) 11)
Limit Values -60 min. 110 130 40 60 - - - - 0 0 3 40 60 max. - - - - 60 15 30 35 - 20 50 - 10.000 min. 130 155 45 70 - - - - 0 0 3 50 70 -70 max. - - - - 70 20 35 40 - 20 50 - 10.000 max. - - - - 50 15 25 30 - 15 50 - 10.000
Unit
tRC tRWC tPC tPRWC tRAC tCAC
95 115 35 55 - - - - 0 0 3 35 50 50 15 50 30 30 15 20
ns ns ns ns ns ns ns ns ns ns ns ns ns
6) 11)
Access time from column tAA 6) 12) address
tCPA Access time from CAS 6) precharge
CAS to output in low-Z 6) tCLZ Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS pulse width (fast page mode) RAS hold time CAS hold time RAS hold time from CAS precharge (FPM) CAS precharge to WE delay time (FPM RMW) CAS pulse width RAS to CAS delay time
11) 7)
tOFF tT tRP tRAS tRASP tRSH tCSH tRHCP tCPWD tCAS tRCD
5)
100.000 60 - - - - 10.000 35 15 60 35 35 15 20
100.000 70 - - - - 10.000 45 20 70 45 45 20 20
100.000 ns - - - - 10.000 50 ns ns ns ns ns ns
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HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
AC Characteristics (cont'd) 4) 13) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol -50 min. RAS to column address tRAD 12) delay time CAS to RAS precharge time 15 5 10 0 10 0 15 25 0 0 0 10 10 15 15 0 10 - - max. 25 - - - - - - - - - - - - - - - - 8 64 min. 15 5 10 0 10 0 15 30 0 0 0 10 10 15 15 0 15 - - Limit Values -60 max. 30 - - - - - - - - - - - - - - - - 8 64 min. 15 5 10 0 10 0 15 35 0 0 0 15 15 20 20 0 15 - - -70 max. 35 - - - - - - - - - - - - - - - - 8 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms Unit
tCRP
CAS precharge time (fast tCP page mode) Row address setup time Row address hold time Column address setup time Column address hold time Column address to RAS lead time Read command setup time Read command hold time
8)
tASR tRAH tASC tCAH tRAL tRCS tRCH
Read command hold time tRRH 8) referenced to RAS Write command hold time tWCH Write command pulse width Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Refresh period Refresh period for L-version only
9) 9)
tWP tRWL tCWL tDS tDH tREF tREF
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HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
AC Characteristics (cont'd) 4) 13) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol -50 min. Write command setup tWCS 10) time CAS to WE delay time
10)
Limit Values -60 min. 0 15 60 30 5 15 0 30 max. - - - - - - - - min. 0 20 70 35 5 15 0 40 -70 max. - - - - - - - - max. - - - - - - - -
Unit
0 15 50 25 5 10 0 25
ns ns ns ns ns ns ns ns
tCWD
RAS to WE delay time 10) tRWD Column address to WE tAWD 10) delay time CAS setup time (CASbefore-RAS cycle) CAS hold time (CASbefore-RAS cycle) RAS to CAS precharge time CAS precharge time (CAS-before-RAS counter test cycle) Test mode enable setup time referenced to RAS Test mode enable hold time referenced to RAS Test mode enable hold time referenced to CAS
tCSR tCHR tRPC tCPT
tTES tTEHR tTEHC
0 0 0
- - -
0 0 0
- - -
0 0 0
- - -
ns ns ns
Capacitance TA = 0 to 70 C; VCC = 5 V 10 %; f = 1 MHz Parameter Input capacitance (A0 to A9, DI) Input capacitance (RAS, CAS, WE, TF) Output capacitance (DO) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CO
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41
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
Notes :
1) All voltages are referenced to VSS . 2) ICC1 , ICC3 , ICC4, ICC6, ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) An initial pause of 200 s is required after power-up followed by 8 RAS cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL . 6) Measured with a load equivalent to 2 TTL loads and 100 pF. 7) tOFF (max.) defines the time at which the output achieves the open-circuit conditions and is not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 10) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD tRWD (min.), tCWD tCWD (min.) and tAWD tAWD (min.), the cycle is a read-write cycle and DO will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of DO (at access time) is indeterminate. 11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC . 12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA . 13) AC measurements assume tT = 5ns.
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42
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
Waveforms
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column Address
tASR
Row Address
A0 - A9
V IH VIL
Row Address
tRCH tRAH tRCS tRRH tAA tCAC tOFF
Valid Data Out Hi Z
WE
V IH VIL
OH DO (Output) V OL
V
tCLZ
Hi Z
tRAC
"H" or "L"
Read Cycle
Semiconductor Group
43
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column Address
tASR
Row Address
A0 - A9
V IH VIL
.
Row Address
tRAH
WE
V IH VIL
tWCS
tCWL t WP tWCH tRWL tDH
tDS
DI (Input)
V IH VIL
Valid Data In
DO (Output)
V OH V OL "H" or "L"
Hi Z
Write Cycle (Early Write)
Semiconductor Group
44
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
tRWC tRAS
RAS
tRP
tCSH tRCD
CAS
V IH VIL
tRSH tCAS
tCRP
tRAH
V IH
tCAH tASC
Column Address
tASR
Row Address
tASR
Row Address
A0 - A9 V IL
tRAD
V IH
tAWD tCWD tRWD
tCWL tRWL tWP
WE
VIL
tAA tRCS
DI (Input)
V IH VIL
tDS tDH
Valid Data in
tCLZ tCAC
Data Out
DO (Output) V OL
V OH
tOFF
tRAC
"H" or "L"
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
45
tRASP tRP tPRWC tCP tCAS tCAS tCAH tASC tASC
Column Address Column Address
V
RAS
IH
V IL
tCSH tRCD tCAS tRAL tASR
Row Address
tRSH tCRP
Semiconductor Group
V
CAS
IH
V IL
tASR tASC
Column Address
tRAD tRAH tCAH tCAH
V
A0-A9
IH
V IL
Row Address
Fast Page Mode Read-Modify-Write Cycle
V
tRCS tAWD tWP tCPA
Data In Data In
tRWD tCWD tCWL tAWD tWP tCPA tCWL
tCPWD tCWD
tCPWD tCWD
tRWL tCWL
WE
IH
46
V IL
tAWD tAA tCLZ
tWP
V
IH DI (Input) V IL
Data In
tCAC tRAC tDH tDS tOFF
Data Out
tCLZ tCAC tAA tDS
Data Out
tCLZ tDH tOFF tAA tDS
Data Out
tDH tOFF
DO (Output) V
V OH
OL
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
"H" or "L"
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
tRASP
V IH
tRP
RAS
VIL
tRCD
V IH
tPC tCP tCAS tCSH tCAS
tRHCP tRSH tCAS tCRP
CAS
VIL
tRAH tASR
A0-A9
V IH VIL
Row Addr
tASC
tCAH
Column Address
tASC
tCAH tASC
tCAH tASR
Row Address Column Address
Column Address
tRAD tRCH tRCS tRCS tRCS
tRCH
V IH
WE
VIL
tAA tCAC tRAC tCLZ
DO (Output) V OL
V OH
Valid Data Out
tCPA tAA tCAC tOFF tCLZ
Valid Data Out
tCPA tAA tCAC tOFF tCLZ
tRRH
tOFF
Valid Data Out
"H" or "L"
Fast Page Mode Read Cycle
Semiconductor Group
47
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
tRASP
V IH
tRP
RAS
VIL
tPC tCAS tRCD tCP
tCAS
tRSH tCAS tCRP
V IH
CAS
VIL
tRAL tRAH tASR tCAH tASC
Column Address
tASC tCAH
Column Address
A0-A9
V IH VIL
tASC
tCAH
tASR
Row Address
Row Addr
Column Address
tRAD
V IH VIL
tCWL tWCS tWCH tWP tDH
tCWL tWCS tWCH tWP
tCWL tRWL tWCS tWCH tWP
WE
tDH tDS
Valid Data In
tDH tDS
Valid Data In
tDS
DI (Input)
V IH VIL Valid Data In
DO V (Output) OH
V OL
HI-Z
"H" or "L"
Fast Page Mode Early Write Cycle
Semiconductor Group
48
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCRP tRPC
V IH
CAS
VIL
tRAH tASR
tASR
Row Address
A0-A9
V IH VIL
Row Address
OH DO (Output) V OL
V
HI-Z
"H" or "L"
RAS-Only Refresh Cycle
Semiconductor Group
49
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
tRC tRP
RAS
V IH VIL
tRAS
tRP
tRPC tCSR
CAS
V IH VIL
tCRP tCHR tRPC
tCP tWRP tWRH
WE
V IH VIL V
OH DO (Output) VOL
HI-Z
tOFF
"H" or "L"
CAS-Before-RAS Refresh Cycle
Semiconductor Group
50
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
tRC
V IH VIL
tRC tRP tRAS tRP
tRAS
RAS
tRCD
V IH VIL
tRSH tCHR tCRP
CAS
tRAD tRAH tASR tASC tWRP tCAH tWRH tASR
Row Address
A0-A9
V IH VIL
Row Addr
Column Address
tRCS
WE
V IH VIL
tRRH
tAA tCAC tCLZ tRAC tOFF
DO (Output) V OL
V OH
Valid Data Out
HI-Z
"H" or "L"
Hidden Refresh Cycle (Read)
Semiconductor Group
51
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
tRC tRP
RAS
V IH VIL
tRC tRAS tRP
tRAS
tRCD
V IH VIL
tRSH
tCHR
tCRP
CAS
tRAD tRAH tASR tASC tCAH
Column Address
tASR
Row Address
A0-A9
V IH VIL
Row Addr
tWCS
tWCH tWP
WE
V IH VIL
tDS
DI (Input)
V IH V IL
tDH
Valid Data
OH DO (Output) V OL
V
HI-Z
"H" or "L"
Hidden Refresh Cycle (Early Write)
Semiconductor Group
52
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
V
tRAS
IH
tRP tRSH tCAS
RAS
V
IL
tCSR
V
tCHR
tCPT
CAS
IH
V
IL
V
tASC
IH
tCAH tAA tCAC
tRAL
tASR
Row Address
A0-A9
V
Read Cycle
WE
IL
Column Address
tWRP
V V
tWRH
IH
tRCS
tRRH tRCH tOFF
IL
tCLZ
DO (Output)
V OH VOL
Write Cycle
V IH
tWRP tWRH
tWCS
Valid Data Out
tRWL tCWL tWCH
WE
V
IL
tDS
DI (Input) DO (Output)
V V IH IL
tDH tCWL tRWL tWP
Valid Data In
V IH V IL V IH
tWRP
HI-Z
Read-Modify-Write Cycle
WE
V IL
tWRH
tRCS tAA
tAWD tCWD tCAC tDS
tDH
DI (Input) DO (Output)
V V IH
Data In
IL
V OH VOL
tCAC t CLZ
HI-Z HI-Z
tOFF
Valid Data Out
"H" or "L"
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
53
HYB 511000BJ/BJL-50/-60/-70 1 M x 1-DRAM
Test Mode
The HYB 511000B/BL is the RAM organized 1 048 576 words by 1-bit, it is internally organized 262 144 words by 4-bit. In "Test Mode", data would be written into a number of sectors (4 sectors) in parallel and retrieved the same way. If upon reading, all bits are equal (all "H" or "L"), the data output pin indicates a same data as all bits. In this case, the data output pin indicates an expected data for good parts, the data output pin indicates a complementary data for bad parts. And also, if any of the bits differed, the data output pin would indicate a high impedance state for bad parts. The next figure shows the block diagram including its truth table when "Test Mode" is used. In test mode, 1M DRAM can be tested as if it were 256K DRAM by the following method. "Test Mode" function is performed on any of the timing cycles including fast page mode when "TF" pin is held on "super voltage (VCC + 4.5 V (VCC = 5 V 10 %), max. voltage = 10.5 V)" for the specified period (tTES , tTEHR and tTEHC ; see next figure). The address input of A9 is ignored in the "Test Mode". On the other hand, normal operation requires the "TF" pin be connected to VIL(TF) level, or left unconnected on the printed wiring board. The "Test Mode" function reduces test times (1/4; in case of using N test pattern).
RAS
V IH VIL
tTEHC
CAS
V IH VIL
tTES
TF
V IH,TF VIL,TF
tTEHR
Test Mode Cycle
Semiconductor Group
54

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