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| www..com INF85116 2048 8 -Bit CMOS EEPROM with I2-bus interface The INF85116N is an 16-Kbits (2048 x 8-bit) floating gate Electrically Erasable Programmable Read Only Memory (EEPROM). Power consumption is low due to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier. As data bytes are received and transmitted via the serial I2C-bus, a package using eight pins is sufficient. Only one INF85116N device is required to support all eight blocks of 256 x 8-bit each. FEATURES * Low power CMOS -maximum active current 1.0 mA -maximum standby current 10 A (at 5.5 V), typical 4 A * Non-volatile storage of 16-Kbits organized as eight blocks of 256x8-bits during 20 years ( at 55oC ) * Single supply (Ucc=2,7 / 5,5 V); * Automatically increased word's address * On-chip voltage multiplier * Serial input/output I2C-bus * 1000000 ERASE/WRITE cycles per byte * Internal timer for writing (no external components) .com DataShee * Write operations: multi byte write mode to 32 bytes * Write - protection input * Power-on-reset Temperature range: -40oC / +85oC PIN DESCRIPTION Simbol n. c. n. c n. c Uss SDA SCL WP Ucc Pin 1 2 3 4 5 6 7 8 Description not connected not connected not connected negative supply voltage serial data input/output ( I2Cbus) serial clock input ( I2C-bus) write - protection input positive supply voltage PIN CONFIGURATION n. c. n. c. n. c. Uss 1 2 8 7 Ucc WP SCL SDA INF85116N 3 4 6 5 Table 1. Quick reference data Symbol Parameter min max Unit 1 .com .com DataSheet 4 U .com www..com INF85116 UDD IOL Tamb Supply voltage LOW level output current Operating ambient temperature 2.7 -40 5.5 6 +85 V m BLOCK DIAGRAM 8 SCL 6 5 SDA VDD 7 WP Input filter I2C-bus control logic VSS Test mode register Address comparator Shift register Address pointer Sequenser Column decoder HV generator Page register Divider EEPROM ARRAY (8x256x8) t4U.com Power-on-reset .com Row dec Oscillator DataShee 4 VSS Table 2. Limiting values Symbol UDD Ui Ii Io Tstg Parameter Supply voltage Input voltage on any pin /Zi/>500 Input current on any pin Output current Storage temperature min -0.3 -0.8 -65 max 6.5 6.5 1 10 +150 Unit V V m m 2 .com .com DataSheet 4 U .com www..com INF85116 Table 3. Characteristics Symbol IDD(stb) ICCR ICCW Parameter Standby supply current Supply current READ Supply current E / W Conditions UDD = 2.7V UDD = 5.5V fSL=400Hz, UDD = 5.5V fSL=400Hz, UDD = 5.5V min max 6 10 1 1 Unit m m WP input (pin 7) UIL LOW level input voltage UIH HIGH level input voltage SCL input (pin 6) UIL LOW level input voltage UIH HIGH level input voltage ILI Input leakage current fSCL Clock input frequency tsp Pulse width of spikes suppressed by filter I Input capacitance SDA input/output (pin 5) UIL LOW level input voltage UIH HIGH level input voltage UOL1 LOW level output voltage UOL2 t4U.com -0.8 0.9UDD -0.8 0.7UDD 0 0 -0.8 0.7UDD - +0.1UDD UDD+0.8 +0.3UDD 6.5 1 400 100 V V V V kHz ns pF V V V UI=UDD or USS UI= USS 7 0.3UDD 6.5 0.4 IOL=3m, UDD = UDD (min) IOL=6m, 0.6 UDD = UDD (min) .com ILO Output leakage current UOH=UDD 1 tO(F) Output fall time from UIHmin with up to 3m sink to UILmax current at UOL1 20+0.1 CB* 250 with up to 6m sink current at UOL2 20+0.1 CB 250 tSP Pulse width of spikes suppressed 0 100 by filter I Input capacitance UI=0V 10 tE/W E/W cycle time 10 100000 NE/W E/W cycle per byte amb =(-40-+85) , 1000000 amb =22 tS Data retention time amb = 55 20 - The bus capacitance ranges from 10 to 400pF ( CB = total capacitance of one bus line in pF) DataShee ns ns ns pF ms years 3 .com .com DataSheet 4 U .com www..com INF85116 ble 4. I2C-bus characteristics Symbol Parameter Conditions Standard mode min max 0 100 4.7 4.0 4.7 4.0 4.7 5 0 250 1000 300 Fast mode min 0 1.3 0.6 1.3 0.6 0.6 0 100 20+0. 1 Cb(2) 20+0. 1 Cb(2) 0.6 max 400 300 300 Unit fSCL tBUF tHD, STA tLOW tHIGH tSU, STA tHD, DAT tHD, DAT tSU, DAT tR tF Clock frequency Time the bus must be free before START condition hold time after which first clock pulse is generated LOW level clock period HIGH level clock period Set-up time for START condition Data hold time for CBUS compatible masters Data hold time for I2C - bus devices Data set-up time SDA and SCL rise time SDA and SCL fall time repeated start note 1 - kHz s s s s s s ns ns ns ns tSU, STO Set-up time for STOP condition 4.0 s Notes: 1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by a transmitter. 2. Cb = total capacitance of one bus line in pF. t4U.com .com 4 .com .com DataSheet 4 U .com |
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