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PAS6301 Gigabit Ethernet Optical Network Unit SOC 44 Released Product Brief PRODUCT BENEFITS * Full IEEE 802.3ah EPON ONU functionality with integrated ARM9 CPU * Integrated SERDES for EPON tranceiver connection * Flexible optical transceiver interface for support of multiple vendors * Integrated encryption for enhanced security and privacy based on and comprehensive software package * Includes support for CTC EPON technical requirements version 1.0 * Advanced classification engine with support for VLAN, IP, TCP & UDP AES or churning * Advanced threshold and queue level reporting to support high * Advanced switch management capabilities including a standard MII Th driver providing an easy maintenance cost effective solution so interface and an L2 software management package (STP, IGMP, etc.) supporting various external switches n ta o EPON MAC SERDES FEC of PAS6301 ee fo BLOCK DIAGRAM cu ur * A glueless interface to on-board limiting amplifier and laser diode sd to provide true "triple-play" services quality of service DBA algorithms FEATURES * Gigabit Ethernet PON ONU based on 802.3ah standard * Integrated SERDES and CDR for loop timing support ay ,1 4D * FEC coding for improved link budget ec em VxWorks and a low footprint RTOS Memory Controller Rate Limiter D/S Queue MAC LLID Bridge Security Classifier be The PAS6301 is a Gigabit Ethernet Optical Network Unit (ONU)system on a chip dedicated for use in an Ethernet Passive Optical Network (IEEE 802.3ah EPON). The PAS6301 chip integrates the Ethernet Media Access Control (MAC) functionality, EPON protocol management, an advanced L2/3/4 classification engine, a powerful embedded CPU and www..com a glueless interface to an on-board Analog Front End (AFE). An integrated software package provides a complete ONU solution. * Open Software development platform with support for Linux, r, and downstream and can be configured to operate per priority queue, per the whole ONU, or per VID . An additional mode exists for upstream enabling the rate limitation of multicast and broadcast frames separately. VLAN 20 06 06 * An advanced Rate Limiter which can be operated in both upstream :3 and up to 8MB of bursty traffic protection liu by Optics Control MPCP Engine U/S Queue VLAN Rate Limiter Classifier 10/ 100 MAC lo ad ed 8: GENERAL DESCRIPTION * A cost effective SDRAM based packet buffer with 8 queue priorities 10/100/ 1000 MAC Do wn RAM ROM ARM922 CPU with MMU PON Queue UNI Queue TWI OAM Registers Memory Controller A2D UART GPIO EEPROM IF PMC-2061051, Issue 1 (c) Copyright PMC-Sierra, Inc. 2006 All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers' internal use. PM MDIO LED PAS6301 Gigabit Ethernet Optical Network Unit SOC * FEC support for improved optical budget and split ratio * Programmable interface logic for optical transceiver * Integrated ARM9 CPU (including MMU) * Complete ONU software package development platform supports * Comprehensive software management package including SNMP, Web-based management, Remote software download, STP and IGMP * Full VoIP stack executed on the embedded ARM9 with no need for an * An integrated Analog to Digital (A2D) automatic operation and OEM vendor extensions * Support for buffer threshold reporting for compatibility with * Glueless interface to an on board Limiting Amplifier (LIA) and Laser dynamic threshold control * 8 priority queues with multiprotocol classifier including: * * * * Diode Driver (LDD) VLAN manipulation and QOS support 802.1p priority, IPv6, IPv4 IGMP INTERFACES * Full duplex transmit and receive EPON port operating at 1.25Gbit/s * Full-duplex 10/100 MII and 1000Mbit/s GMII Ethernet for * 802.1x Authentication engine with remote administration * 802.3x flow control for UNI * 802.1D Bridging: Includes 128 port local address table with aging access * 32 bit memory controller for 8MB SDRAM packet buffer * Optional EEPROM for boot and configuration parameters * Eight LED indications * Dying gasp and vendor event generation pins * Two-wire SFP interface port * Two UART ports for debug and control by external devices * Flow control in uplink queues according to programmable fields including ToS, CoS, VLAN, Ethertype, IP address, TCP/UDP port cu ta o Optical Transceiver of EPON ee fo Packet Buffer so n ONU EXAMPLE USING PAS6301 Th ur sd ay * Optional external CPU management via UART or Ethernet ,1 for isolation of home traffic from network 4D ec em * 128 bit AES encryption - downstream and upstream * 32 bit memory controller for FLASH, SDRAM and general peripheral be * Full OAM feature set termination according to 802.3ah connectivity to standard switch ICs or PHY devices PAS6301 Ethernet Switch r, IP, TCP, UDP www..com 20 with integrated SERDES Laptop liu EEPROM (Optional) FLASH SDRAM VoIP DSP Telephone lo ad ed by FURTHER RESOURCES www.pmc-sierra.com/passave/ www.pmc-sierra.com/ftth-pon/ Do wn Corporate Head Office: PMC-Sierra, Inc. Mission Towers One 3975 Freedom Circle Santa Clara, CA, 95054, U.S.A. Tel: 1.408.239.8000 Fax: 1.408. 492.1157 Operations Head Office: PMC-Sierra, Inc. 100-2700 Production Way Burnaby, BC V5A 4X1 Canada Tel: 1.604.415.6000 Fax: 1.604.415.6200 PMC-2061051 (R1)(c) Copyright PMC-Sierra, Inc. 2006. All rights reserved. For a complete list of PMC-Sierra's trademarks , visit www.pmc-sierra.com/legal/. Other product and company names mentioned herein may be the trademarks of their respective owners. For corporate information, send email to: info@pmc-sierra.com. All product documentation is available on our web site at: www.pmc-sierra.com. 06 PC Set-top box 06 :3 8: 44 PM external CPU |
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