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S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C70F2/C70F4 single-chip CMOS microcontroller has been designed for high-performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The S3P70F4 is the microcontroller which has 4 Kbyte one-time-programmable ROM and the functions are the same to S3C70F2/C70F4. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and its versatile 8-bit timer/counter, the S3C70F2/C70F4 offers an excellent design solution for a wide variety of general-purpose applications. Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast response to internal and external events. In addition, the S3C70F2/C70F4's advanced CMOS technology provides for very low power consumption and a wide operating voltage range -- all at a very low cost.
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PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
FEATURES SUMMARY
Memory
* *
Bit Sequential Carrier
*
512 x 4-bit data memory (RAM) 2048 x 8-bit program memory (ROM):S3C70F2 4096 x 8-bit program memory (ROM):S3C70F4
Supports 16-bit serial data transfer in arbitrary format
Interrupts
* * *
24 I/O Pins
* *
Two external interrupt vectors Three internal interrupt vectors Two quasi-interrupts Data memory bank 15
I/O: 18 pins, including 8 high current pins Input only: 6 pins 4-channel mode: Internal reference (4-bit resolution) 16-step variable reference voltage 3-channel mode: External reference 150 mV resolution (worst case) Programmable interval timer Watch-dog timer
Comparator
*
Memory-Mapped I/O Structure
*
Two Power-Down Modes
* *
*
Idle mode: Only CPU clock stops Stop mode: System clock stops
8-bit Basic Timer
* *
OSCILLATION SOURCES
* * *
Crystal, Ceramic for system clock Crystal/ceramic: 0.4 - 6.0 MHz CPU clock divider circuit (by 4. 8, or 64)
8-bit Timer/Counter 0
* *
Programmable interval timer External event counter function Timer/counter clock output to TCLO0 pin Time interval generation: 0.5 s, 3.9 ms at 4.19 MHz 4 frequency outputs to BUZ pin
Instruction Execution Times
* *
0.95, 1.91, 15.3 s at 4.19 MHz 0.67, 1.33, 10.7 s at 6.0 MHz
Watch Timer
* *
Operating Temperature
*
- 40 C to 85 C
8-bit Serial I/O Interface
* * * *
Operating Voltage Range
*
8-bit transmit/receive mode 8-bit receive-only mode LSB-first or MSB-first transmission selectable Internal or external clock source
1.8 V to 5.5 V
Package Type
*
30 SDIP, 32 SOP
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S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
FUNCTION OVERVIEW
SAM47 CPU All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two cycles. CPU REGISTERS Program Counter A 11-bit program counter (PC) stores addresses for instruction fetch during program execution. Usually, the PC is incremented by the number of bytes of the instruction being fetched. An exception is the 1-byte instruction REF which is used to reference instructions stored in a look-up table in the ROM. Whenever a reset operation or an interrupt occurs, bits PC11 through PC0 are set to the vector address. Bit PC13-12 is reserved to support future expansion of the device's ROM size. Stack Pointer An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in the generalpurpose data memory bank 0. The SP is read or written by 8-bit instructions and SP bit 0 must always be set to logic zero. During an interrupt or a subroutine call, the PC value and the program status word (PSW) are saved to the stack area in RAM. When the service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction is executed. The stack pointer can access the stack regardless of data memory access enable flag status. Since the reset value of the stack pointer is not defined in firmware, it is recommended that the stack pointer be initialized to 00H by program code. This sets the first register of the stack area to data memory location 0FFH. PROGRAM MEMORY In its standard configuration, the 4096 x 8-bit ROM is divided into three functional areas: -- 16-byte area for vector addresses -- 96-byte instruction reference area -- 1920-byte general purpose area (S3C70F2) -- 3968-byte general purpose area (S3C70F4) The vector address area is used mostly during reset operations and interrupts. These 16 bytes can also be used as general-purpose ROM. The REF instruction references 2 x 1-byte and 2-byte instructions stored in locations 0020H-007FH. The REF instruction can also reference 3-byte instructions such as JP or CALL. In order for REF to be able to reference these instructions, however, JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written to the reference area with the format TJP or TCALL instead of the normal instruction name. Unused locations in the instruction reference area can be allocated to general-purpose use.
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PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
DATA MEMORY Overview Data memory is organized into three areas: -- 32 x 4-bit working registers -- 224 x 4-bit general-purpose area in bank 0 -- 256 x 4-bit general-purpose area in bank 1 -- 128 x 4-bit area in bank 15 for memory-mapped I/O addresses Data stored in data memory can be manipulated by 1-, 4-, and 8-bit instructions. Data memory is organized into two memory banks -- bank 0, bank 1 and bank 15. The select memory bank instruction (SMB) selects the bank to be used as working data memory. After power-on reset operation, initialization values for data memory must be redefined by code. Data Memory Addressing Modes The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1 or 15. When the EMB flag is logic zero, restricted area can be accessed. When the EMB flag is set to logic one, all two data memory banks can be accessed according to the current SMB value. The EMB = "0" addressing mode is used for normal program execution, whereas the EMB = "1" mode is commonly used for interrupts, subroutines, mapped I/O, and repetitive access of specific RAM addresses. Working Registers The RAM's working register area in data memory bank 0 is further divided into four register banks. Each register bank has eight 4-bit registers that are addressable either by 1-bit or 4-bit instructions. Paired 4-bit registers can be addressed as double registers by 8-bit instructions. Register A is the 4-bit accumulator and double register EA is the 8-bit extended accumulator. Double registers WX, WL, and HL are used as data pointers for indirect addressing. Unused working registers can be used as general-purpose memory. To limit the possibility of data corruption due to incorrect register bank addressing, register bank 0 is usually used for the main program and banks 1, 2, and 3 for interrupt service routines.
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S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
CONTROL REGISTERS Program Status Word The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also used to restore a program's execution environment when an interrupt has been serviced. Program instructions can always address the PSW regardless of the current value of data memory enable flags. Before an interrupt or subroutine is processed, the PSW values are pushed onto the stack in data memory bank 0. When the service routine is completed, the PSW values are restored. IS1 C IS0 SC2 EMB SC1 ERB SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. You can address the skip condition flags (SC0-SC2) using 8-bit read instructions only. Select Bank (SB) Register Two 4-bit registers store address values used to access specific memory and register banks: the select memory bank register, SMB, and the select register bank register, SRB. 'SMB n' instruction selects a data memory bank (0 or 15) and stores the upper four bits of the 12-bit data memory address in the SMB register. To select register bank 0, 1, 2, or 3, and store the address data in the SRB, you can use the instruction 'SRB n'. The instructions "PUSH SB" and "POP SB" move SRB and SMB values to and from the stack for interrupts and subroutines. CLOCK CIRCUITS System oscillation circuit generates the internal clock signals for the CPU and peripheral hardware. The system clock can use a crystal, or ceramic oscillation source, or an externally-generated clock signal. To drive S3C70F2/C70F4 using an external clock source, the external clock signal should be input to Xin, and its inverted signal to Xout. 4-bit power control register controls the oscillation on/off, and select the CPU clock. The internal system clock signal (fx) can be divided internally to produce three CPU clock frequencies -- fx/4, fx/8, or fx/64. INTERRUPTS Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, and INTS) or externally by peripheral devices (INT0 and INT1). There are two quasi-interrupts: INTK and INTW. INTK (KS0-KS2) detects falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91 milliseconds. The following components support interrupt processing: -- Interrupt enable flags -- Interrupt request flags -- Interrupt priority registers -- Power-down termination circuit
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PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
POWER-DOWN To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle mode; the STOP instruction initiates stop mode. In idle mode, the CPU clock stops while peripherals continue to operate normally. In stop mode, system clock oscillation stops completely, halts all operations except for a few basic peripheral functions. A power-down is terminated either by a RESET or by an interrupt (with exception of the external interrupt INT0). RESET When RESET is input during normal operation or during power-down mode, a reset operation is initiated and the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has elapsed, normal CPU operation resumes. I/O PORTS The S3C70F2/C70F4 has seven I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H-FF6H in bank 15 of the RAM. There are 6 input pins and 18 configurable I/O pins including 8 high current I/O pins for a total of 24 I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. TIMERS and TIMER/COUNTER The timer function has three main components: an 8-bit basic timer, an 8-bit timer/counter, and a watch timer. The 8-bit basic timer generates interrupt requests at precise intervals, based on the selected internal clock frequency. The programmable 8-bit timer/counter is used for counting events, modifying internal clock frequencies, and dividing external clock signals. The 8-bit timer/counter generates a clock signal (SCK) for the serial I/O interface. The watch timer consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. Its functions include real-time, watch-time measurement, and clock generation for frequency output for buzzer sound. SERIAL I/O INTERFACE The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The serial interface has the following functional components: -- 8-bit mode register -- Clock selector circuit -- 8-bit buffer register -- 3-bit serial clock counter The serial I/O circuit can be set to transmit-and-receive, or to receive-only mode. MSB-first or LSB-first transmission is also selectable. The serial interface can operate with an internal or an external clock source, or using the clock signal generated by the 8-bit timer/counter. Transmission frequency can be modified by setting the appropriate bits in the SIO mode register.
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S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
BIT SEQUENTIAL CARRIER The bit sequential carrier (BSC) is a 16-bit register that can be manipulated using 1-, 4-, and 8-bit instructions. Using 1-bit indirect addressing, addresses and bit locations can be specified sequentially. In this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the L register. BSC data can also be manipulated using direct addressing. COMPARATOR The S3C70F2/C70F4 contains a 4-channel comparator which can be multiplexed to normal input port. -- Conversion time: 15.2 s, 121.6 s at 4.19 MHz -- Two operation modes: Three channels for analog input and one channel for external reference voltage input Four channels for analog input and internal reference voltage level -- 16-level internal reference voltage generator -- 150 mV accuracy for input voltage level difference detection (maximum) -- Comparator enable and disable The comparison results are read from the 4-bit CMPREG register after the specified conversion time.
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PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
BLOCK DIAGRAM
Basic Timer
Watch Timer
RESET
8-Bit Timer/Counter
XIN
XOUT I/O Port 0 P0.0/CLO P0.1/TIO P0.2/INT1
Interrupt Control Block P3.0/TCL0 P3.1/TCLO0 P3.2/CLO I/O Port 3 Internal Interrupts P4.0 - P4.3 P5.0 - P5.3 I/O Port 4
Clock
Stack Pointer Serial I/O Port Program Counter Input Port 1
P0.0/SCK P0.1/SO P0.2/SI P2.0/KS0/CIN0 P2.1/KS1/CIN1 P2.2/KS2/CIN2 P2.3/KS3/CIN3
Instruction Decoder I/O Port 5 Arithmetic and Logic Unit I/O Port 6
Program Status Word
Input Port 2
P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3
Flags
Comparator
512 x 4-Bit Data Memory
Program Memory KS57C01502: 2 KByte KS57C01504: 4 KByte
Figure 1-1. S3C70F2/C70F4 Simplified Block Diagram
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S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
PIN ASSIGNMENTS
VSS Xout Xin TEST P1.0/INT0 P1.1/INT1 RESET P0.0/SCK P0.1./SO P0.2/SI P2.0/CIN0 P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S3C70F2 S3C70F4
(Top View)
30-SDIP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
VDD P6.3/BUZ P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 P3.2/CLO P3.1/TCLO0
VSS Xout Xin TEST P1.0/INT0 P1.1/INT1 RESET NC P0.0/SCK P0.1./SO P0.2/SI P2.0/CIN0 P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S3C70F2 S3C70F4
(Top View)
30-SDIP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD P6.3/BUZ P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 NC P3.2/CLO P3.1/TCLO0
Figure 1-2. S3C70F2/C70F4 Pin Assignment Diagram
1-9
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
PIN DESCRIPTIONS
Table 1-1. S3C70F2/C70F4 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P1.0 P1.1 P2.0-P2.3 P3.0 P3.1 P3.2 P4.0-P4.3 P5.0-P5.3 Pin Type I/O Description 3-bit I/O port. 1-bit or 3-bit read/write and test are possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. 2-bit input port. 1-bit or 2-bit read and test are possible. Pull-up resistors are assignable by software. 4-bit input port. 1-bit or 4-bit read and test are possible. Same as port 0 Number 8(9) 9(10) 10(11) 5(5) 6(6) 11-14 (12-15) 15(16) 16(17) 17(18) 18-21(20-23) 22-25(24-27) Share Pin SCK SO SI INT0 INT1 CIN0-CIN3 TCL0 TCLO0 CLO -
I I I/O
I/O
4-bit I/O ports. 1-, 4-, or 8-bit read/write and test are possible. Pins are individually configurable as input or output. 4-bit pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. The N-channel open-drain or push-pull output can be selected by software (1-bit unit) 4-bit I/O port. 1-bit or 4-bit read/write and test are possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. External interrupts with detection of rising and falling edges External interrupts with detection of rising or falling edges 4-channel comparator input. CIN0-CIN2: comparator input only. CIN3: comparator input or external reference input Serial interface clock signal Serial data output Serial data input External clock input for timer/counter Timer/counter clock output CPU clock output 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at 4.19 MHz for buzzer sound
P6.0 P6.1 P6.2 P6.3 INT0 INT1 CIN0-CIN3
I/O
26(28) 27(29) 28(30) 29(31) 5(5) 6(6) 11-14(12-15)
KS0 KS1 KS2 BUZ P1.0 P1.1 P2.0-P2.3
I I I
SCK SO SI TCL0 TCLO0 CLO BUZ
I/O I/O I/O I/O I/O I/O I/O
8(9) 9(10) 10(11) 15(16) 16(17) 17(18) 29(31)
P0.0 P0.1 P0.2 P3.0 P3.1 P3.2 P6.3
NOTE: Pn numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.
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S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
Table 1-1. S3C70F2/C70F4 Pin Descriptions (Continued) Pin Name Pin Type Description Quasi-interrupt input with falling edge detection VDD VSS RESET TEST Xin, Xout -- -- I I -- Main power supply Ground Reset signal Test signal input (must be connected to VSS) Crystal or ceramic oscillator signal for system clock Number 26-28(28-30) 30(32) 1(1) 7(7) 4(4) 3,2(3,2) Share Pin P6.0-P6.2 -- -- -- -- --
NOTE: Pin numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.
Table 1-2. Overview of S3C70F2/C70F4 Pin Data SDIP Pin Numbers 1 2,3 4 5,6 7 8-10 11-14 15-17 18-21 22-25 26-29 30 Pin Names VSS Xout, Xin TEST P1.0, P1.1 RESET P0.0 - P0.2 P2.0 - P2.3 P3.0 - P3.2 P4.0 - P4.3 P5.0 - P5.3 P6.0 - P6.3 VDD Share Pins INT0, INT1 SCK, SO, SI CIN0 - CIN3 TCL0, TCLO0, CLO KS0, KS1, KS2, BUZ I/O Type I I I I/O I I/O I/O I/O I/O Reset Value Input Input Input Input Input Input Input Circuit Type A-3 B D-1 F-1, F-2 (note) D-1 E E D-1
NOTE: I/O circuit type F-2 is implemented for P2.3 only.
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PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
PIN CIRCUIT DIAGRAMS
VDD
VDD
PULL-UP RESISTOR P-CHANNEL
IN N-CHANNEL
IN SCHMITT TRIGGER
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD
PULL-UP RESISTOR
VDD
P-CHANNEL DATA
RESISTOR ENABLE
P-CHANNEL
OUT N-CHANNEL
IN SCHMITT TRIGGER
OUTPUT DISABLE
Figure 1-4. Pin Circuit Type A-3
Figure 1-6. Pin Circuit Type C
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KS57C01502/C01504/P01504
PRODUCT OVERVIEW
VDD
PULL-UP RESISTOR RESISTOR ENABLE P-CHANNEL
DIGITAL INPUT
DATA OUTPUT DISABLE
CIRCUIT TYPE 4
I/O
ANALOG INPUT
SCHMITT TRIGER
Figure 1-7. Pin Circuit Type D-1
Figure 1-9. Pin Circuit Type F-1
VDD
PNE
VDD
PULL-UP RESISTOR
DIGITAL INPUT
DATA
P-CHANNEL I/O
PULL-UP RESISTOR ENABLE
ANALOG INPUT
OUTPUT DISABLE
N-CHANNEL
EXTERNAL V REF
Figure 1-8. Pin Circuit Type E
Figure 1-10. Pin Circuit Type F-2
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PRODUCT OVERVIEW
KS57C01502/C01504/P01504
NOTES
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S3C70F2/C70F4/P70F4
ELECTRICAL DATA
14
(TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High
ELECTRICAL DATA
Table 14-1. Absolute Maximum Ratings
Symbol VDD VI VO I OH I OL
Conditions - All I/O ports - One I/O port active All I/O ports active
Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 -5 - 15 5 30 + 100
Units V V V mA
Output Current Low
Ports 0, 3, and 6 Ports 4 and 5 All ports, total
mA
Operating Temperature Storage Temperature
TA Tstg
- -
- 40 to + 85 - 65 to + 150
C C
Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage VOH Conditions Ports 4 and 5 Ports 0, 1, 2, 3, 6, and RESET XIN and XOUT Ports 4 and 5 Ports 0, 1, 2, 3, 6, and RESET XIN and XOUT VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 0, 3, 4, 5, 6 VDD - 1.0 - Min 0.7VDD 0.8VDD VDD - 0.1 - Typ - - - - Max VDD VDD VDD 0.3VDD 0.2VDD 0.1 - V V Units V
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ELECTRICAL DATA
S3C70F2/C70F4/P70F4
Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output Low Voltage Symbol VOL Conditions VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4, 5 VDD = 4.5V to 5.5 V IOL = 4.0mA All output pins except Ports 4, 5 Input High Leakage Current ILIH1 VIN = VDD All input pins except XIN and XOUT VIN = VDD XIN and XOUT VIN = 0 V All input pins except XIN, XOUT and RESET ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH VIN = 0 V XIN and XOUT VO = VDD All output pins VO = 0 V - - - 20 3 A - - - - 3 A - 2 Min - Typ - Max 2 Units V
ILIH2 Input Low Leakage Current ILIL1
20 -3 A
ILOL
-
-
-3
A
RL1
VI = 0 V; VDD = 5 V Port 0, 1, 3, 4, 5, 6 VDD = 3 V VDD = 5 V; VI = 0 V; RESET VDD = 3 V
25 50 100 200
50 100 250 500
100 200 400 800
k
RL2
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S3C70F2/C70F4/P70F4
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 Conditions Run mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% IDD2 Idle mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% IDD3 Stop mode; VDD = 5.0 V 10% Stop mode; VDD = 3.0 V 10% 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz - - Min - Typ 3.0 2.0 1.3 1.0 0.8 0.6 0.6 0.4 0.5 0.3 Max 8.0 5.5 4.0 3.0 2.5 1.8 1.5 1.0 3.0 2.0 A mA Units mA
NOTES: 1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up resistor, 2. output port drive currents and comparator. The supply current assumes a CPU clock of fx/4.
Main Osc. Freq. ( Divided by 4 ) CPU CLOCK 1.5 MHz 6 MHz
1.05 MHz
4.2 MHz
15.625 kHz 1 2
2.7
400 kHz 3 4 5 6 7
SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. Standard Operating Voltage Range
14-3
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
Table 14-3. Oscillators Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
Xin Xout
Parameter Oscillation frequency (1)
Test Condition VDD = 2.7 V to 5.5 V
Min 0.4
Typ -
Max 6.0
Units MHz
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) Crystal Oscillator
Xin Xout
0.4 - 0.4
- - -
4.2 4 6.0 ms MHz
VDD = 3.0 V VDD = 2.7 V to 5.5 V
Oscillation frequency (1)
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) External Clock
Xin Xout
0.4 - 0.4
- - -
4.2 10 6.0 ms MHz
VDD = 3.0 V VDD = 2.7 V to 5.5 V
XIN input frequency (1)
VDD = 1.8 V to 5.5 V XIN input high and low level width (tXH, tXL) -
0.4 83.3
- -
4.2 1250 ns
NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
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S3C70F2/C70F4/P70F4
ELECTRICAL DATA
Table 14-4. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - Typ - Max 15 15 15 Units pF pF pF
Table 14-5. Comparator Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.0 V to 5.5V, VSS = 0 V) Parameter Input Voltage Range Reference Voltage Range Input Voltage Accuracy Input Leakage Current Symbol - VREF VCIN ICIN, IREF Condition - - - - Min 0 0 - -3 Typ - - - - Max VDD VDD 150 3 Units V V mV A
Table 14-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time TCL0 Input Frequency TCL0 Input High, Low Width SCK Cycle Time tKCY tTIH, tTIL f TI Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source 3800 670 3200 0.48 1.8 800 - - ns - Min 0.67 0.95 0 - 1.5 1 - MHz MHz s Typ - Max 64 Units s
14-5
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
Table 14-6. A.C. Electrical Characteristics ( Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter SCK High, Low Width Symbol tKH, tKL Conditions VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source SI Setup Time to SCK High tSIK VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source SI Hold Time to SCK High tKSI VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source Output Delay for SCK to SO tKSO (1) VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source Interrupt Input High, Low Width tINTH, tINTL tRSL INT0 INT1, KS0-KS2 RESET Input Low Width Input
(2)
Min 335 tKCY/2 - 50 1600 tKCY/2 - 150 100 150 150 500 400 400 600 500 -
Typ -
Max -
Units ns
-
-
ns
-
-
ns
-
300 250 1000 1000
ns
-
-
s
10 10 - - s
NOTES: 1. R (1 Kohm) and C (100 pF) are the load resistance and load capacitance of the SO output line. 2. Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting.
14-6
S3C70F2/C70F4/P70F4
ELECTRICAL DATA
Table 14-7. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.8 V - Released by RESET Released by interrupt Min 1.8 - 0 - - 2 Typ - 0.1 -
17
Max 5.5 10 - - -
Unit V A s ms ms
/ fx
(2)
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator startup. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
TIMING WAVEFORMS
INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE IDLE MODE OPERATING MODE
VDD
EXECUTION OF STOP INSTRUCTION RESET
VDDDR
tWAIT tSREL
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
14-7
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
IDLE MODE STOP MODE DATA RETENTION MODE NORMAL OPERATING MODE
VDD VDDDR
EXECUTION OF STOP INSTRUCTION
tSREL
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST)
Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request
0.8 VDD 0.2 VDD MEASUREMENT POINTS
0.8 VDD
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for XIN)
1 / fx
tXL
tXH
Xin
VDD - 0.2 V 0.2 V
Figure 14-5. Clock Timing Measurement at XIN
14-8
S3C70F2/C70F4/P70F4
ELECTRICAL DATA
1 / fTI
tTIL
TCL
tTIH 0.8 VDD 0.2 VDD
Figure 14-6. TCL Timing
tRSL
RESET 0.2 VDD
Figure 14-7. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1 KS0 to KS2
0.8 VDD 0.2 VDD
Figure 14-8. Input Timing for External Interrupts
14-9
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
tCKY tKL
SCK
tKH
0.8 VDD 0.2 VDD
tSIK
tKSI
0.8 VDD
SI
INPUT DATA 0.2 VDD
tKSO
SO OUTPUT DATA
Figure 14-9. Serial Data Transfer Timing
14-10
S3C70F2/C70F4/P70F4
MECHANICAL DATA
15
OVERVIEW
#30
MECHANICAL DATA
The S3C70F2/C70F4/P70F4microcontroller is available in a 30-pin SDIP package (Samsung part number 30SDIP-400) and a 32-SOP package (Samsung part number 30-SOP-450A).
#16
0-15
8.94 0.20
#1
#15
3.81 0.20
27.88 MAX 27.48 0.20
0.56 0.10 (1.30) 1.12 0.10 1.778
NOTE:
Dimensions are in millimeters.
Figure 15-1. 30-SDIP-400 Package Dimensions
3.30 0.30
0.51 MIN
5.21 MAX
0.2
5
+0 - 0 .10 .05
30-SDIP-400
10.16
15-1
MECHANICAL DATA
S3C70F2/C70F4/P70F4
0-8 #32 #17
12.00 0.30
8.34 0.20
32-SOP-450A
0.25
2.00 0.10
20.30 MAX 19.90 0.20
2.20 MAX
0.10 MAX
(0.43)
0.40 0.10
1.27
NOTE:
Dimensions are in millimeters.
Figure 15-2. 30-SOP-450A Package Dimensions
15-2
0.05 MIN
0.90 0.20
#1
#16
+ 0.10 - 0.05
11.43
S3C70F2/C70F4/P70F4
S3P70F4 OTP
16
OVERVIEW
S3P70F4 OTP
The S3P70F4 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C70F2/C70F4 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P70F4 is fully compatible with the S3C70F2/C70F4, both in function and in pin configuration. Because of its simple programming requirements, the S3P70F4 is ideal for use as an evaluation chip for the S3C70F2/C70F4.
VSS/VSS Xout Xin VPP/TEST P1.0/INT0 P1.1/INT1 RESET /RESET P0.0/SCK P0.1./SO P0.2/SI P2.0/CIN0 P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S3C70F4
(30-SDIP)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
VDD/VDD P6.3/BUZ/SCLK P6.2/KS2/SDAT P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 P3.2/CLO P3.1/TCLO0
NOTE:
The bolds indicate an OTP pin name.
Figure 16-1. S3P70F4 Pin Assignments (30-SDIP Package)
16-1
S3P70F4 OTP
S3C70F2/C70F4/P70F4
VSS/VSS Xout Xin VPP/TEST P1.0/INT0 P1.1/INT1 RESET /RESET NC P0.0/SCK P0.1./SO P0.2/SI P2.0/CIN0 P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S3P70F4
(32-SOP)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD/VDD P6.3/BUZ/SCLK P6.2/KS2/SDAT P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 NC P3.2/CLO P3.1/TCLO0
NOTE:
The bolds indicate an OTP pin name.
Figure 16-2. S3P70F4 Pin Assignments (32-SOP Package)
16-2
S3C70F2/C70F4/P70F4
S3P70F4 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P6.2 Pin Name SDAT Pin No. 28 (30) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming.
P6.3 TEST
SCLK VPP(TEST)
29 (31) 4 (4)
I/O I
RESET VDD / VSS
RESET VDD / VSS
7 (7) 30/1 (32/1)
I I
NOTE: ( ) means the 32-SOP OTP pin number.
Table 16-2. Comparison of S3P70F4 and S3C70F2/C70F4 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P70F4 4 K-byte EPROM 2.0 V to 5.5 V VDD = 5 V, VPP(TEST)=12.5V 30 SDIP, 32 SOP User Program one time 30 SDIP, 32 SOP Programmed at the factory S3C70F2/C70F4 2 K-byte mask ROM: S3C70F2 4 K-byte mask ROM: S3C70F4 1.8 V to 5.5V -
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P70F4, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V Vpp(TEST) 5V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 ADDRESS(A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 MODE EPROM read EPROM program EPROM verify EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-3
S3P70F4 OTP
S3C70F2/C70F4/P70F4
OTP ELECTRICAL DATA Table 16-4. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL All I/O ports - One I/O port active All I/O ports active Output Current Low Ports 0, 3, and 6 Ports 4 and 5 All ports, total Operating Temperature Storage Temperature TA Tstg - - Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 -5 - 15 5 30 + 100 - 40 to + 85 - 65 to + 150
C C
Units V V V mA
mA
Table 16-5. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage VOH Conditions Ports 4 and 5 Ports 0, 1, 2, 3, 6, and RESET XIN and XOUT Ports 4 and 5 Ports 0, 1, 2, 3, 6, and RESET XIN and XOUT VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 0, 3, 4, 5, 6 VDD - 1.0 - Min 0.7VDD 0.8VDD VDD - 0.1 - Typ - - - - Max VDD VDD VDD 0.3VDD 0.2VDD 0.1 - V V Units V
16-4
S3C70F2/C70F4/P70F4
S3P70F4 OTP
Table 16-5. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Output Low Voltage Symbol VOL Conditions VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4, 5 VDD = 4.5 V to 5.5 V IOL = 4.0mA All output pins except Ports 4, 5 Input High Leakage Current ILIH1 VIN = VDD All input pins except XIN and XOUT VIN = VDD XIN and XOUT VIN = 0 V All input pins except XIN, XOUT and RESET ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH VIN = 0 V XIN and XOUT VO = VDD All output pins VO = 0 V - - - 20 3 A - - - - 3 A - 2 Min - Typ - Max 2 Units V
ILIH2 Input Low Leakage Current ILIL1
20 -3 A
ILOL
-
-
-3
A
RL1
VI = 0 V; VDD = 5 V Port 0, 1, 3, 4, 5, 6 VDD = 3 V VDD = 5 V; VI = 0 V; RESET VDD = 3 V
25 50 100 200
50 100 250 500
100 200 400 800
k
RL2
16-5
S3P70F4 OTP
S3C70F2/C70F4/P70F4
Table 16-5. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Supply Current
(1)
Symbol IDD1
Conditions Run mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz
Min -
Typ 3.0 2.0 1.3 1.0
Max 8.0 5.5 4.0 3.0 2.5 1.8 1.5 1.0 3.0 2.0
Units mA
IDD2
Idle mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10%
-
0.8 0.6 0.6 0.4
mA
IDD3
Stop mode; VDD = 5.0 V 10% Stop mode; VDD = 3.0 V 10%
-
0.5 0.3
A
NOTES: 1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers, 2. output port drive currents and comparator. The supply current assumes a CPU clock of fx/4.
Main Osc. Freq. ( Divided by 4 ) CPU CLOCK 1.5 MHz 6 MHz
1.05 MHz
4.2 MHz
15.625 kHz 1 2
2.7
400 kHz 3 4 5 6 7
SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-3. Standard Operating Voltage Range
16-6
S3C70F2/C70F4/P70F4
S3P70F4 OTP
Table 16-6. Oscillators Characteristics (TA = - 40 C + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
Xin Xout
Parameter Oscillation frequency (1)
Test Condition VDD = 2.7 V to 5.5 V
Min 0.4
Typ -
Max 6.0
Units MHz
C1
C2
VDD = 2.0 V to 5.5 V Stabilization time (2) Crystal Oscillator
Xin Xout
0.4 - 0.4
- - -
4.2 4 6.0 ms MHz
VDD = 3.0 V VDD = 2.7 V to 5.5 V
Oscillation frequency (1)
C1
C2
VDD = 2.0 V to 5.5 V Stabilization time (2) External Clock
Xin Xout
0.4 - 0.4
- - -
4.2 10 6.0 ms MHz
VDD = 3.0 V VDD = 2.7 V to 5.5 V
Xin input frequency (1)
VDD = 2.0 V to 5.5 V XIN input high and low level width (tXH, tXL) -
0.4 83.3
- -
4.2 1250 ns
NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
16-7
S3P70F4 OTP
S3C70F2/C70F4/P70F4
Table 16-7. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - Typ - Max 15 15 15 Units pF pF pF
Table 16-8. Comparator Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.0 V to 5.5V, VSS = 0 V) Parameter Input Voltage Range Reference Voltage Range Input Voltage Accuracy Input Leakage Current Symbol - VREF VCIN ICIN, IREF Condition - - - - Min 0 0 - -3 Typ - - - - Max VDD VDD 150 3 Units V V mV A
Table 16-9. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Instruction Cycle Time Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V TCL0 Input Frequency f TI VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V TCL0 Input High, Low Width SCK Cycle Time tTIH, tTIL VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V tKCY VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source 3800 670 3200 0.48 1.8 800 - - ns - Min 0.67 0.95 0 - 1.5 1 - MHz MHz s Typ - Max 64 Units s
16-8
S3C70F2/C70F4/P70F4
S3P70F4 OTP
Table 16-9. A.C. Electrical Characteristics ( Concluded) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter SCK High, Low Width Symbol tKH, tKL Conditions VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source SI Setup Time to SCK High tSIK VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source SI Hold Time to SCK High tKSI VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source Output Delay for SCK to SO tKSO (1) VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source Interrupt Input High, Low Width tINTH, tINTL tRSL INT0 INT1, KS0-KS2 RESET Input Low Width Input
(2)
Min 335 tKCY/2 - 50 1600 tKCY/2 - 150 100 150 150 500 400 400 600 500 -
Typ -
Max -
Units ns
-
-
ns
-
-
ns
-
300 250 1000 1000
ns
-
-
s
10 10 - - s
NOTES: 1. R(1Kohm) and C (100pF) are the load resistance and load capacitance of the SO output line. 2. Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting.
16-9
S3P70F4 OTP
S3C70F2/C70F4/P70F4
Table 16-10. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 2.0 V - Released by RESET Released by interrupt Min 2.0 - 0 - - Typ - 0.1 - 217 / fx
(2)
Max 5.5 10 - - -
Unit V A s ms ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
16-10
S3C70F2/C70F4/P70F4
S3P70F4 OTP
START
Address= First Location
VDD =5V, V PP=12.5V
x=0
Program One 1ms Pulse
Increment X
YES
x = 10
NO FAIL
Verify Byte
Verify 1 Byte
FAIL
Last Address
NO
Increment Address
VDD = VPP= 5 V
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 16-4. OTP Programming Algorithm
16-11
S3P70F4 OTP
S3C70F2/C70F4/P70F4
NOTES
16-12

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