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| L8229 Dual DMOS full bridge stepper/DC motor driver Preliminary Data Features Flexible Motor Driver configurations: - Dual Full Bridge for one bipolar Stepping motor. - Dual or single DC motor driver. Programmable by two input pins to achieve one of the following functionalities: - Pin to pin compatible with ST L6219 or - Stepping motor direct control with 8 current levels or - Driver parameters control by means of Serial Port. Mixed Decay. Micro stepping function. BCD5 technology (No Charge Pump required). Supply Range from 8V to 38V. IOUT up to 1.2A (1.5A peak). RDSon= 0.85 (typ) for each switch. Input logic level compatible with 3.3V or 5V control signals. Package: PwSSO24. PwSSO24 Description This IC is designed to be very flexible in driving Stepping or DC motors. By connecting to Vcc or to Gnd two program pins (pin 7 and 18) the user has the possibility to set up the device in different configurations. 1. The first configuration is an identical application of ST L6219 but with increased current. In this configuration L8229 provides a continuous current of the output stage up to 1.2A (1.5A peak). 2. The second configuration allows a functionality similar to previous one but with the possibility of choosing 8 different current O bs let o Pr e du o (s) ct so Ob - levels to perform a more accurate stepping functionality. This is achieved by multiplexing the input pins dedicated to set the level of the current. Additionally the user can set the mixed mode decay for current recirculation. 3,4. The third and fourth configurations are intended to provide a very flexible programming for several parameters useful to drive different kind of Stepping and DC motors. This is achieved by means of a serial port interface that allows the user to configure the following parameters: a) Current levels (32 values for each bridge). b) Current direction. c) Type of decay for Stepping motors (Mix/Slow) or for DC motors (Fast/Slow). d) Vref input (Ext/Int). e) Vref divider (:5/:10). f) Blanking time (4 values). g) Oscillator freq divider (4 values). h) Off time (32 values). i) Fast decay time (16 values). j) Syncronous rectification. te le ro P uc d s) t( The functionalities of the two configurations are identical except that the internal bit address (first bit of SPI words) can be programmed to be 1 or 0: this enables two different L8229 to share a common serial bus. Order code Part number L8229 Package PwSSO24 Packing Tube September 2006 Rev 5 1/42 www.st.com 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents L8229 Contents 1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 3.2 3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.1 3.3.2 3.3.3 3.3.4 Output Drivers (OUTA or OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Control Logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 5 L6219_HI and L6219_8 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 L6219_HI and L6219_8 Electrical characteristics . . . . . . . . . . . . . . . . . 14 5.1 5.2 DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC/transient specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 L6219_HI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 6.2 6.3 6.4 Input Logic (I0 and I1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bs O 7 8 let o 6.6 7.1 7.2 6.5 Pr e Single-pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 du o (s) ct so Ob - te le ro P uc d s) t( Vs, Vcc, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 L6219_8 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 Level Current Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mixed Decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 L8229_0 and L8229_1 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 Serial interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/42 L8229 Contents 8.2 SPI Bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2.1 8.2.2 Word Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 W0 (OPERATIVE: Bit 2=0, Bit 1=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3 8.4 W1 (PARAMETERS: Bit 2=0, Bit 1=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 W2 (FUNCTIONAL: Bit 2=1, Bit 1=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.4.1 Reading back SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 SPI programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.1 9.2 9.3 9.4 Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Timings Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Decay Modes and Synchronous Rectification . . . . . . . . . . . . . . . . . . . . . 33 Mixed Decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1) ACTIVE SYNC recirculation could be divided in following cases. . . . . . . . . . . . 35 2) - PASSIVE SYNC recirculation could be divided in following cases:. . . . . . . . . 36 3) - SYNC OFF recirculation has only one case: . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4) LOW SIDE recirculation has only one case: . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.5 Slow Decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1) ACTIVE SYNC recirculation is not allowed.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2) PASSIVE SYNC recirculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3) SYNC OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4) LOW SIDE is identical to PASSIVE SYNC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 11 12 DC Motor Driver operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 3/42 List of tables L8229 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Programmable modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating ratings (0C Tj 125C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Drivers (OUTA or OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Control Logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC/transient specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input Logic (I0 and I1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Current levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AC/Transient Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC/Transient Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Word Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 W0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Motor mode selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Nsleep mode selected by W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Brake mode selected by W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Vref mode selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Range mode selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Current direction selected by W0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Current levels selected by W0 for DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Oscillator frequency selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Blanking time selected by W2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Fast decay time selected by W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Toff time selected by W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Stepping decay mode selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC decay mode selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Sync rectification selected by W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC Motor Drivers - DC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DC Motor Drivers - AC/Transient Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DC Motor Drivers Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 4/42 L8229 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ton and Toff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Half and Full Step Drive with Imax=1.2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Normal conduction and slow recirculation current paths. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 L6219_8 mode Stepping Driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 L6219_8 mode Fast and Slow Decay current paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Active and Passive synchronous rectification during Mixed Decay. . . . . . . . . . . . . . . . . . . 34 PowerSSO24 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 40 bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 5/42 Block diagram L8229 1 Figure 1. Block diagram Block Diagram Analog Toff VREFDEC RC1 VS VL VREF1 2 / 7.5 2V M U X VS VH DAC5 + COMPIN1 SQ R Pre Driver OUT1A OUT1B SENSE1 Digital Control Digital Prog Toff PROG1 PROG2 00 01 I01 I11 STB II2 PHA1 PHA2 10 PWM1 PWM2 STB II2 PHA1 PHA2 11 I01 I11 I02 I12 Serial Port I01 I11 I02 I12 PHA1 PHA2 PWM1 PWM2 SCLK SDI OSC nCS Osc Freq Select Stepper/DC Select Decay Ctrl Toff Select Tfastdec Select Synch Rect Select Test Mode DAC Select COMPIN1 VS Digital Prog Toff ADDR 4MHz 2V VREF2 2 / 7.5 M U X Pre Driver COMPIN2 R + + SQ VREFDEC RC2 Note: bs O let o The sensing resistors used for the stepping motor configurations must be not inductive. Pr e od 6/42 - DAC5 VL VH ct u VREFDEC (s) Ob - so 2V UV te le Int Osc ro P OUT2A OUT2B uc d s) t( SENSE2 Test Mux COMPIN2 GND 4MHz Bandgap Temp Mon UVLO GND VCC Tshut Analog Toff L8229 Pin description 2 Pin description Figure 2. Pin Connection (Top view) OUT1A OUT2A SENSE2 COMPIN2 OUT2B GND PROG1 IO2/STB/SCLK I12 /I12/SDI PHASE2 /PHASE2/nCS VREF2/VREFDEC/VREF2 RC2/RC2/FAULT 1 2 3 4 24 23 22 21 VS (Load Supply) SENSE1 COMPIN1 OUT1B I01/I01/PWM1 GND PROG2 I11/I11/PWM2 PHASE1/PHASE1 /OSC VREF1/VREFCOM/VREF1 RC1/RC1/nRESET VCC (Logic Supply) 5 6 7 8 20 19 18 17 9 10 11 12 16 15 14 13 Note: The pin functionality is different according to different configurations, so the relative pin function and name are different: the first name is relative to first configuration (L6219_HI), the second name is relative to second configuration (L6219_8), and the third name is relative to third and fourth configuration (L8229_0 and L8229_1). Pin Description L6219_HI L6219_8 Table 1. Pin N# (Pin7&18=00) (Pin7&18=01) OUT1A 1 2 3 4 5 bs O 6 7 8 9 let o Pr e OUT2A SENSE2 od GND ct u (Pin7&18=10 or 11) (s) L8229_x so Ob - te le ro P uc d s) t( Function Motor Driver Bridge 1 Output A. Motor Driver Bridge 2 Output A. Motor Driver Bridge 2 Sense Resistor. Current Comparator input for Bridge2. Motor Driver Bridge 2 Output B. Ground. Configuration Program pin. When used together with pin 18, it programs device into one of the four configurations (see following Programmable Modes table) COMPIN2 OUT2B PROG1 IO2 STB SCLK I02: Current level control bit for Bridge 2. STB: Strobe input pin for current setting. SCLK: Clock input pin for serial protocol. I12: Current level control bit for Bridge 2. SDI: Data input pin for serial protocol. I12 I12 SDI 7/42 Pin description Table 1. Pin N# L8229 Pin Description (continued) L6219_HI L6219_8 L8229_x (Pin7&18=10 or 11) nCS Function (Pin7&18=00) (Pin7&18=01) 10 PHASE2 PHASE2 PHASE2: Direction input control pin for Bridge 2. nCS: Chip Select input pin for serial protocol. VREF2: Reference voltage input for Bridge 2. VREFDEC: Mixed Decay Reference voltage for both Bridges 1 and 2. RC2: Toff input pin for Bridge 2. FAULT: This pin is high when a generic fault is present. Logic and Low voltage analog Supply. 11 VREF2 VREFDEC VREF2 12 13 14 RC2 RC2 VCC FAULT RC1 RC1 nRESET RC1: Toff input pin for Bridge 1. nRESET: Input pin for reset of serial port. VREF1: Reference voltage input for Bridge 1. VREFCOM: Common Reference voltage input for both Bridges 1 and 2. PHASE1: Direction input control pin for Bridge 1. OSC: Input for external oscillator used for timings. 15 VREF1 VREFCOM VREF1 16 PHASE1 PHASE1 OSC 17 I11 I11 PWM2 I11: Current level control bit for Bridge 1. PWM2: PWM input control pin for Bridge 2 when used as a DC motor driver. 18 19 20 21 22 23 24 I01 PROG2 GND I01 bs O Note: let o od Pr e VS OUT1B COMPIN1 SENSE1 ct u (s) PWM1 so Ob Ground. Configuration Program pin. When used together with pin 7, it programs device into one of the four configurations (see following Programmable Modes table). te le ro P uc d s) t( I01: Current level control bit for Bridge 1. PWM1: PWM input control pin for bridge 1 when used as a DC motor driver Motor Driver Bridge 1 Output B. Current Comparator input for Bridge1. Motor Driver Bridge 1 Sense Resistor. Supply voltage for output stages. ESD on pin PROG1 vs. VS is guaranteed up to +2KV/-1.75KV (Human Body Model, 1500Ohm, 100pF) 8/42 L8229 Table 2. Pin #7 PROG1 0 Pin description Programmable modes Pin # 18 PROG2 0 Description L6219 compatible (up to 1.2A Iout) L6219 like with 8 current levels (up to 1.2A Iout) and Mixed Decay. SPI operation, Chip Address = 0 Mode name Drive Configurations 1 x Stepping MotorDriver. 1 x Stepping MotorDriver. 1 x Stepping MotorDriver or 2 x DC Motor Driver. 1 x Stepping MotorDriver or 2 x DC Motor Driver. L6219_HI 0 1 L6219_8 1 0 L8229_0 1 1 SPI operation, Chip Address = 1 L8229_1 bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 9/42 Electrical Characteristics L8229 3 Electrical Characteristics Independently from the selected configurations, L8229 has some electrical characteristics that are common for all modes. These are listed below while specific characteristics are listed in their respective functionality descriptions. In all modes L8229 is powered by Vs supply voltage. The anti cross-conduction delay is controlled to provide sufficient time for cross-conduction suppression so that at no time both the upper and lower output devices (on the same side of the H bridge) are allowed to conduct simultaneously. During an over-temperature event, when the device Tj is above Tj(shutdown), the internal thermal protection circuit disables the drive outputs until the device temperature drops below the lower thermal threshold temperature. Note: The programming pins, PROG1 and PROG2, must be soldered to Vcc or to GND and must not be driven when supplies are on. 3.1 Absolute maximum ratings Table 3. Symbol Vs Vcc Ipeak Vref Vsense Vin Tj Tstg Absolute maximum ratings Parameter Supply voltage (including ripple). Logic and Low voltage analog supply voltage Motor Driver Output Peak Current (see Note Vref input voltage. Vsense output voltage. Logic input voltage. Junction Temperature. Storage Temperature. 1. This peak current is intended as start up current for max 1 second with D.C. 10% 3.2 Table 4. O bs Symbol Vs let o Operating ratings Operating ratings (0C Tj 125C) Parameter Test Condition Min. 8.5 3.135 L8229_0/1 configuration Sleep mode: NSLEEP (W1, bit3) = 0 Typ. 32 5 Max. 38 5.25 Unit V V Pr e du o (s) ct Ob - so te le (1)). ro P Value 40 7 1.5 7.5 2 uc d s) t( Unit V V A V V V C C -0.3 to +7 170 -25 to 150 Supply voltage (including ripple). Logic and Low voltage analog supply voltage. Vs Standby Current Vcc I_Vs 3 6 mA 10/42 L8229 Table 4. Symbol I_VccL6219 Electrical Characteristics Operating ratings (0C Tj 125C) (continued) Parameter Vcc total supply current (L6219_HI and L6219_8 modes) Test Condition Vcc=5.25V Vcc=5.25V Min. Typ. Max. 7 7 3 0 Vcc 1.2 Unit mA mA mA V A Vcc total supply current I_VccL8229_0/1 (L8229_0 or L8229_1 mode) Vin Iout Logic input voltage Motor Driver Output Current (continuous) Vcc=5.25V, NSLEEP (W1, bit3) = 0 3.3 General electrical characteristics (0C Tj 125C, VS = 32V, unless otherwise specified) 3.3.1 Table 5. Symbol RDSON Icex VF Output Drivers (OUTA or OUTB) Output Drivers (OUTA or OUTB) Parameter Output ON Resistance (Tj = 70 C) Output leakage current Body Diode Forward Voltage Test Condition Source Driver, ILOAD =-1.2A Sink Driver, ILOAD =+1.2A Vout = Vs or Gnd Min. Sink Diode, IF = 1.2A Source Diode, IF = 1.2A tr Output rising time bs O tf let o Pr e du o (s) ct Vs=12V, RL=12 connected to Vs or Gnd Vs=24V, RL=38 connected to Vs or Gnd Vs=36V, RL=58 connected to Vs or Gnd Vs=12V, RL=12 connected to Vs or Gnd Vs=24V, RL=38 connected to Vs or Gnd Vs=36V, RL=58 connected to Vs or Gnd 1 A 75 300 ns 100 350 ns Ob - so te le ro P Typ. uc d s) t( Unit A Max. 1.3 1.3 50 1 1 1.5 1.5 V V Output falling time Tdead Shoot through delay 11/42 Electrical Characteristics L8229 3.3.2 Table 6. Symbol VIN (H) VIN (L) IIN (H) IIN (L) Isdi Control Logic pins Control Logic pins Parameter Input Voltage Input Voltage Input Current Input Current SDI Input Current Test Condition All logic input for Vcc = 3.3V or 5V. All logic input for Vcc = 3.3V or 5V. VIN = 2.0V VIN = 0.8V -20 -20 -200 Min. 2 0.8 20 20 50 Typ. Max. Unit V V A A A 3.3.3 Table 7. Symbol Vref IVref Vcompin Icompin Vsense Isense Analog Input Pins Analog Input Pins Description Vref Input Voltage Vref Input Current Vcompin Input Voltage Vcompin Input Current Vsense Input Voltage Vsense Output Current Vref = 5.0V Condition Min. 1.5 Typ. 3.3.4 Table 8. Symbol Vsc_off Vs_UV Vs_UVhys Vcc_UV General General Parameter Sense comparator offset Vs undervoltage threshold Vs undervoltage hysteresis Vcc undervoltage threshold Vcc undervoltage hysteresis Thermal shutdown junction temperature Thermal enable junction temperature hysteresis Vcc_UVhys Tj(shutdown) O bs let o ro P e du (s) ct Ob - so te le ro P 1 50 uc d 7.5 200 20 100 Max. s) t( V V V Unit A 0.75 A 0.75 A Test Condition Min. Typ. 10 7.5 300 2.9 150 160 25 Max. Unit mV V mV V mV C C Tj(enable_ hysteresis) 12/42 L8229 L6219_HI and L6219_8 modes 4 L6219_HI and L6219_8 modes When configured in one of these modes the device has a functionality similar to ST L6219 with some improvements. The output stage is made by LDMOS devices instead of the BJT present in ST L6219. This allows a reduced saturation drop and an higher current handling with similar power dissipation. Additionally the recirculation diodes are internally available as a part of the LDMOS structure. In case of: a) b) Undervoltage detection (UVD) or Thermal shutdown (TSD), the outputs will be in Hi-Z mode (all outputs off) respectively until the supplies voltage goes over the UV threshold plus hysteresis or the themperature decreases below TSD threshold minus hysteresis. In case of: c) Overcurrent detection (OCD) the outputs will be in Hi-Z mode (all outputs off) and will remain in this condition until the device is reset by turning off and on VCC supply voltage. Common electrical characteristics of both L6219_HI and L6219_8 modes are listed below, while specific characteristics are listed in their respective functionality descriptions. bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 13/42 L6219_HI and L6219_8 Electrical characteristics L8229 5 L6219_HI and L6219_8 Electrical characteristics (0C Tj 125C, VS = 32 V, unless otherwise specified) 5.1 Table 9. Symbol DC specifications DC specifications Description Current Limit Threshold (at trip point ) for Vref = 5V and Tj 70C Condition I0 0.8V, I1 0.8V Min 9.25 13.5 25.5 Typ 10 15 30 Max 10.5 16.5 34.5 Unit Vref/Vsense I0 2.0V, I1 0.8V I0 0.8V, I1 2.0V 5.2 Table 10. Symbol Toff Tdelay Tblank AC/transient specifications AC/transient specifications Parameter Cut off time Turn Off Delay for comparator Blanking time for Sense comparator Test Condition Rt=56Kohm, Ct =820pF Min. Typ. 50 1 bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( Unit A A A Max. 1 14/42 L8229 L6219_HI mode 6 L6219_HI mode The device will be set into the L6219_HI mode by asserting PROG1 and PROG2 pins (pin 7 and 18) to 00. In the L6219_HI mode, the device is pin and function compatible with the ST L6219 device. Please note that while ST L6219 allows good power dissipation by simply connecting to gnd the center pins because of the batwing frame, the L8229 power dissipation will be good only by connecting the exposed pad to a proper heat sink. The circuit is intended to drive both windings of a bipolar stepping motor. The peak current control is made through switch mode regulation. There is a choice of three different current levels with the two logic inputs I01 and I11 for winding 1 and I02 and I12 for winding 2. The current can also be completely switched off. 6.1 Input Logic (I0 and I1) The current level in the motor winding is selected with these inputs (see Figure 1). If any of the logic inputs is left open, the circuit will treat it as a high level input. Table 11. I0X H L H L Input Logic (I0 and I1) I1X H H L L No Current Low Current: Medium Current: 1/3 Io max Current Level Maximum Current: Io max 6.2 Phase This input pin determines the direction of current flow in the windings, depending on the motor connections. The signal is fed through a Schmitt trigger for noise immunity, and through a time delay in order to guarantee that no cross conduction occurs in the output stage during phase-shift. High level on the PHASE input causes the motor current to flow from OutA through the motor winding to OutB. bs O 6.3 Current let Sensing o Pr e du o (s) ct so Ob 2/3 Io max te le ro P uc d s) t( This part contains a low pass filter for the external current sensing resistor (Rs) and three comparators. Only one comparator is active at a time: it is activated by the input logic according to the current level chosen with signals I0 and I1. The motor current flows through the sensing resistor Rs and when the current has increased so that the voltage across Rs becomes higher than the reference voltage on the other comparator input, the comparator output goes high, triggering the pulse generator. The max peak current Imax can be defined by: Imax = Vref / 10 Rs 15/42 L6219_HI mode L8229 Note that Iout max is 1.2A and the wide range allowed for Vref requires the choice of a suitable sense resistor to prevent current range over the maximum. 6.4 Single-pulse Generator The pulse generator is a monostable circuit triggered on the positive going edge of the comparator output. The circuit output is high during the pulse time Toff that is determined by the time components Rt and Ct. Toff =~ 1.1 x RtCt (including switching dead time) The single pulse turns off the power switch connected to the motor winding, causing the winding current to decrease during Toff. If a new trigger signal should occur during Toff it will be ignored. 6.5 Output Stage Each of the two outputs stage contains four LDMOS transistors (P and N channel) connected in two H Bridges. The intrinsic body diode of the LDMOS serve as recirculation diode for flyback current. The LDMOS are used to switch the power supply to the motor winding, thus driving a constant current through the winding. It should be noted however, that is not permitted to short-circuit the outputs. Internal circuitry is added in order to increase the accuracy of the motor current particularly with low current levels. 6.6 Vs, Vcc, Vref The circuit will stand any order of turn-on or turn-off of the supply voltages Vs and Vcc. Normal dV/dt values are then assumed. Preferably, Vref should be tracking Vcc during power-on and power-off if Vs is established. Figure 3. Ton and Toff bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( Normalized output current 1.0 0.5 0 VSense Vref Tdelay Ton Toff VRC 16/42 L8229 Figure 4. Half and Full Step Drive with Imax=1.2A Hold 1 I01 I11 PHASE 1 I02 I12 PHASE 2 1.2A 0.8A 0A -0.8A -1.2A 1.2A 0.8A 0A -0.8A -1.2A Motor Current Phase 2 A to B Motor Current Phase 1 A to B 2 3 Half Step Drive 45 6 7 L6219_HI mode Full Step Drive 8 Figure 5. Normal conduction and slow recirculation current paths. RC Vcc O bs let o Pr e du o (s) ct OUTA1 OUTB1 HA Ton so Ob Toff T1 T2 te le Ton ro P uc d s) t( T3 Slow Decay L6219_HI Mode VS HB Ton Current Toff Current LA LB Slow Decay 17/42 L6219_8 mode L8229 7 L6219_8 mode A second configuration of the device is achieved when PROG1 and PROG2 pins (pin 7 and 18) are asserted to 01. The device is now configured into the L6219_8 configuration. This device mode function is similar to L6219_HI, but with the possibility of using 8 current levels instead of 4, to implement a more accurate microstepping function and with the possibility to set a mixed decay for recirculation current. The remaining functionalities are identical to L6219_HI mode. 7.1 8 Level Current Setting This setting is achieved by using pin 8 (STB) as a strobe for latching the current setting control inputs. The rising edge of STB will latch the I01, I11 and I12 inputs for decoding current levels settings for Bridge 1. Similarly the falling edge will latch the I01, I11 and I12 inputs for decoding current levels settings for Bridge 2. In order to allow a good similitude to sine drive, the levels set by the input pins are not equally spaced but are choosen to approximate a sinusoidal wave. On power up, the device is by default into a no current drive state for both H Bridges and will start driving only upon the rising or falling edges of STB. 7.2 Mixed Decay VREFCOM input (pin 15) is the reference voltage for both bridges while VREFDEC input (pin 11) is a voltage reference for decay control. When the current setting is set from an higher level to a lower level, the device can be set to perform: 1. 2. 3. Slow decay (current is recirculated throught the low side drivers) when VREFDEC > 0.94Vcc. A mix of Fast followed by Slow decay when 0.33Vcc < VREFDEC < 0.94Vcc. Fast decay (current is recirculated from Sense to Vs) when VREFDEC < 0.33Vcc. In case 2, VREFDEC voltage is compared with the RC discharging voltage during the Toff duration. Until the RC voltage is above VREFDEC there will be fast decay: the bridge outputs will be driven to enable recirculation from Rsense to VS. For RC voltages below VREFDEC, the bridges will be driven to recirculate through the low side drivers. (see Figure 8) bs O let o Table 12. STB Pr e du o I01 0 0 0 0 1 1 (s) ct I11 so Ob - te le ro P uc d s) t( Current levels I12 Current level Bridge1 0 0 1 1 0 0 0 1 0 1 0 1 No current IOUT / Imax=0.22 IOUT / Imax=0.42 IOUT / Imax=0.61 IOUT / Imax=0.77 IOUT / Imax=0.87 Bridge 2 - 18/42 L8229 Table 12. STB L6219_8 mode Current levels (continued) I01 1 1 0 0 0 0 1 1 1 1 I11 1 1 0 0 1 1 0 0 1 1 I12 0 1 0 1 0 1 0 1 0 1 Current level IOUT / Imax=0.93 IOUT / Imax=1 IOUT / Imax=1 IOUT / Imax=0.93 IOUT / Imax=0.87 IOUT / Imax=0.77 IOUT / Imax=0.61 IOUT / Imax=0.42 IOUT / Imax=0.22 No current Table 13. Symbol MD_h MD_l AC/Transient Specification Description Mixed decay trip point high Mixed decay trip point low Min Typ 0.93Vcc 75mV 0.33Vcc 50mV Table 14. Name Fstb Thstb Tlstb Trd_stb Tfd_stb Trd_Ixx Timing specifications (0C Tj 125C, VS = 32 V, unless otherwise specified) Description Strobe frequency Strobe high width Strobe low width STB rise time bs O let o Pr e Tfd_Ixx Tsu_Ixx Thd_Ixx du o STB fall time I01,I11,I12 rise time (s) ct so Ob - te le 20 20 0 0 0 0 15 15 ro P TYP uc d MAX 6 s) t( Max Units MHz ns ns MIN 10 10 10 10 ns ns ns ns ns ns I01,I11,I12 fall time I01,I11,I12 setup time I01,I11,I12 hold time 19/42 L6219_8 mode Figure 6. L6219_8 mode Stepping Driving L8229 Bridge2 Bridge1 PHASE2 PHASE1 I12 I11 I01 STB Figure 7. L6219_8 mode Fast and Slow Decay current paths Toff RC Vcc 0.94Vcc VREFDEC 0.33Vcc OUTA bs O let o ro P e L6219_8 Mode OUTB uc d (s) t T1 T2 T3 Fast Decay so Ob T4 T5 Slow Decay te le ro P uc d s) t( SLOW DECAY Toff= 1.1RC inclusive of Tdeadtime T1 and T3 MIXED DECAY T1, T3 and T5 are dead times to ensure no cross conduction FAST DECAY VS HB Ton Current Toff Fast Decay Current Toff Slow Decay Current HA LA LB 20/42 L8229 L8229_0 and L8229_1 modes 8 L8229_0 and L8229_1 modes When in these modes, the device can be programmed via a serial interface. This allows a very precise microstepping functionality as well as the control of several parameters related to the motor functionality. In this configuration there is also the possibilty of driving two DC motors by means of two pulse width modulated (PWM) control signals. The parameters that can be set are the following: 1. 2. 3. 4. 5. 6. 7. 8. 9. Current levels (32 values for each bridge). Current direction. Type of decay for stepping motor (Mix/Slow). Vref input (Ext/Int) Vref divider (:5/:10). Blanking time (4 values). Oscillator freq divider (4 values). Off time (32 values). Fast decay time (16 values). 10. Synchronous rectification (Active/Passive/LowSide/Off). 11. Choose of driving a Stepping or DC motor. 12. Possibility of paralleling bridges (in DC motor drive). 13. Slow or fast decay (in DC motor drive). 14. Possibility of setting outputs in brake mode. 15. Possibility of asserting Sleep mode to reduce current consumption and put outputs in HI-Z. When in L8229 modes, pin 12 (FAULT) is used to provide a "Generic Fault" signal that is intended as a warning for the user. In case of: a) Undervoltage detection (UVD): no action is taken on output bridges and the device will be working, leaving to the user the action of stopping the output bridges functionality. During UVD event, the Generic Fault signal is pulled high. Thermal shutdown (TSD): output bridges will be in Hi-Z mode (all outputs off) until the temperature decreases below TSD threshold minus hysteresis. During TSD event, the Generic Fault signal is pulled high. bs O let o Pr e b) c) du o (s) ct so Ob - te le ro P uc d s) t( Over current detection (OCD): output bridges will be in Hi-Z mode. Depending on the motor (Stepping or DC according to W2 bit 14), the OCD status will be latched as follows: - for stepping motor driving the OCD status will be latched until SPI is reset by means of nRESET pin. - for DC motor driving the OCD status will be latched until next positive PWM edge occurs. For both above cases, the Generic Fault signal is pulled high until the OCD status persists. 21/42 L8229_0 and L8229_1 modes Table 15. Name Vref voltage Ioff-rev L8229 DC Specifications (0C Tj 125C, VS = 32 V, unless otherwise specified) Description Internal reference voltage Reverse current detection offset (in Active Sync recirculation) Conditions Min 1.94 Typ 2 50 Max 2.06 Units V mA Table 16. Name Osc AC/Transient Specifications (0C Tj 125C, VS = 32 V, unless otherwise specified) Description Oscillator frequency Conditions Min Typ 4 Max Units MHz 8.1 Serial interface specification This device, when in L8229_0 or L8229_1 configuration, is managed via a Serial Interface Port for a total of 16 bits with 4 different words. This port provides an interface between the chip and external digital ASIC. For the user this port is write-only: assigned read registers are for test mode purposes only. The interface consists of 3 signal lines: chip select (nCS, active low), serial clock (SCLK) and serial data input (SDI). The digital ASIC initiates a serial transfer by pulling low the chip select line, nCS. Then it generates 16 clock pulses on SCLK while presenting the serial data on input SDI. The data is shifted into the L8229 on the rising edge of SCLK. The digital ASIC presents the data on SDI one setup time (Tdsu) before the rising edge of SCLK. The data is held constant for the data hold time (Tdhd) beyond the SCLK rising edge. The less significant bit, or LSB, is the first to be shifted out of the digital ASIC and into the chip, followed by the remaining bits. The last of the 16 bits is the most significant bit or MSB. SDI will remain at the value presented with the last bit of data. The nCS line is then returned to a high state. The low to high transition of nCS loads the data into the internal L8229 input register where all the inputs are presented to their appropriate functions in a parallel mode. In the event that there are less or more than 16 SCLK rising edges during nCS=0, the device will interprete the packet as invalid. This enables the SPI bus to be shared with others devices with similar packet skipping functionality (and with programming word length different from 16 bits), without the use of nCS. bs O let o The outputs of the serial input port shall not "glitch" during any operation. The serial interface is cleared by nRESET signal applied to pin 14. When nRESET=0, output stages are in Hi-Z mode (all outputs off). Please note that neither TSD nor OCD reset the SPI. Pr e du o (s) ct so Ob - te le ro P uc d s) t( 22/42 L8229 Figure 8. SPI Operations Data latched on rising edge of SCLK L8229_0 and L8229_1 modes nCS TCS-SCLK TSCLK-CS SCLK TDSU Bit0 Bit1 Bit2 TDHD Bit3 Bit4 Bit5 Bit6 Bit7 Bit14 Bit15 SDI LSB MSB Table 17. Name Fclk Tclh Tcll Tcs-sclk Tsclk-cs Tdsu Tdhd Tcs-cs Trd Tfd Trfc SPI Timing specifications (0C Tj 125C, VS = 32 V, unless otherwise specified) Description Serial clock frequency SCLK high width SCLK low width Delay nCS falling to first SCLK rising Delay last SCLK rising edge to nCS rising Data valid to SCLK set up time Data hold time Delay required from (n-1)CS to nCS SDI rise time SDI fall time SCLK rise/fall time 30 30 10 MIN TYP 8 MAX bs O let o Pr e du o ct (s) Ob - so te le 10 10 10 10 0 0 0 ro P uc d 12 s) t( ns ns ns ns ns ns ns Units MHz 20 20 20 ns ns ns 23/42 L8229_0 and L8229_1 modes L8229 8.2 8.2.1 SPI Bit definition Word Description Each of the 3 words used to program the chip when in L8229_0 or L8229_1 mode has the 3 LSB used to address the word as follows: Table 18. BIT # Word Description NAME Value DESCRIPTION This value addresses the word to chip #0 (if two L8229 are present on the same board and a single nCS line is used). Chip address is assigned by configuring the PROG bit according to Table 2. This value addresses the word to chip #1 (if two L8229 are present on the same board and a single nCS line is used). Chip address is assigned by configuring the PROG bit according to Table 2. Bit 1 0 1 0 1 W0: OPERATIVE register W1: PARAMETERS register W2 : FUNCTIONAL register Not allowed 0 0 CHIP ADDRESS 1 Bit 2 0 1 and 2 WORD ADDRESS 1, WORD ADDRESS 2 0 1 1 8.2.2 W0 (OPERATIVE: Bit 2=0, Bit 1=0) This word is mainly used to fix the current level and direction in the bridge. Table 19. BIT # W0 NAME RESET VALUE 0 1 2 CHIP ADDRESS WORD ADDRESS 1 O bs 4 5 6 7 8 9 3 let o PHASE 1 WORD ADDRESS 2 DAC1 BIT 1 (LSB) DAC1 BIT 2 DAC1 BIT 3 DAC1 BIT 4 DAC1 BIT 5 (MSB) ro P e du 0 0 0 0 0 0 0 0 0 0 (s) ct so Ob - te le ro P uc d s) t( DESCRIPTION This bit is used to select if the informations provided by bits 1 to 15 are referred to chip 0 or chip 1. This is useful in the case that two L8229 are present on the same board and a single nCS line is used. This is the LSB of the two bits used to address the word This is the MSB of the two bits used to address the word LSB for DAC intended to regulate the current of Bridge 1 BIT2 for DAC intended to regulate the current of Bridge 1 BIT3 for DAC intended to regulate the current of Bridge 1 BIT4 for DAC intended to regulate the current of Bridge 1 MSB for DAC intended to regulate the current of Bridge 1 Controls the direction of current flow for Bridge1. A logic 0 level causes current flow from A (source) to B (sink). LSB for DAC intended to regulate the current of Bridge 2 DAC2 BIT1 (LSB) 24/42 L8229 Table 19. BIT # 10 11 12 13 14 15 L8229_0 and L8229_1 modes W0 (continued) NAME DAC2 BIT 2 DAC2 BIT 3 DAC2 BIT 4 DAC2 BIT 5 (MSB) PHASE 2 PARALLEL OUTPUT RESET VALUE 0 0 0 0 0 0 DESCRIPTION BIT2 for DAC intended to regulate the current of Bridge 2 BIT3 for DAC intended to regulate the current of Bridge 2 BIT4 for DAC intended to regulate the current of Bridge 2 MSB for DAC intended to regulate the current of Bridge 2 Controls the direction of current flow Bridge 2. A logic HIGH level causes current flow from A (source) to B (sink). This bit must be set to 1 when otputs are paralled to drive a single DC motor 8.3 Table 20. BIT # W1 (PARAMETERS: Bit 2=0, Bit 1=1) This word is mainly used to set motor related parameters. W1 NAME RESET VALUE 0 0 0 0 0 0 DESCRIPTION 0 1 2 3 4 5 6 7 8 9 10 CHIP ADDRESS WORD ADDRESS 1 WORD ADDRESS 2 NSLEEP OFF1 OFF2 OFF3 OFF4 OFF5 This bit is used to select if the informations provided by bits 1 to 15 are referred to chip 0 or chip 1. This is useful in the case that two L8229 are present on the same board and a single nCS line is used. This is the LSB of the two bits used to address the word. This is the MSB of the two bits used to address the word. This bit is used to decide if the device should exit sleep mode. bs O 12 13 14 15 11 let o Brake FASTDEC1 FASTDEC2 Pr e du o 0 0 0 0 0 0 0 0 0 0 (s) ct LSB for fixing the Toff time (see following Table 32). BIT 2 for fixing the Toff time (see following Table 32). BIT 3 for fixing the Toff time (see following Table 32). BIT 4 for fixing the Toff time (see following Table 32). so Ob - te le ro P uc d s) t( MSB for fixing the Toff time (see following Table 32). LSB for fixing the Fast Decay time (see followingTable 31). BIT 2 for fixing the Fast Decay time (see following Table 31). BIT 3 for fixing the Fast Decay time (see following Table 31). MSB for fixing the Fast Decay time (see following Table 31). LSB to decide the rectification mode (see following Table 35). MSB to decide the rectification mode (see following Table 35). This bit is used to put outputs in brake mode FASTDEC3 FASTDEC4 SYNCRECT1 SYNCRECT2 25/42 L8229_0 and L8229_1 modes L8229 8.4 Table 21. BIT # W2 (FUNCTIONAL: Bit 2=1, Bit 1=0) This word is mainly used to set the functional mode W2 NAME RESET VALUE 0 0 0 0 0 0 0 0 0 0 0 0 DESCRIPTION This bit is used to select if the informations provided by bits 1 to 15 are referred to chip 0 or chip 1. This is useful in the case that two L8229 are present on the same board and a single nCS line is used. This is the LSB of the two bits used to address the word. This is the MSB of the two bits used to address the word. This bit is to decide if Slow or Mixed Decay is applied to Bridge 1 (Stepping motor). This bit is to decide if Slow or Mixed Decay is applied to Bridge 2 (Stepping motor). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CHIP ADDRESS WORD ADDRESS 1 WORD ADDRESS 2 MIX/SLOW 1 (St. mot) MIX/SLOW 2 (St. mot) REFERENCE INT/EXT RANGE BLANK LSB BLANK MSB OSC LSB OSC MSB TEST 1 TEST 2 TEST 3 STEP/DC This bit is used to decide if the reference voltage will be internal (0) or external (1) This bit is to decide if the reference voltage will be divided by 10 (0) or by 5 (1). This is the LSB bit used to fix the Blanking time (see following Table 30). This is the MSB bit used to fix the Blanking time (see following Table 30). This is the LSB bit used to fix the Oscillator values (see following Table 29). bs O let o SLOW/FAST (DC mot) Pr e du o 0 0 0 0 (s) ct This is the MSB bit used to fix the Oscillator values (see following Table 29). This bit is used for trim mode. This bit is used for trim mode. This bit is used for trim mode. so Ob - te le ro P uc d s) t( This bit is used to set the drive of a Stepping Motor (0) or a DC Motor (1). This bit is used to decide if Slow (0) or Fast (1) decay is applied to DC Motor configuration 26/42 L8229 L8229_0 and L8229_1 modes 8.4.1 Reading back SPI. When W2 bit 11 to 13 are to 111, read back from SPI is enabled. This function is to check the actual data in W0 and W1; W2 can't be read back. To read back the following procedure is requested: 1. 2. 3. 4. Set PROG1=1, PROG2=0 Write W0 and W1 to SDI Write W2 (with bits 11, 12, 13 set to 111) to SDI. This enables read back mode from SPI. Write 0001 1111 1111 1111 to SDI (the first three bits mean that W0 is requested to be read out, the other bits have no sense just to fill the blank bits). This allows to check if the SDI output is W0 bit3~15. Write W2 (with bits 11, 12, 13 set to 111) to SDI. This enables read back mode from SPI. Write 0101 1111 1111 1111 to SDI (the first three bits mean that W1 is requested to be read out, the other bits have no sense just to fill the blank bits). This allows to check if the SDI output is W1 bit3~15. 5. 6. If the data to be read out are the same as the data write in, it means write function of SPI is right. bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 27/42 SPI programming L8229 9 SPI programming On power up, the device is by default in sleep mode. Before coming out from sleep, the device needs to be programmed to drive either Stepping or DC motor. This is controlled by W2 bit 14. Default is stepping motor drive. Table 22. Motor mode selected by W2 Bit 14 0 1 Mode Stepping motor DC motor The device can be awoken from the sleep mode by means of the bit 3 of W1. Table 23. Nsleep mode selected by W1 Bit 3 0 1 Mode Sleep Normal The device can be set in brake mode ( both outputs are LL) by means of W1 bit 15. Please note that Brake mode overcomes Nsleep mode. Table 24. Brake mode selected by W1 Bit 15 0 1 9.1 Current Control Current level in the motor is set by means of a combination of Vref (ext or int), Rsense and DAC control bits. The max current is set as follows: Imax = Vref / (Range x Rsense) bs O let o Vref can be set to be internal at 2V or externally applied to VREF1 and VREF2 pins. On power up, the default is the internal 2V. Table 25. Vref mode selected by W2 Bit 5 0 1 Mode Internal ref. 2V External ref. (7.5V max) Pr e du o (s) ct Ob - so te le ro P uc d s) t( Mode Normal Brake Vref voltage is divided according to Range value that is defined by W2 bit 6 to be either 10 or 5. 28/42 L8229 Table 26. Range mode selected by W2 Bit 6 0 1 Mode Range = 10 Range = 5 SPI programming The direction of current is determined by W0 bits 8 and 14. During Ton, outputs will be according to following table: Table 27. Current direction selected by W0 Bit 8 (14) 0 1 OUT A L H OUT B H L The 5 bit DACs for each Bridge enable an accurate resolution control defined by Current levels table below. The current level Iset is then defined as: Iset = Vdac / (Range x Rsense) where: Vdac = (DAC/31) x Vref where DAC is defined from 0 to 31, so the current level is fixed by W0 bits 7 (MSB) to 3 (LSB) (13 to 9) as in following table. Table 28. Bit 7 (13) 0 0 0 0 0 0 Current levels selected by W0 for DAC Bit 6 (12) 0 0 Bit 5 (11) bs O let o Pr e 0 0 0 0 0 0 0 0 0 0 1 du o (s) ct 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Ob 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 so Bit 4 (10) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 te le ro P 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 uc d s) t( Bit 3 (9) IPH_A (B)/Imax 0 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 16/31 29/42 SPI programming Table 28. Bit 7 (13) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 L8229 Current levels selected by W0 for DAC (continued) Bit 6 (12) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 5 (11) 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 4 (10) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 3 (9) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 IPH_A (B)/Imax 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 9.2 Timings Control All timings are controlled by a master oscillator that can be internal or externally provided. At power up, OSC will default to the internal 4MHz oscillator. Setting W2 bits 9 and 10 will select the external oscillator frequency or it's dividing by either 2 or 4. Table 29. Oscillator frequency selected by W2 Bit 10 0 Bit 9 0 1 0 1 bs O let o ro P e 0 1 1 du (s) ct so Ob - te le Pr 1 od uc s) t( 27/31 28/31 29/31 30/31 31/31 Freq Internal (4MHz) Ext Ext/2 Ext/4 The switching blanking time for masking transient can be selected by W2 bits 7 and 8. Table 30. Blanking time selected by W2 Bit 8 0 0 1 1 Bit 7 0 1 0 1 Time 2/fosc 4/fosc 8/fosc 12/fosc 30/42 L8229 Fast decay timing is set by W1 bits 9 (LSB) to 12 (MSB). Tfast = (N+1) x 8/Fosc SPI programming Where N = 0 to 15 and Fosc is either the internal 4 MHz or the external oscillator frequency with selected division. Setting Toff to be smaller than Tfast will result in fast decay only. Table 31. Bit 12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Fast decay time selected by W1 Bit 11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit10 0 0 1 1 0 0 1 1 0 0 1 1 0 Bit9 0 1 0 1 0 1 0 1 0 1 Fast decay 1x8/fosc 2x8/fosc 3x8/fosc 4x8/fosc 5x8/fosc 6x8/fosc The Toff timing is controlled by bits 4 (LSB) to 8 (MSB) of W1 and is based on the oscillator frequency. O bs let o Where N = 0 to 31 and Fosc is either the internal 4 MHz or the external oscillator frequency with selected division. Table 32. Bit 8 0 0 0 0 0 0 Pr e od ct u (s) Ob 0 1 1 so te le 0 1 0 1 0 1 ro P uc d 7x8/fosc 8x8/fosc 9x8/fosc s) t( 10x8/fosc 11x8/fosc 12x8/fosc 13x8/fosc 14x8/fosc 15x8/fosc 16x8/fosc Toff = (N+1) x 8/Fosc Toff time selected by W1 Bit 7 0 0 0 0 0 0 Bit 6 0 0 0 0 1 1 Bit 5 0 0 1 1 0 0 Bit 4 0 1 0 1 0 1 Toff 1x8/fosc 2x8/fosc 3x8/fosc 4x8/fosc 5x8/fosc 6x8/fosc 31/42 SPI programming Table 32. Bit 8 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 L8229 Toff time selected by W1 (continued) Bit 7 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 5 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Toff 7x8/fosc 8x8/fosc 9x8/fosc 10x8/fosc 11x8/fosc 12x8/fosc 13x8/fosc 14x8/fosc 15x8/fosc 16x8/fosc 17x8/fosc 18x8/fosc bs O let o Pr e 1 1 du o 1 1 1 1 (s) ct Ob 0 0 0 0 1 1 1 1 so 1 0 0 1 1 0 0 1 1 te le Pr 0 1 0 1 0 1 0 1 0 1 0 1 od uc 19x8/fosc 20x8/fosc 21x8/fosc 22x8/fosc 23x8/fosc 24x8/fosc 25x8/fosc 26x8/fosc 27x8/fosc 28x8/fosc 29x8/fosc 30x8/fosc 31x8/fosc 32x8/fosc s) t( 32/42 L8229 SPI programming 9.3 Decay Modes and Synchronous Rectification For stepping motor drive, the recirculation mode during Toff could be slow, fast or mixed (that is fast followed by slow decay): W2, by means of bit 3 (for Out1) and bit 4 (for Out2), allows to select MIXED or SLOW decay for bridge 1 and bridge 2 respectively; by selecting (with W1, bits 9 to 12) Tfast longer than Toff, it is possible to select FAST decay for all the Toff duration. Table 33. Stepping decay mode selected by W2 Bit 3 (4) 0 1 Mode Mixed decay Slow decay For DC motor drive, W2 bit 15 allows to choose slow or fast decay. Table 34. DC decay mode selected by W2 Bit 15 0 1 Mode Slow Fast During the decay, it is possible for the current to flow through the intrinsic body diodes of the LDMOS or through switched on LDMOS channel (in this case the current conduction will be reversed from Source to Drain). This switching on of the active device in parallel with the diode is called SYNCHRONOUS rectification and means that the recirculation path is not obtained only through the internal diodes but also by turning on the DMOS in parallel with the diode needed to recirculate current; because of the low RDSon of this LDMOS the dissipation is reduced. For stepping motors only with W1, by means of bits 13 and 14, it is possible to choose several kinds of SYNCHRONOUS recirculation modes: ACTIVE recirculation, PASSIVE recirculation, SYNC OFF recirculation, and LOW SIDE recirculation. Table 35. Sync rectification selected by W1 Bit 14 bs O let o Pr e du o 0 0 1 1 (s) ct so Ob Bit 13 0 1 0 1 te le ro P uc d s) t( Mode Active(1) Passive Off Low side 1. Only for Mixed Decay mode. ACTIVE means that the current is monitored to avoid reverse current in the load: this could happen because of FAST SYNC recirculation (that reverse the conduction of the bridge). When a reverse current is detected, synchronous rectification is turned off, so the outputs are placed in Hi-Z state until the end of Toff. Please note that Active Synchronous rectification can't be used when in Slow Decay mode. PASSIVE means that the current is not monitored to avoid a reverse current in the load. In this case the current, during Toff, could be inverted and no action is taken until the current reaches the current limit selected by the user by means of Vref and Rsense. When this 33/42 SPI programming L8229 value is reached, synchronous rectification is turned off, so the outputs are placed in Hi-Z state until the end of Toff. Please note that a typical 50mA reverse current could be present during Active Sync rectification. SYNC OFF means that the current will recirculate through the body diodes in parallel with power DMOS. This is intended to allow the user to use external Schottky diodes to save the internal dissipation. LOW SIDE means that the synchronous recirculation is forced only through the low side power DMOS. Please note that while the current reversal is always sensed, if required, the current level is sensed only by means of Rsense, so no current control is performed when current flows away from Rsense, as in SLOW recirculation. Active and passive synchronous rectification modes are illustrated in the following drawing: Figure 9. Active and Passive synchronous rectification during Mixed Decay. VS HA I1 HB ADgtS I2 + LA LB + BDgtS Ilimit + VDAC Active Sync during Fast decay Drive Recirculat. Hi-Z I1 I2 ADgtS O bs let o Pr e du o LA HB I1 I2 (s) ct ON ON Ob - so I1 I2 ADgtS LA LB te le ro P uc d s) t( Active Sync during Slow decay Recirculation Drive Hi-Z ON ON Passive Sync during Fast decay Drive Recir lation Recirculation Hi-Z Passive Sync during Slow decay Dri Drive R Recirculation Hi-Z I1 I2 ADgtS LA HB Ilimit ON ON ADgtS LA ON LB ON Remains ON till end of Toff or Ilimit reached Remains ON till end of Toff 34/42 L8229 SPI programming The output states during these cases of recirculation could be summarized as below: (only OUTA to OUTB current flowing is described) 9.4 Mixed Decay 1) ACTIVE SYNC recirculation could be divided in following cases. 1a) No reverse current detected during Toff HA on HB off LA off LB on Current increasing in the load. Anticross state (fast recirculation through LA and HB body diodes). LB off LB off LB on LB on LB on FAST SYNC recirculation through DMOS till end of fast decay time. Anticross state (fast recirculation through LA DMOS and HB body diode). SLOW SYNC recirculation till end of Toff. All off HA off HA off HA off HA off HA on HB on HB off HB off HB off HB off LA on LA on LA on LA off LA off Anticross state (slow recirculation through LA body diode and LB DMOS). Current increasing in the load. 1b) Reverse current detected during Fast Recirculation of Toff HA on HB off LA off LB on Current increasing in the load. Anticross state (fast recirculation through LA and HB body diodes). All off HA off HB on LA on All off HA on HB off 1c) Reverse current detected during Slow Recirculation of Toff bs O let o HA on ro P e HB off HB on HB off HB off du LA off (s) ct LB off LB on LB on FAST SYNC recirculation through DMOS till reverse current is detected. Hi-Z state till end of Toff. Current increasing in the load. so Ob - te le ro P uc d s) t( LA off Current increasing in the load. Anticross state (fast recirculation through LA and HB body diodes). All off LA on LA on LA on LB off LB off LB on HA off HA off HA off FAST SYNC recirculation through DMOS decay time. till end of fast Anticross state (fast recirculation through LA DMOS and HB body diode). SLOW SYNC recirculation till reverse current is detected. Hi-Z state till end of Toff. All off HA on HB off LA off LB on Current increasing in the load. 35/42 SPI programming L8229 2) - PASSIVE SYNC recirculation could be divided in following cases: 2a) The reverse current (if present) does not exceed the regulated value (Note: this case is identical to ACTIVE SYNC case 1a) HA on HB off LA off LB on Current increasing in the load. Anticross state (fast recirculation through LA and HB body diodes). LB off LB off LB on LB on LB on FAST SYNC recirculation through DMOS till end of fast decay time. Anticross state (fast recirculation through LA DMOS and HB body diode). SLOW SYNC recirculation till end of Toff. Anticross state (slow recirculation through LA body diode and LB DMOS). Current increasing in the load. All off HA off HA off HA off HA off HA on HB on HB off HB off HB off HB off LA on LA on LA on LA off LA off 2b) The reverse current exceeds the regulated value during FAST recirculation. (Note: if the current exceed the regulated value during SLOW recirculation, no action is taken and the behaviour will be that of case 2a) HA on HB off LA off LB on Current increasing in the load. All off HA off HB on LA on LB off Anticross state (fast recirculation through LA and HB body diodes). FAST SYNC recirculation through DMOS till reverse current reaches the regulated value). Hi-Z state till end of Toff. Current increasing in the load. All off HA on HB off LA off 3) - SYNC OFF recirculation has only one case: HA on bs O let o Pr e HB off du o All off (s) ct LB on LB on LB on LB on so Ob - te le ro P uc d s) t( LA off Current increasing in the load. Fast recirculation through LA and HB body diodes till end of fast decay time. Slow recirculation through LA body diode and LB DMOS till end of Toff. Current increasing in the load. HA off HA on HB off HB off LA off LA off 36/42 L8229 SPI programming 4) LOW SIDE recirculation has only one case: HA on HB off LA off LB on Current increasing in the load. Fast recirculation through LA and HB body diodes) till end of fast decay time. LB on LB on LB on SLOW SYNC recirculation till end of Toff. Anticross state (slow recirculation through the LA body diode and LB DMOS). Current increasing in the load. All off HA off HA off HA on HB off HB off HB off LA on LA off LA off 9.5 Slow Decay When in Slow Decay, Active Synchronous rectification can't be used since current is not expected to be reversed because of BEMF. Therefore only Passive, Off or Low side recirculation cases can be selected. 1) ACTIVE SYNC recirculation is not allowed. 2) PASSIVE SYNC recirculation HA on HA off HA off HA off HA on HB off HB off HB off HB off HB off LA off LA off LA on LA off LA off LB on LB on LB on LB on LB on Current increasing in the load. Anticross state (slow recirculation through LA body diode and LB DMOS). SLOW SYNC recirculation till end of Toff. Anticross state (slow recirculation through the LA body diode and LB DMOS). Current increasing in the load. 3) SYNC OFF HA on bs O 4) LOW SIDE is identical to PASSIVE SYNC. let o HA off HA on od Pr e HB off HB off HB off LA off LA off ct u (s) so Ob - te le ro P uc d s) t( LB on Current increasing in the load. Slow recirculation (through the LA body diode and LB DMOS) till end of Toff Current increasing in the load. LB on LB on LA off 37/42 DC Motor Driver operation L8229 10 DC Motor Driver operation When in L8229_0 or L8229_1 configuration, the device could be configured to drive two different DC motors. Each drive provides bi-directional drive to a DC motor via the serial control and the PWM pins. The W0 bits 8 and 14 in the register will control the direction of drive while the PWM input pin controls the switching of the drivers. According to above description, the motor drive will be in voltage mode only. The device could also drive a single DC motor with increased current by paralleling the two bridges. If this is required, W0 bit 15 must be set to 1 and OUT1A must be shorted to OUT2A while OUT1B must be shorted to OUT2B. In this case of two bridges paralled to drive a single DC motor, the W0 bit 14 (PHASE2) will not be used as well as pin 17 (PWM2). This means that the device will act as a single bridge with ouputs OUTA (OUT1A in parallel with OUT2A), OUTB (OUT1B in parallel with OUT2B) and driven by PHASE1 (W0 bit 8) and PWM1 (pin 20). The drives are powered by VS. The crossover delay is controlled to provide sufficient time for cross-conduction suppression, so that at no time both the upper and lower output devices on the same side of the H bridge are allowed to conduct simultaneously. A blanking period following a current turn-on event is included to prevent false current protection turnoffs due to the initial current spike resulting from circuit capacitance. When OCD happens, outputs are placed in Hi_Z untill next PWM positive edge occurs. During an over-temperature event, when the device junction temperature Tj is above Tj(shutdown), the internal thermal protection circuit disables the drive outputs by driving all outputs to the high impedance state until the device temperatures have dropped below the lower thermal threshold temperature. Table 36. Name DC Motor Drivers - DC Specifications (0C Tj 125C, VS = 32 V, unless otherwise specified) Description (1) IDCMOTOR OCT DC Motor Over Current Threshold 1. The current limitation is applied to the bottom H bridge LDMOS only, therefore over current protection applies to motor current, but no short circuit protection exists against shorts from the DC motor outputs to ground or to VS. Table 37. Name bs O 0 0 fPWM Tblank let o OCD 0 0 DC Motor Drivers - AC/Transient Specifications (0C Tj 125C, VS = 32 V, unless otherwise specified) Description Conditions Min 10 1 Typ Max 30 Units KHz s Pr e du o (s) ct so Ob - te le ro P uc d s) t( Conditions Min 1.5 Typ Max Units A PWM frequency Blanking time (for OCD) Table 38. Therm. prot. DC Motor Drivers Truth Table W2 bit 15 (SLOW /FAST) 0 0 W0 bit 8 or 14 (PHASE) 0 0 Pin 20 OUT A or 17 high side (PWM) 0 1 Off Off OUT Al ow side On On OUT B high side Off On OUT B low side On Off Out State L-L L-H 38/42 L8229 Table 38. Therm. prot. 0 0 0 0 0 0 x 1 DC Motor Driver operation DC Motor Drivers Truth Table (continued) OCD 0 0 0 0 0 0 1 x W2 bit 15 (SLOW /FAST) 0 0 1 1 1 1 X X W0 bit 8 or 14 (PHASE) 1 1 0 0 1 1 X X Pin 20 OUT A or 17 high side (PWM) 0 1 0 1 0 1 X X Off On On Off Off On Off Off OUT Al ow side On Off Off On On Off Off Off OUT B high side Off Off Off On On Off Off Off OUT B low side On On On Off Off On Off Off Out State L-L H-L H-L L-H L-H H-L Hi. Z Hi. Z bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 39/42 Package Information L8229 11 Package Information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 10. PowerSSO24 Mechanical Data & Package Dimensions DIM. A A2 a1 b c D (1) E (1) e e3 G G1 H h L N X Y 4.10 6.50 0.55 10.10 mm MIN. 2.15 2.15 0 0.33 0.23 10.10 7.4 0.8 8.8 0.10 0.06 10.50 0.40 0.85 0.022 0.398 TYP. MAX. 2.47 2.40 0.075 0.51 0.32 10.50 7.6 MIN. 0.084 0.084 0 0.013 0.009 0.398 0.291 0.031 0.346 0.004 0.002 0.413 0.016 0.033 inch TYP. MAX. 0.097 0.094 0.003 0.020 0.012 0.413 0.299 OUTLINE AND MECHANICAL DATA 10 (max) 4.70 7.10 0.161 0.256 (1) "D and E1" do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006") (2) No intrusion allowed inwards the leads. (3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side bs O let o Pr e du o (s) ct so Ob 0.185 0.279 te le ro P uc d s) t( PowerSSO -24 (Exposed Pad) 7412818 A 40/42 L8229 Revision history 12 Revision history Table 39. Date 17-Feb-2005 10-Aug-2005 20-Feb- 2006 30-May-2006 12-Sep- 2006 Document revision history Revision 1 2 3 4 5 Initial release. Many modify of texts and table. Corrected some errors/imprecisions in the whole document. Cancelled the L8229S part number, and all information about HSOP24 package. Added note at the table 2. Applied new graphic design template. Modified the tables 2, 5, 6, 7, 8. 10, 13, 14, 15, 16, 17, 23 and 24. Changes bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 41/42 L8229 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. bs O The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 42/42 |
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