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HM66WP18513/HM66WP36257
9M Flow Through Zero Bus Latency (ZBL) SRAM (HM66WP18513) 512-Kword x 18-bit (HM66WP36257) 256-Kword x 36-bit
ADE-203-1285C (Z) Preliminary Rev. 0.3 Mar. 29, 2002 Description
The HM66WP18513 is a synchronous fast static RAM organized as 512-Kword x 18-bit. The HM66WP36257 is a synchronous fast static RAM organized as 256-Kword x 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 100pin LQFP and 119-pin BGA. Note : All power supply(VDD,VDDQ) and ground(VSS) pins must be connected for proper operation of the device. TM TM ZBL : Zero Bus Latency and compatible ZBT SRAM. ZBT is trademark of Integrated Device Technology, Inc.,
Features
* 3.3 V or 2.5V power supply, 3.3 V or 2.5 V I/O supply voltage * Clock frequency: 133/117/100 MHz * Fast clock access time: 6.5/7.5/8.5 ns (max) * Low operating current: 200/180/160 mA (max) * Address data pipeline capability * Internal input registers (Address, Data, Control) * Internal self-timed write cycle * ADV/LD burst control pins * Asynchronous output enable controlled three-state outputs * Individual byte write control * Power down state via ZZ * Common data inputs and data outputs * High board density 100-pin LQFP package and 119-pin BGA package * Burst control selected pin LBO (Interleave or linear burst oder)
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications.
HM66WP18513, HM66WP36257
Ordering Information
Type No. HM66WP18513FP-65 HM66WP18513FP-75 HM66WP18513FP-85 HM66WP36257FP-65 HM66WP36257FP-75 HM66WP36257FP-85 HM66WP18513BP-65 HM66WP18513BP-75 HM66WP18513BP-85 HM66WP36257BP-65 HM66WP36257BP-75 HM66WP36257BP-85 Access Time 6.5 ns 7.5 ns 8.5 ns 6.5 ns 7.5 ns 8.5 ns 6.5 ns 7.5 ns 8.5 ns 6.5 ns 7.5 ns 8.5 ns CPU Clock Rate 133 MHz 117 MHz 100 MHz 133 MHz 117 MHz 100 MHz 133 MHz 117 MHz 100 MHz 133 MHz 117 MHz 100 MHz BGA 119-pin (BP-119A) Package LQFP 100-pin (FP-100H)
Rev.0.3, Mar. 2002, page 2 of 31
HM66WP18513, HM66WP36257
Pin Arrangement (HM66WP36257) 100PIN-LQFP
100-pin LQFP
ADV/ NC A17 A8 A9 VDD VSS CLK CE2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A6 A7
DQc0 DQc1 DQc2 V DDQ V SSQ DQc3 DQc4 DQc5 DQc6 V SSQ V DDQ DQc7 DQc8 V SS (1) V DD
V DD V SS
DQd8 DQd7 V DDQ V SSQ DQd6 DQd5 DQd4 DQd3 V SSQ V DDQ DQd2 DQd1 DQd0
Note : Pins 14 and 66 are not VSS Supply ,but have to be connected VSS or < VIL.
A5 A4 A3 A2 A1 A0 NC NC V SS V DD NC NC A10 A11 A12 A13 A14 A15 A16
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQb0 DQb1 DQb2 V DDQ V SSQ DQb3 DQb4 DQb5 DQb6 V SSQ V DDQ DQb7 DQb8 V SS V SS (1) V DD ZZ DQa8 DQa7 V DDQ V SSQ DQa6 DQa5 DQa4 DQa3 V SSQ V DDQ DQa2 DQa1 DQa0
(Top view)
Rev.0.3, Mar. 2002, page 3 of 31
HM66WP18513, HM66WP36257
Pin Arrangement (HM66WP18513) 100PIN-LQFP
100-pin LQFP
ADV/ NC A18 A8 A9 VDD VSS CLK CE2 NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A6 A7
NC NC NC
VDDQ VSSQ NC NC DQb8 DQb7 VSSQ VDDQ DQb6 DQb5 VSS (1) VDD VDD VSS DQb4 DQb3 VDDQ VSSQ
DQb2 DQb1 DQb0 NC V
SSQ
VDDQ
NC NC NC
Note : Pins 14 and 66 are not VSS Supply ,but have to be connected VSS or < VIL.
Rev.0.3, Mar. 2002, page 4 of 31
A5 A4 A3 A2 A1 A0 NC NC V SS V DD NC NC A11 A12 A13 A14 A15 A16 A17
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A10 NC NC V DDQ V SSQ NC DQa8 DQa7 DQa6 V SSQ V DDQ DQa5 DQa4 V SS V SS (1) V DD ZZ DQa3 DQa2 V DDQ V SSQ DQa1 DQa0 NC NC V SSQ V DDQ NC NC NC
(Top view)
HM66WP18513, HM66WP36257
Pin Arrangement (HM66WP36257) 119PIN-BGA
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc1 DQc3 VDDQ DQc6 DQc8 VDDQ DQd8 DQd6 VDDQ DQd3 DQd1 NC NC VDDQ 2 A6 CE2 A7 DQc0 DQc2 DQc4 DQc5 DQc7 VDD DQd7 DQd5 DQd4 DQd2 DQd0 A5 NC TMS 3 A4 A3 A2 VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS LBO A10 TDI 4 NC
ADV/LD
5 A8 A9 A12 VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC A14 TDO
6 A16 CE3 A15 DQb0 DQb2 DQb4 DQb5 DQb7 VDD DQa7 DQa5 DQa4 DQa2 DQa0 A13 NC NC
7 VDDQ NC NC DQb1 DQb3 VDDQ DQb6 DQb8 VDDQ DQa8 DQa6 VDDQ DQa3 DQa1 NC ZZ VDDQ
VDD NC CE1 OE A17 WE VDD CLK NC CEN A1 A0 VDD A11 TCK
(Top view)
Pin Arrangement (HM66WP18513) 119PIN-BGA
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQb8 NC VDDQ NC DQb5 VDDQ NC DQb3 VDDQ DQb1 NC NC NC VDDQ 2 A6 CE2 A7 NC DQb7 NC DQb6 NC VDD DQb4 NC DQb2 NC DQb0 A5 A10 TMS 3 A4 A3 A2 VSS VSS VSS BWb VSS NC VSS VSS(1) VSS VSS VSS LBO A15 TDI 4 NC
ADV/LD
5 A8 A9 A13 VSS VSS VSS VSS(1) VSS NC VSS BWa VSS VSS VSS NC A14 TDO
6 A16 CE3 A17 DQa8 NC DQa6 NC DQa4 VDD NC DQa2 NC DQa1 NC A12 A11 NC
7 VDDQ NC NC NC DQa7 VDDQ DQa5 NC VDDQ DQa3 NC VDDQ NC DQa0 NC ZZ VDDQ
VDD NC CE1 OE A18 WE VDD CLK NC CEN A1 A0 VDD NC TCK
(Top view) Note: Pin 3L and 5G are not VSS Supply, but have to be connected VSS or have to be NC.
Rev.0.3, Mar. 2002, page 5 of 31
HM66WP18513, HM66WP36257
Pin Description (See Detailed Pin Description)
Name A0, A1 and A2-17 (HM66WP36257) A0 ,A1 and A2-18 (HM66WP18513) BWm I/O type Input Input Input Description 18 address inputs 19 address inputs Byte write enables BWa controls DQa0 to DQa8 BWb controls DQb0 to DQb8 BWc controls DQc0 to DQc8 BWd controls DQd0 to DQd8 Write enable Clock Chip enable Output enable Address load control Clock enable control Power down Burst mode control No connection Data input/output m = a, b, c, d (HM66WP36257) m = a, b (HM66WP18513) VDD VDDQ VSS Supply Supply Supply Power supply I/O power supply Ground m = a, b, c, d (HM66WP36257) m = a, b (HM66WP18513) Notes
WE CLK CE1, CE3, CE2 OE ADV/LD CEN ZZ LBO NC DQmn n=0-8
Input Input Input Input Input Input Input Input -- Input/ Output
Rev.0.3, Mar. 2002, page 6 of 31
HM66WP18513, HM66WP36257
Detailed Pin Description
Pin number(s) LQFP 35, 34, 33, 32, 44, 45, 46, 47, 48, 49, 50, 81, 82, 83, 99, 100 37, 36 80 93, 94, 95, 96 BGA 2A, 2C, 2R, 3A, 3B, 3C, 3T, 4G, 5A, 5B, 5C, 5T, 6A, 6C, 6R 4P, 4N 2T, 6T 4T 5L, 5G, 3G, 3L A (x 36-bit x 18-bit common) A0,A1 A (x 18-bit) A (x 36-bit) BWa, BWb BWc, BWd (x 36-bit) Input Synchronous byte write enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. BWa controls DQa0 to DQa8. BWb controls DQb0 to DQb8. BWc controls DQc0 to DQc8. BWd controls DQd0 to DQd8. Data I/O are tri-stated if any of these four inputs are LOW. Input Synchronous address inputs: These inputs are registered and must meet setup and hold times around the rising edge of CLK . Burst address inputs Symbol Type Description
93, 94 87 88
5L, 3G 4M 4H
BWa, BWb (x 18-bit) CEN WE Input Synchronous clock enable: This active LOW internal clock signal is active. Input Synchronous write enable: This active LOW input permits write operations and must meet the setup and hold times around the rising edge of CLK. Input Clock: This signal latches the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Input Synchronous chip enables: This active LOW input is used to enable the device. This input is sampled only when a external address is loaded. This input can be used for memory depth expansion. Input Input Synchronous chip enable: This active HIGH input is used to enable the device. This input sampled only when a new external address is load. This input can be used for memory depth expansion. Input Output enable: This active LOW asynchronous input enables the data I/O output drivers. Input Synchronous address advance or load control: This active HIGH input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A LOW input is caused a new external address to be latched.
89
4K
CLK
98
4E
CE1
92 97
6B 2B
CE3 CE2
86 85
4F 4B
OE ADV/LD
Rev.0.3, Mar. 2002, page 7 of 31
HM66WP18513, HM66WP36257
Detailed Pin Description (cont)
Pin number(s) LQFP 38, 39, 42, 43, 84 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96 51, 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 80, 1, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29, 30 BGA 1B, 1C, 1R, 1T, 3J, 4A, 4D, 4L,5J,5R,6T,6U,7B,7C,7R 1B, 1C, 1E, 1G, 1K, 1P, 1R, 1T,2D,2F,2H,2L,2N,4A,4L, 4T,5J,5R,6E,6G,6K,6M,6P, 6U,7B,7C,7D,7H,7L,7N,7R 6K, 6L, 6M, 6N, 6P, 7K, 7L, 7N, 7P, 6D, 6E, 6F, 6G, 6H, 7D, 7E, 7G, 7H, 1D, 1E, 1G, 1H, 2D, 2E 2F, 2G, 2H, 1K, 1L, 1N 1P,2K , 2L, 2M, 2N, 2P NC -- (x 36-bit) NC -- (x 18-bit) No Connect: These signals are internally not connected. No Connect: These signals are internally not connected. Symbol Type Description
DQmn Input/ m = a, b, Output c, d n=0-8 (x 36-bit)
SRAM data I/O: Byte a is DQa0 to DQa8; Byte b is DQb0 to DQb8; Byte c is DQc0 to DQc8; Byte d is DQd0 to DQd8. Input data must meet setup and hold times around the rising edge of CLK. SRAM data I/O: Byte a is DQa0 to DQa8; Byte b is DQb0 to DQb8. Input data must meet setup and hold times around the rising edge of CLK. Power supply: 3.3 V (+5%/-5%) or 2.5 V (+5%/-5%) I/O power supply: 3.3 V (+5%/-5%) or 2.5 V (+5%/-5%) Ground: GND
58, 59, 62, 63, 68, 69, 6D, 6F, 6H, 6L, 6N, 7E, 72, 73, 74, 8, 9, 12, 13, 7G, 7K, 7P, 1D, 1H, 1L, 18, 19, 22, 23, 24 1N, 1E, 1G, 1K, 1M, 1P
DQmn Input/ m = a, b Output n=0-8 (x 18-bit) VDD VDDQ Supply Supply
15, 16, 41, 65, 91 4, 11, 20, 27, 54 61, 70, 77 14, 17, 40, 66, 67, 90, 5, 10, 21, 26, 55, 60, 71, 76
2J, 4C, 4J, 4R, 6J, 1A, 1F, 1J, 1M, 1U, 7A, 7F, 7J, 7M, 7U 3D,3E,3F,3H,3K,3M,3N,3P, 5D,5E,5F,5H,5K,5M,5N,5P 3L, 5G
VSS
Supply
Supply VSS (x 18-bit) ZZ Input
Ground: GND Asynchronous power-down (Snooze): This active HIGH input enables SRAM to enter a power-down (Snooze) state with data retention. During Snooze state, data retention is guaranteed. At this time, internal state of the SRAM is not preserved. After Snooze state, SRAM must be initiated with CEN or ADV/LD using a new external address. This pin must be connected to VSS in systems that do not use ZZ feature. Burst order (Interleave burst or linear burst) select pin (DC) This pin must connect VDD or VDDQ or VSS.
64
7T
31
3R
LBO
Input
Rev.0.3, Mar. 2002, page 8 of 31
HM66WP18513, HM66WP36257
Block Diagram (HM66WP36257)
18 2nd address registers 18
CLK
CLR
Binary counter
A0
A0'
A1
A1'
A0 to A17 ADV/
18
1st address registers Write enable register 1 st byte a write register 1 st byte b write register 1 st byte c write register 1 st byte d write register Enable register
18
16
18
MUX
2 nd byte a write register 2 nd byte b write register 2 nd byte c write register 2 nd byte d write register
Byte a write driver
9
Byte b write driver
9
256k x 9 x 4 Memory array
Byte c write driver
9
Byte d write driver
9
CE2
36
36
Input registers
36
Note: The functional block diagram illustrates simplified device operation. See truth table, detailed pin descriptions and timing diagrams for detailed information.
DQa0 to DQa8 DQb0 to DQb8 DQc0 to DQc8 DQd0 to DQd8
Rev.0.3, Mar. 2002, page 9 of 31
HM66WP18513, HM66WP36257
Block Diagram (HM66WP18513)
19 2nd address registers 19
CLK
CLR
Binary counter
A0
A0'
A1
A1'
A0 to A18
19
1 st Address registers
19
17
19
ADV/ Write enable register
MUX
1 st byte a write register 1 st byte b write register Enable register
2 nd byte a write register 2 nd byte b write register
Byte a write driver
9 512k x 9 x 2 Memory array 9
Byte b write driver
CE2
18 18
Input registers
18
Note: The functional block diagram illustrates simplified device operation. See truth table, detailed pin descriptions and timing diagrams for detailed information.
DQa0 to DQa8 DQb0 to DQb8
Rev.0.3, Mar. 2002, page 10 of 31
HM66WP18513, HM66WP36257
Synchronous Truth Table
Operation Deselected cycle, power-down Deselected cycle, power-down Deselected cycle, power-down WRITE cycle, begin burst NOP/WRITE Abort, begin burst READ cycle, begin burst Dummy READ cycle, begin burst WRITE cycle, continue burst WRITE Abort, continue burst READ cycle, continue burst Address CE1 CE3 CE2 None None None H x x x H x L L L L x x x x x x x x x L H H H H x x x x x x x ADV /LD CEN WE BWm OE CLK DQ LD L L L L L L L H H H H x x x L L L L L L L L L L L H H H x x x L L H H x x x x x x x x x x L H x x L H x x x x x x x x x x L H x x L H x L H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H High-Z High-Z High-Z D High-Z Q High-Z D High-Z Q High-Z Q High-Z
External L External L External L External L Next Next Next x x x x x x x
Dummy READ cycle, continue burst Next WRITE cycle, suspend READ cycle, suspend Dummy READ cycle, suspend Current Current Current
Notes: 1. H means logic HIGH, L means logic LOW. x means H or L. WE = L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) are LOW. Write = H means all byte write enable signals are HIGH. 2. BWa enables write to Bytea (DQa0 to DQa8). BWb enables write to Byteb (DQb0 to DQb8). BWc enables write to Byte2 (DQc0 to DQc8). BWd enables write to Byted (DQd0 to DQd8). 3. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 4. A WRITE is performed by setting one or more byte write enable signals and WE LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 5. The status for DQ described in this synchronous truth table appears one clock after the cycle in which the Read or Write command is asserted. 6. If ADV/LD is sampled High that it is continue burst cycle follows before the operation cycle. 7. Wait states are inserted by CEN = High. When CEN is sampled High after Read cycle, the Read data is maintain as output data. When CEN is sampled High after Write cycle, the Write Input Data is ignored and is maintained High-Z. Refer to Timing diagram for clarification.
Rev.0.3, Mar. 2002, page 11 of 31
HM66WP18513, HM66WP36257
Asynchronous Truth Table
Operation Read Read Write Deselect Power down (Snooze) ZZ L L L L H OE L H x x x I/O status Data out High-Z High-Z, Data in High-Z High-Z
Note: H means logic HIGH. L means logic LOW. x means H or L.
Partial Truth Table for Writes
Operation Read No write Write byte a Write all bytes WE H L L L BWa x H L L BWb x H H L BWc x H H L BWd x H H L
Note: H means logic HIGH. L means logic LOW. x means H or L.
Rev.0.3, Mar. 2002, page 12 of 31
HM66WP18513, HM66WP36257
Interleave Sequence Table (LBO = VDD or VDDQ)
Parameter External address 1st internal address 2nd internal address 3rd internal address Sequence 1 (A1, A0) 00 01 10 11 Sequence 2 (A1, A0) 01 00 11 10 Sequence 3 (A1, A0) 10 11 00 01 Sequence 4 (A1, A0) 11 10 01 00
Note: Each sequence wraps around to its initial state upon completion.
Linear Sequence Table (LBO = VSS)
Parameter External address 1st internal address 2nd internal address 3rd internal address Sequence 1 (A1, A0) 00 01 10 11 Sequence 2 (A1, A0) 01 10 11 00 Sequence 3 (A1, A0) 10 11 00 01 Sequence 4 (A1, A0) 11 00 01 10
Note: Each sequence wraps around to its initial state upon completion.
Absolute Maximum Ratings
Parameter Supply voltage Voltage on any pins relative to VSS Except VDD Power dissipation Operating temperature Storage temperature range (with bias) Storage temperature range (DQ) (Others) Symbol VDD VT VT PT Topr Tstg (bias) Tstg Value -0.5 to +4.6 -0.5 to VDDQ + 0.5 -0.5 to VDD + 0.5 1.6 0 to +70 -10 to +85 -55 to +125 Unit V V V W C C C
Rev.0.3, Mar. 2002, page 13 of 31
HM66WP18513, HM66WP36257
Recommended DC Operating Conditions (3.3V Power supply)
(Ta = 0 to +70C)
Parameter Supply voltage (Operating voltage range) Supply I/O voltage (3.3 V I/O) Supply I/O voltage (2.5 V I/O) Supply voltage to VSS Input high voltage (3.3 V I/O) (DQ) (Others) Input high voltage (2.5 V I/O) (DQ) (Others) Input low voltage (3.3 V I/O) Input low voltage (2.5 V I/O) Note: Symbol VDD VDDQ VDDQ VSS VIH VIH VIH VIH VIL VIL Min 3.135 3.135 2.375 0.0 2.0 2.0 1.7 1.7 -0.3 -0.3 Typ 3.3 3.3 2.5 0.0 -- -- -- -- -- -- Max 3.465 3.465 2.625 0.0 VDDQ + 0.3 VDD + 0.3 VDDQ + 0.3 VDD + 0.3 0.8 0.7 Unit V V V V V V V V V V 1 1 Note
1. -2.0 V for undershoot pulse width 20% tCYC.
Recommended DC Operating Conditions (2.5V Power supply)
(Ta = 0 to +70C)
Parameter Supply voltage (Operating voltage range) Supply I/O voltage (2.5 V I/O) Supply voltage to VSS Input high voltage (2.5 V I/O) (DQ) (Others) Input low voltage (2.5 V I/O) Note: Symbol VDD VDDQ VSS VIH VIH VIL Min 2.375 2.375 0.0 1.7 1.7 -0.3 Typ 2.5 2.5 0.0 Max 2.625 2.625 0.0 VDDQ + 0.3 VDD + 0.3 0.7 Unit V V V V V V 1 Note
1. -2.0 V for undershoot pulse width 20% tCYC .
Rev.0.3, Mar. 2002, page 14 of 31
HM66WP18513, HM66WP36257
DC Characteristics
(Ta = 0 to +70C, VDD = 3.3 V +5%/-5% or 2.5 V +5%/-5% )
HM66WP18513/HM66WP36257 -65 Parameter Symbol Min -2 -5 -- -75 Max Min 2 5 200 -2 -5 -- -85 Max Min 2 5 180 -2 -5 -- Max Unit Test conditions 2 5 160 A A All inputs Vin = VSS to VDD OE = VIH, Vout = VSS to VDDQ
Input leakage current ILI Output leakage current Operating current ILO IDD
mA Device selected, Iout = 0 mA, all inputs = VIH or VIL, cycle time = tCYC min. mA Device deselected all inputs = fixed and all inputs VDD - 0.2 V or 0.2 V, cycle time = tCYC min. mA Device deselected all inputs = fixed and all inputs VDD - 0.2 V or 0.2 V, Frequency = 0 MHz. mA Device deselected all inputs = fixed and all inputs VDD - 0.2 V or 0.2 V, ZZ VDD - 0.2 V, Frequency = 0 MHz. V V V V IOL = 8 mA IOH = -4 mA IOL = 1 mA IOH = -1 mA
Standby current
ISB
--
80
--
70
--
60
ISB1
--
30
--
30
--
30
ISBZZ
10
10
10
Output low voltage (3.3 V I/O) Output high voltage (3.3 V I/O) Output low voltage (2.5 V I/O) Output high voltage (2.5 V I/O) Note:
VOL VOH VOL VOH
-- 2.4 -- 2.0
0.4 -- 0.4 --
-- 2.4 -- 2.0
0.4 -- 0.4 --
-- 2.4 -- 2.0
0.4 -- 0.4 --
1. LBO pin has an internal pull-up, ZZ pin has an internal pull-down, and input leakage current < |5A|.
Rev.0.3, Mar. 2002, page 15 of 31
HM66WP18513, HM66WP36257
Capacitance
(Ta = +25C, f = 1.0 MHz, VDD = 3.3 V and 2.5 V)
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min -- -- Typ 4 6 Max 5 7 Unit pF pF Note 1 1
1. This parameter is sampled and not 100% tested.
Rev.0.3, Mar. 2002, page 16 of 31
HM66WP18513, HM66WP36257
AC Characteristics
(Ta = 0 to +70C, VDD = 3.3 V +5%/-5% and 2.5 V +5%/-5%, VSS = 0 V) Test Conditions * Input timing measurement reference level: 1.4 V (3.3 V I/O) 1.2 V (2.5 V I/O) * Input pulse levels: 0 V to 2.8 V (3.3 V I/O) 0 V to 2.4 V (2.5 V I/O) * Input rise and fall time: 2 V/ns (10% - 90%) * Output timing reference level: 1.4 V (3.3 V I/O) 1.2 V (2.5 V I/O) * Output load: See figure
16.7 16.7 DQ 16.7 50 5 pF* 50 5 pF* 50 VL 50 VL
VL VL = 1.4 V (3.3 V I/O) or 1.2 V (2.5 V I/O) *(Including scope and jig)
Rev.0.3, Mar. 2002, page 17 of 31
HM66WP18513, HM66WP36257
HM66WP18513/HM66WP36257 Symbol Parameter Cycle time Clock access time Output enable to output valid Clock high to output active Clock high to output change -65 -75 Max Min -- 6.5 3.5 -- -- -- 3.5 3.8 -- -- -- 8.5 -- -- 2.5 2.5 0 -- -- 2.8 2.8 1.5 -85 Max Min -- 7.5 3.5 -- -- -- 3.5 4.0 -- -- -- Max Unit ns ns ns ns ns -- 4.0 5.0 -- -- -- ns ns ns ns ns ns 1 1 Notes
Standard Alternate Min tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGHQZ tKHQZ tKHKL tKLKH tAVKH tCENVKH tDVKH tWVKH tADVVK tEVKH tKHAX tKHCENX tKHDX tKHWX tKHADVX tKHEX tCYC tACK tOE tCLZ tCOH tOLZ tOHZ tCHZ tCH tCL tSA tSCEN tSD tSW tSADV tSCE 0.5 tHA tHCEN tHD tHW tHADV tHCE tPDS tPUS tZZI tRZZI 2 2 -- 0 7.5 -- -- 2.5 2.5 0 -- -- 2.5 2.5 1.5
10.0 -- -- -- 2.5 2.5 0 -- -- 3.0 3.0 1.5 8.5 4.0 --
Output enable to output active tGLQX Output disable to Q High-Z Clock high to Q High-Z Clock high pulse width Clock low pulse width Setup Times: Address Clock Enable Input Data Write (WE,BWa-d) Address Advance Chip Enable Hold Times: Address Clock Enable Input Data Write (WE,BWa-d) Address Advance Chip Enable ZZ Active to input ignored ZZ Inactive to input Sampled ZZ Active to sleep current ZZ Inactive to exit sleep current
--
0.5
--
0.5
--
ns
-- -- 2 --
2 2 -- 0
-- -- 2 --
2 2 -- 0
-- -- 2 --
cycle 4 cycle 4 cycle 4 cycle 4
Notes: 1. Transition is measured 100 mV from steady-state voltage. This parameter is sampled. 2. A READ cycle is defined by WE HIGH for the required setup and hold times. A WRITE cycle is defined by WE LOW for the required setup and hold times. 3. This is a synchronous device. All address must meet the specified setup and hold times for all rising edges of CLK when chip enabled. All other Synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when chip is enabled. Chip enable must be valid at each rising edge of CLK to remain enabled. 4. Data-output is not guaranteed during the cycle when transition of ZZ from low to high occurs.
Rev.0.3, Mar. 2002, page 18 of 31
HM66WP18513, HM66WP36257
A3 Burst continues with new base address
;; ;; ;; ;; ; ;; ;; ; ;; ; ;; ;; ;; ; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ; ; ;; ; ; ;; ;; ; ; ;; ;; ; ; ;; ; ; ;; ;; ; ; ; ;; ;; ;; ;; ;; ; ; ; ; ;; ;; ;; ; ; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ; ;; ; ; ;; ; ; ;; ;; ;; ; ;; ; ;; ; ;; ;; ;; ; ;; ;; ; ; ;; ;; ;; ; ; ;; ; ; ;; ;; ;; ;; ;; ; ; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;;
Q (A2)
;; ;; ;; ; ;; ; ;; ; ;; ;;
Q (A2+3)
;; ;; ; ;; ;; ;; ;;
;; ; ;; ; ; ;; ;; ; ;; ;; ; ; ;; ;;
;;
;; ;; ;;
;; ;; ;; ;;
;; ;;
;; ;; ; ; ;; ;
Q (A2+1)
;; ;;
;; ;; ;;
;; ;; ;
;;
Burst wraps around to its initial state.
; ; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;;
;; ;;
; ;; ; ;; ;;
;;
;; ;; ; ;; ; ;; ; ;; ;; ;; ;;
;; ;;
tACK
t SW t HW
A2
Timing Waveforms
tCH tCL
t SCE t HCE
;;
;;
; ;; ;; ;;; ;
tSA t HA
A1
;;
;;
Read Cycle
Address
CLK
*2
ADV/
;;
;;
;;
Q
;;
;; ;; ; ;; ;; ;; ;;; ; ; ;;
;;
;;
;;
;;
;;
;;
; ;; ; ;; ; ; ;; ;; ;;
;;
;; ;
; ; ;; ;; ;; ; ;; ;;
tCLZ
tACK
; ; ;; ; ;; ;; ;;
tCYC
;;
t OE
;;
;;
;;
; ;; ; ;; ; ;; ; ;; ;;
;;
; ;;
; ; ;; ;; ;; ;; ;;
Single READ
; ;; ; ;; ;;
;;
;;
Q (A1)
;; ;; ;;
tOHZ
;
;;
;;
;;
;;
;; ;; ;; ; ;; ;; ; ;
; ;;
;; ; ; ; ; ;; ;; ;; ;; ;;
t OLZ
;;
;;
;;
Q (A2)*1
;;
t COH
;;
;;
;;
;
Q (A2+1)
;;
;;
;;
;;
;;
;;
;;
;;
Q (A2+2)
;;
;;
;;
;;
;;
Notes: 1. Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from next internal burst address following A2. 2. and CE2 have timing identical to . On this diagram, when is LOW, is LOW and CE2 is HIGH. When is HIGH, is HIGH and CE2 is LOW. 3. Outputs are disabled within one clock cycle after deselect. 4. ZZ is LOW.
Q (A3)
; ;; ;; ;; ; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ; ;; ;;
; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;
;;
;; ; ;; ;; ;; ;;
BURST READ
H or L Undefined
Deselect cycle *3
;; ;; ;; ;; ;; ;;
;; ;;
;;
Rev.0.3, Mar. 2002, page 19 of 31
D (A3)
;;
;;
tSW tHW
;;
HM66WP18513, HM66WP36257
and CE2 have timing identical to . On this diagram, when is LOW, is LOW and CE2 is HIGH. When is HIGH, is HIGH and CE2 is LOW. 2. must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. , to are LOW. 3. Full width WRITE can be initiated by 4. ZZ is LOW.
BURST WRITE
BURST WRITE
Write Cycle
CLK
Address
ADV/
;;
;;
;
;;
;
Notes: 1.
; ;; ;; ; ; ;; ;; ;;
;; ; ;; ; ; ;; ;; ;;
;;
; ;; ; ; ;; ;;
*1
D
Q
;; ;; ; ;; ; ;; ; ;; ;;
;;
;; ;; ; ;; ;;
;;
Rev.0.3, Mar. 2002, page 20 of 31
tCH t CL
; ;; ; ; ;; ;; ;; ; ; ;; ;; ;; ;; ;; ; ;; ; ;; ;; ;; ;; ;; ;; ;; ; ;; ; ; ;; ;; ;; ; ; ;; ; ;; ; ; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ; ; ;; ;; ;; ; ;; ; ; ;; ;; ;; ;; ;; ; ; ; ;; ; ; ;; ; ;; ;; ; ; ;; ; ; ; ;; ;; ;; ;; ; ;; ;; ; ; ;; ;; ;; ; ;; ;; ;; ; ;; ; ;; ; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ; ; ;; ;; ;; ;; ; ;; ; ; ; ;; ; ;; ;; ;; ;; ; ; ; ;; ; ; ;; ;; ; ;; ;; ; ;; ;; ; ;; ;; ;;;; ; ;; ; ; ; ;; ; ; ;; ;;;; ;; ;; ;;; ;; ;;; ;; ; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ; ;;;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ; ; ;; ; ;; ; ; ; ;; ;; ;; ; ; ; ;; ; ; ;; ;; ;; ;; ; ; ; ; ;; ; ; ;; ; ;; ;; ;; ; ; ;; ; ; ;; ;; ;; ;;;; ;; ;; ; ;; ;; ; ; ; ;; ;; ;; ;; ;; ;; ;; ;; ; ; ;; ;;;; ;; ;; ;; ;; ;;;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ; ; ;; ; ;; ; ; ;; ;; ;; ; ; ; ;; ; ;; ; ;; ;; ;; ;; ; ;; ; ;; ;;;; ; ;; ; ;; ;;;; ;;;; ;; ;; ; ; ;; ;; ;;;; ;;;; ;; ;; ; ; ; ;; ;;;; ;; ;; ; ;; ;; ;; ; ; ;; ;; ;;;; ;; ;; ;; ;; ;; ;;;; ; ; ;; ;; ;; ;; ;; ;; ;; ; ; ;; ;; ;;;; ;; ; ;; ; ; ;; ;; ; ;;;; ;; ;; ;; ;; ;; ; ;;;; ;; ;; ;; ;; ; ;; ;;;; ;;;; ;; ; ;; ; ;; ;; ;;;; ;;;; ; ; ;; ; ;; ; ;; ;;;; ;; ; ;; ;; ;; ;; ;; ;; ;;;; ;; ;; ; ;; ;; ;;;; ; ; ;; ;; ;; ;;;; ; ;; ;; ; ; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ; ;; ; ;; ;; ;; ;; ; ;; ; ;; ;; ;; ; ;; ; ;; ;; ;; ;; ;;;; ;; ; ; ;; ;; ;; ;; ;;;; ;; ; ;; ;; ;; ;; ;;;; ;; ;; ;; ;; ;;;; ; ; ; ;; ;; ;; ;; ;; ; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ; ; ;; ; ;; ; ; ; ;; ; ;; ; ;; ; ;; ; ;; ; ;; ;; ;; ; ;;;; ; ; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ; ; ;; ; ; ;; ;; ;; ;; ;; ;; ; ; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ; ;; ; ;; ; ;; ;; ;; ;; ;; ;; ; ; ;; ; ;; ; ;; ;; ;; ;; ; ; ;; ;; ;; ; ; ;; ;; ;; ;; ;; ; ; ;; ;; ; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ; ; ;; ;; ;; ;; ;; ;; ; ; ;; ; ; ;; ;; ; ;; ; ;; ;; ; ;; ;; ;; ;; ;; ;; ; ;; ;; ; ; ;; ; ; ;; ;; ;; ;; ; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ;; ; ; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;;
tSD tHD
D (A1)
A2
D (A2)
D (A2+1)
D (A2+2)
D (A2+3)
D (A2)
A3
tCYC
t SCE t HCE
t SA t HA
A1
tOHZ
*2
Single WRITE
H or L Undefined
D (A3+1)
HM66WP18513, HM66WP36257
D (A4+2)
;;
;;
;
t SD t HD
D (A2)
;;
;;
t SW t HW
t CL
t CYC
;;
;;
t SCE t HCE
t SA t HA
High-Z
Read-Write Cycle
;;
; ;; ; ;; ; ;; ;; ;;
;
*3
CLK
Address
*2
ADV/
; ; ;;
Q
D
High-Z
;;
;
*3
;; ; ;; ; ;; ; ;; ;;
t ACK
A1
t CLZ
t CH
Q (A1)
; ;; ;; ; ;; ;; ;;
Single READ Single WRITE
; ;; ;; ;; ; ;; ; ;; ;;
A3
A2
t CHZ
t ACK t CLZ
;;
;;
; ;; ; ; ;; ;; ;; ; ;; ;;
Single READ
;;
;;
Notes: 1. Q (A3) refers to output from address A3. and CE2 have timing identical to . On this diagram, when is LOW, is LOW and CE2 is 2. HIGH. When is HIGH, is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. does not cause Q to be driven until after the following clock rising edge. 4. ZZ is LOW.
; ;; ; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ; ; ;; ;; ; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;;;;; ;; ;; ;; ;; ; ; ;; ; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;;;;; ;; ; ;;; ; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ; ;; ;; ;; ;; ; ;; ; ;; ;;;;; ;; ; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ; ;; ;; ;; ;; ;; ;; ;; ;; ; ; ;; ;; ;;; ; ;; ; ;; ;; ; ;; ; ;; ; ;; ;; ;; ;; ; ;; ;; ; ;; ;; ; ; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ;; ;; ;; ;;;;; ;; ;; ; ;; ;; ;; ; ;; ;; ;; ; ;; ; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ; ;; ; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ; ;; ;; ;; ; ; ;; ;; ; ;; ;; ; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ; ;; ;; ;; ; ;; ;; ;; ;; ; ;; ;; ; ; ; ;; ;; ; ;; ;; ;; ;; ;; ;; ; ;; ;; ; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ; ;; ;; ;; ;;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;;; ; ;; ;; ;; ; ;; ;; ; ;; ;; ;; ;; ;;
;;
D (A4)
A4
t CHZ
Q (A3 )
Rev.0.3, Mar. 2002, page 21 of 31
BURST WRITE
D (A4+2)
High-Z
H or L Undefined
D (A4+3)
HM66WP18513, HM66WP36257
Power-down State
CLK
ZZ
ISUPPLY
ALL INPUTS (except ZZ)
Outputs(Q)
Notes: 1. The terms of tZZ and tRZZ have to be that is LOW. 2. Data-output is not guaranteed during the cycle when transition of ZZ from low to high occurs.
Rev.0.3, Mar. 2002, page 22 of 31
;; ; ;
tZZ tRZZ tZZI IISB2Z tRZZI DESELECT or Read Only DESELECT or Read Only High-Z Power-down State with Data retention
;
DON' T CARE
HM66WP18513, HM66WP36257
Boundary Scan Test Access Port Operations (only BGA)
Overview In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 - 1990. But does not implement all of the functions required for 1149.1 compliance The HM66WP series contains a TAP controller. Instruction register, Boundary scans register, Bypass register and ID register.
Test Access Port Pins
Symbol I/O TCK TMS TDI TDO Name Test Clock Test Mode Select Test Data In Test Data Out
Notes: This Device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. To disable the TAP, TCK must be connected to Vss. TDO should be left unconnected. To test Boundary scan, ZZ pin need to be kept below VIL.
TAP DC Operating Characteristics (Ta = 0C to 70C)
Parameter Boundary scan Input High voltage (3.3V I/O) Boundary scan Input High voltage (2.5V I/O) Boundary scan Input Low voltage (3.3V I/O) Boundary scan Input Low voltage (2.5V I/O) Boundary scan Input Leakage Current Boundary scan Output Leakage Current Boundary scan Output Low voltage (3.3V/2.5V) Boundary scan Output High voltage (3.3V/2.5V) Symbol VIH VIH VIL VIL ILI ILo VOL VOH Min 2.0 V 1.7 V -0.3 V -0.3 V -5 A -5 A -- 2.4 V/2.0V Max VDD +0.3V VDD +0.3V 0.8 V 0.7 V +5 A +5 A 0.4 V/0.4 V -- 1 1 2 3 Notes
Notes: 1. 0 Vin VDD for all logic input pin 2. IOL = -8 mA at VDD = 3.3 V , IOL = -1 mA at VDD = 2.5 V. 3. IOH = 4 mA at VDD = 3.3 V , IOH = 1 mA at VDD = 2.5 V.
Rev.0.3, Mar. 2002, page 23 of 31
HM66WP18513, HM66WP36257
TAP AC Operating Characteristics (Ta = 0C to +70C)
Parameter Test Clock Cycle Time Test Clock High Pulse Width Test Clock Low Pulse Width Test Mode Select Setup Test Mode Select Hold Capture Setup Capture Hold TDI Valid to TCK High TCK High to TDI Don't Care TCK Low to TDO Unknown TCK Low to TDO Valid Note: Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tCS tCH tDVTH tTHDX tTLQX tTLQV Min 20 8 8 5 5 5 5 5 5 0 -- Max -- -- -- -- -- -- -- -- -- -- 10 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 Note
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP AC Test Conditions (VDD = 3.3 V and 2.5V)
VDD =3.3V * Temperature * Input timing measurement reference Level * Input pulse levels * Input Rise/Fall Time(10% to 90%) * Output timing measurement reference Level * Test load termination supply voltage (VT) * Output Load 0C Ta 70C 1.4 V 0 to 2.8 V 2.0 ns typical 1.4 V 1.4 V See figures VDD =2.5V 0C Ta 70C 1.2 V 0 to 2.4 V 2.0 ns typical 1.2 V 1.2 V See figures
VT DUT 50 Z0=50 TDO
Boundary Scan AC Test Load
Rev.0.3, Mar. 2002, page 24 of 31
HM66WP18513, HM66WP36257
TAP Controller Timing Diagram
tTHTH TCK tMVTH tTHMX TMS tDVTH tTHDX TDI tTLQV TDO tCS tCH RAM ADDRESS TAP Controller Timing Diagram tTLQX tTHTL tTLTH
Test Access Port Registers
Register Name Instruction Register Bypass Register ID Register Boundary Scan Register Length 3 bits 1 bits 32 bits 70 bits Symbol IR [0;2] BP ID [0;31] BS [1;70] Note
TAP Controller Instruction Set
IR2 0 0 0 0 1 1 1 1 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 Instruction SAMPLE-Z IDCODE SAMPLE-Z BYPASS SAMPLE BYPASS BYPASS BYPASS Tristate all data drivers and capture the pad value Operation Tristate all data drivers and capture the pad value
Note: This Device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE 1149.1.
Rev.0.3, Mar. 2002, page 25 of 31
HM66WP18513, HM66WP36257
Boundary Scan Order (HM66WP36257BP)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Notes:
Bump ID 2R 3T 4T 5T 6R 3B 5B 6P 7N 6M 7L 6K 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 7H 6G 6E 7D 6A 5A 4G 4A 4B 4F 4M 4H 4K
Signal name A5 A10 A11 A14 A13 A3 A9 DQa0 DQa3 DQa4 DQa6 DQa7 DQa1 DQa2 DQa5 DQa8 ZZ DQb7 DQb6 DQb4 DQb3 DQb0 DQb8 DQb5 DQb2 DQb1 A16 A8 A17 NC ADV/LD OE CEN WE CLK
Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Bump ID 6B 5L 5G 3G 3L 2B 4E 3A 2A 2D 1E 2F 1G 2H 1D 2E 2G 1H 5R 2K 1L 2M 1N 2P 1K 2L 2N 1P 3R 2C 3C 5C 6C 4N 4P
Signal name CE3 BWa BWb BWc BWd CE2 CE1 A4 A6 DQc0 DQc3 DQc4 DQc6 DQc7 DQc1 DQc2 DQc5 DQc8 NC DQd7 DQd6 DQd4 DQd3 DQd0 DQd8 DQd5 DQd2 DQd1 LBO A7 A2 A12 A15 A1 A0
1. Bit#1 is the first scan bit to exit the chip. 2. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a "Place Holder". Place holder registers are internally connected to VSS. 3. ZZ must remain at VIL during boundary scan.
Rev.0.3, Mar. 2002, page 26 of 31
HM66WP18513, HM66WP36257
Boundary Scan Order (HM66WP18513BP)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Notes:
Bump ID 2R 2T 3T 5T 6R 3B 5B 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 6T 6A 5A 4G 4A 4B 4F 4M 4H 4K 6B 5L 3G 2B 4E 3A 2A 1D
Signal name A5 A10 A15 A14 A12 A3 A9 DQa0 DQa1 DQa2 DQa3 ZZ DQa4 DQa5 DQa6 DQa7 DQa8 A11 A16 A8 A18 NC ADV/LD OE CEN WE CLK CE3 BWa BWb CE2 CE1 A4 A6 DQb8
Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
Bump ID 2E 2G 1H 5R 2K 1L 2M 1N 2P 3R 2C 3C 5C 6C 4N 4P
Signal name DQb7 DQb6 DQb5 NC DQb4 DQb3 DQb2 DQb1 DQb0 LBO A7 A2 A13 A17 A1 A0
1. Bit#1 is the first scan bit to exit the chip. 2. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a "Place Holder". Place holder registers are internally connected to VSS. 3. ZZ must remain at VIL during boundary scan.
Rev.0.3, Mar. 2002, page 27 of 31
HM66WP18513, HM66WP36257
ID Register
Part HM66WP36257 HM66WP18513 Revision Number (31:28) XXXX XXXX Device Density and Configuration (27:18) 0011000100 0011100011 Vendor Definition (17:12) xxxxxx xxxxxx Vendor JEDEC Code (11:1) 00000000111 00000000111 Start Bit (0) 1 1
TAP Controller State Diagram
1
Test-LogicReset 0
0
Run-Test/ Idle
1
SelectDR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0
1
SelectIR-Scan 0 1 Capture-IR 0 0 Shift-IR 1
1
0 1
1
Exit1-IR 0 0 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0
0
Notes: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK
Rev.0.3, Mar. 2002, page 28 of 31
HM66WP18513, HM66WP36257
Package Dimensions
HM66WP18513FP, HM66WP36257FP Series (FP-100H)
Preliminary
80 81
22.00 0.10 20.00 51 50
As of January, 2002
Unit: mm
16.00 0.10
14.00
100 1 *0.32 0.08 0.30 0.06 0.575 30
31
*0.17 0.05 0.15 0.04
1.60 Max
0.10 M
0.65
1.40
1.00 0.825
0 - 10
0.50 0.10
0.1
*Dimension including the plating thickness Base material dimension
0.10 0.05
Hitachi Code JEDEC JEITA Mass (reference value)
FP-100H Conforms -- 0.95 g
Rev.0.3, Mar. 2002, page 29 of 31
HM66WP18513, HM66WP36257
HM66WP18513BP, HM66WP36257BP Series (BP-119A)
As of January, 2002
Unit: mm
4x
0.20
0.35 C
4 x C1.2
14.00
Y C 7654321 A B C D E F G H J K L M N P R T U 1.27
A
Pin 1 Index
21.0 0.10
22.00
B 13.0 0.10
0.60 0.10
119 x 0.75 0.15 0.30 M C A B 0.15 M C
Details of the part Y
Hitachi Code JEDEC JEITA Mass (reference value) BP-119A Conforms -- 1.2 g
Rev.0.3, Mar. 2002, page 30 of 31
2.10 0.25
1.27
0.15 C
HM66WP18513, HM66WP36257
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Sales Offices
Hitachi, Ltd.
Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585200 Hitachi Europe GmbH Electronic Components Group Dornacher Strae 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281 URL : http://semiconductor.hitachi.com.hk
Copyright (c) Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 6.0
Rev.0.3, Mar. 2002, page 31 of 31

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