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TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) direct/ultra high IF sampling
Rev. 02 -- 9 December 2004 Objective data sheet
1. General description
The TDA9910 is a 12-bit Analog-to-Digital Converter (ADC) optimized for direct IF sampling, and supporting the most demanding use conditions in ultra high IF radio transceivers for cellular infrastructure and other applications such as wireless access system, optical networking and fixed telecommunication. Thanks to its broadband input capabilities, the TDA9910 is ideal for single and multiple carriers data conversion. Operating at a maximum sampling rate of 80 Msample/s, analog input signals are converted into 12-bit binary coded digital words. All static digital inputs are CMOS compatible. All output signals are LVCMOS compatible. The TDA9910 offers the most possible flexible acquisition control system thanks to its programmable Complete Conversion Signal (CCS) that allows to adjust the delay of the acquisition clock. Thanks to its internal front-end buffer, the TDA9910 offers the lowest input capacitance (< 1 pF) and therefore the highest flexibility in front-end aliasing filter strategy. Released in HTQFP48, it keeps the industry's smallest ADC of its category.
2. Features
s s s s s s s s s s s s s s s 12-bit resolution Direct IF sampling up to 370 MHz 90 dB SFDR; 71 dB SNR (fi = 225 MHz; B = 5 MHz) 72 dB SFDR; 66 dB SNR (fi = 175 MHz; B = Nyquist) High-speed sampling rate up to 80 Msample/s Programmable acquisition output clock (complete conversion signal) Internal front-end buffer (input capacitance below 1 pF) Full-scale controllable from 1.5 V to 2 V (p-p); continuous scale Single 5 V power supply 3.3 V LVCMOS compatible digital outputs Binary or two's-complement LVCMOS outputs CMOS compatible static digital inputs Only 2 clock cycles latency Industrial temperature range from -40 C to +85 C HTQFP48 package.
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
3. Applications
s s s s s 2.5G and 3G cellular base infrastructure radio transceivers Wireless access systems Fixed telecommunication Optical networking WLAN infrastructure.
4. Ordering information
Table 1: Ordering information Package Name TDA9910HW/6 TDA9910HW/8 HTQFP48 Description plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad Version SOT545-2 Sampling frequency (Msample/s) 60 80 Type number
5. Block diagram
CLK CLKN
TDA9910
CLOCK DRIVER
2
DEL0 to DEL1 CCS
12
LATCH
12
D0 to D11 OTC
front-end buffer IN INN TRACK AND HOLD RESISTOR LADDERS ADC CORE
U/I FSIN
VCCO LATCH IR
FSOUT
VREF REFERENCE
CMADC REFERENCE
OUTPUTS ENABLE
001aaa511
CMADC
DEC
CE_N
Fig 1. Block diagram.
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Objective data sheet
Rev. 02 -- 9 December 2004
2 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
6. Pinning information
6.1 Pinning
41 VCCD1(5V0) 47 VCCA1(5V0) 45 VCCA1(5V0) 44 VCCA2(5V0)
42 DGND1
38 DGND1
48 AGND1
46 AGND1
43 AGND2
39 CLKN
n.c. AGND1 IN CMADC INN AGND1 DEC n.c. FSOUT
37 CCS 36 D0 35 D1 34 D2 33 D3 32 D4 31 D5 30 D6 29 D7 28 D8 27 D9 26 D10 25 D11 IR 24
001aaa512
1 2 3 4 5 6 7 8 9 DGND
TDA9910HW
FSIN 10 n.c. 11 n.c. 12 n.c. 13 DEL1 14
DEL0 15
VCCD2(5V0) 16
DGND2 17
CE_N 18
OTC 19
OGND 20
VCCO(3V3) 21
40 CLK
OGND 22
Fig 2. Pin configuration.
6.2 Pin description
Table 2: Symbol n.c. AGND1 IN CMADC INN AGND1 DEC n.c. FSOUT FSIN n.c. n.c. n.c. DEL1
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Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Type [1] G I O I G I/O O I I Description not connected analog ground 1 analog input voltage regulator common mode ADC output complementary analog input voltage analog ground 1 decoupling node not connected full-scale reference voltage output full-scale reference voltage input not connected not connected not connected complete conversion signal delay input 1
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Objective data sheet
Rev. 02 -- 9 December 2004
VCCO(3V3) 23
3 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Pin description ...continued Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Type [1] I P G I I G P G P O O O O O O O O O O O O O O G I I P G G P P G P G Description complete conversion signal delay input 0 digital supply voltage 2 (5.0 V) digital ground 2 chip enable input (CMOS level; active LOW) control input for two's complement output (active HIGH) data output ground data output supply voltage (3.3 V) data output ground data output supply voltage (3.3 V) in-range output data output bit 11 (MSB) data output bit 10 data output bit 9 data output bit 8 data output bit 7 data output bit 6 data output bit 5 data output bit 4 data output bit 3 data output bit 2 data output bit 1 data output bit 0 (LSB) complete conversion signal output digital ground 1 complementary clock input clock input digital supply voltage 1 (5.0 V) digital ground 1 analog ground 2 analog supply voltage 2 (5.0 V) analog supply voltage 1 (5.0 V) analog ground 1 analog supply voltage 1 (5.0 V) analog ground 1 digital ground
Table 2: Symbol DEL0 VCCD2(5V0) DGND2 CE_N OTC OGND VCCO(3V3) OGND VCCO(3V3) IR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CCS DGND1 CLKN CLK VCCD1(5V0) DGND1 AGND2 VCCA2(5V0) VCCA1(5V0) AGND1 VCCA1(5V0) AGND1 DGND
exposed G die pad
[1]
P: power supply; G: ground; I: input; O: output.
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Objective data sheet
Rev. 02 -- 9 December 2004
4 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
7. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCA VCCD VCCO VCC Parameter analog supply voltage digital supply voltage output supply voltage supply voltage difference VCCA - VCCD VCCD - VCCO VCCA - VCCO VIN, VINN input voltage referenced to AGND referenced to DGND -1.0 -1.0 -1.0 0 0 -55 -40 +1.0 +4.0 +4.0 VCCA + 1 VCCD + 1 +150 +85 150 V V V V V mA C C C Conditions
[1] [1] [2]
Min -0.5 -0.5 -0.5
Max +7.0 +7.0 +5.0
Unit V V V
VCLK, VCLKN input voltage for differential clock drive IO Tstg Tamb Tj
[1] [2]
output current storage temperature ambient temperature junction temperature
The supply voltages VCCA and VCCD may have any value between -0.5 V and +7.0 V provided that the supply voltage differences VCC are respected. The supply voltage VCCO may have any value between -0.5 V and +5.0 V provided that the supply voltage differences VCC are respected.
8. Thermal characteristics
Table 4: Symbol Rth(j-a) Rth(j-c)
[1]
Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions
[1]
Typ 36.2 14.3
Unit K/W K/W
[1]
In compliance with JEDEC test board, in free air.
9. Characteristics
Table 5: Characteristics VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to +85 C; VIN(p-p) - VINN(p-p) = 2.0 V - 0.5 dB; VFSIN = VCCA1 - 1.77 V; Vi(CM) = VCCA1 - 1.85 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Supplies VCCA VCCD VCCO
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Conditions
Test [1] Min 4.75 4.75 2.7
Typ 5.0 5.0 3.3
Max 5.25 5.25 3.6
Unit V V V
5 of 21
analog supply voltage digital supply voltage output supply voltage
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 -- 9 December 2004
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Table 5: Characteristics ...continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to +85 C; VIN(p-p) - VINN(p-p) = 2.0 V - 0.5 dB; VFSIN = VCCA1 - 1.77 V; Vi(CM) = VCCA1 - 1.85 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter ICCA ICCD ICCO Ptot analog supply current digital supply current output supply current total power dissipation fCLK = 80 Msample/s; fi = 175 MHz fCLK = 80 Msample/s; DC input referenced to DGND; VCCD = 5 V PECL mode TTL mode VIH HIGH-level input voltage referenced to DGND; VCCD = 5 V PECL mode TTL mode IIL LOW-level input current VCLK or VCLKN = 3.52 V VCLK or VCLKN = 2.00 V IIH HIGH-level input current VCLK or VCLKN = 3.83 V VCLK or VCLKN = 0.80 V VCLK differential AC input voltage for switching (VCLK - VCLKN) input resistance input capacitance LOW-level input current HIGH-level input current input resistance AC mode; DC voltage level is 2.5 V fCLK = 80 Msample/s fCLK = 80 Msample/s VFSIN = VCCA - 1.75 V VFSIN = VCCA - 1.75 V fi = 21.4 MHz fi = 93 MHz fi = 175 MHz Ci input capacitance fi = 21.4 MHz fi = 93 MHz fi = 175 MHz Vi(CM) common mode input voltage LOW-level input voltage HIGH-level input voltage VIN = VINN; output code = 2047 D D D D D D D 3.83 2.0 20 1 1.5 4.12 VCCD 30 2 V V A nA A nA V 3.19 DGND 3.52 0.8 V V Conditions Test [1] Min Typ 122 52 29 870 Max Unit mA mA mA mW
Clock inputs: pins CLK and CLKN [2] VIL LOW-level input voltage
Ri Ci IIL IIH Ri
6.3 6.3 6.3 VCCA - 2
6.3 1.1 5 5 -
700 700 700
k pF A A M M M fF fF fF V
Analog inputs: pins IN and INN
VCCA - 1.85 VCCA - 1.6
Digital inputs: pins OTC and CE_N VIL VIH
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DGND
-
0.3 x VCCD VCCD
V V
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0.7 x VCCD Rev. 02 -- 9 December 2004
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Table 5: Characteristics ...continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to +85 C; VIN(p-p) - VINN(p-p) = 2.0 V - 0.5 dB; VFSIN = VCCA1 - 1.77 V; Vi(CM) = VCCA1 - 1.85 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter IIL IIH VIL VIH IIL IIH Vo(CM) LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current common mode output voltage VIL = 0.8 V VIH = 2.0 V IL = 0 mA IL = 2 mA Conditions VIL = 0.8 V VIH = 2.0 V Test [1] Min DGND see Figure 5; Vi = VIN - VINN; Vi(CM) = VCCA - 1.91 V IL = IFSIN IL = 2 mA 1.5 Typ 5 5 80 80 Max 0.3 x VCCD VCCD Unit A A V V A A V V V A V
Digital inputs: pins DEL0 and DEL1 0.7 x VCCD -
Voltage controlled regulator output: pin CMADC VCCA - 1.88 VCCA - 1.91 VCCA - 1.84 1 1.9 2.0
Reference voltage input: pin VFSIN IFSIN Vi(p-p) input current input voltage (peak-to-peak value)
FSIN [3]
full-scale fixed voltage
Full-scale voltage controlled regulator output: pin FSOUT Vo(ref) 1.9 V full-scale output voltage VCCA - 1.84 VCCA - 1.87 V V
Digital outputs: pins D11 to D0, IR and CCS Output levels VOL VOH IOZ Timing [4] td(s) th(o) td(o) tdZH tdZL tdHZ tdLZ fCLK(min) sampling delay time output hold time output delay time enable HIGH enable LOW disable HIGH disable LOW minimum clock frequency CL = 10 pF CL = 10 pF CL = 10 pF 80 5.6 5.6 0.2 4 5 3 5 8 5 8 ns ns ns ns ns ns ns Msample/s Msample/s ns ns LOW-level output voltage output current in 3-state IOL = 2 mA output level between 0.5 V and VCCO DGND -20 1 DGND + 0.5 VCCO +20 V V A HIGH-level output voltage IOH = -0.4 mA VCCO - 0.5 -
3-state output delay
Clock timing inputs: pins CLK and CLKN fCLK(max) maximum clock frequency duty cycle 45 % to 65 % tCLKH tCLKL
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clock pulse width HIGH clock pulse width LOW
fi = 175 MHz fi = 175 MHz
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Objective data sheet
Rev. 02 -- 9 December 2004
7 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Table 5: Characteristics ...continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to +85 C; VIN(p-p) - VINN(p-p) = 2.0 V - 0.5 dB; VFSIN = VCCA1 - 1.77 V; Vi(CM) = VCCA1 - 1.85 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter tcd(o) complete conversion signal delay time Conditions CL = 10 pF; DEL0 = LOW; DEL1 = HIGH CL = 10 pF; DEL0 = HIGH; DEL1 = LOW CL = 10 pF; DEL0 = HIGH; DEL1 = HIGH INL DNL integral non-linearity differential non-linearity fCLK = 20 Msample/s; fi = 21.4 MHz fCLK = 20 Msample/s; fi = 21.4 MHz; no missing code guaranteed VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C; output code = 2047 VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C fCLK = 80 Msample/s; -3 dB; full-scale input fi = 21.4 MHz fi = 93 MHz fi = 175 MHz total harmonic distortion TDA9910/8 [6] fi = 21.4 MHz fi = 93 MHz fi = 175 MHz SNR signal-to-noise ratio TDA9910/6 [7] fi = 21.4 MHz fi = 93 MHz fi = 175 MHz signal-to-noise ratio TDA9910/8 [7] fi = 21.4 MHz fi = 93 MHz fi = 175 MHz Test [1] Min Typ 0.2 Max Unit ns Timing complete conversion signal: pin CCS; see Figure 6
-
1.3
-
ns
-
2.4
-
ns
Analog signal processing (clock duty cycle 50 %; VIN - VINN = 1.9 V; Vref = VCCA3 - 1.75 V) 1.6 0.4 LSB LSB
Eoffset
offset error
-
5
-
mV
EG
gain error amplitude (spread from device to device) analog bandwidth [5] total harmonic distortion TDA9910/6 [6]
-
0.8
-
%FS
B THD
-
370 -74 -72 -72 -76 -74 -70 67.5 67.2 66.5 67 66.7 66
-
MHz dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc
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Objective data sheet
Rev. 02 -- 9 December 2004
8 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Table 5: Characteristics ...continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to +85 C; VIN(p-p) - VINN(p-p) = 2.0 V - 0.5 dB; VFSIN = VCCA1 - 1.77 V; Vi(CM) = VCCA1 - 1.85 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter SFDR spurious free dynamic range TDA9910/6 Conditions fi = 21.4 MHz fi = 93 MHz fi = 175 MHz spurious free dynamic range TDA9910/8 fi = 21.4 MHz fi = 93 MHz fi = 175 MHz ACPR adjacent channel power rejection fi = 93 MHz; 5 MHz channel spacing; B = 4.096 MHz fi = 175 MHz; 5 MHz channel spacing; B = 4.096 MHz d2(IM2) second order intermodulation distortion [8] fi1 = 21 MHz; fi2 = 22 MHz fi1 = 93 MHz; fi2 = 96 MHz fi1 = 174 MHz; fi2 = 176 MHz d3(IM3) third order intermodulation distortion [8] fi1 = 21 MHz; fi2 = 22 MHz fi1 = 93 MHz; fi2 = 96 MHz fi1 = 174 MHz; fi2 = 176 MHz
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation: a) PECL mode 1: (DC levels vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC levels vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC levels vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has to be connected to the ground. The ADC input range can be adjusted with an external reference connected to FSIN pin. This voltage has to be referenced to VCCA. Output data acquisition: the output data is available after the maximum delay of td(o). The -3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. The total harmonic distortion is obtained with the addition of the first five harmonics. The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency.
Test [1] Min -
Typ 76 73 73 79 75 72 86
Max -
Unit dBc dBc dBc dBc dBc dBc dB
-
74
-
dB
-
-81 -83 -80 -87 -88 -83
-
dBFS dBFS dBFS dBFS dBFS dBFS
[2]
[3] [4] [5] [6] [7]
9397 750 14418
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Objective data sheet
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Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
[8]
Intermodulation measured relative to either tone with analog input frequencies fi1 and fi2. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (-6 dB below full-scale for each input signal). d3(IM3) is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product; d2(IM2) is the ratio of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product.
Table 6: Output coding with differential inputs VIN(p-p) - VINN(p-p) = 1.9 V; VFSIN = VCCA1 - 1.77 V; typical values to AGND. Code Underflow 0 1 ... 2047 ... 4094 4095 Overflow Table 7: VIN(p-p) (V) < 2.675 2.675 ... 3.15 ... 3.625 > 3.625 VINN(p-p) (V) > 3.625 3.625 ... 3.15 ... 2.675 < 2.675 IR 0 1 1 ... 1 ... 1 1 0 Binary outputs (D11 to D0) 0000 0000 0000 0000 0000 0000 0000 0000 0001 ... 0111 1111 1111 ... 1111 1111 110 1111 1111 111 1111 1111 111 Two's complement outputs (D11 to D0) 1000 0000 0000 1000 0000 0000 1000 0000 0001 ... 1111 1111 111 ... 0111 1111 110 0111 1111 111 0111 1111 111
Mode selection Chip enable input (CE_N) 0 0 1 Data output (D0 to D11; IR) binary; active two's complement; active high-impedance
Two's complement output (OTC) 0 1 X [1]
[1] X = don't care.
CLK
n
50 %
td(o) D0 to D11 data n-1 data n th(o) td(s) IN sample n sample n+1 sample n+2 sample n+3 sample n+4
001aaa513
data n+1
VCCO - 0.5 V 0.5 V
Fig 3. Output timing diagram.
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Objective data sheet
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Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
0 power spectrum (dBc) -40
001aaa514
(1)
-80
(2)
(3)
(4)
(5)
(6)
-120
-160 0 10 20 30 fi (MHz) 40
(1) fi = 15 MHz; 0 dBc (2) fi = 5.1 MHz; -73.64 dBc (3) fi = 9.88 MHz; -82.6 dBc (4) fi = 20.1 MHz; -77.26 dBc (5) fi = 30 MHz; -71.73 dBc (6) fi = 35.1 MHz; -71.68 dBc THD (5H): 66.93 dBc SFDR: -71.68 dBc
Fig 4. Single tone; fi = 175 MHz; fCLK = 80 Msample/s.
2.2 Vi(CM) (V) 2.0
001aaa515
(3)
(2)
1.8
1.6
(1)
1.4 1.5
1.6
1.7
1.8
1.9 2.0 VCCA - VFSIN (V)
(1) Vi(CM) = 1.54 V; VCCA - VFSIN = 1.5 V (2) Vi(CM) = 1.9 V; VCCA - VFSIN = 1.84 V (3) Vi(CM) = 2.07 V; VCCA - VFSIN = 2.0 V
Fig 5. ADC full-scale; Vi(CM) as a function of VCCA - VFSIN.
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Objective data sheet
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Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
The TDA9910 allows to modify the ADC full-scale. This could be done with FSIN (full-scale input) according to Figure 5. The TDA9910 generates an adjustable clock output called Complete Conversion Signal (CCS), which can be used to control the acquisition of converted output data by the digital circuit connected to the TDA9910 output data bus. Two logic inputs, DEL0 and DEL1 pins, allow to adjust the delay of the edge of the CCS signal to achieve an optimal position in the stable, usable zone of the data.
Table 8: DEL1 0 0 1 1 0 1 0 1 Complete conversion signal selection DEL0 CCS output high-impedance active, typical delay 0.2 ns active, typical delay 1.3 ns active, typical delay 2.4 ns
(1)
D0 to D11 tcd(o) CCS
001aaa516
(1) tcd(o) is referenced to the middle of the active data.
Fig 6. Complete conversion signal timing diagram.
10. Definitions
10.1 Static parameters
10.1.1 INL (integral non-linearity)
It is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of the code i is obtained from the equation: V I ( i ) - V I ( ideal ) INL ( i ) = -----------------------------------------S where: S is corresponding to the slope of the ideal straight line (code width); i is corresponding to the code value.
10.1.2 DNL (differential non-linearity)
It is the deviation in code width from the value of 1 LSB. V I (i + 1) - V I (i) DNL ( i ) = ---------------------------------------S
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Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
where: i = 0x ( 2 - 2 )
n
10.2 Dynamic parameters
Figure 7 shows the spectrum of a single tone full-scale input sine wave with frequency ft, conforming to coherent sampling (ft/fs = M/N, with M number of cycles and N number of samples, M and N being relatively prime), and digitized by the ADC under test.
001aaa518
magnitude
a1
SFDR a3
a2
ak
measured output range (MHz)
fs/2
Fig 7. Single tone spectrum of full-scale input sine wave with frequency ft.
Remark: In the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and "quantization noise".
10.2.1 SINAD (signal-to-noise and distortion)
The ratio of the output signal power to the noise plus distortion power for a given sample rate and input frequency, excluding the DC component: P signal SINAD [ dB ] = 10log 10 --------------------------------------- P noise + distortion
10.2.2 ENOB (effective number of bits)
It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the real ADC. A good approximation gives: SINAD - 1.76 ENOB = ---------------------------------6.02
10.2.3 THD (total harmonic distortion)
The ratio of the power of the harmonics to the power of the fundamental. For k - 1 harmonics the THD is:
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Objective data sheet
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Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
P harmonics THD [ dB ] = 10log 10 ------------------------ P signal - where: P harmonics = a 2 + a 3 + ... + a k P signal = a 1 The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics).
2 2 2 2
10.2.4 SNR (signal-to-noise ratio)
The ratio of the output signal power to the noise power, excluding the harmonics and the DC component is: P signal SNR [ dB ] = 10log 10 --------------- P noise-
10.2.5 SFDR (spurious free dynamic range)
The number SFDR specifies available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious harmonic and non-harmonic, excluding DC component: a1 SFDR [ dB ] = 20log 10 ------------------ max ( S )
10.2.6 IMD2 (IMD3)
001aaa527
magnitude
IMD3
measured output range (MHz)
fs/2
Fig 8. Spectral of dual tone input sine wave with frequency.
9397 750 14418
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 -- 9 December 2004
14 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
From a dual tone input sinusoid (ft1 and ft2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd order components) are defined, as follows. The ratio of the RMS value of either tone to the RMS value of the worst second (third) order intermodulation product. The total intermodulation distortion IMD is given by: P intermod IMD [ dB ] = 10log 10 --------------------- P signal - where: P intermod = a im ( f
2 - f t2 )
t1
- a im ( f
2
2
t1
+ f t2 ) - f t2 )
+ a im ( f
2
2
t1
- 2 f t2 ) + f t2 )
+ a im ( f
2
t1
+ 2 f t2 )
+...
... + a im ( 2 f with a im ( f
2
t1 )
t1
+ a im ( 2 f
t1
corresponding to the power in the intermodulation component at frequency ft.
2
t2
P signal = a f + a f
t1
2
9397 750 14418
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 -- 9 December 2004
15 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
11. Application information
11.1 TDA9910 in 3G radio receivers
The TDA9910 has been proven in many 3G radio receivers with various operating conditions regarding Input Frequency (IF), signal IF bandwidth and sampling frequency. The TDA9910 provides with a maximum analog input signal frequency of 400 MHz. It allows a significant cost-down of the RF front-end, from two mixers to only one, even in multi-carriers architecture. Table 9 describes some possible applications with the TDA9910 in high IF sampling mode.
Table 9: fi (MHz) 350 243.95 96 96 96 80 78.4 70
[1]
Examples of possible fi, fCLK, IF BW combinations supported fCLK (Msample/s) 80 9.60 76.80 76.80 76.80 61.44 44.80 40.00 IF BW (MHz) [1] 5.00 0.25 1.60 4.80 20.00 10.00 3.50 1.25 SNR (dB) 65 71 72 71 68 70 71 72 SFDR (dBc) 71 80 76 77 76 85 76 79
IF bandwidth corresponds to the observed area on the ADC output spectrum.
For a dual carrier W-CDMA receiver, the most important parameters are sensitivity and Adjacent Channel Selectivity (ACS). The sensitivity is defined as the lowest detectable signal level. In W-CDMA, it can be far below the noise floor. This difference, between the sensitivity and the noise floor, is defined by the Sensitivity-to-Noise Ratio (SENR). Its value is negative due to the gain processing. The Adjacent Channel Power Ratio (ACPR) is the difference between the full-scale -3 dB peak and the noise floor. It represents the ratio of the adjacent-channel power and the average power level of the channel. The ACS is defined by the sum of SENR and ACPR.
interfering channel
wanted channel
ACS
ACPR
noise floor NF SENR sensibility thermal noise
001aaa517
Fig 9. Adjacent channel sensitivity and ADC sensibility.
9397 750 14418
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Objective data sheet
Rev. 02 -- 9 December 2004
16 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
11.2 Application diagram
ADT1_1WT 100 nF 6 2 4 VCCA VCCD 2.2 k VCCA1(5V0) VCCD1(5V0) VCCA1(5V0) VCCA2(5V0) DGND1 AGND1 DGND1 AGND1 AGND2 TL431CPK CCS 100 nF VCCD1 3 5 1 n.c. 50 CLK
CLKN
CLK
48 330 nF ADT1_1WT 3 n.c. 100 nF IN 100 5 1 6 2 4 100 n.c. AGND1 IN CMADC INN AGND1 10 nF 100 nF DEC n.c. FSOUT FSIN n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 n.c.
47
46
45
44
43
42
41
40
39
38
37
36
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
35 34 33 32
TDA9910HW
31 30 29
DGND
28 27 26 25
14 DEL1
15 DEL0
16 VCCD2(5V0)
17 DGND2
18 CE_N
19 OTC
20 OGND
21 VCCO(3V3)
22 OGND
23 VCCO(3V3)
24 IR G1
10 nF
VCCD VCCD (16) 100 nF 10 nF
VCCO (41) 10 nF
4700_000_S analog ground digital ground 330 nF
4700_000_S 330 nF
VCCA (44) 100 nF 10 nF (45) 10 nF (47) 10 nF HF70ACB
5V
xx 10 V 4.7 F
IN 470 nF
LM317MDT
3 1 ADJ 2
VCCO OUT 240 100 nF (21) 10 nF (23) 10 nF
GND
xx
300
coa002
Fig 10. Application diagram.
9397 750 14418
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 -- 9 December 2004
17 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
12. Package outline
HTQFP48: plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad
SOT545-2
c y exposed die pad side X
Dh 36 37 25 24 ZE A
e Eh wM bp pin 1 index 48 1 wM 12 ZD vM A 13 detail X Lp L E HE A A2 A1 (A 3)
bp e D HD
B vM B
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 7.1 6.9 Dh 4.6 4.4 E(1) 7.1 6.9 Eh 4.6 4.4 e 0.5 HD 9.1 8.9 HE 9.1 8.9 L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 0.9 0.6 0.9 0.6 7 0
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT545-2 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-04-07 04-01-29
Fig 11. Package outline SOT545-2 (HTQFP48).
9397 750 14418 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 -- 9 December 2004
18 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
13. Revision history
Table 10: Revision history Release date 20041209 Data sheet status Objective data sheet Change notice Doc. number 9397 750 14418 Supersedes TDA9910_1 Document ID TDA9910_2 Modifications:
*
Four values changed in Table 5 (Clock timing inputs)
9397 750 14418
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 -- 9 December 2004
19 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
14. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
15. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
16. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
17. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14418
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 -- 9 December 2004
20 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
18. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.1.1 10.1.2 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 11 11.1 11.2 12 13 14 15 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Static parameters . . . . . . . . . . . . . . . . . . . . . . 12 INL (integral non-linearity) . . . . . . . . . . . . . . . 12 DNL (differential non-linearity) . . . . . . . . . . . . 12 Dynamic parameters. . . . . . . . . . . . . . . . . . . . 13 SINAD (signal-to-noise and distortion) . . . . . . 13 ENOB (effective number of bits) . . . . . . . . . . . 13 THD (total harmonic distortion). . . . . . . . . . . . 13 SNR (signal-to-noise ratio) . . . . . . . . . . . . . . . 14 SFDR (spurious free dynamic range) . . . . . . . 14 IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information. . . . . . . . . . . . . . . . . . 16 TDA9910 in 3G radio receivers. . . . . . . . . . . . 16 Application diagram . . . . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information . . . . . . . . . . . . . . . . . . . . 20
(c) Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 9 December 2004 Document number: 9397 750 14418
Published in The Netherlands

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