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| Freescale Semiconductor Data Book. Advanced Clock Drivers. DL207 Rev. 2 8/2004 Advanced Clock Drivers Selector Guide Clock Generator Data Sheets QUICCClock Generator Data Sheets Failover or Redundant Clock Data Sheets Clock Synthesizer Data Sheets Zero-Delay Buffer Data Sheets LVCMOS Fanout Buffer Data Sheets Differential Fanout Buffer Data Sheets Packaging Information Application Notes 1 2 3 4 5 6 7 8 9 10 BLANK Advanced Clock Drivers Device Data Foreword This publication includes technical information for the several product families that comprise Freescale Semiconductor Advanced Clock Drivers products. Freescale's broad portfolio of devices support voltage levels from 2.5 V to 5.0 V in both CMOS I/O and various differential I/O technologies. Advanced Clock Drivers are developed by the Freescale Semiconductor Timing Solutions Operations organization. All devices are listed in alphanumeric order in the Device Index of this book. Just turn to the appropriate page for technical details of the known device. A Selector Guide by product family is provided at the beginning of the book to aid you in identifying devices that meet your application and functional performance requirements. Complete device specifications are provided in the form of Data Sheets which are categorized into the six product types: Clock Generators, QUICCClocks, Failover / Redundant Clocks, Clock Synthesizers, Zero-Delay Buffers, LVCMOS Fanout Buffers, and Differential Fanout Buffers. Chapters on Packaging Information and Application Notes include additional information to aid you in the design process. The information in this book has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. This document was revised in 2004 during the Motorola to Freescale Semiconductor, Inc. transition. References to Motorola still appear in this current revision. If this document is revised, all references to Motorola will be removed at that time. (c) Freescale Semiconductor, Inc. 2004 Previous Edition (c) 2003 "All Rights Reserved" Printed in U.S.A. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 5 Freescale Semiconductor Technical Support and Literature Worldwide Access: Internet: E-mail: www.freescale.com support@freescale.com Quick References: Technical Support www.freescale.com/support For Technical or Literature questions or comments you may select "Technical Support", log in and use the "Service Request" feature. You may directly access PDF files on the website, or use the shopping cart to request Postal delivery of our literature. To browse and order literature through the Literature Distribution Center, select "Order Literature" on the main "Documentation" page. Retrieve/Order Literature Telephone, Fax, and E-mail Contacts: North and South America: Phone: +1-800-521-6274 or +1-480-768-2130 Fax: +1-480-768-2131 E-mail: support@freescale.com For fastest response use the Worldwide Internet access listed above. Europe, Middle East, and Africa: Phone: +44 1296 380 456 +46 8 52200080 +49 89 92103 559 +33 1 69 35 48 48 Fax: E-mail: Asia/Pacific:* Phone: Fax: E-mail: Japan: Phone: Fax: E-mail: Internet: +49 89 92103 466 support@freescale.com +800 2666 8080* +000 800 852 1155 +852 2661 7736 support.asia@freescale.com 0120 191 014 0120 191 060 support.japan@freescale.com www.freescale.co.jp (Toll Free: Domestic only) (Toll Free: Domestic only) (Toll Free within Asia/Pacific) (Toll Free within India) (Chinese and English) (English) (English) (German) (French) (German and English) *Countries covered within Asia/Pacific are: China, Taiwan, South Korea, Macau, Malaysia, Singapore, Thailand, Australia and New Zealand. To get Pricing and Delivery for a product: Budgetary pricing is available for most products on the Freescale web site; however, to obtain pricing and delivery quotes, contact your local authorized distributor or Freescale sales representative. To find your local distributor, visit www.freescale.com, select "Where to Buy" on the Freescale Home Page. 6 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor's Technical Information Center: The Freescale Semiconductor Technical Information Center (TIC) is a worldwide service organization that provides our customers and distributors with the following services: * Access to technical information and literature * Answers to questions on Freescale Semiconductor products * Assistance in locating Technical Training on Freescale Semiconductor's microprocessors, embedded processors, and microcontroller products. support pages offer device errata, technical training course information, and answers to frequently asked questions. To submit a written technical request, visit www.freescale.com. Select "Support", then "Technical Support" from the menu. Written technical requests help eliminate misunderstandings and shorten answer response intervals. Requests generated from this Internet interface are automatically fed into a worldwide customer database as a technical service request. You immediately receive a service request reference number. This reference number enables you to view the request status, deliver additional information directly to our specialists, and cancel or re-open a request by using the Internet interface. This customer database enables us to direct your service request to the appropriate person and track the response time. Through our worldwide network, one of our Freescale specialists can immediately start working on your service request. We are located in the Americas, Europe, Middle East, Africa, Asia/Pacific, and Japan. Our goal is to answer your request within two days. In most cases, our customers receive an overnight response. We have developed a system to respond to you, the customer, in the most efficient and timely manner possible. Technical Information and Literature: To complement Freescale Semiconductor's broad line of products, we offer a complete library of technical literature. Data books detail the electrical characteristics of our products. User's manuals describe the capabilities of our products in circuit and system design. Visit our Products Library and Documentation Library at www.freescale.com. From the Home Page you can select "Products" and then the desired Product Family or "Support" and then "Documentation" from the menu. From the Products Library, our customers can quickly browse device-specific information in our Product Catalog. From the Documentation Library, our customers can perform the following functions: * Download files found in the online catalog or through the online search * Order data sheets, data books, user's manuals, selector guides, stocked CDs, and any other inventory item in print or on a CD-ROM * Select literature files and create a fully customized CD-ROM through our CD-ON-DEMAND process. The literature service is free-of-charge. However, literature and CD quantities are limited. If you need larger quantities (for example, for a special promotion), contact your local authorized distributor, Freescale sales representative, or use the contact information listed on the previous page. Technical Training on Freescale Semiconductor products: We can assist you in locating Web-based training on our web site, or instructor-lead processor training courses in your region. These training courses enable design engineers to quickly gain product knowledge; getting designs to market faster. Through our Training Partners in-plant courses are available where instructors come to your premises or a convenient location, to present the training to your design engineers. Alternatively, in cases where course attendance is too small to justify a training course of its own, general training courses are available through our Training Partners. These courses accommodate a single or small number of engineers that can join in with those of other companies. Technical Questions and Support: We strive to provide you the information you need. Our Web sites are designed to provide detailed information on our current devices and system solutions. The To see available Technical Training for Freescale Semiconductor products: Visit www.freescale.com, select "Design Support" from the menu, and then select "Training". FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 7 ATTENTION: Freescale Semiconductor Advanced Clock Driver Customers The Timing Solutions Operation of Freescale Semiconductor is currently undergoing a technology update on several of the Advanced Clock Driver devices. This technology update moves the current product to a newer process technology. This semiconductor technology update results in an introduction of a pin and functional equivalent device, which will provide superior electrical performance. Clock Generators Old Device MPC930 MPC931 MPC950 MPC951 MPC952 MPC972 MPC973 MPC974 MPC992 MPC993 MPC9952 Replaced by MPC9330 MPC9331 MPC9350 MPC93R51 MPC93R52 MPC9772 MPC9773 MPC9774 MPC9992 MPC9993 MPC9352 The following tables list the devices that are involved in this technology update. These lists also contain the replacement device part number. Please consult the selector guide and associated device data sheets for the details of these devices. If additional product information is desired please contact your local Freescale Semiconductor representative. Clock Synthesizers Old Device MC12429 MC12430 MC12439 Replaced by MPC9229 or MPC92429 MPC9230 or MPC92430 MPC9239 or MPC92439 Zero-Delay Buffers Old Device MPC953 MPC958 Replaced by MPC9653A MPC9658 LVCMOS Fanout Buffers Old Device MPC946 MPC947 MPC948 MPC949 Replaced by MPC9446 MPC9447 MPC9448 MPC9449 Differential Fanout Buffers Old Device MC100EP111 MC100EP210 MC100EP220 MC100EP221 MC100EP222 Replaced by MC100ES6111 MC100ES6210 MC100ES6220 MC100ES6221 MC100ES6222 8 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Advanced Clock Drivers Device Data Table of Contents Page Foreword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Freescale Semiconductor Technical Support and Literature . . . . . . . . . . . . . . . . . . . . . . . . 6 Freescale Semiconductor's Technical Information Center . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Note to Freescale Semiconductor Advanced Clock Driver Customers . . . . . . . . . . . . . . . . . . . . . . . 8 Device Index (Alphanumeric) . . . . . . . . . . . . . . . . . . 10 Page Chapter Three QUICCClock Generator Data Sheets . . . . . . . . . . . 259 Chapter Four Failover or Redundant Clock Data Sheets. . . . . . . 285 Chapter Five Clock Synthesizer Data Sheets. . . . . . . . . . . . . . . . 351 Chapter Six Zero-Delay Buffer Data Sheets . . . . . . . . . . . . . . . . 473 Chapter One Advanced Clock Drivers Selector Guide. . . . . . . . . 13 Clock Generator Reference Table . . . . . . . . . . . . . 14 QUICCClock Reference Table . . . . . . . . . . . . . . . . 16 Failover or Redundant Clock Reference Table . . . . 17 Clock Synthesizer Reference Table . . . . . . . . . . . . 18 Zero-Delay Buffer Reference Table . . . . . . . . . . . . 19 LVCMOS Fanout Buffer Reference Table . . . . . . . . 20 Differential Fanout Buffer Reference Table . . . . . . 21 Clock Characteristic Diagrams . . . . . . . . . . . . . . . . 23 Chapter Seven LVCMOS Fanout Buffer Data Sheets . . . . . . . . . . . 559 Chapter Eight Differential Fanout Buffer Data Sheets . . . . . . . . . 647 Chapter Nine Packaging Information . . . . . . . . . . . . . . . . . . . . . . 781 Case Dimension Cross-Reference Tables . . . . . . . 782 Case Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 784 Chapter Two Clock Generator Data Sheets. . . . . . . . . . . . . . . . . . 25 Chapter Ten Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 799 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 9 Device Index Device Number Page Device Number Page MC100ES6011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 MC100ES6014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 MC100ES60T22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 MC100ES60T23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 MC100ES6030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 MC100ES6039 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 MC100ES6056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 MC100ES6111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 MC100ES6130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 MC100ES6139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 MC100ES6210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 MC100ES6220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 MC100ES6221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 MC100ES6222 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 MC100ES6226 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 MC100ES6254 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 MC100ES6535 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 MC100ES7011H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 MC100ES7011P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 MC100ES7014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 MC100ES7111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 MC100ES8011H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 MC100ES8011P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 MC100ES8014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 MC100ES8111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 MC12429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 MC12430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 MC12439 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 MC88915T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MC88LV915T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 MC88LV926 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 MPC905 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 MPC9109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 MPC9229 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 MPC9230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 MPC9239 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 MPC92429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 MPC92430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418 MPC92432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 MPC92439 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444 MPC92459 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453 MPC926508 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .461 MPC9315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 MPC9330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 MPC9331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 MPC9350 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 MPC9351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 MPC93H51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 MPC93R51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 MPC9352 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 MPC93H52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 MPC93R52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 MPC940L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570 MPC941 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .576 MPC942C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .585 MPC942P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .588 MPC9443 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .592 MPC9446 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .604 MPC9447 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611 MPC9448 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .618 MPC9449 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .628 MPC94551 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .636 MPC9456 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639 MPC9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 MPC9608 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474 MPC961C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .483 MPC961P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492 MPC962304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .501 MPC962305 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .507 MPC962308 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .513 MPC9653 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .520 MPC9653A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529 MPC9658 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538 MPC96877 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547 10 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Device Number Page Device Number Page MPC9772 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 MPC9773 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 MPC97H73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 MPC9774 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 MPC97H74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 MPC9817 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 MPC9850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 MPC9855 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 MPC9892 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 MPC9893 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 MPC9894 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 MPC9895 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328 MPC992 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 MPC9994 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465 MPC9992 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 MPC9993 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 MPC99J93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 11 12 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Chapter One Advanced Clock Drivers Selector Guide Freescale Semiconductor provides a one stop shop for your high performance clocking needs. Our broad portfolio of devices support voltage levels from 2.5 V to 5.0 V in both CMOS I/O and various differential I/O technologies. With one of the widest selection of products in the industry, Freescale Semiconductor should be your first stop when you need to design a high performance clock tree. Advanced Clock Drivers are developed by the Freescale Semiconductor Timing Solutions Operations organization. Access Advanced Clock Drivers Technical Information On-Line Freescale Semiconductor has provided a World Wide Web Server to deliver it's technical data to the global Internet community. Technical data (such as data sheets, application notes, and selector guides) are available on the Internet server with full, easy text search capabilities. Ordering literature from the Literature Center is available on-line. Other features of Freescale Semiconductor's Internet server include the availability of a searchable press release database, technical training information with on-line registration capabilities, an on-line technical support form to send technical questions and receive answers through e-mail, information on product groups, full search capabilities of device models, a listing of authorized distributors, and links directly to other Freescale Semiconductor World Wide Web servers. To access Freescale Timing Solutions Operations information, use one of the following URLs: www.freescale.com/Clocks www.freescale.com/AdvancedClockDrivers www.freescale.com/TimingSolutions To Replace Devices in an Existing Design Call your local Freescale Semiconductor Sales Office or Distributor to determine the closest replacement device. Applications Assistance Applications assistance is available from your nearest Freescale Semiconductor Sales office. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 13 Clock Generator Reference Table Introduction This classification of product uses PLL technology to generate output clocks that are synchronous, and in most cases phase aligned, to an input reference clock. Limited frequency synthesis and zero delay performance is provided. Device Processor and Application Temp. Range (C) (TA) -40 to 85 VCC (V) Package Output Frequency Range (MHz) 18 to 160 Max Output Skew (ps) 120 Max Period Jitter (ps) 8 (rms) 250 Input No. of Outputs Status MPC9315 Telecom/Networking Applications 3.3/ 2.5 3.3 32 LQFP 2 selectable LVCMOS XTAL LVCMOS LVCMOS LVPECL XTAL LVCMOS LVCMOS LVPECL LVCMOS LVCMOS LVPECL LVCMOS LVPECL LVCMOS LVCMOS LVCMOS LVPECL XTAL LVCMOS LVCMOS LVPECL LVCMOS LVPECL LVCMOS 8 LVCMOS 6 LVCMOS 6 LVCMOS 9 LVCMOS 9 LVCMOS 11 LVCMOS 9 LVCMOS 9 LVCMOS 11 LVCMOS 11 LVCMOS 21 LVCMOS 12 LVCMOS 12 LVCMOS 12 LVCMOS 15 LVCMOS P MPC9330 Pentium or PowerPC603/740/750 Class Processor Designs (on-board crystal oscillator) Pentium or PowerPC603/740/750 Class Processor Designs (faster VCO than 930) Networking and Telecommunications Ideal for PowerQUICC II and PowerPC MPC74XX applications Networking and Telecommunications Ideal for PowerQUICC II and PowerPC MPC74XX applications General Purpose or RISC/CSIC Class Processor Designs High output drive version of MPC93R51 Networking and Telecommunications Ideal for PowerQUICC II and PowerPC MPC74XX applications High output drive version of MPC93R52 General Purpose or RISC/CSIC Class Processor Designs General purpose 2.5 V, high fanout zero delay buffer General Purpose or RISC/CSIC Class Designs (independent output enable/disable "lo-power" scheme) Pentium or PowerPC603/740/750 Class Designs (output enable/disable "lo-power" scheme) High output drive version of MPC9773 Fault Tolerant (redundant Clock Source needed) Pentium/PowerPC603/740/750/RISC Class Processor Design High output drive version of MPC9774 Pentium or PowerPC603/740/750 Class Designs (output enable/disable "lo-power" scheme) 0 to 70 32 LQFP 16 to 200 150 P MPC9331 0 to 70 3.3 32 LQFP 16 to 200 150 125 P MPC9350 -40 to 85 3.3/ 2.5 3.3/ 2.5 3.3/ 2.5 3.3 3.3 32 LQFP 25 to 200 200 -- P MPC9351 -40 to 85 32 LQFP 25 to 200 100 -- P MPC9352 MPC93H51 MPC93R51 -40 to 85 0 to 70 0 to 70 32 LQFP 32 LQFP 32 LQFP 16 to 200 240 240 150 150 150 200 15 (rms) 15 (rms) -- -- 50 150 P P P MPC93H52 MPC93R52 MPC9600 MPC9772 0 to 70 0 to 70 -40 to 85 0 to 70 3.3 3.3 3.3/ 2.5 3.3 32 LQFP 32 LQFP 48 LQFP 52 LQFP 240 240 25 to 200 25 to 240 200 200 150 300 P P P P MPC9773 0 to 70 3.3 52 LQFP 25 to 240 300 150 P MPC97H73 MPC9774 0 to 70 0 to 70 3.3 3.3 52 LQFP 52 LQFP 25 to 240 25 to 125 300 300 150 90 P P MPC97H74 MPC9992 0 to 70 -40 to 85 3.3 3.3/ 2.5 52 LQFP 32 LQFP 25 to 125 20 to 400 300 150 90 TBD LVCMOS LVPECL XTAL 15 LVCMOS 7 Differential Pairs P S Legend: IN = In Development (TARGET specifications) P = Production (FINAL specifications) S = Sampling (PRELIM specifications) 14 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Clock Generator Reference Table (continued) Device Processor and Application Temp. Range (C) (TA) 0 to 70 VCC (V) Package Output Frequency Range (MHz) 5 to 55 Max Output Skew (ps) 500 Max Period Jitter (ps) -- Input No. of Outputs Status MC88915FN55 PC Work Station, Servers, Memory Modules, Graphics Cards, High End Printers, Networking, and Telecom PC Work Station, Servers, Memory Modules, Graphics Cards, High End Printers, Networking, and Telecom PC Work Station, Servers, Memory Modules, Graphics Cards, High End Printers, Networking, and Telecom PC Work Station, Servers, Memory Modules, Graphics Cards, High End Printers, Networking, and Telecom PC Work Station, Servers, Memory Modules, Graphics Cards, High End Printers, Networking, and Telecom PC Work Station, Servers, Memory Modules, Graphics Cards, High End Printers, Networking, and Telecom PC Work Station, Servers, Memory Modules, Graphics Cards, High End Printers, Networking, and Telecom PC Work Station, Servers, Memory Modules, Graphics Cards, High End Printers, Networking, and Telecom PC Work Station, Servers, Memory Modules, Graphics Cards, High End Printers, Networking, and Telecom 5.0 28 PLCC CMOS 8 LVCMOS P MC88915FN70 0 to 70 5.0 28 PLCC 5 to 70 500 -- CMOS 8 LVCMOS 8 LVCMOS 8 LVCMOS 8 LVCMOS 8 LVCMOS 8 LVCMOS 8 LVCMOS 6 LVCMOS 6 LVCMOS 6 LVCMOS P MC88915TFN55 -40 to 85 5.0 28 PLCC 55 500 -- CMOS P MC88915TFN70 -40 to 85 5.0 28 PLCC 5 to 70 500 -- CMOS P MC88915TFN100 -40 to 85 5.0 28 PLCC 5 to 100 500 -- CMOS P MC88915TFN133 -40 to 85 5.0 28 PLCC 5 to 133 500 -- CMOS P MC88915TFN160 0 to 70 5.0 28 PLCC 5 to 160 500 -- CMOS P MC88LV915TFN 0 to 70 3.3 28 PLCC 5 to 100 500 -- CMOS P MC88LV926DW 0 to 70 3.3 20 SOIC 300 Mil 20 SOIC 300 Mil 20 SOIC 300 Mil 5 to 133 500 -- CMOS P MC88916DW70/80 PC Work Station, Servers, Memory Modules, Graphics Cards, High End Printers, Networking, and Telecom MC88920DW PC Work Station, Servers, Memory Modules, Graphics Cards, High End Printers, Networking, and Telecom -40 to 85 5.0 5 to 80 500 -- CMOS P -40 to 85 5.0 5 to 50 500 -- CMOS P Legend: IN = In Development (TARGET specifications) P = Production (FINAL specifications) S = Sampling (PRELIM specifications) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 15 QUICCClock Reference Table Introduction This classification of products is specifically designed to meet the clock requirements for the PowerPC and PowerQUICC microprocessors and microcontrollers. Although designed for PowerPC processors these devices also provide the widely used clock frequencies for most microprocessor families. Device Processor and Application Temp. Range (C) -40 to 85 -40 to 85 VCC (V) 3.3 3.3 Core 3.3 or 2.5 I/O 3.3 Core 3.3 or 2.5 I/O Package Output Frequencies 25, 33, 50, 66 16, 25, 33, 50, 83, 100, 125, 133,166 16, 25, 33, 50, 83, 100, 125, 133,166 Input No. of Outputs 5 + 3 reference outputs 8-LVCMOS 2-Rapid I/O 1 @ 25 MHz ref 8-LVCMOS 2 @ 25 MHz ref Status MPC9817 MPC9850 Low-cost PowerPC ISA and PowerQUICC designs PowerQUICC 3 w/Rapid I/O 20 SSOP 100 MAPBGA 100 MAPBGA Crystal or LVCMOS Crystal LVCMOS LVPECL Crystal LVCMOS LVPECL S S MPC9855 PowerPC, PowerQUICC 2 and PowerQUICC 3 w/o Rapid I/O -40 to 85 S Legend: IN = In Development (TARGET specifications) P = Production (FINAL specifications) S = Sampling (PRELIM specifications) 16 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Failover or Redundant Clock Reference Table Introduction Redundant or Failover Clock Applications are required for high reliability telecommunications, networking and other applications where the loss of a clock source would cause system failure. Clock sources for these applications may be generated by master system clocks and distributed over a backplane to various modules in a pc board, chassis or electronics cabinet. Device Processor and Application Temp. Range (C) (TA) -40 to 85 VCC (V) Package Output Frequency Range (MHz) 50 to 180 Max Output Skew (ps) 150 Max Period Jitter (ps) TBD Input No. of Outputs Status MPC9892 Systems with clock redundancy needs (high-end computing and telecomm) Differential LVPECL 50 MHz to 90 MHz input frequency Systems with clock redundancy needs (high-end computing and telecomm), FAILOVER Clock Four (4) input redundant clock with I2C configuration interface Systems with clock redundancy needs (high-end computing and telecomm), FAILOVER Clock with restore function Systems with clock redundancy needs (high-end computing and telecomm) Differential LVPECL 50 MHz to 90 MHz input frequency Systems with clock redundancy needs (high-end computing and telecomm) Differential LVPECL 50 MHz to 90 MHz input frequency 3.3 32 LQFP LVPECL 5 Differential Pairs 12 LVCMOS 8 LVPECL 12 LVCMOS S MPC9893 -40 to 85 3.3/ 2.5 3.3/ 2.5 3.3 48 LQFP 25 to 200 TBD TBD LVCMOS P MPC9894 MPC9895 -40 to 105 (TJ) -40 to 85 100 PBGA 100 PBGA 21.25 to 340 25 to 200 TBD TBD TBD TBD LVPECL LVCMOS S S MPC9993 -40 to 85 3.3 32 LQFP 50 to 200 150 TBD LVPECL 5 Differential Pairs 5 Differential Pairs P MPC99J93 -40 to 85 3.3 32 LQFP 50 to 180 150 TBD LVPECL P Legend: IN = In Development (TARGET specifications) P = Production (FINAL specifications) S = Sampling (PRELIM specifications) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 17 Clock Synthesizer Reference Table Introduction This classification of products uses PLL technology to synthesize high frequency clocks from low cost crystal sources. Programmable frequency steps are typically 1 MHz or less with output frequencies as high as 800 MHz. Device Processor and Application Temp. Range (C) (TA) 0 to 70 VCC (V) Package Output Frequency Range (MHz) 400 Max Period Jitter (ps) 25 Input Outputs Status MPC9229 Clock source for 25 MHz to 450 MHz processor designs (serial and/or parallel) 1 MHz steps Clock source for 50 MHz to 900 MHz processor designs (serial and/or parallel) 1 MHz steps Clock source for 50 MHz to 900 MHz processor designs (serial and/or parallel) 16.66 MHz steps Clock source for 50 MHz to 900 MHz processor designs (serial or parallel) 16.66 MHz steps Clock source for 25 MHz to 450 MHz processor designs (serial and/or parallel) 1 MHz steps Clock source for 50 MHz to 900 MHz processor designs (serial and/or parallel) 1 MHz steps Mid-range to high performance telecom, networking, and computing applications Clock source for 50 MHz to 900 MHz processor designs (serial and/or parallel) 16.66 MHz steps Clock synthesizer for networking applications (Pin compatible with ICS65008) 3.3 28 PLCC 32 LQFP 28 PLCC 32 LQFP 28 PLCC 32 LQFP 32 LQFP XTAL LVPECL P MPC9230 0 to 70 3.3 800 25 XTAL LVCMOS XTAL LVCMOS XTAL LVCMOS XTAL LVPECL P MPC9239 0 to 70 3.3 900 25 LVPECL P MPC9259 0 to 70 3.3 900 25 LVDS S MPC92429 0 to 70 3.3 28 PLCC 32 LQFP 28 PLCC 32 LQFP 48 LQFP 28 PLCC 32 LQFP 20 TSSOP 400 25 LVPECL S MPC92430 0 to 70 3.3 800 25 XTAL LVCMOS Crystal LVCMOS XTAL LVCMOS XTAL LVCMOS LVPECL S MPC92432 MPC92439 -40 to 85 0 to 70 3.3 3.3 21.25 to 1360 900 TBD 25 2 LVPECL LVPECL S IN MPC926508 -40 to 85 3.3 100 to 133 -- LVCMOS P Legend: IN = In Development (TARGET specifications) P = Production (FINAL specifications) S = Sampling (PRELIM specifications) 18 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Zero-Delay Buffer Reference Table Introduction This classification of products uses PLL technology to reproduce exact copies, in frequency and phase, of the input reference clock. These specialized products provide superior AC performance to clock generators, but lack any frequency synthesis capabilities. Device Processor and Application Temp. Range (C) (TA) -40 to 85 VCC (V) Package Output Frequency Range (MHz) 12.5 to 200 Max Output Skew (ps) 150 Max Period Jitter (ps) 150 Input Outputs Status MPC9608 General Purpose Zero-delay applications, Companion to PowerQUICK and PPC designs, DRAM applications General Purpose also PowerQUICC: Zero-delay applications (CMOS clock signal retiming without insertion delay) DRAM driver Zero-delay applications (PECL clock signal retiming without insertion delay) General Purpose Zero-delay applications (Pin compatible with CY2304) General Purpose Zero-Delay applications. (Pin compatible with CY2305/CY23S05) General Purpose Zero-delay applications. (Pin compatible with CY2308/CY23S08) General Purpose Zero-delay applications. (Pin compatible with CY2309/CY23S09) High Performance Clock Tree Design, PC100SDRAM 3.3 32 LQFP LVCMOS 10 LVCMOS P MPC961C -40 to 85 3.3/ 2.5 32 LQFP 50 to 200 150 10 (RMS) LVCMOS Ref LVCMOS fdbk LVPECL Ref LVCMOS fdbk LVCMOS 17 + feedback LVCMOS P MPC961P -40 to 85 3.3/ 2.5 32 LQFP 50 to 200 150 10 (RMS) 17 + feedback LVCMOS 4 + feedback LVCMOS 4 + feedback LVCMOS 8 LVCMOS 8 + feedback LVCMOS 8 + feedback LVCMOS 10 + feedback LVCMOS 10 SSTL-18 P MPC962304 0 to 70 or -40 to 85 0 to 70 or -40 to 85 3.3 8 SOIC 133 200 IN MPC962305 3.3 8 SOIC 8 TSSOP 16 SOIC 16 TSSOP 16 SOIC 16 TSSOP 8 SOIC 8 TSSOP 16 SOIC 16 TSSOP 32 LQFP 133 250 200 LVCMOS S MPC962308 0 to 70 or -40 to 85 0 to 70 or -40 to 85 3.3 133 200 200 LVCMOS S MPC962309 3.3 133 250 200 LVCMOS S MPC9653A 0 to 70 3.3 125 150 100 LVPECL Ref LVCMOS fdbk LVPECL Ref LVCMOS fdbk SSTL-18 P MPC9658 Very High Performance Clock Tree Design up to 200 MHz, PC100SDRAM DDR2 zero-delay application 0 to 70 3.3 32 LQFP 250 120 80 P MPC96877 Legend: 0 to 70 1.8 52 VFBGA 40 MLF 125 to 270 TBD 40 S IN = In Development (TARGET specifications) P = Production (FINAL specifications) S = Sampling (PRELIM specifications) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 19 LVCMOS Fanout Buffer Reference Table Introduction This classification of product uses digital circuitry to produce multiple copies of its input clock. In some cases the output frequencies will be divided down versions of the input clock. Device Processor and Application Temp. Range (C) (TA) 0 to 70 VCC (V) Package Max Output Frequency (MHz) 100 Max Output Skew (ps) 500 Max Part-Part Skew (ns) -- Input Outputs Status MPC905 Pentium PCI Processor Bus Clock or PCI Bus Hi-Speed Transmission Line Driver General Purpose or RISC/CSIC PCI Clock Distribution to Synchronous Memory (better performance than MPC9109) General Purpose or RISC/CSIC PCI Clock Distribution to Synchronous Memory (more outputs than MPC940) Pentium II and other high performance synchronous designs (CMOS inputs) Pentium II and other high performance synchronous designs (PECL inputs) General Purpose or RISC/CSIC PCI Clock Distribution to Synchronous Memory Low Voltage High-performance Telecom, Networking and computing Applications Low Voltage Mid-range and Highperformance Telecom, Networking and Computing Applications General Purpose or RISC/CSIC Class Processor Clock Fanout for L2 Cache General Purpose or RISC/CSIC Class Processor Clock Fanout for L2 Cache (faster & more outputs than the MPC947) General Purpose or RISC/CSIC Class Processor PCI Clock Distribution to Synch Memory (5 more outputs than the MPC946) 1:4 LVCMOS fanout buffer Low Voltage Mid-range and Highperformance Telecom, Networking and Computing Applications 3.3 16 SOIC XTAL external LVCMOS LVPECL LVCMOS 6 P MPC940L 0 to 70 3.3/ 2.5 32 QFP/LQFP 250 150 1.7 18 P MPC941 -40 to 85 3.3/ 2.5 48 QFP 250 250 1.2 LVPECL LVCMOS 27 P MPC942C 0 to 70 3.3/ 2.5 3.3/ 2.5 3.3/ 2.5 3.3/ 2.5 3.3/ 2.5 3.3/ 2.5 3.3/ 2.5 32 LQFP 250 250 1 LVTTL LVCMOS LVPECL 18 P MPC942P 0 to 70 32 LQFP 250 250 1 18 P MPC9109 0 to 70 32 QFP/LQFP 48 LQFP 250 150 1.7 LVPECL LVCMOS LVPECL LVCMOS LVCMOS 18 P MPC9443 -40 to 85 250 200 -- 16 P MPC9446 -40 to 85 32 LQFP 250 200 -- 10 P MPC9447 -40 to 85 32 LQFP 275 150 TBD LVTTL 9 P MPC9448 -40 to 85 32 LQFP 275 150 TBD LVPECL LVCMOS 12 P MPC9449 -40 to 85 3.3/ 2.5 52 LQFP 200 200 TBD LVPECL LVCMOS 15 P MPC94551 MPC9456 -40 to 85 -40 to 85 3.3 3.3/ 2.5 8 SOIC 32 LQFP 160 250 250 250 TBD --- LVCMOS LVPECL 4 10 S P Supports single and mixed mode power supply Legend: IN = In Development (TARGET specifications) P = Production (FINAL specifications) S = Sampling (PRELIM specifications) 20 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Differential Fanout Buffer Reference Table Introduction This classification of product uses digital circuitry to produce multiple copies of its input clock. In some cases the output frequencies will be divided down versions of the input clock. Device Processor and Application Temp. Range (C) (TJ) -40 to 85 (TA) -40 to 85 (TA) -40 to 85 (TA) -40 to 85 (TA) -40 to 85 (TA) -40 to 85 (TA) -40 to 85 (TA) -40 to 85 (TA) 0 to 110 VCC (V) Package Max Part-Part Skew (ps) 150 225 Max Output Skew (ps) 20 45 Output Technology Input Outputs Status MC100ES6011 MC100ES6014 ECL Differential Fanout Buffer Differential ECL/PECL/HSTL Clock Driver ECL Quad Differential Receiver Dual LVTTL/LVCMOS to Differential LVPECL Translator Dual Differential LVPECL to LVTTL Translator ECL Triple D flip-flop with set and reset ECL /2/4, /4/6 Clock Generation Chip ECL Dual Differential 2:1 Multiplexer Clock distribution schemes requiring "very low" part-to-part and output-to-output skews 2.5 GHz PECL/ECL clock driver with 2:1 differential input MUX ECL divided by 2/4, divided by 4/5/6 Clock Generation Chip Clock distribution schemes requiring "very low" part-to-part and output-to-output skews LV/PECL Designs needing low skew. Telecom BackBone Equipment, Semi Test Equipment LV/PECL Designs needing low skew. Telecom BackBone Equipment, Semi Test Equipment LV/PECL Designs needing low skew. Telecom BackBone Equipment, Semi Test Equipment Clock distribution schemes requiring "extremely low" partto-part and output-to-output skews 3.3/ 2.5 3.3/ 2.5 3.3 3.3 3.3 3.3/ 2.5 3.3/ 2.5 3.3 3.3/ 2.5 3.3/ 2.5 3.3 3.3/ 2.5 3.3/ 2.5 8 SOIC 8 TSSOP 20 TSSOP LVPECL LVPECL ECL ECL PECL HSTL LVPECL LVTTL LVCMOS LVPECL PECL PECL LVDS HSTL ECL ECL LVPECL HSTL PECL LVDS HSTL ECL ECL LVPECL ECL LVPECL 1:2 1:5 P P MC100ES6017 MC100ES60T22 MC100ES60T23 MC100ES6030 MC100ES6039 20 SOIC 8 SOIC 8 SOIC 20 SOIC 20 SOIC TBD 300 TBD TBD TBD TBD n/a TBD TBD TBD LVPECL PECL LVTTL PECL PECL Quad 1:1 Dual 1:1 Dual 1:1 Triple 1:1 1:4 IN S IN S P MC100ES6056 MC100ES6111 20 SOIC 20 TSSOP 32 LQFP 200 250 50 35 LVPECL 3 GHz LVPECL PECL Dual 2:1 1:10 P P MC100ES6130 -40 to 85 (TA) -40 to 85 (TA) 0 to 110 16 TSSOP 150 25 1:4 P MC100ES6139 MC100ES6210 20 SOIC 20 TSSOP 32 LQFP TBD 175 TBD 35 LVPECL 3 GHz LVPECL 3 GHz LVPECL 1:4 Dual 1:5 P P MC100ES6220 0 to 110 52 LQFP exposed pad 52 LQFP exposed pad 52 LQFP exposed pad 32 LQFP 200 50 Dual 1:10 DIFF P MC100ES6221 0 to 110 3.3/ 2.5 300 50 3 GHz LVPECL ECL LVPECL 1:20 DIFF P MC100ES6222 0 to 110 3.3/ 2.5 300 50 3 GHz LVPECL ECL LVPECL 1:15 DIFF P MC100ES6226 0 to 110 3/ 2.5 325 35 3 GHz LVPECL LVPECL 1:9 P Legend: IN = In Development (TARGET specifications) P = Production (FINAL specifications) S = Sampling (PRELIM specifications) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 21 Differential Fanout Buffer Reference Table (continued) Device Processor and Application Temp. Range (C) (TJ) 0 to 110 VCC (V) Package Max Part-Part Skew 250 Max Output Skew (ps) 35 Output Technology Input Outputs Status MC100ES6254 Differential 2x2 clock switch and Fanout Buffer 1:4 LVCMOS to LVPECL clock fanout buffer 1:2 differential HSTL/LVDS clock fanout buffer 1:2 differential PECL to LVDS clock fanout buffer 1:5 differential LVDS clock fanout buffer Clock distribution schemes requiring very low part-to-part and output-to-output skews 1:2 differential HSTL clock fanout buffer 1:2 differential PECL to HSTL clock fanout buffer 1:5 differential HSTL clock fanout buffer Clock distribution schemes requiring "extremely low" partto-part and output-to-output skews 3/ 2.5 3.3 3.3 3.3 3.3 3.3 32 LQFP 3 GHz LVPECL PECL LVDS LVDS LVDS LVDS LVPECL Single 1:6 or Double 1:3 1:4 1:2 1:2 1:5 1:10 P MC100ES6535 MC100ES7011H MC100ES7011P MC100ES7014 MC100ES7111 -40 to 85 (TA) 0 to 110 0 to 110 0 to 110 0 to 110 20 TSSOP 8 SOIC 8 SOIC 20 TSSOP 32 LQFP 190 TBD TBD TBD TBD 30 TBD TBD TBD TBD PECL LVDS HSTL PECL PECL LVDS LVPECL HSTL LVDS HSTL PECL PECL HSTL HSTL LVPECL P IN IN IN IN MC100ES8011H MC100ES8011P MC100ES8014 MC100ES8111 0 to 110 0 to 110 0 to 110 0 to 110 3.3 3.3 3.3 3.3 8 SOIC 8 SOIC 20 TSSOP 32 LQFP TBD TBD TBD 200 TBD TBD TBD 50 HSTL HSTL HSTL HSTL 1:2 1:2 1:5 1:10 IN IN IN P Legend: IN = In Development (TARGET specifications) P = Production (FINAL specifications) S = Sampling (PRELIM specifications) 22 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Clock Characteristic Diagrams PECL_CLK CLK PECL_CLK VCC VCC/2 GND tPD tPD FB VCC VCC/2 GND VCC VCC/2 GND Ext_FB Propagation Delay (tPD, static phase offset) Test Reference (PECL) VCC VCC/2 GND tP t0 DC = tP/t0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Propagation Delay (tPD, static phase offset) Test Reference (CMOS) VCC VCC/2 GND VOH VCC/2 tSK(O) GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Output Duty Cycle (DC) Output-to-Output Skew tSK(O) t tN tN+1 JIt(CC) = |tN-tN+1| t0 t JIt(P) = |tN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Cycle-to-Cycle Jitter Period Jitter CLK VCC=3.3V Ext_FB 2.4 0.55 tJIt(IO) = |t0-t1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles tF tR VCC=2.5V 1.8V 0.6V I/O (Phase) Jitter Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 23 24 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Chapter Two Clock Generator Data Sheets Clock Generator Device Index Device Number Page Device Number Page MC88915T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MC88LV915T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 MC88LV926 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 MPC9315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 MPC9330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 MPC9331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 MPC9350 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 MPC9351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 MPC93H51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 MPC93R51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 MPC9352 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 MPC93H52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 MPC93R52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 MPC9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 MPC9772 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 MPC9773 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 MPC97H73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 MPC9774 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 MPC97H74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 MPC992 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 MPC9992 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 25 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC88915T Rev 6, 08/2004 Low Skew CMOS PLL Clock Drivers, 3-State 55, 70, 100, 133, and 160 MHz Versions The MC88915T Clock Driver utilizes phase-locked loop (PLL) technology to lock its low skew outputs frequencies and phase onto an input reference clock. It is designed to provide clock distribution for high performance PCs and workstations. For a 3.3 V version, see the MC88LV915T data sheet. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components LOW SKEW CMOS on a board. The PLL also allows the MC88915T to multiply a low frequency PLL CLOCK DRIVER input clock and distribute it locally at a higher (2X) system frequency. Multiple 88915s can lock onto a single reference clock, ideal for applications when a central system clock must be distributed synchronously to multiple boards (see Figure 9). Five "Q" outputs (Q0-Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180 phase shift) from the "Q" outputs. The 2X_Q output runs at twice the "Q" output frequency, while the Q/2 runs at 1/2 the "Q" frequency. The VCO is designed to run optimally between 20 MHz and the 2X_Q fmax FN SUFFIX 28-LEAD PLCC PACKAGE specification. The wiring diagrams in Figure 7 detail the different feedback CASE 776-02 configurations, creating specific input/output frequency relationships. Possible frequency ratios of the "Q" outputs to the SYNC input are 2:1, 1:1, and 1:2. The FREQ_SEL pin provides one bit programmable divide-by in the feedback path of the PLL. It selects between divide-by-1 and divide-by-2 of the VCO before its signal reaches the internal clock distribution section of the chip (see Figure 2. MC88915T Block Diagram (All Versions)). In most applications FREQ_SEL should be held high (/1). If a low frequency reference clock input is used, holding FREQ_SEL low (/2) allows the VCO to run in its optimal range (>20 MHz and >40 MHz for the TFN133 version). In normal phase-locked operation the PLL_EN pi is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88915 in a static "test mode." In this mode, there is no frequency limitation on the input clock, necessary for a low frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board-level testing (see APPLICATIONS INFORMATION FOR ALL VERSIONS). Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0-Q4, Q5, and Q/2 into a high impedance state (3-state). After the OE/RST pin goes back high Q0-Q4, Q5, and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse. A lock indicator output (LOCK) will go high when the loop is in steady-state phase and frequency lock. The LOCK output will go low if phase-lock is lost, or when the PLL_EN pin is low. The LOCK output will go high no later than 10 ms after the 88915 sees a SYNC signal and full 5.0 V VCC. Features * Five outputs (Q0-Q4) with output-output skew < 500 ps, each being phase and frequency locked to the SYNC input * The phase variation from part-to-part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, defining the part-to-part skew). * Input/output phase-locked frequency ratios of 1:2, 1:1, and 2:1 are available * Input frequency range from 5 MHz - 2X_Q fmax specification (10 MHz - 2X_Q fmax for the TFN133 version) * Additional outputs available at 2X and +2 the system "Q" frequency. Also, a Q (180 phase shift) output available * All outputs have 36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are TTL-level compatible. 88 mA IOL/IOH specifications guarantee 50 transmission line switching on the incident edge. * Test mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. All outputs can go into high impedance (3-state) for board test purposes. * Lock indicator (LOCK) accuracy indicates a phase-locked state MC88915TFN55 MC88915TFN70 MC88915TFN100 MC88915TFN133 MC88915TFN160 Yield Surface Modeling and YSM are trademarks of Motorola, Inc. 26 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88915T OE/RST VCC Q5 GND Q4 VCC 2X_Q 4 FEEDBACK REF_SEL SYNC[0] VCC(AN) RC1 GND(AN) SYNC[1] 5 6 7 8 9 10 11 12 13 14 15 16 17 18 3 2 1 28 27 26 25 24 23 22 21 20 19 Q/2 GND Q3 VCC Q2 GND LOCK FREQ_SEL GND Q0 VCC Q1 GND PLL_EN Figure 1. Pinout: 28-Lead PLCC (Top View) Table 1. Pin Summary Pin Name SYNC[0] SYNC[1] REF_SEL FREQ_SEL FEEDBACK RC1 Q(0-4) Q5 2x_Q Q/2 LOCK OE/RST PLL_EN VCC, GND Number 1 1 1 1 1 1 5 1 1 1 1 1 1 11 I/O Input Input Input Input Input Input Output Output Output Output Output Input Input Reference clock input Reference clock input Chooses reference between SYNC[0] and SYNC[1] Doubles VCO internal frequency (low) Feedback input to phase detector Input for external RC network Clock output (locked to SYNC) Inverse of clock output 2 x clock output (Q) frequency (synchronous) Clock output (Q) frequency / 2 (synchronous) Indicates phase lock has been achieved (high when locked) Output enable/asynchronous reset (active low) Disables phase-lock for low frequency testing Power and ground pins (note pins 8 and 10 are "analog" supply pins for internal PLL only) Function FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 27 MC88915T LOCK FEEDBACK SYNC (0) 0 SYNC (1) REF_SEL 1 M U X PHASE/FREQ DETECTOR CHARGE PUMP/LOOP FILTER VOLTAGE CONTROLLED OSCILLATOR EXTERNAL REC NETWORK (RC1 PIN) PLL_EN 0 MUX 1 2x_Q (/1) D 1 M U X CP R Q Q Q0 (/2) DIVIDE BY TWO 0 D CP R Q Q1 FREQ_SEL OE/RST D CP R Q Q2 D CP R Q Q3 D CP R Q Q4 D CP R Q Q5 D CP R Q Q/2 Figure 2. MC88915T Block Diagram (All Versions) 28 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88915T MC88915TFN55 AND MC88915TFN70 Table 2. SYNC Input Timing Requirements Symbol tRISE/FALL, SYNC Inputs tCYCLE, SYNC Inputs Parameter Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V Input Clock Period SYNC Inputs Minimum TFN70 -- 28.5 1 TFN55 -- 36.0 1 Maximum 3.0 200 2 Unit ns ns Duty Cycle SYNC Inputs Input Duty Cycle SYNC Inputs 50% 25% 1. These tCYCLE minimum values are valid when "Q" output is fed back and connected to the FEEDBACK pin. This is the configuration shown in Figure 7b. 2. Information in Table 22 and in Note 3 of the AC specification notes describe this specification with its limits depending on what output is fed back, and if FREQ_SEL is high or low. Table 3. DC Electrical Characteristics (Voltages Referenced to GND) TA = -40C to +85C for 55 MHz Version; TA = 0C to +70C for 70 MHz Version; VCC = 5.0 V 5% Symbol VIH VIL VOH VOL Iin ICCT IOLD IOHD ICC IOZ Maximum Quiescent Supply Current (per Package) Maximum 3-State Leakage Current Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Test Conditions Vout = 0.1 V or VCC - 0.1 V Vout = 0.1 V or VCC - 0.1 V Vin = VIH or VIL IOH = -36 mA1 Maximum Low-Level Output Voltage Vin = VIH or VIL IOH = 36 mA1 Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current VI = VCC or GND VI = VCC - 2.1 V VOLD = 1.0 V Maximum VOHD = 3.85 V Minimum VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VCC V 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 5.25 5.25 5.25 5.25 5.25 5.25 Target Limit 2.0 2.0 0.8 0.8 4.01 4.51 0.44 0.44 1.0 2.0 88 -88 1.0 50 2 Unit V V V V A mA mA mA mA A 1. Maximum test duration is 2.0 ms, one output loaded at a time. 2. Specification value for IOZ is preliminary, will be finalized upon "MC" status. Table 4. Capacitance and Power Specifications Symbol CIN CPD PD1 1 Parameter Input Capacitance Power Dissipation Capacitance Power Dissipation @ 50 MHz with 50 Thevenin Termination Power Dissipation @ 50 MHz with 50 Parallel Termination to GND Typical Values 4.5 40 23 mW/Output 184 mW/Device 57 mW/Output 456 mW/Device Unit pF pF mW mW Conditions VCC = 5.0 V VCC = 5.0 V VCC = 5.0 V T = 25C VCC = 5.0 V T = 25C PD21 1. PD1 nd PD2 mW/Output numbers are for a "Q" output. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 29 MC88915T MC88915TFN55 AND MC88915TFN70 (Continued) Table 5. Frequency Specifications (TA = -40C to +85 C, VCC = 5.0 V 5%) Symbol fmax1 Parameter Maximum Operating Frequency (2X_Q Output) Maximum Operating Frequency (Q0-Q4, Q5 Output) Guaranteed Minimum TFN70 70 35 TFN55 55 27.5 Unit MHz MHz 1. Maximum Operating Frequency is guaranteed with the part in a phase-locked condition, and all outputs loaded with 50 terminated to VCC/2. Table 6. AC Characteristics (TA = -40C to +85C, VCC = 5.0 V 5%, Load = 50 Terminated to VCC/2) Symbol tRISE/FALL Outputs tRISE/FALL1 2X_Q Output Parameter Rise/Fall Time, All Outputs (Between 0.2 VCC and 0.8 VCC) Rise/Fall Time into a 20 pF Load, with Termination Specified in Note2 0.5 tCYCLE - 0.52 0.5 tCYCLE + 0.52 2 2 66 MHz 0.5 t CYCLE - 0.5 0.5 tCYCLE + 0.5 50 MHz 0.5 tCYCLE - 1.0 0.5 tCYCLE + 1.0 40 MHz 0.5 tCYCLE - 1.5 0.5 tCYCLE + 1.5 2 2 50 - 65 MHz 0.5 t CYCLE - 1.0 0.5 tCYCLE + 1.0 40 - 49 MHz 0.5 tCYCLE - 1.5 0.5 tCYCLE + 1.5 66 - 70 MHz 0.5 tCYCLE - 0.5 0.5 tCYCLE + 0.5 Min 1.0 0.5 Max 2.5 1.6 Unit ns ns ns ns Condition Into a 50 Load Terminated to VCC/2 tRISE: 0.8 V - 2.0 V tFALL: 2.0 V - 0.8 V Into a 50 Load Terminated to VCC/2 Must Use Termination Specified in Note2 Output Pulse Width: Q0, Q1, Q2, Q4, Q4, tPULSEWIDTH1 (Q0-Q4, Q5, Q/2) Q5, Q/2 @ VCC/2 tPULSEWIDTH1 (2X_Q Output) tPULSEWIDTH1 (2X_Q Output) tPD1,3 SYNC Feedback Output Pulse Width: 2X_Q @ 1.5 V Output Pulse Width: 2X_Q @ VCC/2 SYNC Input to Feedback Delay (Measured at SYNC0 or 1 and FEEDBACK Input Pins) ns Into a 50 Load Terminated to VCC/2 See Note4 and Figure 4 for Detailed Explanation (With 1 M from RC1 to An VCC) -1.05 +1.25 -0.40 +3.25 500 (With 1 M from RC1 to An GND) ns tSKEWr 1,4 (Rising)5 tSKEWf1,4 (Falling) tSKEWall1,4 Output-to-Output Skew Between Outputs Q0-Q4, Q/2 (Rising Edges Only) Output-to-Output Skew Between Outputs Q0-Q4 (Falling Edges Only) Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Q5 Falling Time Required to Acquire Phase-Lock from Time SYNC Input Signal is Received Output Enable Time OE/RST to 2X_Q, Q0-Q4, Q5, and Q/2 Output Disable Time OE/RST to 2X_Q, Q0-Q4, Q5, and Q/2 -- ps All Outputs into a Matched 50 Load Terminated to VCC/2 All Outputs into a Matched 50 Load Terminated to VCC/2 All Outputs into a Matched 50 Load Terminated to VCC/2 Also Time to LOCK Indicator High Measured with the PLL_EN Pin Low Measured with the PLL_EN Pin Low -- 500 ps -- 750 ps tLOCK5 tPZL6 tPHZ, tPLZ6 1. 2. 3. 4. 5. 1.0 3.0 3.0 10 14 14 ms ns ns These specifications are not tested. They are guaranteed by statistical characterization. See AC specification Note 1. tCYCLE in this spec is 1/Frequency at which the particular output is running. The tPD specification's min/max values may shift closer to zero if a larger pullup resistor is used. Under equally loaded conditions and at a fixed temperature and voltage. With VCC fully powered on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 F, tLOCK minimum is with C1 = 0.01 F. 6. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates. The final guaranteed values will be available when "MC" status is reached. 30 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88915T MC88915TFN100 Table 7. SYNC Input Timing Requirements Symbol tRISE/FALL, SYNC Inputs tCYCLE, SYNC Inputs Duty Cycle SYNC Inputs Parameter Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V Input Clock Period SYNC Inputs Input Duty Cycle SYNC Inputs Minimum -- 20.0 1 Maximum 3.0 200 2 Unit ns ns 50% 25% 1. These tCYCLE minimum values are valid when "Q" output is fed back and connected to the FEEDBACK pin. This is the configuration shown in Figure 7b. 2. Information in Table 22 and in Note 3 of the AC specification notes describe this specification with its limits depending on what output is fed back, and if FREQ_SEL is high or low. Table 8. DC Electrical Characteristics (Voltages Referenced to GND) TA = -40C to +85C, VCC = 5.0 V 5% Symbol VIH VIL VOH VOL Iin ICCT IOLD IOHD ICC IOZ 1. 2. 3. 4. Maximum Quiescent Supply Current (per Package) Maximum 3-State Leakage Current Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current 3 Test Conditions Vout = 0.1 V or VCC - 0.1 V Vout = 0.1 V or VCC - 0.1 V Vin = VIH or VIL IOH = -36 mA1 1 VCC V 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 5.25 5.25 5.25 5.25 5.25 5.25 Target Limit 2.0 2.0 0.8 0.8 4.01 4.51 0.44 0.44 1.0 2.0 2 Unit V V V V A mA mA mA mA A Vin = VIH or VIL IOH = 36 mA VI = VCC or GND VI = VCC -2.1 V VOLD = 1.0 V Maximum VOHD = 3.85 V Minimum VI = VCC or GND VI = VIH or VIL; VO = VCC or GND 88 -88 1.0 504 IOL and IOH are 12 mA and -12 mA respectively for the LOCK output. The PLL_EN input pin is not guaranteed to meet this specification. Maximum test duration is 2.0 ms, one output loaded at a time. Specification value for IOZ is preliminary, will be finalized upon "MC" status. Table 9. Capacitance and Power Specifications Symbol CIN CPD PD1 1 Parameter Input Capacitance Power Dissipation Capacitance Power Dissipation @ 50 MHz with 50 Thevenin Termination Power Dissipation @ 50 MHz with 50 Parallel Termination to GND Typical Values 4.5 40 23 mW/Output 184 mW/Device 57 mW/Output 456 mW/Device Unit pF pF mW mW Conditions VCC = 5.0 V VCC = 5.0 V VCC = 5.0 V T = 25C VCC = 5.0 V T = 25C PD21 1. PD1 nd PD2 mW/Output numbers are for a "Q" output. Table 10. Frequency Specifications (TA = -40C to +85 C, VCC = 5.0 V 5%) Symbol fmax1 Parameter Maximum Operating Frequency (2X_Q Output) Maximum Operating Frequency (Q0-Q4, Q5 Output) Guaranteed Minimum TFN100 100 50 Unit MHz MHz 1. Maximum Operating Frequency is guaranteed with the part in a phase-locked condition, and all outputs loaded with 50 terminated to VCC/2. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 31 MC88915T MC88915TFN100 (Continued) Table 11. AC Characteristics (TA = -40C to +85C, VCC = 5.0 V 5%, Load = 50 Terminated to VCC/2) Symbol tRISE/FALL Outputs tRISE/FALL1 2X_Q Output Parameter Rise/Fall Time, All Outputs (Between 0.2 VCC and 0.8 VCC) Rise/Fall Time into a 20 pF Load, with Termination Specified in Note2 0.5 tCYCLE - 0.52 0.5 tCYCLE + 0.52 0.5 tCYCLE - 0.52 0.5 tCYCLE + 0.52 2 2 40 - 49 MHz 0.5 t CYCLE - 1.5 0.5 tCYCLE + 1.5 50 - 65 MHz 0.5 tCYCLE - 1.0 0.5 tCYCLE + 1.0 66 - 100 MHz 0.5 tCYCLE - 0.5 0.5 tCYCLE + 0.5 Min 1.0 0.5 Max 2.5 1.6 Unit ns ns ns ns ns Condition Into a 50 Load Terminated to VCC/2 tRISE: 0.8 V - 2.0 V tFALL: 2.0 V - 0.8 V Into a 50 Load Terminated to VCC/2 Must Use Termination Specified in Note2 Into a 50 Load Terminated to VCC/2 Output Pulse Width: Q0, Q1, Q2, Q4, Q4, tPULSEWIDTH1 (Q0-Q4, Q5, Q/2) Q5, Q/2 @ VCC/2 tPULSEWIDTH1 (2X_Q Output) tPULSEWIDTH1 (2X_Q Output) tPD1,3 SYNC Feedback Output Pulse Width: 2X_Q @ 1.5 V Output Pulse Width: 2X_Q @ VCC/2 SYNC Input to Feedback Delay (Measured at SYNC0 or 1 and FEEDBACK Input Pins) (With 1 M from RC1 to An VCC) -1.05 +1.25 -0.30 +3.25 500 (With 1 M from RC1 to An GND) ns See Note4 and Figure 4 for Detailed Explanation tSKEWr 1,4 5 (Rising) Output-to-Output Skew Between Outputs Q0-Q4, Q/2 (Rising Edges Only) Output-to-Output Skew Between Outputs Q0-Q4 (Falling Edges Only) Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Q5 Falling Time Required to Acquire Phase-Lock from Time SYNC Input Signal is Received Output Enable Time OE/RST to 2X_Q, Q0-Q4, Q5, and Q/2 Output Disable Time OE/RST to 2X_Q, Q0-Q4, Q5, and Q/2 -- ps All Outputs into a Matched 50 Load Terminated to VCC/2 All Outputs into a Matched 50 Load Terminated to VCC/2 All Outputs into a Matched 50 Load Terminated to VCC/2 Also Time to LOCK Indicator High Measured with the PLL_EN Pin Low Measured with the PLL_EN Pin Low tSKEWf1,4 (Falling) tSKEWall1,4 -- 500 ps -- 750 ps tLOCK5 tPZL6 tPHZ, tPLZ6 1. 2. 3. 4. 5. 1.0 3.0 3.0 10 14 14 ms ns ns These specifications are not tested. They are guaranteed by statistical characterization. See AC specification Note 1. tCYCLE in this spec is 1/Frequency at which the particular output is running. The tPD specification's min/max values may shift closer to zero if a larger pullup resistor is used. Under equally loaded conditions and at a fixed temperature and voltage. With VCC fully powered on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 F, tLOCK minimum is with C1 = 0.01 F. 6. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates. The final guaranteed values will be available when "MC" status is reached. 32 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88915T MC88915TFN133 Table 12. SYNC Input Timing Requirements Symbol tRISE/FALL, SYNC Inputs tCYCLE, SYNC Inputs Duty Cycle SYNC Inputs Parameter Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V Input Clock Period SYNC Inputs Input Duty Cycle SYNC Inputs Minimum -- 15.01 50% 25% Maximum 3.0 1002 Unit ns ns 1. These tCYCLE minimum values are valid when "Q" output is fed back and connected to the FEEDBACK pin. This is the configuration shown in Figure 7b. 2. Information in Table 22 and in Note 3 of the AC specification notes describe this specification with its limits depending on what output is fed back, and if FREQ_SEL is high or low. Table 13. DC Electrical Characteristics (Voltages Referenced to GND) TA = -40C to +85C, VCC = 5.0 V 5% Symbol VIH VIL VOH VOL Iin ICCT IOLD IOHD ICC IOZ 1. 2. 3. 4. Maximum Quiescent Supply Current (per Package) Maximum 3-State Leakage Current Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current3 Test Conditions Vout = 0.1 V or VCC - 0.1 V Vout = 0.1 V or VCC - 0.1 V Vin = VIH or VIL IOH = -36 mA1 Vin = VIH or VIL IOH = 36 mA1 VI = VCC or GND VI = VCC -2.1 V VOLD = 1.0 V Maximum VOHD = 3.85 V Minimum VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VCC V 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 5.25 5.25 5.25 5.25 5.25 5.25 Target Limit 2.0 2.0 0.8 0.8 4.01 4.51 0.44 0.44 1.0 2.02 88 -88 1.0 504 Unit V V V V A mA mA mA mA A IOL and IOH are 12 mA and -12 mA respectively for the LOCK output. The PLL_EN input pin is not guaranteed to meet this specification. Maximum test duration is 2.0 ms, one output loaded at a time. Specification value for IOZ is preliminary, will be finalized upon "MC" status. Table 14. Capacitance and Power Specifications Symbol CIN CPD PD11 PD21 Input Capacitance Power Dissipation Capacitance Power Dissipation @ 50 MHz with 50 Thevenin Termination Power Dissipation @ 50 MHz with 50 Parallel Termination to GND Parameter Typical Values 4.5 40 23 mW/Output 184 mW/Device 57 mW/Output 456 mW/Device Unit pF pF mW mW Conditions VCC = 5.0 V VCC = 5.0 V VCC = 5.0 V T = 25C VCC = 5.0 V T = 25C 1. PD1 nd PD2 mW/Output numbers are for a "Q" output. Table 15. Frequency Specifications (TA = -40C to +85 C, VCC = 5.0 V 5%) Symbol fmax1 Parameter Maximum Operating Frequency (2X_Q Output) Maximum Operating Frequency (Q0-Q4, Q5 Output) Guaranteed Minimum TFN133 133 66 Unit MHz MHz 1. Maximum Operating Frequency is guaranteed with the part in a phase-locked condition, and all outputs loaded with 50 terminated to VCC/2. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 33 MC88915T MC88915TFN133 (Continued) Table 16. AC Characteristics (TA = -40C to +85C, VCC = 5.0 V 5%, Load = 50 Terminated to VCC/2) Symbol tRISE/FALL Outputs tRISE/FALL1 2X_Q Output Parameter Rise/Fall Time, All Outputs (Between 0.2 VCC and 0.8 VCC) Rise/Fall Time into a 20 pF Load, with Termination Specified in Note2 0.5 tCYCLE - 0.52 0.5 tCYCLE + 0.52 ns ns Min 1.0 0.5 Max 2.5 1.6 Unit ns ns Condition Into a 50 Load Terminated to VCC/2 tRISE: 0.8 V - 2.0 V tFALL: 2.0 V - 0.8 V Into a 50 Load Terminated to VCC/2 Must Use Termination Specified in Note2 ns Into a 50 Load Terminated to VCC/2 See Note4 and Figure 4 for Detailed Explanation Output Pulse Width: Q0, Q1, Q2, Q4, Q4, tPULSEWIDTH1 (Q0-Q4, Q5, Q/2) Q5, Q/2 @ VCC/2 tPULSEWIDTH1 (2X_Q Output) tPULSEWIDTH1 (2X_Q Output) tPD1,3 SYNC Feedback Output Pulse Width: 2X_Q @ 1.5 V Output Pulse Width: 2X_Q @ VCC/2 SYNC Input to Feedback Delay (Measured at SYNC0 or 1 and FEEDBACK Input Pins) 2 2 66 - 133 MHz 0.5 t CYCLE - 0.5 0.5 tCYCLE + 0.5 40 - 65 MHz 0.5 tCYCLE - 0.9 0.5 tCYCLE + 0.9 2 2 66 - 133 MHz 0.5 t CYCLE - 0.5 0.5 tCYCLE + 0.5 40 - 65 MHz 0.5 tCYCLE - 0.9 0.5 tCYCLE + 0.9 (With 1 M from RC1 to An VCC) -1.05 +1.25 -0.25 +3.25 500 (With 1 M from RC1 to An GND) ns tSKEWr 1,4 5 (Rising) Output-to-Output Skew Between Outputs Q0-Q4, Q/2 (Rising Edges Only) Output-to-Output Skew Between Outputs Q0-Q4 (Falling Edges Only) Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Q5 Falling Time Required to Acquire Phase-Lock from Time SYNC Input Signal is Received Output Enable Time OE/RST to 2X_Q, Q0-Q4, Q5, and Q/2 Output Disable Time OE/RST to 2X_Q, Q0-Q4, Q5, and Q/2 -- ps All Outputs into a Matched 50 Load Terminated to VCC/2 All Outputs into a Matched 50 Load Terminated to VCC/2 All Outputs into a Matched 50 Load Terminated to VCC/2 Also Time to LOCK Indicator High Measured with the PLL_EN Pin Low Measured with the PLL_EN Pin Low tSKEWf1,4 (Falling) tSKEWall1,4 -- 500 ps -- 750 ps tLOCK5 tPZL6 tPHZ, tPLZ6 1. 2. 3. 4. 5. 1.0 3.0 3.0 10 14 14 ms ns ns These specifications are not tested. They are guaranteed by statistical characterization. See AC specification Note 1. tCYCLE in this spec is 1/Frequency at which the particular output is running. The tPD specification's min/max values may shift closer to zero if a larger pullup resistor is used. Under equally loaded conditions and at a fixed temperature and voltage. With VCC fully powered on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 F, tLOCK minimum is with C1 = 0.01 F. 6. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates. The final guaranteed values will be available when "MC" status is reached. 34 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88915T MC88915TFN160 Table 17. SYNC Input Timing Requirements Symbol tRISE/FALL, SYNC Inputs tCYCLE, SYNC Inputs Duty Cycle SYNC Inputs Parameter Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V Input Clock Period SYNC Inputs Input Duty Cycle SYNC Inputs Minimum -- 12.5 1 Maximum 3.0 100 2 Unit ns ns 50% 25% 1. These tCYCLE minimum values are valid when "Q" output is fed back and connected to the FEEDBACK pin. This is the configuration shown in Figure 7b. 2. Information in Table 22 and in Note 3 of the AC specification notes describe this specification with its limits depending on what output is fed back, and if FREQ_SEL is high or low. Table 18. DC Electrical Characteristics (Voltages Referenced to GND) TA = 0C to +70C, VCC = 5.0 V 5% Symbol VIH VIL VOH VOL Iin ICCT IOLD IOHD ICC IOZ 1. 2. 3. 4. Maximum Quiescent Supply Current (per Package) Maximum 3-State Leakage Current Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current 3 Test Conditions Vout = 0.1 V or VCC -0.1 V Vout = 0.1 V or VCC - 0.1 V Vin = VIH or VIL IOH = -36 mA1 Vin = VIH or VIL IOH = 36 mA1 VI = VCC or GND VI = VCC -2.1 V VOLD = 1.0 V Maximum VOHD = 3.85 V Minimum VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VCC V 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 5.25 5.25 5.25 5.25 5.25 5.25 Target Limit 2.0 2.0 0.8 0.8 4.01 4.51 0.44 0.44 1.0 2.02 88 -88 1.0 504 Unit V V V V A mA mA mA mA A IOL and IOH are 12 mA and -12 mA respectively for the LOCK output. The PLL_EN input pin is not guaranteed to meet this specification. Maximum test duration is 2.0 ms, one output loaded at a time. Specification value for IOZ is preliminary, will be finalized upon "MC" status. Table 19. Capacitance and Power Specifications Symbol CIN CPD PD1 1 Parameter Input Capacitance Power Dissipation Capacitance Power Dissipation @ 50 MHz with 50 Thevenin Termination Power Dissipation @ 50 MHz with 50 Parallel Termination to GND Typical Values 4.5 40 15 mW/Output 120 mW/Device 57 mW/Output 456 mW/Device Unit pF pF mW mW Conditions VCC = 5.0 V VCC = 5.0 V VCC = 5.0 V T = 25C VCC = 5.0 V T = 25C PD21 1. PD1 nd PD2 mW/Output numbers are for a "Q" output. Table 20. Frequency Specifications (TA = 0C to +70C, VCC = 5.0 V 5%) Symbol fmax1 Parameter Maximum Operating Frequency (2X_Q Output) Maximum Operating Frequency (Q0-Q4, Q5 Output) Guaranteed Minimum TFN160 160 80 Unit MHz MHz 1. Maximum Operating Frequency is guaranteed with the part in a phase-locked condition, and all outputs loaded with 50 terminated to VCC/2. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 35 MC88915T MC88915TFN160 (Continued) Table 21. AC Characteristics (TA = 0C to +70C, VCC = 5.0 V 5%, Load = 50 Terminated to VCC/2) Symbol tRISE/FALL Outputs tRISE/FALL 2X_Q Output Parameter Rise/Fall Time, All Outputs (Between 0.2 VCC and 0.8 VCC) Rise/Fall Time Min 1.0 0.5 Max 2.5 1.6 Unit ns ns ns ns Condition Into a 50 Load Terminated to VCC/2 tRISE: 0.8 V - 2.0 V tFALL: 2.0 V - 0.8 V Into a 50 Load Terminated to VCC/2 tPULSEWIDTH Output Pulse Width: Q0, Q1, Q2, Q4, Q4, (Q0-Q4, Q5, Q/2) Q5, Q/2 @ VCC/2 tPULSEWIDTH (2X_Q Output) Output Pulse Width: 2X_Q @ 1.5 V 0.5 tCYCLE - 0.52 0.5 tCYCLE + 0.52 0.5 tCYCLE + 0.7 0.5 tCYCLE + 0.5 0.5 tCYCLE + 0.5 TBD 80 MHz 0.5 tCYCLE - 0.7 100 MHz 0.5 tCYCLE - 0.5 133 MHz 0.5 tCYCLE - 0.5 TBD 160 MHz tPD1 SYNC Feedback SYNC Input to Feedback Delay (Measured at SYNC0 or 1 and FEEDBACK Input Pins) 133 MHz 160 MHz ns (With 1 M from RC1 to An VCC) -1.05 -0.9 -0.25 -0.10 tCYCLE + 300 ps tCYCLE + 300 ps 500 ps See Note2 and Figure 4 for Detailed Explanation tCYCLE (2x_Q Output) tSKEWr3 (Rising)4 tSKEWf3 (Falling) tSKEWall3 Cycle-to-Cycle Variation 133 MHz tCYCLE - 300 ps 160 MHz tCYCLE - 300 ps -- Output-to-Output Skew Between Outputs Q0-Q4, Q/2 (Rising Edges Only) Output-to-Output Skew Between Outputs Q0-Q4 (Falling Edges Only) Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Q5 Falling Time Required to Acquire Phase-Lock from Time SYNC Input Signal is Received Output Enable Time OE/RST to 2X_Q, Q0-Q4, Q5, and Q/2 Output Disable Time OE/RST to 2X_Q, Q0-Q4, Q5, and Q/2 All Outputs into a Matched 50 Load Terminated to VCC/2 All Outputs into a Matched 50 Load Terminated to VCC/2 All Outputs into a Matched 50 Load Terminated to VCC/2 Also Time to LOCK Indicator High Measured with the PLL_EN Pin Low Measured with the PLL_EN Pin Low -- 500 ps -- 750 ps tLOCK4 tPZL5 tPHZ, tPLZ5 1. 2. 3. 4. 1.0 3.0 3.0 10 14 14 ms ns ns TCYCLE in this spec is 1/Frequency at which the particular output is running. The TPD specification's min/max values may shift closer to zero if a larger pullup resistor is used. Under equally loaded conditions and at a fixed temperature and voltage. With VCC fully powered on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 F, tLOCK minimum is with C1 = 0.01 F. 5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when "MC" status is reached. 36 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88915T APPLICATIONS INFORMATION FOR ALL VERSIONS General AC Specification Notes 1. Several specifications can only be measured when the MC88915TFN55, 70 and 100 are in phase-locked operation. It is not possible to have the part in phase-lock on automated test equipment (ATE). Statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88915TFN55, 70 and 100 units were fabricated with key transistor properties intentionally varied to create a 14-cell designed experimental matrix. IC performance was characterized over a range of transistor properties (represented by the 14 cells) in excess of the expected process variation of the wafer fabrication area, to set performance limits of ATE testable specifications within those to be guaranteed by statistical characterization. In this way, all units passing the ATE test will meet or exceed the non-tested specifications limits. 2. These two specs (tRISE/FALL and tPULSE Width 2X_Q output) guarantee the MC88915T meets the 40 MHz and 33 MHz MC68040 P-Clock input specification (at 80 MHz and 66 MHz, respectively). For these two specs to be guaranteed by Freescale Semiconductor, the termination scheme shown below in Figure 3 must be used. The wiring diagrams and explanations in Figure 7 demonstrate the input and output frequency relationships for three possible feedback configurations. The allowable SYNC input range for each case is also indicated. There are two allowable SYNC frequency ranges, depending whether FREQ_SEL is high or low. Although not shown, it is possible to feed back the Q5 output, thus creating a 180 phase shift between the SYNC input and the "Q" outputs. Table 22 below summarizes the allowable SYNC frequency range for each possible configuration. 3. 88915 2X_Q OUTPUT RS RS = ZO - 7 ZO (CLOCK TRACE) 68040 P-CLOCK INPUT RP RP = 1.5 ZO Figure 3. MC68040 P-Clock Input Termination Scheme Table 22. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations FREQ_SEL Level HIGH HIGH HIGH HIGH LOW LOW LOW LOW Feedback Output Q/2 Any "Q" (Q0-Q4) Q5 2X_Q Q/2 Any "Q" (Q0-Q4) Q5 2X_Q Allowable SYNC Input Frequency Range (MHz) 5 to (2X_Q FMAX Spec)/4 10 to (2X_Q FMAX Spec)/2 10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAX Spec) 2.5 to (2X_Q FMAX Spec)/8 5 to (2X_Q FMAX Spec)/4 5 to (2X_Q FMAX Spec)/4 10 to (2X_Q FMAX Spec)/2 Corresponding VCO Frequency Range 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) Phase Relationships of the "Q" Outputs to Rising SYNC Edge 0 0 180 0 0 0 180 0 4. A 1 M resistor tied to either Analog VCC or Analog GND, depicted in Figure 4, is required to ensure no jitter is present on the MC88915T outputs. This technique causes a phase offset between the SYNC input and the output connected to the FEEDBACK input, measured at the input pins. The tPD spec describes how this offset varies with process, temperature, and voltage. The specs were determined by measuring the phase relationship for the 14 lots described in Note 1 while the part was in phase-locked operation. The actual measurements were made with a 10 MHz SYNC input (1.0 ns edge rate from 0.8 V - 2.0 V) with the Q/2 output fed back. The phase measurements were made at 1.5 V. The Q/2 output was terminated at the FEEDBACK input with 100 to VCC and 100 to ground. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 37 MC88915T RC1 EXTERNAL LOOP FILTER 330 ANALOG VCC RC1 R2 1 M REFERENCE RESISTOR 1 M REFERENCE RESISTOR 330 R2 0.1 F C1 0.1 F C1 ANALOG GND ANALOG GND With the 1.0 M resistor tied in this fashion, the tPD specification measured at the input pins is: tPD = 2.25 ns 1.0 ns SYNC INPUT 2.25 ns OFFSET FEEDBACK OUTPUT 3.0 V With the 1.0 M resistor tied in this fashion, the tPD specification measured at the input pins is: tPD = -0.775 ns 0.275 ns SYNC INPUT -0.775 ns OFFSET 5.0 V 3.0 V 5.0 V FEEDBACK OUTPUT Figure 4. Depiction of the Fixed SYNC to Feedback Offset (tPD) Which is Present When a 1 m Resistor is Tied to VCC or Ground 5. The tSKEWr specification guarantees the rising edges of outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall within a 500 ps window within one part. However, if the relative position of each output within this window is not specified, the 500 ps window must be added to each side of the tPD specification limits to calculate the total part-to-part skew. For this reason, the absolute distribution of these outputs are provided in Table 23. When taking the skew data, Q0 was used as a reference, so all measurements are relative to this output. The information in Table 23 is derived from measurements taken from the 14 process lots described in Note 1, over the temperature and voltage range. clock with equal delay of input signal to each part. This skew value is valid at the 88915 output pins only (equally loaded), it does not include PCB trace delays due to varying loads. With a 1.0 M resistor tied to analog VCC as shown in Note 4, the tPD spec. limits between SYNC and the Q/2 output (connected to the FEEDBACK pin) are -1.05 ns and -0.5 ns. To calculate the skew of any given output between two or more parts, the absolute value of the distribution of the output given in Table 23 must be subtracted and added to the lower and upper tPD spec limits respectively. For output Q2, [276 - (-44)] = 320 ps is the absolute value of the distribution. Therefore, [-1.05 ns - 0.32 ns] = -1.37 ns is the lower tPD limit, and [-0.5 ns + 0.32 ns] = -0.18 ns is the upper limit. Therefore, the worst case skew of output Q2 between any number of parts is |(-1.37) - (-0.18)| = 1.19 ns. Q2 has the worst case skew distribution of any output, so 1.2 ns is the absolute worst case output-to-output skew between multiple parts. Note 4 explains the tPD specification was measured and is guaranteed for the configuration of the Q/2 output connected to the FEEDBACK pin and the SYNC input running at 10 MHz. The fixed offset (tPD) as described above has some dependence on the input frequency and at what frequency the VCO is running. The graphs of Figure 5 demonstrate this dependence. The data presented in Figure 5 is from devices representing process extremes, and the measurements were also taken at the voltage extremes (VCC = 5.25 V and 4.75 V). Therefore, the data in Figure 5 is a realistic representation of the variation of tPD. Table 23. Relative Positions of Outputs Q/2, Q0-Q4, 2X_Q Within the 500 ps tSKEWr Spec Window Output Q0 Q1 Q2 Q3 Q4 Q/2 2X_Q - (ps) 0 -72 -44 -40 -274 -16 -633 + (ps) 0 40 276 255 -34 250 -35 7. 6. Calculation of Total Output-to-Skew Between Multiple Parts (Part-to-Part Skew) By combining the tPD specification and the information in Note 5, the worst case output-to-output skew between multiple 88915s connected in parallel can be calculated. This calculation assumes all parts have a common SYNC input 38 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88915T -0.50 tPD SYNC TO FEEDBACK (ns) -0.75 tPD SYNC TO FEEDBACK (ns) -0.5 -1.0 -1.00 -1.25 -1.5 -1.50 2.5 5.0 7.5 10.0 12.5 15.0 SYNC INPUT FREQUENCY (MHz) Figure 5a 17.5 -2.0 2.5 5.0 7.5 12.5 17.5 27.5 25.0 10.0 15.0 20.0 22.5 SYNC INPUT FREQUENCY (MHz) Figure 5b tPD versus Frequency Variation for Q/2 Output Fed Back, Including Process and Voltage Variation @ 25C (with 1.0 M Resistor Tied to Analog VCC) tPD versus Frequency Variation for Q4 Output Fed Back, Including Process and Voltage Variation @ 25C (with 1.0 M Resistor Tied to Analog VCC) 3.5 tPD SYNC TO FEEDBACK (ns) 3.0 2.5 2.0 1.5 1.0 0.5 2.5 5.0 7.5 10.0 12.5 15.0 SYNC INPUT FREQUENCY (MHz) Figure 5c tPD versus Frequency Variation for Q/2 Output Fed Back, Including Process and Voltage Variation @ 25C (with 1.0 M Resistor Tied to Analog GND) 17.5 tPD SYNC TO FEEDBACK (ns) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5 10 15 20 SYNC INPUT FREQUENCY (MHz) Figure 5d tPD versus Frequency Variation for Q4 Output Fed Back, Including Process and Voltage Variation @ 25C (with 1.0 M Resistor Tied to Analog GND) 25 Figure 5. Graphs 8. The lock indicator pin (LOCK) will reliably indicate a phase-locked condition at SYNC input frequencies down to 10 MHz. At frequencies below 10 MHz, the frequency of correction pulses going into the phase detector form the SYNC and FEEDBACK pins may not be sufficient to allow the lock indicator circuitry to accurately predict a phase-locked condition. The MC88915T is guaranteed to provide stable phase-locked operation down to the appropriate minimum input frequency given in Table 22, even though the LOCK pin may be LOW at frequencies below 10 MHz. The exact minimum frequency where the lock indicator functionality can be guaranteed will be available when the MC88915T reaches "MC" status. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 39 MC88915T SYNC INPUT (SYNC[1] OR SYNC[0]) tCYCLE SYNC INPUT tPD FEEDBACK INPUT Q/2 OUTPUT tSKEWALL tSKEWf Q0-Q4 OUTPUTS tSKEWr tSKEWf tSKEWr tCYCLE "Q" OUTPUTS Q5 OUTPUT 2X_Q OUTPUT Figure 6. Output/Input Switching Waveforms and Timing Diagrams (These waveforms represent the hook-up configuration of Figure 7a) TIMING NOTES: 1. The MC88915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows," not as a deviation around a center point. 3. If a "Q" output is connected to the FEEDBACK input (this situation is not shown), the "Q" output frequency would match the SYNC input frequency, the 2X_Q output would run at twice the SYNC frequency, and the Q/2 output would run at half the SYNC frequency. 40 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88915T 100 MHz SIGNAL 1:2 Input to "Q" Output Frequency Relationship In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2 frequency will equal the SYNC frequency. The "Q" outputs (Q0-Q4, Q5) will always run at 2X the Q/2 frequency, and the 2X_Q output will run at 4X the Q/2 frequency. 50 MHz "Q" CLOCK OUTPUTS Q2 Q1 PLL_EN HIGH NOTE: If the OE/RST input is active, a pullup or pull-down resistor isn't necessary at the FEEDBACK pin so it won't when the fed back output goes into 3-state. Allowable Input Frequency Range: 5 MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH) 2.5 MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW) 25 MHz FEEDBACK SIGNAL HIGH RST Q5 FEEDBACK LOW CRYSTAL 25 MHz INPUT OSCILLATOR EXTERNAL LOOP FILTER REF_SEL SYNC[0] ANALOG VCC RC1 ANALOG GND FQ_SEL HIGH Q0 Q4 2X_Q Q/2 Q3 MC88915T Figure 7a. Wiring Diagram and Frequency Relationships with Q/2 Output Feedback 50 MHz FEEDBACK SIGNAL HIGH RST Q5 FEEDBACK LOW CRYSTAL 50 MHz INPUT OSCILLATOR EXTERNAL LOOP FILTER REF_SEL SYNC[0] ANALOG VCC RC1 ANALOG GND FQ_SEL HIGH Q0 Q4 100 MHz SIGNAL 1:1 Input to "Q" Output Frequency Relationship In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4 frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The Q/2 output will always rn at 1/2 the "Q" frequency, and the 2X_Q output will run at 2X the "Q" frequency. Allowable Input Frequency Range: 10 MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH) 5 MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW) 2X_Q Q/2 Q3 25 MHz SIGNAL MC88915T Q2 Q1 PLL_EN HIGH 50 MHz "Q" CLOCK OUTPUTS Figure 7b. Wiring Diagram and Frequency Relationships with Q4 Output Feedback 100 MHz FEEDBACK SIGNAL HIGH RST Q5 FEEDBACK LOW CRYSTAL 100 MHz INPUT OSCILLATOR EXTERNAL LOOP FILTER REF_SEL SYNC[0] ANALOG VCC RC1 ANALOG GND FQ_SEL HIGH Q0 Q2 Q1 PLL_EN HIGH Q4 2X_Q Q/2 Q3 25 MHz SIGNAL MC88915T 50 MHz "Q" CLOCK OUTPUTS 2:1 Input to "Q" Output Frequency Relationship In this application, the 2X_Q output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of 2X_Q and SYNC, thus the 2X_Q frequency will equal the SYNC frequency. The Q/2 output will always run at 1/3 the 2X_Q frequency, and the "Q" outputs will run at 1/2 the 2X_Q frequency. Allowable Input Frequency Range: 20 MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH) 10 MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW) Figure 7c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feedback Figure 7. Wiring Diagrams FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 41 MC88915T BOARD VCC 47 8 1 M 10 F LOW FREQUENCY BYPASS 0.1 F HIGH FREQUENCY BYPASS 330 0.1 F (LOOP FILTER CAP) 9 RC1 ANALOG VCC ANALOG LOOP FILTER/VCO SECTION OF THE MC88915T 28-PIN PLCC PACKAGE (NOT DRAWN TO SCALE) 10 ANALOG GND 47 NOTE: A separate analog power supply is not necessary and should not be used. Following these prescribed guidelines is all that is necessary to use the MC88915T in a normal digital environment. BOARD GND Figure 8. Recommended Loop Filter and Analog Isolation Scheme for the MC88915T 1. Notes Concerning Loop Filter and Board Layout Issues scheme shown in Figure 8 is to give the 88915T Figure 8 shows a loop filter and analog isolation scheme additional protection from the power supply and which will be effective in most applications. The following ground plane transients potentially occurring in a high guidelines should be followed to ensure stable and frequency, high speed digital system. jitter-free operation: c. There are no special requirements set forth for the a. All loop filter and analog isolation components should loop filter resistors (1.0 M and 330 ). The loop filter be tied as close to the package as possible. Stray capacitor (0.1 F) can be a ceramic chip capacitor, current passing through the parasitics of long traces the same as a standard bypass capacitor. can cause undesirable voltage transients at the RC1 pin. d. The 1.0 M reference resistor injects current into the internal charge pump of the PLL, causing a fixed b. The 47 resistors, the 10 F low frequency bypass offset between the outputs and the SYNC input. This capacitor, and the 0.1 F high frequency bypass also prevents excessive jitter caused by inherent PLL capacitor form a wide bandwidth filter minimizing the dead-band. If the VCO (2X_Q output) is running 88915T's sensitivity to voltage transients from the above 40 MHz, the 1.0 M resistor provides the system digital VCC supply and ground planes. This correct amount of current injection into the charge filter will typically ensure a 100 mV step deviation on pump the digital VCC supply, causing no more than a 100 ps (2-3 A). For the TFN55, 70 or 100, if the VCO is phase deviation o the 88915T outputs. A 250 mV step running below 40 MHz, a 1.5 M reference resistor deviation on VCC using the recommended filter should be used (instead of 1 M). values should cause no more than 250 ps phase 2. In addition to the bypass capacitors used in the analog deviation; if a 25 F bypass capacitor is used (instead filter of Figure 8, there should be a 0.1 F bypass of 10 F) a 250 mV VCC step should cause no more capacitor between each of the other (digital) four VCC pins than a 100 ps phase deviation. and the board ground plane. This will reduce output If good bypass techniques are used on a board switching noise caused by the 88915T outputs. In addition design near components potentially causing digital to reducing potential for noise in the "analog" section of VCC and ground noise, the above described VCC step the chip. These bypass capacitors should also be tied as deviations should not occur at the 88915T's digital close to the 88915T package as possible. VCC supply. The purpose of the bypass filtering 42 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88915T CPU CARD CLOCK @f SYSTEM CLOCK SOURCE MC88915T PLL 2f CMMU CMMU CPU CMMU CMMU CMMU CPU CARD MC88915T PLL 2f DISTRIBUTE CLOCK @ f CMMU CMMU CPU CMMU CMMU CMMU CLOCK @ 2f AT POINT OF USE MC88915T PLL 2f MEMORY CONTROL MEMORY CARDS CLOCK @ 2f AT POINT OF USE Figure 9. Representation of a Potential Multi-Processing Application Utilizing the MC88915T for Frequency Multiplication and Low Board-to-Board Skew MC88915T System Level Testing Functionality Three-state functionality was added to the 100 MHz version of the MC88915T to ease system board testing. Bringing the OE/RST pin low will put all outputs (except for LOCK) into the high impedance state. As long as the PLL_EN pin is low, the Q0-Q4, Q5, and the Q/2 outputs will remain in the low state after the OE/RST until a falling SYNC edge is seen. The 2X_Q output is the inverse of the SYNC signal in this mode. If the 3-state functionality is used, a pull-up or pull-down resistor must be tied to the FEEDBACK input pin to prevent it from floating when the fed back output goes into high impedance. With the PLL_EN pin low the selected SNC signal is gated directly into the internal clock distribution network, bypassing and disabling the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can also be used for low frequency board testing. NOTE: If the outputs are put into 3-state during normal PLL operation, the loop will be broken and phase-lock will be lost. It will take a maximum of 10 ms (tLOCK spec) to regain phase-lock after the OE/RST pin goes back high. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 43 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC88LV915T Rev 3, 08/2001 Low Voltage Low Skew CMOS PLL Clock Driver, 3-State MC88LV915T The MC88LV915T Clock Driver utilizes phase-locked loop technology to lock LOW SKEW CMOS its low skew outputs' frequency and phase onto an input reference clock. It is PLL CLOCK DRIVER designed to provide clock distribution for high performance PC's and workstations. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the MC88LV915T to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple 88LV915's can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards (see Figure 6). FN SUFFIX Five "Q" outputs (Q0-Q4) are provided with less than 500 ps skew between 28-LEAD PLCC PACKAGE their rising edges. The Q5 output is inverted (180 phase shift) between their CASE 776-02 rising edges. The Q5 output is inverted (180 phase shift) from the "Q" outputs. The 2X_Q output runs at twice the "Q" output frequency, while the Q/2 runs at 1/2 the "Q" frequency. The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in detail the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the "Q" outputs to the SYNC input are 2:1, 1:1, and 1:2. The FREQ_SEL pin provides one bit programmable divide-by in the feedback path of the PLL. It selects between divide-by-1 and divide-by-2 of the VCO before its signal reaches the internal clock distribution section of the chip (see Figure 2). In most applications FREQ_SEL should be held high (/1). If a low frequency reference clock input is used, holding FREQ_SEL low (/2) will allow the VCO to run in its optimal range (>20MHz). In normal phase-locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88LV915T in a static "test mode". In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board-level testing (see Applications Information for All Versions). Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0-Q4, Q5 and Q/2 into a high impedance state (3-state). After the OE/RST pin goes back high Q0-Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC input. Assuming PLL_EN is low, the outputs will remain reset until the 88LV915 sees a SYNC input pulse. A lock indicator output (LOCK) will go high when the loop is in steady-state phase and frequency lock. The LOCK output will go low if phase-lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88LV915 sees a SYNC signal and full 5V VCC. Features * * * * * * * * Five Outputs (Q0-Q4) with Output-Output Skew < 500 ps each being phase and frequency locked to the SYNC input The phase variation from part-to-part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which defines the part-to-part skew) Input/Output phase-locked frequency ratios of 1:2, 1:1, and 2:1 are available Input frequency range from 5MHz - 2X_Q FMAX spec. Additional outputs available at 2X and +2 the system "Q" frequency. Also a Q (180 phase shift) output available All outputs have 36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are TTL-level compatible. 88mA IOL/IOH specifications guarantee 50 transmission line switching on the incident edge Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. All outputs can go into high impedance (3-state) for board test purposes Lock Indicator (LOCK) accuracy indicates a phase-locked state Yield Surface Modeling and YSM are trademarks of Motorola, Inc. 44 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88LV915T OE/RST VCC 4 FEEDBACK REF_SEL SYNC[0] VCC(AN) RC1 GND(AN) SYNC[1] 5 6 7 8 9 10 11 12 FREQ_SEL 13 GND 14 Q0 15 VCC 16 Q1 17 GND 18 PLL_EN 3 Q5 2 GND Q4 1 28 VCC 27 2X_Q 26 25 24 23 22 21 20 19 Q/2 GND Q3 VCC Q2 GND LOCK FN SUFFIX PLASTIC PLCC CASE 776-02 Figure 1. Pinout: 28-Lead PLCC (Top View) Table 1. Pin Summary Pin Name SYNC[0] SYNC[1] REF_SEL FREQ_SEL FEEDBACK RC1 Q(0-4) Q5 2X_Q Q/2 LOCK OE/RST PLL_EN VCC, GND Number 1 1 1 1 1 1 5 1 1 1 1 1 1 11 I/O Input Input Input Input Input Input Output Output Output Output Output Input Input Reference clock input Reference clock input Chooses reference between SYNC[0] and SYNC[1] Doubles VCO Internal Frequency (low) Feedback input to phase detector Input for external RC network Clock output (locked to SYNC) Inverse of clock output 2 x clock output (Q) frequency (synchronous) Indicates phase lock has been achieved (high when locked) Output Enable/Asynchronous reset (active low) Disables phase-lock for low frequency testing Power and ground pins (NOTE: Pins 8 and 10 are "analog" supply pins for internal PLL only) Function FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 45 MC88LV915T LOCK FEEDBACK SYNC (0) 0 M U X PHASE/ FREQ. DETECTOR CHARGE PUMP/ LOOP FILTER SYNC (1) VOLTAGE CONTROLLED OSCILLATOR 1 REF_SEL EXTERNAL REC NETWORK (RC1 Pin) PLL_EN 0 MUX 1 2x_Q D (/1) 1 DIVIDE BY TWO (/2) 0 M U X D CP FREQ_SEL OE/RST R CP R Q Q Q0 Q Q1 D CP R Q Q2 D CP R Q Q3 D CP R Q Q4 D CP R Q Q5 D CP R Q Q/2 Figure 2. MC88LV915T Block Diagram 46 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88LV915T Table 2. Maximum Ratings1 Symbol VCC, AVCC Vin Vout Iin Iout ICC Tstg Parameter DC Supply Voltage Referenced to GND DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, Per Pin DC Output Sink/Source Current, Per Pin DC VCC or GND Current Per Output Pin Storage Temperature Limits -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 -65 to +150 Unit V V V mA mA mA C 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Table 3. Recommended Operating Conditions Symbol VCC Vin Vout TA ESD Supply Voltage DC Input Voltage DC Output Voltage Ambient Operating Temperature Static Discharge Voltage Parameter Limits 3.3 0.3 0 to VCC 0 to VCC 0 to 70 > 1000 Unit V V V C V Table 4. DC Characteristics (TA = 0C to 70C; VCC = 3.3 V 0.3 V) Symbol VIH VIL VOH VOL IIN ICCT IOLD IOHD ICC Maximum Quiescent Supply Current Parameter Minimum High Level Input Voltage Minimum Low Level Input Voltage Minimum High Level Output Voltage Minimum Low Level Output Voltage Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic3 Output Current VCC 3.0 3.3 3.0 3.3 3.0 3.3 3.0 3.3 3.6 3.6 3.6 3.6 3.6 Guaranteed Limits 2.0 2.0 0.8 0.8 2.4 2.7 0.44 0.44 1.0 2.0 +50 -50 TBD Unit V V V V A mA mA mA A Condition VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V VIN = VIH or VIL IOH= -24 mA VIN = VIH or VIL IOH= 24 mA VI = VCC, GND VI = VCC - 2.1 V VOLD = 1.25 V VOHD =2.35 V VI = VCC, GND 1. IOL is +12 mA for the RST_OUT output. 2. The PLL_EN input pin is not guaranteed to meet this specification. 3. Maximum test duration 2.0 ms, one output loaded at a time. Table 5. SYNC Input Timing Requirements Symbol tRISE/FALL SYNC Input tCYCLE, SYNC Input Duty Cycle Rise/Fall Time, SYNC Input From 0.8 V to 2.0 V Input Clock Period SYNC Input Duty Cycle, SYNC Input Parameter Minimum - 1 f2X_Q/4 50% 25% Maximum 5.0 100 Unit ns ns FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 47 MC88LV915T Table 6. Frequency Specifications (TA = 0C to 70C; VCC = 3.3 V 0.3 V) Symbol Fmax (2X_Q) Fmax (`Q') NOTE: Parameter Maximum Operating Frequency, 2X_Q Output Maximum Operating Frequency, Q0-Q3 Outputs Guaranteed Minimum 100 50 Unit MHz MHz Maximum Operating Frequency is guaranteed with the 88LV926 in a phase-locked condition. Table 7. AC Characteristics (TA = 0 C to +70 C, VCC = 3.3 V 0.3 V, Load = 50 Terminated to VCC/2) Symbol tRISE/FALL Outputs tPULSE WIDTH (Q0-Q4, Q5, Q/2) tPULSE WIDTH (2X_Q Output) Parameter Rise/Fall Time, All Outputs (Between 0.8 to 2.0 V) Output Pulse Width: Q0, Q1, Q2, Q3, Q4, Q5, Q/2 @ VCC/2 Output Pulse Width: 2X_Q @ 1.5 V 40 MHz 66 MHz 80 MHz 100 MHz 40MHz 66 MHz 80 MHz 100 MHz Min 0.5 0.5 tCYCLE - 0.5 1 0.5 tCYCLE - 1.5 0.5 tCYCLE - 1.0 0.5 tCYCLE - 1.0 0.5 tCYCLE - 1.0 tCYCLE - 600ps tCYCLE - 300ps tCYCLE - 300ps tCYCLE - 400ps Max 2.0 0.5 tCYCLE + 0.5 1 0.5 tCYCLE + 0.5 0.5 tCYCLE + 0.5 0.5 tCYCLE + 0.5 0.5 tCYCLE + 0.5 tCYCLE + 600ps tCYCLE + 300ps tCYCLE + 300ps tCYCLE + 400ps Unit ns ns ns Condition Into a 50 Load Terminated to VCC/2 Into a 50 Load Terminated to VCC/2 Into a 50 Load Terminated to VCC/2 tCYCLE1 (2x_Q Output) Cycle-to-Cycle Variation 2x_Q @ VCC/2 tPD2 SYNC Feedback (With 1 M from RC1 to An VCC) SYNC Input to Feedback Delay 66 MHz (Measured at SYNC0 or 1 and 80 MHz FEEDBACK Input Pins) 100 MHz Output-to-Output Skew Between Outputs Q0-Q4, Q/2 (Rising Edges Only) Output-to-Output Skew Between Outputs Q0-Q4 (Falling Edges Only) Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Q5 Falling Time Required to Acquire Phase-Lock From Time SYNC Input Signal is Received Output Enable Time OE/RST to 2X_Q, Q0-Q4, Q5, and Q/2 Output Disable Time OE/RST to 2X_Q, Q0-Q4, Q5, and Q/2 -1.65 -1.45 -1.25 -- -1.05 -0.85 -0.65 500 ns tSKEWr3 (Rising) See Note 4 tSKEWf3 (Falling) tSKEWall3 ps All Outputs Into a Matched 50 Load Terminated to VCC/2 All Outputs Into a Matched 50 Load Terminated to VCC/2 All Outputs Into a Matched 50 Load Terminated to VCC/2 Also Time to LOCK Indicator High Measured With the PLL_EN Pin Low Measured With the PLL_EN Pin Low -- 750 ps -- 750 ps tLOCK4 1.0 10 ms tPZL5 tPHZ,tPLZ5 1. 2. 3. 4. 3.0 3.0 14 14 ns ns tCYCLE in this spec is 1/Frequency at which the particular output is running. The tPD specification's min/max values may shift closer to zero if a larger pullup resistor is used. Under equally loaded conditions and at a fixed temperature and voltage. With VCC fully powered-on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 F, tLOCK minimum is with C1 = 0.01 F. 5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when `MC' status is reached. 48 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88LV915T APPLICATIONS INFORMATION FOR ALL VERSIONS SYNC INPUT (SYNC[1] or SYNC[0]) tCYCLE SYNC INPUT t PD FEEDBACK INPUT Q/2 OUTPUT tSKEWALL tSKEWf tSKEWr tSKEWf tSKEWR Q0 - Q4 OUTPUTS tCYCLE "Q" OUTPUTS Q5 OUTPUT 2X_Q OUTPUT (These waveforms represent the hook-up configuration of Figure 4a) Timing Notes: 1. The MC88LV915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as `windows', not as a deviation around a center point. 3. If a "Q" output is connected to the FEEDBACK input (this situation is not shown), the "Q" output frequency would match the SYNC input frequency, the 2X_Q output would run at twice the SYNC frequency, and the Q/2 output would run at half the SYNC frequency. Figure 3. Output/Input Switching Waveforms and Timing Diagrams FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 49 MC88LV915T 25MHz FEEDBACK SIGNAL HIGH RST FEEDBACK CRYSTAL OSCILLATOR 100MHz SIGNAL 1:2 Input to "Q" Output Frequency Relationship In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2 frequency will equal the SYNC frequency. The "Q" outputs (Q0-Q4, Q5) will always run at 2X the Q/2 frequency, and the 2X_Q output will run at 4X the Q/2 frequency. Allowable Input Frequency Range: 5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH) 2.5MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW) Q5 Q4 2X_Q Q/2 Q3 Q2 50MHz "Q" CLOCK OUTPUTS LOW 25MHz INPUT EXTERNAL LOOP FILTER REF_SEL SYNC[0] MC88LV915T ANALOG VCC RC1 ANALOG GND FQ_SEL Q0 Q1 PLL_EN HIGH NOTE: If the OE/RST input is active, a pull-up or pull-down resistor isn't necessary at the FEEDBACK pin so it won't when the fed back output goes into 3-state. HIGH Figure 4a. Wiring Diagram and Frequency Relationships with Q/2 Output Feedback 100MHz SIGNAL 1:1 Input to "Q" Output Frequency Relationship In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4 frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The Q/2 output will always run at 1/2 the "Q" frequency, and the 2X_Q output will run at 2X the "Q" frequency. Allowable Input Frequency Range: 10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH) 5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL LOW) 50MHz FEEDBACK SIGNAL HIGH RST Q5 FEEDBACK CRYSTAL OSCILLATOR Q4 2X_Q Q/2 Q3 Q2 LOW 50MHz INPUT EXTERNAL LOOP FILTER REF_SEL SYNC[0] MC88LV915T ANALOG VCC RC1 ANALOG GND FQ_SEL Q0 Q1 25MHz SIGNAL 50MHz "Q" CLOCK OUTPUTS PLL_EN HIGH HIGH Figure 4b. Wiring Diagram and Frequency Relationships with Q4 Output Feedback 100MHz FEEDBACK SIGNAL HIGH RST Q5 FEEDBACK CRYSTAL OSCILLATOR Q4 2X_Q Q/2 Q3 Q2 LOW 100MHz INPUT EXTERNAL LOOP FILTER REF_SEL SYNC[0] MC88LV915T ANALOG VCC RC1 ANALOG GND FQ_SEL Q0 Q1 25MHz SIGNAL 50MHz "Q" CLOCK OUTPUTS 2:1 Input to "Q" Output Frequency Relationship In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4 frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The Q/2 output will always run at 1/2 the "Q" frequency, and the 2X_Q output will run at 2X the "Q" frequency. Allowable Input Frequency Range: 20MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH) 10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW) PLL_EN HIGH HIGH Figure 4c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feedback Figure 4. Wiring Diagrams 50 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88LV915T BOARD VCC 47 8 ANALOG VCC 10F LOW FREQ BYPASS 0.1 F HIGH FREQ BYPASS 1 M 330 9 RC1 0.1 F (LOOP FILTER CAP) 47 ANALOG LOOP FILTER/VCO SECTION OF THE MC88LV915T 28-PIN PLCC PACKAGE (NOT DRAWN TO SCALE) 10 ANALOG GND BOARD GND A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES IS ALL THAT IS NECESSARY TO USE THE MC88LV915T IN A NORMAL DIGITAL ENVIRONMENT. Figure 5. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV915T NOTES CONCERNING LOOP FILTER AND BOARD LAYOUT ISSUES Figure 5 shows a loop filter and analog isolation scheme, effective in most applications. The following guidelines should be followed ensuring stable and jitter-free operation: 1a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the RC1 pin. 1b. The 47 resistors, the 10 F low frequency bypass capacitor, and the 0.1 F high frequency bypass capacitor form a wide bandwidth filter that will minimize the 88LV915T's sensitivity to voltage transients from the system digital VCC supply and ground planes. This filter will typically ensure that a 100mV step deviation on the digital VCC supply will cause no more than a 100pS phase deviation on the 88LV915T outputs. A 250mV step deviation on VCC using the recommended filter values should cause no more than a 250pS phase deviation; if a 25 F bypass capacitor is used (instead of 10 F) a 250 mV VCC step should cause no more than a 100 pS phase deviation. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, the above described VCC step deviations should not occur at the 88LV915T's digital VCC supply. 1. The purpose of the bypass filtering scheme shown in Figure 5 is to give the 88LV915T additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 1c. There are no special requirements set forth for the loop filter resistors (1 M and 330 ). The loop filter capacitor (0.1 F) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 1d. The 1 M reference resistor injects current into the internal charge pump of the PLL, causing a fixed offset between the outputs and the SYNC input. This also prevents excessive jitter caused by inherent PLL dead-band. If the VCO (2X_Q output) is running above 40 MHz, the 1 M resistor provides the correct amount of current injection into the charge pump (2-3 A). For the TFN55, 70 or 100, if the VCO is running below 40 MHz, a 1.5 M reference resistor should be used (instead of 1 M). 2. In addition to the bypass capacitors used in the analog filter of Figure 5, there should be a 0.1 F bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 88LV915T outputs, in addition to reducing potential for noise in the `analog' section of the chip. These bypass capacitors should also be tied as close to the 88LV915T package as possible. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 51 MC88LV915T MC88LV915T CLOCK @f PLL 2f CMMU CMMU CPU CARD CPU CMMU SYSTEM CLOCK SOURCE CMMU CMMU CMMU MC88LV915T PLL 2f DISTRIBUTE CLOCK @ f CPU CMMU CPU CARD CMMU CMMU CMMU CLOCK @ 2f AT POINT OF USE MC88LV915T PLL 2f MEMORY CONTROL MEMORY CARDS CLOCK @ 2f AT POINT OF USE Figure 6. Representation of a Potential Multi-Processing Application Utilizing the MC88LV915T for Frequency Multiplication and Low Board-to-Board Skew MC88LV915T SYSTEM LEVEL TESTING FUNCTIONALITY Three-state functionality has been added to the 100 MHz version of the MC88LV915T to ease system board testing. Bringing the OE/RST pin low will put all outputs (except for LOCK) into the high impedance state. As long as the PLL_EN pin is low, the Q0-Q4, Q5, and the Q/2 outputs will remain reset in the low state after the OE/RST until a falling SYNC edge is seen. The 2X_Q output will be the inverse of the SYNC signal in this mode. If the 3-state functionality will be used, a pull-up or pull-down resistor must be tied to the FEEDBACK input pin to prevent it from floating when the feedback output goes into high impedance. With the PLL_EN pin low the selected SYNC signal is gated directly into the internal clock distribution network, bypassing and disabling the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can also be used for low frequency board testing. Note: If the outputs are put into 3-state during normal PLL operation, the loop will be broken and phase-lock will be lost. It will take a maximum of 10 mS (tLOCK spec) to regain phase-lock after the OE/RST pin goes back high. 52 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC88LV926 Rev 5, 08/2004 Low Skew CMOS PLL 68060 Clock Driver The MC88LV926 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a processor reset function designed specifically for the MC68/EC/LC030/040/060 microprocessor family. To support the 68060 processor, the 88LV926 operates from a 3.3 V as well as a 5.0 V supply. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88LV926 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Features * MC88LV926 LOW SKEW CMOS PLL 68080 CLOCK DRIVER 2X_Q Output Meets All Requirements of the 50 and 66 MHz 68060 Microprocessor PCLK Input Specifications * Low Voltage 3.3 V VCC * Three Outputs (Q0-Q2) With Output-Output Skew <500 ps * CLKEN Output for Half Speed Bus Applications * The Phase Variation From Part--to--Part Between SYNC and the `Q' Outputs Is Less Than 600 ps (Derived From the TPD Specification, Which Defines the Part-to-Part Skew) * SYNC Input Frequency Range From 5.0 MHz to 2X_Q FMax/4 * All Outputs Have 36 mA Drive (Equal High and Low) CMOS Levels * Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL--Level Compatible with VCC = 3.3 V * Test Mode Pin (PLL_EN) Provided for Low Frequency Testing Three `Q' outputs (Q0-Q2) are provided with less than 500ps skew between their rising edges. A 2X_Q output runs at twice the `Q' output frequency. The 2X_Q output is ideal for 68060 systems which require a 2X processor clock input, and it meets the tight duty cycle spec of the 50 and 66MHz 68060. The QCLKEN output is designed to drive the CLKEN input of the 68060 when the bus logic runs at half of the microprocessor clock rate. The QCLKEN output is skewed relative to the 2X_Q output to ensure that CLKEN setup and hold times of the 68060 are satisfied. A Q/2 frequency is fed back internally, providing a fixed 2X multiplication from the `Q' outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is provided) the input/output frequency relationships are fixed. The Q3 output provides an inverted clock output to allow flexibility in the clock tree design. In normal phase-locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88LV926 in a static `test mode'. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The RST_OUT(LOCK) pin doubles as a phase-lock indicator. When the RST_IN pin is held high, the open drain RST_OUT pin will be pulled actively low until phase-lock is achieved. When phase-lock occurs, the RST_OUT(LOCK) is released and a pull-up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST_OUT(LOCK) pin will stay low for 1024 cycles of the `Q' output frequency after the RST_IN pin is brought back high. Description of the RST_IN/RST_OUT(LOCK) Functionality The RST_IN and RST_OUT(LOCK) pins provide a 68030/040/060 processor reset function, with the RST_OUT pin also acting as a lock indicator. If the RST_IN pin is held high during system power-up, the RST_OUT pin will be in the low state until steady state phase/frequency lock to the input reference is achieved. 1024 `Q' output cycles after phase-lock is achieved the RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull-up resistor (see the AC/DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power-up, the RST_OUT(LOCK) pin will remain low. DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-06 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 53 MC88LV926 Q3 VCC MR RST_IN VCC(AN) RC1 GND(AN) SYNC GND 1 2 3 4 5 6 7 8 9 20 GND 19 2X_Q 18 QCLKEN 17 VCC 16 Q2 15 GND 14 RST_OUT(LOCK) 13 PLL_EN 12 Q1 11 VCC Q0 10 Figure 1. Pinout: 20-Lead Wide SOIC Package (Top View) Description of the RST_IN/RST_OUT(LOCK) Functionality (continued) After the system start-up is complete and the 88LV926 is phase-locked to the SYNC input signal (RST_OUT high), the processor reset functionality can be utilized. When the RST_IN pin is toggled low (min. pulse width=10nS), RST_OUT(LOCK) will go to the low state and remain there for 1024 cycles of the `Q' output frequency (512 SYNC cycles). During the time in which the RST_OUT(LOCK) is actively pulled low, all the 88LV926 clock outputs will continue operating correctly and in a locked condition to the SYNC input (clock signals to the 68030/040/060 family of processors must continue while the processor is in reset). A propagation delay after the 1024th cycle RST_OUT(LOCK) goes back to the high impedance state to be pulled high by the resistor. Power Supply Ramp Rate Restriction for Correct 030/040 Processor Reset Operation During System Start-up Because the RST_OUT(LOCK) pin is an indicator of phase-lock to the reference source, some constraints must be placed on the power supply ramp rate to make sure the RST_OUT(LOCK) signal holds the processor in reset during system start-up (power-up). With the recommended loop filter values (see Figure 7) the lock time is approximately 10ms. The phase-lock loop will begin attempting to lock to a reference source (if it is present) when VCC reaches 2V. If the VCC ramp rate is significantly slower than 10ms, then the PLL could lock to the reference source, causing RST_OUT(LOCK) to go high before the 88LV926 and '030/040 processor is fully powered up, violating the processor reset specification. Therefore, if it is necessary for the RST_IN pin to be held high during power-up, the VCC ramp rate must be less than 10mS for proper 68030/040/060 reset operation. This ramp rate restriction can be ignored if the RST_IN pin can be held low during system start-up (which holds RST_OUT low). The RST_OUT(LOCK) pin will then be pulled back high 1024 cycles after the RST_IN pin goes high. Table 1. Capacitance and Power Specifications Symbol CIN CPD PD1 PD2 Parameter Input Capacitance Power Dissipation Capacitance Power Dissipation at 33MHz With 50 Thevenin Termination Power Dissipation at 33MHz With 50 Parallel Termination to GND Value Type 4.5 1 Unit pF pF mW mW Test Conditions VCC = 5.0V VCC = 5.0V VCC = 5.0V T = 25C VCC = 5.0V T = 25C 401 15mW/Output1 90mW/Device 37.5mW/Output1 225mW/Device 1. Value at VCC = 3.3 V TBD 54 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88LV926 Table 2. Maximum Ratings1 Symbol VCC, AVCC Vin Vout Iin Iout ICC Tstg Parameter DC Supply Voltage Referenced to GND DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, Per Pin DC Output Sink/Source Current, Per Pin DC VCC or GND Current Per Output Pin Storage Temperature Limits -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 -65 to +150 Unit V V V mA mA mA C 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Table 3. Recommended Operating Conditions Symbol VCC Vin Vout TA ESD Supply Voltage DC Input Voltage DC Output Voltage Ambient Operating Temperature Static Discharge Voltage Parameter Limits 3.3 0.3 0 to VCC 0 to VCC 0 to 70 > 1500 Unit V V V C V Table 4. DC Characteristics (TA = 0C to 70C; VCC = 3.3V 0.3V)1 Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Minimum Low Level Input Voltage 1 VCC 3.0 3.3 3.0 3.3 3.0 3.3 Guaranteed Limits 2.0 2.0 0.8 0.8 2.2 2.5 Unit V Condition VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V VIN = VIH or VIL = -24mA IOH = -24mA VIN = VIH or VIL = +24mA2 IOH = +24mA V Minimum High Level Output Voltage V VOL Minimum Low Level Output Voltage 3.0 3.3 0.55 0.55 V IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current 4 3.3 3.3 3.3 3.3 1.0 2.0 3 50 -50 750 A mA mA mA A VI = VCC, GND VI = VCC - 2.1V VOLD = 1.25V Max VOHD = 2.35 Min VI = VCC, GND Maximum Quiescent Supply Current 3.3 1. The MC88LV926 can also be operated from a 5.0V supply. VOH output levels will vary 1:1 with VCC, input levels and current specs will be unchanged, except VIH; when VCC > 4.0 volts, VIH minimum level is 2.7 volts. 2. IOL is +12mA for the RST_OUT output. 3. Maximum test duration 2.0ms, one output loaded at a time. 4. The PLL_EN input pin is not guaranteed to meet this specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 55 MC88LV926 RST_OUT RST_IN LOCK INDICATOR RESET_OUT Q /2 R 2X_Q SYNC1 PFD CH PUMP VCO Q /4 R Q /4 R Q /4 R Q /4 R Q0 PLL_EN /8 0 1 Q1 Q2 Q3 POWER-ON RESET DELAY CLKEN /4 R MR Figure 2. MC88LV926 Logic Block Diagram Table 5. Sync Input Timing Requirements Symbol tRISE/FALL SYNC Input tCYCLE, SYNC Input Duty Cycle Rise/Fall Time, SYNC Input From 0.8V to 2.0V Input Clock Period SYNC Input1 Duty Cycle, SYNC Input Parameter Minimum - 1 f2X_Q/4 50% 25% Maximum 5.0 2001 Unit ns ns 1. When VCC > 4.0 volts, Maximum SYNC Input Period is 125ns. 56 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88LV926 Table 6. Frequency Specifications (TA = 0C to 70C; VCC = 3.3V 0.3V or 5.0V 5%) Symbol Fmax (2X_Q) Fmax (`Q') NOTE: Parameter Maximum Operating Frequency, 2X_Q Output Maximum Operating Frequency, Q0-Q3 Outputs Guaranteed Minimum 66 33 Unit MHz MHz Maximum Operating Frequency is guaranteed with the 88LV926 in a phase-locked condition. Table 7. AC Characteristics (TA = 0C to 70C; VCC = 3.3V 0.3V or 5.0V 5%) Symbol tRISE/FALL All Outputs tRISE/FALL 2X_Q Output tpulse width(a)1 (Q0, Q1, Q2, Q3) tpulse width(b)1 (2X_Q Output) tSKEWr2 (Rising) tSKEWf2 (Falling) tSKEWall2 Parameter Rise/Fall Time, into 50 Load Rise/Fall Time into a 50 Load Output Pulse Width Q0, Q1, Q2, Q3 at 1.65V Output Pulse Width 2X_Q at 1.65V Output-to-Output Skew Between Outputs Q0-Q2 (Rising Edge Only) Output-to-Output Skew Between Outputs Q0-Q2 (Falling Edge Only) Output-to-Output Skew 2X_Q, Q0-Q2, Q3 Output-to-Output Skew QCLKEN to 2X_Q 2X_Q = 50MHz 2X_Q = 66MHz Phase-Lock Acquisition Time, All Outputs to SYNC Input Propagation Delay, MR to Any Output (High-Low) Minimum 0.3 0.5 0.5tcycle - 0.5 0.5tcycle - 0.5 - Maximum 1.6 1.6 0.5tcycle + 0.5 0.5tcycle + 0.5 500 Unit ns ns ns ns ps Condition tRISE - 0.8V to 2.0V tFALL - 2.0V to 0.8V tRISE - 0.8V to 2.0V tFALL - 2.0V to 0.8V 50 Load Terminated to VCC/2 (See Application Note 3) 50 Load Terminated to VCC/2 (See Application Note 3) Into a 50 Load Terminated to VCC/2 (See Timing Diagram in Figure 6) Into a 50 Load Terminated to VCC/2 (See Timing Diagram in Figure 6) Into a 50 Load Terminated to VCC/2 (See Timing Diagram in Figure 6) Into a 50 Load Terminated to VCC/2 (See Timing Diagram in Figure 6) - 1.0 ns - 750 ps tSKEW QCLKEN1,2 ns 9.7 1 1.5 9 5 10 1.5 1016 `Q' Cycles (508 Q/2 Cycles) 6 - 7.06 10 13.5 - - - 16.5 1024 `Q' Cycles (512 Q/2 Cycles) ms ns ns ns ns ns ns tLOCK3 tPHL MR - Q1 Into a 50 Load Terminated to VCC/2 tREC, MR to SYNC5, 1 Reset Recovery Time rising MR edge to falling SYNC edge tW, MR LOW5, 1 tW, RST_IN LOW1 tPZL1 tPLZ1 Minimum Pulse Width, MR input Low Minimum Pulse Width, RST_IN Low Output Enable Time RST_IN Low to RST_OUT Low Output Enable Time RST_IN High to RST_OUT High Z When in Phase-Lock See Application Note 5 See Application Note 5 1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this methodology. 2. Under equally loaded conditions and at a fixed temperature and voltage. 3. With VCC fully powered-on: tCLOCK Max is with C1 = 0.1F; tLOCK Min is with C1 = 0.01F. 4. See Application Note 4 for the distribution in time of each output referenced to SYNC. 5. Specification is valid only when the PLL_EN pin is low. 6. Guaranteed that QCLKEN will meet the setup and hold time requirement of the 68060. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 57 MC88LV926 APPLICATION NOTES 1. Several specifications can only be measured when the MC88LV926 is in phase-locked operation. It is not possible to have the part in phase-lock on automated test equipment (ATE). Statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88LV926 units were fabricated with key transistor properties intentionally varied to create a 14 cell designed experimental matrix. IC performance was characterized over a range of transistor properties (represented by the 14 cells) in excess of the expected process variation of the wafer fabrication area. Response Surface Modeling (RSM) techniques were used to relate IC performance to the CMOS transistor properties over operation voltage and temperature. IC performance to each specification and fab variation were used in conjunction with Yield Surface Modeling (YSM) methodology to set performance limits of ATE testable specifications within those which are to be guaranteed by statistical characterization. In this way, all units passing the ATE test will meet or exceed the non-tested specifications limits. A 470K resistor tied to either Analog VCC or Analog GND, as shown in Figure 3, is required to ensure no jitter is present on the MC88LV926 outputs. This technique causes a phase offset between the SYNC input and the Q0 output, measured at the pins. The tPD spec describes how this offset varies with process, temperature, and voltage. The specs were arrived at by measuring the phase relationship for the 14 lots described in note 1 while the part was in phase-locked operation. The actual measurements were made with a 10MHz SYNC input (1.0ns edge rate from 0.8V to 2.0V). The phase measurements were made at 1.5V. See Figure 3 for a graphical description. Two specs (tRISE/FALL and tPULSE Width 2X_Q output, see AC Specifications) guarantee that the MC88LV926 meets the 33MHz and 66MHz 68060 P-Clock input specification. 2. 3. RC1 EXTERNAL LOOP FILTER 330 0.1F ANALOG VCC 470K REFERENCE RESISTOR RC1 R2 C1 R2 C1 470K REFERENCE RESISTOR 330 0.1F ANALOG GND WITH THE 470K RESISTOR TIED IN THIS FASHION THE TPD SPECIFICATION, MEASURED AT THE INPUT PINS IS: tPD = 2.25ns 1.0ns (TYPICAL VALUES) 3V SYNC INPUT 2.25ns OFFSET SYNC INPUT 5V Q0 OUTPUT ANALOG GND WITH THE 470K RESISTOR TIED IN THIS FASHION THE TPD SPECIFICATION, MEASURED AT THE INPUT PINS IS: tPD = -0.80ns 0.30ns 3V -0.8ns OFFSET 5V Q0 OUTPUT Figure 3. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present When a 470K Resistor Is Tied to VCC or Ground 58 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88LV926 RST_OUT PIN VCC 1K INTERNAL LOGIC CL ANALOG GND Figure 4. RST_OUT Test Circuit 2X_Q 12.5MHz CRYSTAL OSCILLATOR SYNC Q0 Q1 Q2 Q3 QCLKEN RST_OUT 66MHz P-CLOCK OUTPUT 33MHz B-CLOCK AND SYSTEM OUTPUTS DELAY 33MHz CLKEN OUTPUT MR PLL_EN RST_IN Figure 5. Logical Representation of the MC88LV926 With Input/Output Frequency Relationships SYNC Input tCYCLE SYNC Input tSKEWall tSKEWf tSKEWr tSKEWf tSKEWr Q0-Q3 Outputs tCYCLE `Q' Outputs 2X_Q Output QCLKEN tSKEWQCLKEN tSKEWQCLKEN TIMING NOTES: 1. The MC88LV926 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as `windows', not as a deviation around a center point. Figure 6. Output/Input Switching Waveforms and Timing Relationships FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 59 MC88LV926 4. The tPD spec includes the full temperature range from 0C to 70C and the full VCC range from 3.0V to 3.3V. If the T and VCC is a given system are less than the specification limits, the tPD spec window will be reduced. The tPD window for a given T and VCC is given by the following regression formula: TBD 5. The RST_OUT pin is an open drain N-Channel output. Therefore an external pull-up resistor must be provide to pull up the RST_OUT pin when it goes into the high impedance state (after the MC88LV926 is phase-locked to the reference input with RST_IN held high or 1024 `Q' cycles after the RST_IN pin goes high when the part is locked). In the tPLZ and tPZL specifications, a 1K resistor is used as a pull-up as shown in Figure 3. NOTES CONCERNING LOOP FILTER AND BOARD LAYOUT ISSUES Figure 7 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation: 1a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the RC1 pin. 1b. The 47 resistors, the 10F low frequency bypass capacitor, and the 0.1F high frequency bypass capacitor form a wide bandwidth filter that will make the 88LV926 PLL insensitive to voltage transients from the system digital VCC supply and ground planes. This filter will typically ensure that a 100mV step deviation on the digital VCC supply will cause no more than a 100ps phase deviation on the 88LV926 outputs. A 250mV step deviation on VCC using the recommended filter values will cause no more than a 250ps phase deviation; if a 25F bypass capacitor is used (instead of 10F) a 250mV VCC step will cause no more than a 100ps phase deviation. . If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, the above described VCC step deviations should not occur at the 88LV926's digital VCC supply. The 1. purpose of the bypass filtering scheme shown in Figure 6 is to give the 88LV926 additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 1c. There are no special requirements set forth for the loop filter resistors (470K and 330). The loop filter capacitor (0.1uF) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 1d. The 470K reference resistor injects current into the internal charge pump of the PLL, causing a fixed offset between the outputs and the SYNC input. This also prevents excessive jitter caused by inherent PLL dead-band. If the VCO (2X_Q output) is running above 40MHz, the 470K resistor provides the correct amount of current injection into the charge pump (2-3A). If the VCO is running below 40MHz, a 1M reference resistor should be used (instead of 470K). 2. In addition to the bypass capacitors used in the analog filter of Figure 7, there should be a 0.1F bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 88LV926 outputs, in addition to reducing potential for noise in the `analog' section of the chip. These bypass capacitors should also be tied as close to the 88LV926 package as possible. 60 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC88LV926 BOARD VCC NOTE: FURTHER LOOP OPTIMIZATION MAY OCCUR 47 5 470K 10F LOW FREQ BIAS 0.1F HIGH FREQ BIAS 330 6 0.1F (LOOP FILTER CAP) 47 RC1 ANALOG VCC ANALOG LOOP FILTER/VCO SECTION OF THE MC88LV926 20-PIN SOIC PACKAGE (NOT DRAWN TO SCALE) 7 ANALOG GND BOARD GND A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES IS ALL THAT IS NECESSARY TO USE THE MC88LV926 IN A NORMAL Figure 7. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV926 MC68060 16.67MHz X-TAL OSCILLATOR SYNC 2X_Q QCLKEN Q0 Q1 Q2 Q3 RST_OUT 66MHz PCLK CLKEN RESET ASIC ASIC 33MHz SYSTEM RESET RST_IN MEMORY MODULE Figure 8. Typical MC88LV926/MC68060 System Configuration FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 61 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9315 Rev 3, 08/2004 2.5V and 3.3V CMOS PLL Clock Generator and Driver The MPC9315 is a 2.5V and 3.3V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to high-performance telecom, networking and computing applications. The MPC9315 offers 8 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1, 2:1, 4:1, 1:2 and 1:4 output to input frequency ratios. In addition, a selectable output 180 phase control supports advanced clocking schemes with inverted clock signals. The MPC9315 is specified for the extended temperature range of -40 to +85C. Features * Configurable 8 outputs LVCMOS PLL clock generator * Compatible to various microprocessors such as PowerQuicc I and II * Wide range output clock frequency of 18.75 to 160 MHz * 2.5V and 3.3V CMOS compatible * Designed for mid-range to high-performance telecom, networking and computer applications * Fully integrated PLL supports spread spectrum clocking * Supports applications requiring clock redundancy * Max. output skew of 120 ps (80 ps within one bank) * Selectable output configurations (1:1, 2:1, 4:1, 1:2, 1:4 frequency ratios) * Two selectable LVCMOS clock inputs * External PLL feedback path and selectable feedback configuration * Tristable outputs * 32-Lead LQFP package * Ambient operating temperature range of -40 to +85C * 32-Lead Pb-free Package Available MPC9315 LOW VOLTAGE 2.5V AND 3.3V PLL CLOCK GENERATOR FA SUFFIX LQFP PACKAGE CASE 873A-03 Functional Description The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation requires a connection of one of the device outputs to the selected feedback (FB0 or FB1) input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4 the internal VCO of the MPC9315 is running at either 1x, 2x or 4x of the reference clock frequency. The frequency of the QA, QB, QC output groups is either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The REF_SEL pin selects one of the two available LVCMOS compatible reference input (CLK0 and CLK1) supporting clock redundant applications. The selectable feedback input pin allows the user to select different feedback configurations and input to output frequency ratios. The MPC9315 also provides a static test mode when the PLL supply pin (VCCA) is pulled to logic low state (GND). In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to lose lock due to no feedback signal presence at FB0 or FB1. Asserting OE will enable the outputs and close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9315 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9315 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm2 32-lead LQFP package. The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal. 62 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9315 VCCA VCC 6 CLK0 CLK1 (PULLDOWN) (PULLDOWN) BANK A 0 Ref 1 FB REF_SEL (PULLDOWN) 75 - 160 MHz CLK/4 (PULLDOWN) (PULLDOWN) (PULLDOWN) QB3 (PULLDOWN) (PULLDOWN) (PULLUP) 0 1 FSELC OE (PULLUP) (PULLDOWN) GND 6 BANK C QC0 QC1 CLK/2 1 1 BANK B QB0 FB0 FB1 FB_SEL FSELA PSELA FSELB 0 1 0 1 QB1 QB2 QA1 PLL CLK 0 0 QA0 Figure 1. MPC9315 Logic Diagram GND GND 18 QB0 QB1 QB2 QB3 17 16 15 14 VCC QC0 QC1 GND OE PSELA FBSEL VCC 13 12 11 10 9 1 2 3 4 5 6 7 8 GND VCC VCC 20 VCCA 24 GND QA1 QA0 VCC FSELC FSELB FSELA GND 25 26 27 28 29 30 31 32 23 22 21 19 MPC9315 REF_SEL VCC CLK0 CLK1 FB0 Figure 2. Pinout: 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA FB1 63 MPC9315 ] Table 1. Pin Configuration Pin CLK0 CLK1 FB0 FB1 REF_SEL FB_SEL FSELA FSELB FSELC PSELA QA0, QA1 QB0 to QB3 QC0, QC1 OE VCCA VCC GND Input Input Input Input Input Input Input Input Input Input Output Output Output Input I/O Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Supply Supply Ground Reference clock input Alternative clock input PLL feedback input Alternative feedback input Selects clock input reference clock input, default low (pull-down) Selects PLL feedback clock input, default low (pull-down) Selects divider ratio of bank A outputs, default low (pull-down) Selects divider ratio of bank B outputs, default low (pull-up) Selects divider ratio of bank C outputs, default low (pull-up) Selects phase of bank A outputs Bank A outputs Bank B outputs Bank C outputs Output tristate Analog (PLL) positive supply voltage. Requires external RC filter Digital positive supply voltage Digital negative supply voltage (ground) Function Table 2. Function Table Control REF_SEL FB_SEL FSELA FSELB FSELC PSELA VCCA MR OE Default 0 0 0 1 1 0 none 0 0 CLK0 FB0 QAx = VCO clock frequency QBx = VCO clock frequency QCx = VCO clock frequency / 2 0 (QA0, QA1 non-inverted) VCCA = GND, PLL off and bypassed for static test and diagnosis Normal operation Outputs enabled 0 CLK1 FB1 QA0, QA1 = VCO clock frequency / 2 QB0 - QB3 = VCO clock frequency / 2 QC0, QC1 = VCO clock frequency / 4 180 (QA0, QA1 inverted) VCCA = 3.3 or 2.5V, PLL enabled Reset (VCO clamped to min. range) Outputs disabled (tristate), open PLL loop 1 Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -55 Characteristics Min -0.3 -0.3 -0.3 Max 4.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. 64 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9315 Table 4. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD (Machine Model) ESD (Human Body Model) Latch-Up Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 5. DC Characteristics (VCC = 3.3V 5%, TA = -40 to 85C) Symbol VIH VIL VOH VOL ZOUT IIN ICCA ICCQ Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage 2.4 0.55 0.30 14 - 17 200 3.5 7.0 1.0 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V V V A mA mA VIN = VCC or GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS IOH=-24 mA1 IOL= 24mA1 IOL= 12mA Output Impedance Input Current2 Maximum PLL Supply Current Maximum Quiescent Supply Current 1. The MPC9315 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. Inputs have pull-up or pull-down resistors affecting the input current. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 65 MPC9315 Table 6. AC Characteristics (VCC = 3.3V 5%, TA = -40 to 85C)1 Symbol fref Input Frequency Characteristics /1 feedback /2 feedback /4 feedback PLL bypass mode fVCO fMAX VCO Lock Range Maximum Output Frequency /1 output /2 output /4 output Min 1002 37.50 18.75 0 75b 75 37.50 18.75 25 Typ Max 160 80 40 TBD 160 160 80 40 75 1.0 -150 +150 80 120 45 0.1 50 55 1.0 10 10 /1 feedback /2 feedback /4 feedback (1) (1) (1) TBD 2.0 - 20 0.6 - 6.0 10 8.0 8.0 - 253 22 15 TBD 1.0 Unit MHz MHz MHz MHz MHz MHz MHz MHz % ns ps ps ps % ns ns ns MHz MHz MHz ps ps ps ms RMS value RMS value RMS value 0.55 to 2.4V 0.8 to 2.0V PLL locked Condition PLL locked PLL locked PLL locked VCCA = GND frefDC tr, tf t() tSK() DC tr, tf tPLZ, HZ tPZL, LZ BW Reference Input Duty Cycle CLK0, CLK1 Input Rise/Fall Time Propagation Delay (Static Phase Offset) Output-to-Output Skew Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time PLL closed loop bandwidth CLK0 or CLK1 to FB Within one bank Any output tJIT(CC) tJIT(PER) tJIT() tLOCK Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The VCO range in /1 feedback configuration (e.g. QAx connected to FBx and FSELA = 0) is limited to 100 fVCO 160 MHz. Please see next revision of the MPC9315 for improved VCO frequency range. 3. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics. Table 7. DC Characteristics (VCC = 2.5V 5%, TA = -40 to 85C) Symbol VIH VIL VOH VOL ZOUT IIN ICCA ICCQ Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current2 Maximum PLL Supply Current Maximum Quiescent Supply Current 2.0 17 - 20 200 5.0 1.0 1.8 0.6 Min 1.7 Typ Max VCC + 0.3 0.7 Unit V V V V A mA mA VIN = VCC or GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS IOH=-15 mA1 IOL= 15mA 1. The MPC9315 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. Inputs have pull-up or pull-down resistors affecting the input current. 66 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9315 Table 8. AC Characteristics (VCC = 2.5V 5%, TA = -40 to 85C)1 Symbol fref Input Frequency Characteristics /2 feedback /4 feedback PLL bypass mode fVCO fMAX VCO Lock Range Maximum Output Frequency /1 output /2 output /4 output Min 37.50 18.75 0 752 75 37.50 18.75 25 Typ Max 80 40 TBD 160b 160 80 40 75 1.0 -150 +150 80 120 45 0.1 50 55 1.0 12 12 /2 feedback /4 feedback (1) (1) (1) 1.0 - 10 0.4 - 3.0 10 8.0 10 - 253 22 15 TBD 1.0 Unit MHz MHz MHz MHz MHz MHz MHz % ns ps ps ps % ns ns ns MHz MHz ps ps ps ms RMS value RMS value RMS value 0.55 to 2.4V 0.7 to 1.7V PLL locked Condition PLL locked PLL locked VCCA = GND frefDC tr, tf t() tSK() DC tr, tf tPLZ, HZ tPZL, LZ BW tJIT(CC) tJIT(PER) tJIT() tLOCK Reference Input Duty Cycle CLK0, CLK1 Input Rise/Fall Time Propagation Delay (Static Phase Offset) Output-to-Output Skew Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time PLL closed loop bandwidth Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time CLK0 or CLK1 to FB Within one bank Any output 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. /1 feedback is responsible for VCC = 2.5V operation. Please see application section for I/O jitter versus VCO frequency characteristics. 3. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 67 MPC9315 APPLICATIONS INFORMATION Programming the MPC9315 The PLL of the MPC9315 supports output clock frequencies from 18.75 to 160 MHz. Different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. The feedback frequency and divider should be used to situate the VCO in the frequency range between 75 and 160 MHz for stable and optimal operation. The FSELA, FSELB, FSELC pins select the desired output clock frequencies. Possible frequency ratios of the reference clock input to the outputs are 1:1, 1:2, 1:4 as well as 2:1 and 4:1, Table 9, Table 10, and Table 11 illustrate the various output configurations and frequency ratios supported by the MPC9315. PSELA controls the output phase of the QA0 and QA1 outputs, allowing the user to generate inverted clock signals synchronous to non-inverted clock signals. See also Example Configurations for the MPC9315 for further reference. Table 9. Output Frequency Relationship for QA0 connected to FB01 Inputs FSELA 0 0 0 0 1 1 1 1 FSELB 0 0 1 1 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 QA0, QA1 CLK CLK CLK CLK CLK CLK CLK CLK Outputs QB0-QB3 CLK CLK CLK / 2 CLK / 2 2 * CLK 2 * CLK CLK CLK QC0, QC1 CLK / 2 CLK / 4 CLK / 2 CLK / 4 CLK CLK / 2 CLK CLK / 2 1. Output frequency relationship with respect to input reference frequency CLK. Table 10. Output Frequency Relationship for QB0 connected to FB01 Inputs FSELA 0 0 0 0 1 1 1 1 FSELB 0 0 1 1 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 QA0, QA1 CLK CLK 2 * CLK 2 * CLK CLK / 2 CLK / 2 CLK CLK Outputs QB0-QB3 CLK CLK CLK CLK CLK CLK CLK CLK QC0, QC1 CLK / 2 CLK / 4 CLK CLK / 2 CLK / 2 CLK / 4 CLK CLK / 2 1. Output frequency relationship with respect to input reference frequency CLK. Table 11. Output Frequency Relationship for QC0 connected to FB01 Inputs FSELA 0 0 0 0 1 1 1 1 FSELB 0 0 1 1 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 QA0, QA1 2 * CLK 4 * CLK 2 * CLK 4 * CLK CLK 2 * CLK CLK 2 * CLK Outputs QB0-QB3 2 * CLK 4 * CLK CLK 2 * CLK 2 * CLK 4 * CLK CLK 2 * CLK QC0, QC1 CLK CLK CLK CLK CLK CLK CLK CLK 1. Output frequency relationship with respect to input reference frequency CLK. 68 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9315 Example Configurations for the MPC9315 fref=80 MHz CLK0 CLK1 REF_SEL FB0 FB1 FBSEL FSELA FSELB FSELC PSELA QA0 QA1 QB0 QB1 QB2 QB3 QC0 QC1 fref = 75 MHz CLK0 CLK1 REF_SEL FB0 FB1 FBSEL 1 0 FSELA FSELB FSELC PSELA QA0 QA1 QB0 QB1 QB2 QB3 QC0 QC1 160 MHz 80 MHz 75 MHz 75 MHz 40 MHz 75 MHz MPC9315 80 MHz (Feedback) MPC9315 75 MHz (Feedback) MPC9315 default configuration (feedback of QB3 = 100 MHz). All control pins are left open. Frequency range Input QA outputs QB outputs QC outputs Min 37.50 MHz 75.00 MHz 37.50 MHz 18.75 MHz Max 80 MHz 160 MHz 80 MHz 40 MHz MPC9315 1:1 frequency configuration (feedback of QB3 = 75 MHz). FSELA = H, FSELC = L. All other control pins are left open. Frequency range Input QA outputs QB outputs QC outputs Min 37.50 MHz 37.50 MHz 37.50 MHz 37.50 MHz Max 80 MHz 80 MHz 80 MHz 80 MHz Figure 3. MPC9315 Default Configuration Figure 4. MPC9315 Zero Delay Buffer Configuration fref = 33 MHz CLK0 CLK1 REF_SEL FB0 FB1 FBSEL QA0 QA1 QB0 QB1 QB2 QB3 QC0 QC1 66 MHz inv, fref = 19 MHz CLK0 CLK1 REF_SEL FB0 FB1 FBSEL FSELA FSELB FSELC PSELA QA0 QA1 QB0 QB1 QB2 QB3 QC0 QC1 76 MHz 66 MHz 38 MHz 1 1 FSELA FSELB FSELC PSELA MPC9315 33 MHz 19 MHz MPC9315 19 MHz (Feedback) 33 MHz (Feedback) MPC9315 1:1 frequency configuration (feedback of QC1 = 33 MHz). FSELA = PSELA = H. All other control pins are left open. Frequency range Input QA outputs QB outputs QC outputs Min 18.75 MHz 37.50 MHz 37.50 MHz 18.75 MHz Max 40 MHz 80 MHz 80 MHz 40 MHz MPC9315 4x, 2x, 1x frequency configuration (feedback of QC1 = 19 MHz). All control pins are left open. Frequency range Input QA outputs QB outputs QC outputs Min 18.75 MHz 75.00 MHz 37.50 MHz 18.75 MHz Max 40 MHz 160 MHz 80 MHz 40 MHz Figure 5. MPC9315 180 Phase Inversion Configuration Figure 6. MPC9315 x4 Multiplier Configuration FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 69 MPC9315 Using the MPC9315 in Zero-Delay Applications The external feedback option of the MPC9315 PLL allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. The remaining insertion delay (skew error) of the MPC9315 in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset (SPO or t()), I/O jitter (tJIT(), phase or long-term jitter), feedback path delay and the output-to-output skew (tSK(O) relative to the feedback output. Calculation of Part-to-Part Skew The MPC9315 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (TCLK or PCLK) of two or more MPC9315 are connected together, the maximum overall timing uncertainty from the common TCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() * CF This maximum timing uncertainty consists of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: TCLKCOMMON --t() QFBDevice 1 tPD,LINE(FB) The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -300 ps to +300 ps relative to TCLK (VCC=3.3V and fVCO = 160 MHz): tSK(PP) = [-150ps...150ps] + [-150ps...150ps] + [(10ps @ -3)...(10ps @ 3)] + tPD, LINE(FB) tSK(PP) = [-300ps...300ps] + tPD, LINE(FB) Above equation uses the maximum I/O jitter number shown in the AC characteristic table for VCC=3.3V (10 ps RMS). I/O jitter is frequency dependant with a maximum at the lowest VCO frequency (160 MHz for the MPC9315). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in Figure 8. Max. I/O Jitter (RMS) versus frequency for VCC=2.5V and Figure 9. Max. I/O Jitter (RMS) versus frequency for VCC=3.3V can be used to derive a smaller I/O jitter number at the specific VCO frequency, resulting in tighter timing limits in zero-delay mode and for part-to-part skew tSK(PP). I/O Jitter (RMS) versus VCO frequency 30 tJIT() [ps] ms 25 20 15 10 5 tJIT() +tSK(O) +t() Any QDevice 1 0 75 100 125 150 175 200 VCO frequency [MHz] QFBDevice2 Figure 8. Max. I/O Jitter (RMS) versus frequency for VCC=2.5V I/O Jitter (RMS) versus VCO frequency tJIT() 30 tSK(PP) tJIT() [ps] ms 25 20 15 10 5 0 75 100 125 150 175 200 VCO frequency (MHz) Any QDevice 2 Max. skew +tSK(O) Figure 7. MPC9315 max. Device-to-Device Skew Due to the statistical nature of I/O jitter, an RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12. Table 12. Confidence Factor CF CF 1 2 3 4 5 6 Probability of Clock Edge within the Distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 Figure 9. Max. I/O Jitter (RMS) versus frequency for VCC=3.3V Power Supply Filtering The MPC9315 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Noise on the VCCA (PLL) power supply impacts the device characteristics, for 70 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9315 instance I/O jitter. The MPC9315 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9315. Figure 10. VCCA Power Supply Filter illustrates a typical power supply filter scheme. The MPC9315 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the VCCA pin. The resistor RF shown in Figure 10. VCCA Power Supply Filter must have a resistance of 270 (VCC=3.3V) or 9-10 (VCC=2.5V) to meet the voltage drop criteria. RF = 270 for VCC = 3.3V RF = 9-10 for VCC = 2.5V VCC RF CF 10 nF CF = 1 F for VCC = 3.3V CF = 22 F for VCC = 2.5V VCCA MPC9315 VCC 33...100 nF MPC9315 OUTPUT BUFFER IN 14 Driving Transmission Lines The MPC9315 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9315 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 11. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9315 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9315 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA Figure 10. VCCA Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 10. VCCA Power Supply Filter, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9315 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 11. Single versus Dual Transmission Lines The waveform plots in Figure 11. Single versus Dual Transmission Lines show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9315 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9315. The output waveform in Figure 12. Single versus Dual Line Termination Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 71 MPC9315 of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+17+25) = 1.31V 3.0 2.5 VOLTAGE (V) 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 MPC9315 OUTPUT BUFFER 14 At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 13. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 13. Optimized Dual Line Termination Figure 12. Single versus Dual Line Termination Waveforms MPC9315 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 14. CLK0, CLK1 MPC9315 AC test reference 72 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9315 VCC CLK0, 1 VCC / 2 GND FB0, 1 t() VCC VCC / 2 GND Figure 15. Propagation delay (t(), SPO) test reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage tSK(O) VCC VCC / 2 GND VCC VCC / 2 GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 16. Output Duty Cycle (DC) Figure 17. Output-to-output Skew tSK(O) TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 18. Cycle-to-cycle Jitter Figure 19. Period Jitter TCLK0, 1 VCC=3.3V FB0, 1 TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles 2.4 0.55 tF tR VCC=2.5V 1.8V 0.6V Figure 20. I/O Jitter Figure 21. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 73 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9330 Rev 4, 08/2004 3.3V 1:60 LVCMOS PLL Clock Generator The MPC9330 is a 3.3 V compatible, 1:6 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance telecomm, networking and computing applications. With output frequencies up to 120 MHz and output skews less than 150 ps the device meets the needs of the most demanding clock applications. The MPC9330 is specified for the temperature range of 0C to +70C. Features * * * * * * * * * * * * * * * * * 1:6 PLL based low-voltage clock generator 3.3 V power supply Generates clock signals up to 120 MHz Maximum output skew of 150 ps On-chip crystal oscillator clock reference Alternative LVCMOS PLL reference clock input Internal and external PLL feedback PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4 Supports zero-delay operation in external feedback mode Synchronous output clock stop in logic low eliminates output runt pulses Power_down feature reduces output clock frequency Drives up to 12 clock lines 32-lead LQFP packaging 32-lead Pb-free package available Ambient temperature range 0C to +70C Internal power-up reset Pin and function compatible to the MPC930 MPC9330 3.3V 1:6 LVCMOS PLL CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC9330 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9330 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback configuration and with the available post-PLL dividers (divide-by-2, divide-by-4 and divide-by-6), the internal VCO of the MPC9330 is running at either 4x, 8x, 12x, 16x, or 24x of the reference clock frequency. In internal feedback configuration (divide-by-16) the internal VCO is running 16x of the reference frequency. The frequency of the QA, QB, QC output banks is a division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible input as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) by deasserting the OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9330 output clock stop control allows the outputs to start and stop synchronously in the logic low state, without the potential generation of runt pulses. The MPC9330 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9330 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is packaged in a 7x7 mm2 32-lead LQFP package. 74 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9330 VCC BANK A 0 1 Ref PLL 25k FB_IN 25k VCC FB_SEL 25k VCC 25k PWR_DN VCC 25k PLL_EN FSELA FSELB FSELC 3 x 25k CLK_STOP0 CLK_STOP1 OE/MR VCC 3 x 25k POWER_ON RESET 3 0 1 1 0 FB VCO /2 /4 REF_SEL 0 1 0 1 /2 /4 /6 BANK B QB0 0 1 /16 CLK STOP QB1 BANK C QC0 CLK STOP QC1 QA0 0 1 CLK STOP QA1 25k XTAL_IN XTAL_OUT CCLK XTAL Figure 1. MPC9330 Logic Diagram REF_SEL PLL_EN 18 FB_SEL GND QB0 QB1 VCC 24 GND QA1 QA0 VCC FSELA FSELB FSELC NC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 NC 17 16 15 14 GND QC1 QC0 VCC FB_IN CLK_STOP1 CLK_STOP0 NC 13 12 11 10 9 8 GND MPC9330 2 3 4 5 6 7 PWR_DN XTAL_IN CCLK NC OE/MR It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see application section for details. Figure 2. MPC9330 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA XTAL_OUT VCC_PLL 75 MPC9330 Table 1. Pin Configuration Pin CCLK XTAL_IN, XTAL_OUT FB_IN FB_SEL REF_SEL PWR_DN FSELA FSELB FSELC PLL_EN CLK_STOP0-1 OE/MR QA0-1, QB0-1, QC0-1 GND VCC_PLL VCC I/O Input Input Input Input Input Input Input Input Input Input Input Input Output Supply Supply Supply Type LVCMOS Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock signal Crystal oscillator interface PLL feedback signal input, connect to an output Feedback select Reference clock select Output frequency and power down select Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs PLL enable/disable Clock output enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function Table 2. Function Table Control REF_SEL FB_SEL PLL_EN Default 0 0 1 0 The crystal oscillator output is the PLL reference clock Internal PLL feedback of 16. fVCO = 16 * fref Test mode with PLL disabled. The reference clock is substituted for the internal VCO output. MPC9330 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. VCO / 2 (High output frequency range) Output divider / 2 Output divider / 2 Output divider / 4 See Table 3 Outputs disabled (high-impedance state) and reset of the device. Outputs enabled (active) During reset in external feedback configuration, the PLL feedback loop is open. The VCO is tied to its lowest frequency. The MPC9330 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLK). Reset does not affect PLL lock in internal feedback configuration. 1 CCLK is the PLL reference clock External feedback. Zero-delay operation enabled for CCLK as reference clock Normal operation mode with PLL enabled. PWR_DN FSELA FSELB FSELC CLK_STOP[0:1] OE/MR 1 0 0 0 11 1 VCO / 4 (Low output frequency range) Output divider / 4 Output divider / 4 Output divider / 6 PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios. See Table 8 through Table 10 for supported frequency ranges and output to input frequency ratios. 76 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9330 Table 3. Clock Output Synchronous Disable (CLK_STOP) Function Table1 CLK_STOP0 0 0 1 1 CLK_STOP1 0 1 0 1 QA[0:1] Active Active Stopped in logic L state Active QB[0:1] Stopped in logic L state Stopped in logic L state Stopped in logic L state Active QC[0:1] Stopped in logic L state Active Active Active 1. Output operation for OE/MR=1 (outputs enabled). OE/MR=0 will disable (high-impedance state) all outputs independent on CLK_STOP[0:1] Table 4. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 5. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 6. DC Characteristics (VCC = 3.3V 5%, TA = 0C to 70C) Symbol VIH VIL VOH VOL ZOUT IIN ICC_PLL ICCQ Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current 2 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V Condition LVCMOS LVCMOS IOH=-24 mA1 IOL= 24 mA IOL= 12 mA 2.4 0.55 0.30 14 - 17 100 5.0 5.0 10 10 V V A mA mA VIN = VCC or GND VCC_PLL Pin All VCC Pins Maximum PLL Supply Current Maximum Quiescent Supply Current 1. The MPC9330 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. Inputs have pull-down or pull-up resistors affecting the input current. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 77 MPC9330 Table 7. AC Characteristics (VCC = 3.3V 5%, TA = 0C to 70C)1 Symbol fref Characteristics Input Reference Frequency PLL mode, external feedback 2 Min / 4 feedback / 8 feedback / 12 feedback / 16 feedback / 24 feedback / 16 feedback) 3 Typ Max 120 60 40 30 20 30 TBD Unit Condition PLL mode, internal feedback fVCO fXTAL fMAX VCO Lock Frequency Range5 Crystal Interface Frequency Range6 Output Frequency 50 25 16.67 12.5 8.33 12.5 MHz PLL locked MHz MHz MHz MHz MHz MHz MHz MHz MHz PLL locked MHz MHz MHz MHz % ns ns ps ps ps ps % ns ns ns ps ps ps MHz MHz MHz MHz MHz 0.55 to 2.4V 0.8 to 2.0V Input Reference Frequency in PLL bypass mode4 200 10 / 4 output / 8 output / 12 output / 16 output / 24 output 50 25 16.67 12.5 8.33 25 2 480 25 120 60 40 30 20 75 frefDC tPW, MIN tr, tf t() Reference Input Duty Cycle Minimum Input Reference Pulse Width CCLK Input Rise/Fall Time Propagation Delay (SPO)7 for the - entire fref range - fref = 8.33 MHz - fref = 50.0 MHz (within output bank) (any output) 1.0 -1.2 -400 -70 +1.2 +400 +70 50 150 45 0.1 50 55 1.0 10 10 50 35 RMS (1) / 4 feedback / 8 feedback / 12 feedback / 16 feedback / 24 feedback 10 0.8-5.0 0.5-2.0 0.3-1.0 0.25-0.6 0.2-0.5 10 300 250 70 tsk(o) DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW Output-to-Output Skew8 Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter I/O Phase Jitter PLL closed loop bandwidth9 PLL mode, external feedback tLOCK Maximum PLL Lock Time ms 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. PLL mode requires PLL_EN = 0 to enable the PLL. 3. /4 feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one /2 output to FB_IN. See Table 3 to Table 5 for other feedback configurations. 4. In bypass mode, the MPC9330 divides the input reference clock. 5. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO / FB. 6. The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio. 7. SPO is the static phase offset between CCLK and FB_IN (FB_SEL=1 and PLL locked). tsk(o) [ps] = tsk(o) [] B(fref / 360) 8. Skew data applicable for equally loaded outputs only. 9. -3 dB point of PLL transfer characteristics. 78 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9330 APPLICATIONS INFORMATION Output Power Down (PWR_DN) Timing Diagram VCO/2 VCO/4 PWR_DWN QAx (/2) QBx (/4) QCx (/6) Output Clock Stop (CLK_STOP) Timing Diagram QAx (/2) QBx (/4) QCx (/6) CLK_STOP0 CLK_STOP1 QAx (/2) QBx (/4) QCx (/6) Programming the MPC9330 The MPC9330 supports output clock frequencies from 8.33 to 120 MHz. Different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. The feedback frequency and divider should be used to situate the VCO in the frequency lock range between 200 and 480 MHz for stable and optimal operation. The FSELA, FSELB, FSELC and PWR_DN pins select the desired output clock frequencies. Possible frequency ratios of the reference clock input to the outputs are 1:4, 1:3, 1:2, 1:1, 2:3, 4:3 and 3:2. Table 8 through Table 10 illustrate the various output configurations and frequency ratios supported by the MPC9330. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 79 MPC9330 Table 8. MPC9330 Example Configurations (Internal Feedback: FB_SEL = 0) fref1 [MHz] PWR_DN 0 0 0 0 0 0 0 12.5-30.0 0 1 1 1 1 1 1 1 1 FSELA 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSELB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA[0:1]:fref ratio fref 4 fref 4 fref 4 fref 4 fref 2 fref 2 fref 2 fref 2 fref 2 fref 2 fref 2 fref 2 fref fref fref fref QB[0:1]:fref ratio QC[0:1]:fref ratio (25-60 MHz) (16.6-40 MHz) (25-60 MHz) (16.6-40 MHz) (25-60 MHz) (16.6-40 MHz) (25-60 MHz) (16.6-40 MHz) (12.5-30 MHz) (8.33-20 MHz) (12.5-30 MHz) (8.33-20 MHz) (12.5-30 MHz) (8.33-20 MHz) (12.5-30 MHz) (8.33-20 MHz) (50-120 MHz) fref 4 (50-120 MHz) fref 4 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (25-60 MHz) fref 4 (25-60 MHz) fref 4 (25-60 MHz) fref 2 (25-60 MHz) fref 2 (25-60 MHz) fref 2 (25-60 MHz) fref 2 (25-60 MHz) fref (25-60 MHz) fref (12.5-30 MHz) fref 2 (12.5-30 MHz) fref 2 (12.5-30 MHz) fref (12.5-30 MHz) fref (50-120 MHz) fref 2 (50-120 MHz) fref 4 / 3 (25-60 MHz) fref 2 (25-60 MHz) fref 4 / 3 (50-120 MHz) fref 2 (50-120 MHz) fref 4 / 3 (25-60 MHz) fref 2 (25-60 MHz) fref 4 / 3 (25-60 MHz) fref (25-60 MHz) fref 2 / 3 (12.5-30 MHz) fref (12.5-30 MHz) fref 2 / 3 (25-60 MHz) fref (25-60 MHz) fref 2 / 3 (12.5-30 MHz) fref (12.5-30 MHz) fref 2 / 3 1. fref is the input clock reference frequency (CCLK or XTAL) Table 9. MPC9330 Example Configurations (External Feedback and PWR_DN = 0) PLL Feedback fref1 [MHz] FSELA 0 VCO / 42 50-120 0 0 0 1 VCO / 83 25-60 1 1 1 0 VCO / 124 16.67-40 0 1 1 FSELB 0 0 1 1 0 0 1 1 0 1 0 1 FSELC 0 1 0 1 0 1 0 1 1 1 1 1 fref fref fref fref fref fref fref fref fref 3 fref 3 QA[0:1]:fref ratio (50-120 MHz) (50-120 MHz) (50-120 MHz) (50-120 MHz) (25-60 MHz) (25-60 MHz) (25-60 MHz) (25-60 MHz) (50-120 MHz) (50-120 MHz) fref fref fref / 2 fref / 2 fref 2 fref 2 fref fref fref 3 fref 3 / 2 fref 3 fref 3 / 2 QB[0:1]:fref ratio QC[0:1]:fref ratio (25-60 MHz) (16.6-40 MHz) (25-60 MHz) (16.6-40 MHz) (25-60 MHz) (16.6-40 MHz) (25-60 MHz) (16.6-40 MHz) (16.6-40 MHz) (16.6-40 MHz) (16.6-40 MHz) (16.6-40 MHz) (50-120 MHz) fref / 2 (50-120 MHz) fref / 3 (25-60 MHz) fref / 2 (25-60 MHz) fref / 3 (50-120 MHz) fref (50-120 MHz) fref 2 / 3 (25-60 MHz) fref (25-60 MHz) fref 2 / 3 (50-120 MHz) fref (25-60 MHz) fref (50-120 MHz) fref (25-60 MHz) fref fref 3 / 2 (25-60 MHz) fref 3 / 2 (25-60 MHz) 1. fref is the input clock reference frequency (CCLK or XTAL) 2. QAx connected to FB_IN and FSELA=0, PWR_DN=0 3. QAx connected to FB_IN and FSELA=1, PWR_DN=0 4. QCx connected to FB_IN and FSELC=1, PWR_DN=0 Table 10. MPC9330 Example Configurations (External Feedback and PWR_DN = 1) PLL Feedback fref1 [MHz] FSELA 1 VCO / 162 12.5-30 1 1 1 0 VCO / 243 8.33-20 0 1 1 FSELB 0 0 1 1 0 1 0 1 FSELC 0 1 0 1 1 1 1 1 fref fref fref fref fref 3 fref 3 QA[0:1]:fref ratio (12.5-30 MHz) (12.5-30 MHz) (12.5-30 MHz) (12.5-30 MHz) (25-60 MHz) (25-60 MHz) QB[0:1]:fref ratio fref 2 fref 2 fref fref fref 3 fref 3 (25-60 MHz) fref (25-60 MHz) fref 2 / 3 (12.5-30 MHz) fref (12.5-30 MHz) fref 2 / 3 (25-60 MHz) fref (25-60 MHz) fref QC[0:1]:fref ratio (12.5-30 MHz) (8.33-20 MHz) (12.5-30 MHz) (8.33-20 MHz) (8.33-20 MHz) (8.33-20 MHz) (8.33-20 MHz) (8.33-20 MHz) fref 3 / 2 (12.5-30 MHz) fref fref 3 / 2 (12.5-30 MHz) fref fref 3 / 2 (12.5-30 MHz) fref 3 / 2 (12.5-30 MHz) 1. fref is the input clock reference frequency (CCLK or XTAL) 2. QAx connected to FB_IN and FSELA=1, PWR_DN=1 3. QCx connected to FB_IN and FSELC=1, PWR_DN=1 80 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9330 APPLICATIONS INFORMATION Power Supply Filtering The MPC9330 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9330 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9330. Figure 3 illustrates a typical power supply filter scheme. The MPC9330 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 5 mA (10 mA maximum), assuming that a minimum of 2.985 V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 3 should have a resistance of 10-15 to meet the voltage drop criteria. RF = 10 - 15 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9330 VCC 33...100 nF MPC9330 OUTPUT BUFFER IN 14 adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC9330 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola Application Note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/ 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9330 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9330 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9330 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA Figure 3. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9330 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 4. Single versus Dual Transmission Lines The waveform plots in Figure 4 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9330 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9330. The output waveform in Figure 5. Single versus Dual Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 81 MPC9330 impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+14+25) = 1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 1. Final skew data pending specification. 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9330 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 6. Optimized Dual Line Termination VOLTAGE (V) Figure 5. Single versus Dual Waveforms MPC9930 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 7. CCLK MPC9330 AC Test Reference for Vcc = 3.3 V 82 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9330 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device FB_IN t() CCLK VCC VCC / 2 GND VCC VCC / 2 GND Figure 8. Output-to-Output Skew tSK(O) Figure 9. Propagation Delay (t(), static phase offset) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage FB_EN TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles CCLK Figure 10. Output Duty Cycle (DC) Figure 11. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 12. Cycle-to-Cycle Jitter Figure 13. Period Jitter VCC=3.3 V 2.4 0.55 tF tR Figure 14. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 83 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9331 Rev 5, 08/2004 3.3V 1:6 LVCMOS PLL Clock Generator The MPC9331 is a 3.3V compatible, 1:6 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking, and computing applications. With output frequencies up to 240 MHz and output skews less than 150 ps, the device meets the needs of most the demanding clock applications. The MPC9331 is specified for the temperature range of 0C to +70C. Features * 1:6 PLL based low-voltage clock generator * 3.3V power supply * Generates clock signals up to 240 MHz * Maximum output skew of 150 ps * Differential LVPECL reference clock input * Alternative LVCMOS PLL reference clock input * Internal and external PLL feedback * Supports zero-delay operation in external feedback mode * PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3 or x/4 * Synchronous output clock stop in logic low eliminates output runt pulses * Power_down feature reduces output clock frequency * Drives up to 12 clock lines * 32-lead LQFP packaging * 32-lead Pb-free Package Available * Ambient temperature range 0C to +70C * Internal Power-Up Reset * Pin and function compatible to the MPC931 Functional Description MPC9331 LOW VOLTAGE 3.3V LVCMOS 1:6 CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback configuration and with the available post-PLL dividers (divide-by-2, divide-by-4, and divide-by-6), the internal VCO of the MPC9331 is running at either 2x, 4x, 6x, 8x, or 12x of the reference clock frequency. In internal feedback configuration (divide-by-8) the internal VCO is running 8x of the reference frequency. The frequency of the QA, QB, QC output banks is a division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB, and FSELC pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4. The REF_SEL pin selects the differential LVPECL or the LVCMOS compatible input as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) by deasserting the OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9331 output clock stop control allows the outputs to start and stop synchronously in logic low state, without the potential generation of runt pulses. The MPC9331 is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is packaged in a 7x7 mm2 32-lead LQFP package. 84 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9331 VCC 3 x 25 K PCLK PCLK CCLK REF_SEL 25k FB_IN 25k VCC FB_SEL 25k VCC 25k PWR_DN VCC 25k PLL_EN FSELA FSELB FSELC 3 x 25 K CLK_STOP0 CLK_STOP1 OE/MR VCC 3 x 25 K POWER_ON RESET 3 0 1 1 0 FB BANK A 0 1 Ref PLL 200 - 480 MHz VCO /1 /2 0 1 0 1 /2 /4 /6 BANK B QB0 0 1 /8 CLK STOP QB1 BANK C QC0 CLK STOP QC1 QA0 0 1 CLK STOP QA1 Figure 1. MPC9331 Logic Diagram REF_SEL FB_SEL PLL_EN 18 GND QB0 QB1 VCC 24 GND QA1 QA0 VCC FSELA FSELB FSELC NC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 NC 17 16 15 14 GND QC1 QC0 VCC FB_IN CLK_STOP1 CLK_STOP0 NC 13 12 11 10 9 8 GND MPC9331 2 3 4 5 6 7 PWR_DN CCLK PCKL It is recommended to use an external RC filter for the analog VCC_PLL power supply pin. Please see application section for details. Figure 2. MPC9331 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA VCC_PLL OE/MR PCKL NC 85 MPC9331 Table 1. Pin Configuration Pin CCLK PCLK, PCLK FB_IN FB_SEL REF_SEL PWR_DN FSELA FSELB FSELC PLL_EN CLK_STOP0-1 OE/MR QA0-1, QB0-1, QC0-1 GND VCC_PLL VCC I/O Input Input Input Input Input Input Input Input Input Input Input Input Output Supply Supply Supply Type LVCMOS LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock signal Differential PECL reference clock signal PLL feedback signal input, connect to an output Feedback select Reference clock select Output frequency and power down select Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs PLL enable/disable Clock output enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Negative power supply (GND) PLL positive power supply (analog power supply). It is recommended to use external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function Table 2. Function Table Control REF_SEL FB_SEL 0 1 Default 0 PCLK is the PLL reference clock Internal PLL feedback of 8. fVCO = 8 * fref 1 CCLK is the PLL reference clock External feedback. Zero-delay operation enabled for CCLK or PCLK as reference clock Normal operation mode with PLL enabled. PLL_EN 1 Test mode with PLL disabled. The reference clock is substituted for the internal VCO output. MPC9331 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. VCO / 1 (High output frequency range) Output divider / 2 Output divider / 2 Output divider / 4 PWR_DN FSELA FSELB FSELC OE/MR 1 0 0 0 1 VCO / 2 (Low output frequency range) Output divider / 4 Output divider / 4 Output divider / 6 Outputs disabled (high-impedance state) and reset of the device. Outputs enabled (active) During reset in external feedback configuration, the PLL feedback loop is open. The VCO is tied to its lowest frequency. The MPC9331 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLK or PCLK). Reset does not affect PLL lock in internal feedback configuration. See Table 3 CLK_STOP[0:1] 11 PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios. See Table 8 through Table 10 for supported frequency ranges and output to input frequency ratios. 86 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9331 Table 3. Clock Output Synchronous Disable (CLK_STOP) Function Table1 CLK_STOP0 0 0 1 1 CLK_STOP1 0 1 0 1 QA[0:1] Active Active Stopped in logic L state Active QB[0:1] Stopped in logic L state Stopped in logic L state Stopped in logic L state Active QC[0:1] Stopped in logic L state Active Active Active 1. Output operation for OE/MR=1 (outputs enabled). OE/MR=0 will disable (high-impedance state) all outputs independent on CLK_STOP[0:1] Table 4. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 5. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 6. DC Characteristics (VCC = 3.3V 5%, TA = 0C to 70C) Symbol VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICC_PLL ICCQ Characteristics Input high voltage Input low voltage Peak-to-peak input voltage Common Mode Range Output High Voltage Output Low Voltage Output impedance Input Current3 8.0 14 - 17 200 12 26 PCLK, PCLK PCLK, PCLK 250 1.0 2.4 0.55 0.30 VCC - 0.6 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V mV V V V V A mA mA VIN = VCC or GND VCC_PLL Pin All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -24 mA2 IOL = 24 mA IOL = 12 mA Maximum PLL Supply Current Maximum Quiescent Supply Current4 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification 2. The MPC9331 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 3. Inputs have pull-down or pull-up resistors affecting the input current. 4. OE/MR=0 (outputs in high-impedance state). FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 87 MPC9331 Table 7. AC Characteristics (VCC = 3.3V 5%, TA = 0C to 70C)1 Symbol fREF Characteristics Input reference frequency PLL mode, external feedback /2 feedback /4 feedback /6 feedback /8 feedback /12 feedback (/8 feedback) Min 100.0 50.0 33.3 25.0 16.67 25.0 200 /2 output /4 output /6 output /8 output /12 output PCLK, PCLK PCLK, PCLK 100.0 50.0 33.3 25.0 16.67 400 1.2 2.0 1.0 CCLK to PCLK to FB_INg CCLK or PCLK to FB_IN8 FB_IN7 -250 -180 -3.0 -130 -30 -50 +120 +3.0 150 (T/2)-500 0.1 T/2 (T/2)+500 1.0 8.0 10 200 125 RMS (1 ) / 4 feedback / 6 feedback / 8 feedback /12 feedback 2.0-8.0 1.2-4.0 1.0-3.0 0.7-2.0 10 25 Typ Max 240.0 120.0 80.0 60.0 40.0 60.0 240 480 240.0 120.0 80.0 60.0 40.0 1000 VCC - 0.9 Unit Condition MHz PLL locked MHz MHz MHz MHz MHz MHz MHz MHz PLL locked MHz MHz MHz MHz mV V ns ns ps ps ps ps ns ns ns ps ps ps MHz MHz MHz MHz ms 0.55 to 2.4V 0.8 to 2.0V FB_SEL = 1 and PLL locked LVPECL LVPECL PLL mode, internal feedback fVCO fMAX VCO lock frequency range3 Output Frequency Input reference frequency in PLL bypass mode2 VPP VCMR4 tPW,MIN tR, tF t() Peak-to-peak input voltage Common Mode Range Input Reference Pulse Width5 CCLK Input Rise/Fall Time6 Propagation Delay (static phase offset) Output-to-output Skew Output duty cycle9 Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter10 Period Jitter I/O Phase Jitter PLL closed loop bandwidth11 PLL mode, external feedback tsk(O) DC tR, tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW tLOCK 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Maximum PLL Lock Time AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9331 divides the input reference clock. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO / FB. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF,MIN. The MPC9331 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. Data valid for fREF=50 MHz and a PLL feedback of /8 (e.g. QAx connected to FB_IN and FSELA=1, PWR_DN=1). Data valid for 16.67 MHz < fREF < 100 MHz and any feedback divider. tsk(O) [s] = tsk(O) [] / (fREF 360). Output duty cycle is DC = (0.5 500 ps fOUT) 100%. (e.g. the DC range at fOUT = 100 MHz is 45% < DC < 55%). All outputs in /4 divider configuration. -3 dB point of PLL transfer characteristics. 88 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9331 APPLICATIONS INFORMATION Output Power Down (PWR_DN) Timing Diagram VCO/2 VCO/4 PWR_DWN QAx (/2) QBx (/4) QCx (/6) Output Clock Stop (CLK_STOP) Timing Diagram QAx (/2) QBx (/4) QCx (/6) CLK_STOP0 CLK_STOP1 QAx (/2) QBx (/4) QCx (/6) Programming the MPC9331 The MPC9331 supports output clock frequencies from 16.67 to 240 MHz. Different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. The feedback frequency and divider should be used to situate the VCO in the frequency lock range between 200 and 480 MHz for stable and optimal operation. The FSELA, FSELB, FSELC and PWR_DN pins select the desired output clock frequencies. Possible frequency ratios of the reference clock input to the outputs are 4:1, 3:1, 2:1, 1:1, 1:2, 2:3 and 3:2. Table 8 illustrates the various output configurations and frequency ratios supported by the MPC9331. See also Table 9 and Table 10 for further reference. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 89 MPC9331 Table 8. MPC9331 Example Configurations (Internal Feedback: FB_SEL = 0) fref1 [MHz] PWR_DN 0 0 0 0 0 0 0 25.0 - 60.0 0 1 1 1 1 1 1 1 1 FSELA 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSELB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA[0:1]:fref ratio fref 4 fref 4 fref 4 fref 4 fref 2 fref 2 fref 2 fref 2 fref 2 fref 2 fref 2 fref 2 fref fref fref fref QB[0:1]:fref ratio QC[0:1]:fref ratio (50-120 MHz) (33.3-80 MHz) (50-120 MHz) (33.3-80 MHz) (50-120 MHz) (33.3-80 MHz) (50-120 MHz) (33.3-80 MHz) (25.0-60 MHz) (16.67-40 MHz) (25.0-60 MHz) (16.67-40 MHz) (25.0-60 MHz) (16.67-40 MHz) (25.0-60 MHz) (16.67-40 MHz) (100-240 MHz) fref 4 (100-240 MHz) fref 4 (100-240 MHz) fref 2 (100-240 MHz) fref 2 (50-120 MHz) fref 4 (50-120 MHz) fref 4 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref (50-120 MHz) fref (25.0-60 MHz) fref 2 (25.0-60 MHz) fref 2 (25.0-60 MHz) fref (25.0-60 MHz) fref (100-240 MHz) fref 2 (100-240 MHz) fref 4/3 (50-120 MHz) fref 2 (50-120 MHz) fref 4/3 (100-240 MHz) fref 2 (100-240 MHz) fref 4/3 (50-120 MHz) fref 2 (50-120 MHz) fref 4/3 (50-120 MHz) fref (50-120 MHz) fref 2/3 (25.0-60 MHz) fref (25.0-60 MHz) fref 2/3 (50-120 MHz) fref (50-120 MHz) fref 2/3 (25.0-60 MHz) fref (25.0-60 MHz) fref 2/3 1. fref is the input clock reference frequency (CCLK or PCLK) Table 9. MPC9331 Example Configurations (External Feedback and PWR_DN = 0) PLL Feedback fref1 [MHz] 100 - 240 FSELA FSELB FSELC 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 QA[0:1]:fref ratio fref (100-240 MHz) fref (100-240 MHz) fref (100-240 MHz) fref (100-240 MHz) fref (50-120 MHz) fref (50-120 MHz) fref (50-120 MHz) fref (50-120 MHz) fref 3 (100-240 MHz) fref 3 (100-240 MHz) fref 3 / 2 (50-120 MHz) fref 3 / 2 (50-120 MHz) QB[0:1]:fref ratio fref fref fref / 2 fref / 2 fref 2 fref 2 fref fref fref 3 fref 3 / 2 fref 3 fref 3 / 2 (100-240 MHz) (100-240 MHz) (50-120 MHz) (50-120 MHz) (100-240 MHz) (100-240 MHz) (100-240 MHz) (100-240 MHz) (100-240 MHz) (50-120 MHz) (100-240 MHz) (50-120 MHz) QC[0:1]:fref ratio fref / 2 fref / 3 fref / 2 fref / 3 fref fref 2/3 fref fref 2 / 3 fref fref fref fref (50-120 MHz) (33.3-80 MHz) (50-120 MHz) (33.3-80 MHz) (50-120 MHz) (33.3-80 MHz) (50-120 MHz) (33.3-80 MHz) (33.3-80 MHz) (33.3-80 MHz) (33.3-80 MHz) (33.3-80 MHz) VCO / 22 50 -120 VCO / 43 33.3 - 80 VCO / 64 1. 2. 3. 4. fref is the input clock reference frequency (CCLK or PCLK) QAx connected to FB_IN and FSELA=0, PWR_DN=0 QAx connected to FB_IN and FSELA=1, PWR_DN=0 QCx connected to FB_IN and FSELC=1, PWR_DN=0 PLL Feedback fref1 [MHz] Table 10. MPC9331 Example Configurations (External Feedback and PWR_DN = 1) FSELA 1 VCO / 82 25.0 - 60.0 1 1 1 0 VCO / 123 16.67 - 40 0 1 1 FSELB 0 0 1 1 0 1 0 1 FSELC 0 1 0 1 1 1 1 1 fref fref fref fref fref 3 fref 3 fref 3 / 2 fref 3 / 2 QA[0:1]:fref ratio QB[0:1]:fref ratio (50-120 MHz) fref (50-120 MHz) fref 2/3 (25-60 MHz) fref (25-60 MHz) fref 2/3 (50-120 MHz) fref (25-60 MHz) fref (50-120 MHz) fref (25-60 MHz) fref QC[0:1]:fref ratio (2.25-60 MHz) (16.6-40 MHz) (25-60 MHz) (16.6-40 MHz) (16.67-40 MHz) (16.67-40 MHz) (16.67-40 MHz) (16.67-40 MHz) 25-60 MHz) fref 2 (25-60 MHz) fref 2 (25-60 MHz) fref (25-60 MHz) fref (50-120 MHz) fref 3 (50-120 MHz) fref 3 / 2 (25-60 MHz) fref 3 (25-60 MHz) fref 3 / 2 1. fref is the input clock reference frequency (CCLK or PCLK) 2. QAx connected to FB_IN and FSELA=1, PWR_DN=1 3. QCx connected to FB_IN and FSELC=1, PWR_DN=1 90 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9331 APPLICATIONS INFORMATION Power Supply Filtering The MPC9331 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9331 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9331. Figure 3 illustrates a typical power supply filter scheme. The MPC9331 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 8 mA (12 mA maximum), assuming that a minimum of 3.0V must be maintained on the VCC_PLL pin. RF = 10 - 15 CF = 22 F VC RF CF 10 nF VCC_PLL MPC9331 VCC 33...100 nF MPC9331 OUTPUT BUFFER IN 14 Driving Transmission Lines The MPC9331 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9331 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9331 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9331 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 Figure 3. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9331 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. RS = 36 Figure 4. Single versus Dual Transmission Lines The waveform plots in Figure 5. Single versus Dual Line Termination Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9331 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9331. The output waveform in Figure 5. Single versus Dual Line Termination Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 91 MPC9331 combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+14+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 1. Final skew data pending specification. 3.0 2.5 VOLTAGE (V) 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9331 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 6. Optimized Dual Line Termination Figure 5. Single versus Dual Line Termination Waveforms MPC9931 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 7. CCLK MPC9331 AC Test Reference for Vcc = 3.3V 92 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9331 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device FB_IN t() CCLK VCC VCC / 2 GND VCC VCC / 2 GND Figure 8. Output-to-Output Skew tSK(O) Figure 9. Propagation Delay (t(), Static Phase offset) Test Reference VCC VCC / 2 GND tP FB_IN T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage TJIT(y) = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles CCLK Figure 10. Output Duty Cycle (DC) Figure 11. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 12. Cycle-to-Cycle Jitter Figure 13. Period Jitter VCC=3.3V 2.4 0.55 tF tR Figure 14. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 93 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9350 Rev 4, 08/2004 Low Voltage PLL Clock Driver The MPC9350 is a 2.5V and 3.3V compatible, PLL-based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 200 MHz and maximum output skews of 150 ps, the MPC9350 is ideal for the most demanding clock tree designs. The device offers 9 low skew clock outputs, with each one configurable to support the clocking needs of the various high-performance microprocessors, including the PowerQuicc II integrated communication microprocessor. The extended temperature range of the MPC9350 supports telecommunication and networking requirements. The device employs a fully differential PLL design to minimize cycle-to-cycle and long-term jitter. Features * * * * * * * * * * * * * * * * 9 output LVCMOS PLL clock generator 25 - 200 MHz output frequency range 2.5V and 3.3V compatible Compatible to various microprocessors such as PowerQuicc II Supports networking, telecommunications and computer applications Fully integrated PLL Configurable outputs: divide-by-2, 4 and 8 of VCO frequency Selectable output to input frequency ratio of 8:1, 4:1, 2:1 or 1:1 Oscillator or crystal reference inputs Internal PLL feedback Output disable PLL enable/disable Low skew characteristics: maximum 150 ps output-to-output 32-lead LQFP package 32-lead Pb-free Package Available Temperature range -40C to +85C MPC9350 LOW VOLTAGE 3.3V AND 2.5V PLL CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC9350 generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference clock signal. The internal PLL allows the MPC9350 to operate in frequency locked condition and to multiply the input reference clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable PLL feedback frequency ratios are available on the MPC9350 to provide input frequency range flexibility. The FBSEL pin selects between divide-by-16 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match the VCO frequency range. With the available feedback output dividers, the internal VCO of the MPC9350 is running at either 16x or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 16:1, 8:1, 4:1 and 2:1. The REF_SEL pin selects the crystal oscillator input or the LVCMOS compatible reference input (TCLK). TCLK also provides an external test clock in static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly to the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path. The MPC9350 is fully 2.5V and 3.3V compatible and requires no external loop filter components. The on-chip crystal oscillator requires no external components beyond a series resonant crystals. All inputs except the crystal oscillator interface accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9350 outputs can drive one or two traces giving the device an effective fanout of 1:18. The device is packaged in a 7x7 mm2 32-lead LQFP package. 94 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9350 XTAL1 XTAL2 TCLK REF_SEL (PULLDOWN) (PULLDOWN) 0 Ref PLL 1 0 /2 0 D 1 Q QA 1 /4 /8 FB 200 - 400 MHz 0 1 FBSEL PLL_EN FSELA FSELB FSELC FSELD (PULLDOWN) (PULLUP) (PULLDOWN) (PULLDOWN) (PULLDOWN) (PULLDOWN) /16 /32 0 D 1 Q QB QC0 0 D 1 QD0 QD1 0 D 1 QD3 QD4 Q QD2 Q QC1 OE (PULLDOWN) Figure 1. MPC9350 Logic Diagram VCCO VCCO GND GND 17 16 15 14 QD2 VCCO QD3 GND QD4 VCCO OE XTAL2 13 12 11 10 9 1 2 3 4 5 6 7 8 XTAL1 QC0 QC1 QD0 QD1 18 GND 24 GND QB VCCO QA GND TCLK PLL_EN REF_SEL 25 26 27 28 29 30 31 32 23 22 21 20 19 MPC9350 FSELA FSELB FSELC Figure 2. Pinout: 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA FSELD FBSEL VCCA 95 MPC9350 Table 1. Pin Description Number XTAL1, XTAL2 TCLK FBSEL REF_SEL FSELA FSELB FSELC FSELD OE QA QB QC0, QC1 QD0 - QD4 GND VCCA VCC Input Input Input Input Input Input Input Input Input Output Output Output Output Supply Supply Supply Name Type Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC Crystal oscillator terminals Single ended reference clock signal or test clock Selects feedback divider ratio Selects input reference source Output A divider selection Output B divider selection Outputs C divider selection Outputs D divider selection Output enable/disable Bank A clock output Bank B clock output Bank C clock outputs Bank D clock outputs Negative power supply Positive power supply for the PLL Positive power supply for I/O and core Description Table 2. Function Table Control REF_SEL PLL_EN FBSEL OE FSELA FSELB FSELC FSELD Default 0 1 0 0 0 0 0 0 Selects XTAL Test mode with PLL disabled. The input clock is directly routed to the output dividers Selects feedback divider / 32 VCO = 32 * Input reference clock Outputs enabled QA = VCO / 2 QB = VCO / 4 QC = VCO / 4 QD = VCO / 4 0 Selects TCLK PLL enabled. The VCO output is routed to the output dividers Selects feedback divider / 16 VCO = 16 * Input reference clock Outputs disabled QA = VCO / 4 QB = VCO / 8 QC = VCO / 8 QD = VCO / 8 1 Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -40 Characteristics Min -0.3 -0.3 -0.3 Max 4.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. 96 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9350 Table 4. DC Characteristics (VCC = 3.3V 5%, TA = -40 to 85C) Symbol VIH VIL VOH VOL IIN ZOUT CIN CPD ICCA ICC VTT Characteristics Input high voltage Input low voltage Output High Voltage Output Low Voltage Input Current Output impedance Input capacitance Power Dissipation Capacitance Maximum PLL Supply Current Maximum Quiescent Supply Current Output termination voltage VCC/2 14 - 17 4.0 10 10 1.0 Min 2.0 -0.3 2.4 0.55 0.30 200 Typ Max VCC + 0.3 0.8 Unit V V V V V A pF pF mA mA V Per Output VCCA Pin All VCC Pins Condition LVCMOS LVCMOS IOH=-24 mA1 IOL= 24 mA IOL= 12 mA VIN = 0V or VIN = VCC 1. The MPC9350 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. Table 5. AC Characteristics (VCC = 3.3V 5% or VCC = 2.5V 5%, TA = -40 to 85C)1 Symbol fref Characteristics Input Frequency / 16 feedback / 32 feedback Static Test Mode fXTAL fVCO fMAX Crystal Oscillator Frequency VCO Frequency Maximum Output Frequency / 2 output / 4 output / 8 output Reference Input Duty Cycle TLCK Input Rise/Fall Time Output-to-output Skew Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time PLL closed loop bandwidth / 16 feedback (VCC = 3.3V) / 16 feedback (VCC = 2.5V) / 32 feedback (VCC = 3.3V) / 32 feedback (VCC = 2.5V) Cycle-to-cycle jitter Period Jitter Maximum PLL Lock Time I/O Phase Jitter (RMS) 5 - 20 single frequency multiple frequencies / 16 feedback / 32 feedback 2.0 - 8.0 1.0 - 4.0 1.5 - 3.5 0.7 - 2.0 30 100 30 80 200 300 150 200 1 45 0.1 VCC = 2.5V VCC = 3.3V 45 50 0.5 12.5 6.25 0 10 200 100 50 25 25 25 12.5 300 25 400 200 100 50 75 1.0 1.0 150 55 1.0 10 10 MHz FBSEL = 1 MHz FBSEL = 0 MHz PLL_EN = 0 MHz XTAL inputs MHz PLL_EN = 1 MHz MHz MHz % ns ns ps ps ns ns ns MHz MHz MHz MHz ps ps ps ps ms ps RMS value T=Clock period see Figure 10 0.7V to 1.7V 0.8V to 2.0V Min Typ Max Unit Condition frefDC tr, tf tsk(o) tPW tr, tf tPLZ, HZ tPZL, LZ BW tJIT(CC) tJIT(PER) tLOCK tJIT() 1. AC characteristics apply for parallel output termination of 50 to VTT. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 97 MPC9350 Table 6. DC Characteristics (VCC = 2.5V 5%, TA = -40 to 85C) Symbol VIH VIL VOH VOL ZOUT IIN CIN CPD ICCA ICC VTT Characteristics Input high voltage Input low voltage Output High Voltage Output Low Voltage Output impedance Input Current Input capacitance Power Dissipation Capacitance Maximum PLL Supply Current Maximum Quiescent Supply Current Output termination voltage VCC/2 4.0 10 10 1.0 17 - 20 200 Min 1.7 -0.3 1.8 0.6 Typ Max VCC + 0.3 0.7 Unit V V V V A pF pF mA mA V Per Output VCCA Pin All VCC Pins VIN = 0V or VIN = VCC Condition LVCMOS LVCMOS IOH = -15 mA1 IOL = 15 mA 1. The MPC9350 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output. 98 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9350 APPLICATIONS INFORMATION Programming the MPC9350 The MPC9350 clock driver outputs can be configured into several divider modes.In addition, the internal feedback of the device allows for flexibility in establishing two input to output frequency relationships. The output division settings establish the output frequency relationship. The output divider of the four output groups allows the user to configure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even dividers ensures that the output duty cycle is always 50%. Table 7 and Table 8 illustrate the various output configurations. The tables describe the outputs using the input clock frequency CLK as a reference. In addition, it must be ensured that the VCO will be stable given the frequency of the outputs desired. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL supports output frequencies from 25 MHz to 200 MHz while the VCO frequency range is specified from 200 MHz to 400 MHz and should not be exceeded for stable operation. Table 7. Output Frequency Relationship1 FBSEL = 1, (VC0 = 32 * CLK) Inputs FSELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA 16 * CLK 16 * CLK 16 * CLK 16 * CLK 16 * CLK 16 * CLK 16 * CLK 16 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK QB 8 * CLK 8 * CLK 8 * CLK 8 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK Outputs QC0, QC1 8 * CLK 8 * CLK 4 * CLK 4 * CLK 8 * CLK 8 * CLK 4 * CLK 4 * CLK 8 * CLK 8 * CLK 4 * CLK 4 * CLK 8 * CLK 8 * CLK 4 * CLK 4 * CLK QD0-QD4 8 * CLK 4 * CLK 8 * CLK 4 * CLK 8 * CLK 4 * CLK 8 * CLK 4 * CLK 8 * CLK 4 * CLK 8 * CLK 4 * CLK 8 * CLK 4 * CLK 8 * CLK 4 * CLK 1. Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351 data sheet for more input to output relationships in external feedback mode. Table 8. Output Frequency Relationship1 FBSEL = 0, (VC0 = 16 * CLK) Inputs FSELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA 8 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK QB 4 * CLK 4 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK 2 * CLK 2 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK 2 * CLK 2 * CLK Outputs QC0, QC1 4 * CLK 4 * CLK 2 * CLK 2 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK QD0-QD4 4 * CLK 2 * CLK 4 * CLK 2 * CLK 4 * CLK 2 * CLK 4 * CLK 2 * CLK 4 * CLK 2 * CLK 4 * CLK 2 * CLK 4 * CLK 2 * CLK 4 * CLK 2 * CLK 1. Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351 data sheet for more input to output relationships in external feedback mode. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 99 MPC9350 Power Supply Filtering The MPC9350 is a mixed analog/digital product and as such, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC9350 provides separate power supplies for the output buffers (VCCO) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC9350. Figure 3 illustrates a typical power supply filter scheme. The MPC9350 is most susceptible to noise with spectral content in the 10kHz to 5MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC9350. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 10 mA (15 mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin. Very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 3 must have a resistance of 10-15 to meet the voltage drop criteria for VCC = 3.3V. For VCC = 2.5V operation, RS must be selected to maintain the minimum VCC specification of 2.375V for the PLL supply pin for proper operation. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. It is recommended that the user start with an 8-10 resistor to avoid potential VCC drop problems and only move to the higher value resistors when a higher level of attenuation is shown to be needed. 2.5V or 3.3V Although the MPC9350 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC9350 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 15, the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9350 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9350 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9350 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA MPC9350 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 RS=5-15 VCCA MPC9350 VCC 0.01F 0.01F 22F Figure 4. Single versus Dual Transmission Lines The waveform plots in Figure 5. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the MPC9350 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to Figure 3. Power Supply Filter 100 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9350 maintain the tight output-to-output skew of the MPC9350. The output waveform in Figure 5 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 17 VL = 3.0 (25 / (18+17+25)) = 1.25V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment toward the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9350 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 6. Optimized Dual Line Termination VOLTAGE (V) Figure 5. Single versus Dual Waveforms MPC9350 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 7. TCLK MPC9350 AC Test Reference for Vcc = 3.3V and Vcc = 2.5V FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 101 MPC9350 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage VCC VCC / 2 GND Figure 8. Output-to-Output Skew tSK(O) Figure 9. Output Duty Cycle (DC) VCC=3.3V 2.4 0.55 tF tR VCC=2.5V 1.8V 0.6V The time from the maximum low level voltage to minimum high level of a clock signal, expressed in ns Figure 10. Transition Time Test Reference TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 11. Cycle-to-Cycle Jitter Figure 12. Period Jitter 102 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9351 Rev 3, 08/2004 Low Voltage PLL Clock Driver The MPC9351 is a 2.5 V and 3.3 V compatible, PLL based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 200 MHz and a maximum output skew of 150 ps the MPC9351 is an ideal solution for the most demanding clock tree designs. The device offers 9 low skew clock outputs, each is configurable to support the clocking needs of the various high-performance microprocessors including the PowerQuicc II integrated communication microprocessor. The extended temperature range of the MPC9351 supports telecommunication and networking requirements.The device employs a fully differential PLL design to minimize cycle-to-cycle and long-term jitter. Features * * * * * * * * * * * * * * * 9 outputs LVCMOS PLL clock generator 25 - 200 MHz output frequency range Fully integrated PLL 2.5 V and 3.3 V compatible Compatible to various microprocessors such as PowerQuicc II Supports networking, telecommunications and computer applications Configurable outputs: divide-by-2, 4 and 8 of VCO frequency LVPECL and LVCMOS compatible inputs External feedback enables zero-delay configurations Output enable/disable and static test mode (PLL enable/disable) Low skew characteristics: maximum 150 ps output-to-output Cycle-to-cycle jitter max. 22 ps RMS 32-lead LQFP package 32-lead Pb-free Package Available Ambient Temperature Range -40C to +85C MPC9351 LOW VOLTAGE 2.5 V AND 3.3 V PLL CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC9351 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation of the MPC9351 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-2, divide-by-4 and divide-by-8 the internal VCO of the MPC9351 is running at either 2x, 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either the one-half, one-fourth or one-eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output-to-input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK). The MPC9351 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9351 is fully 2.5 V and 3.3 V compatible and requires no external loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9351 outputs can drive one or two traces giving the device an effective fanout of 1:18. The device is packaged in a 7x7 mm2 32-lead LQFP package. Application Information The fully integrated PLL of the MPC9351 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 103 MPC9351 PCLK PCLK TCLK REF_SEL EXT_FB (PULLUP) (PULLDOWN) (PULLDOWN) (PULLDOWN) 0 Ref 1 PLL 0 /2 0 D 1 Q QA 1 /4 /8 FB 200 - 400 MHz 0 D 1 Q QB PLL_EN (PULLUP) QC0 0 (PULLDOWN) (PULLDOWN) (PULLDOWN) (PULLDOWN) 0 D 1 QD3 QD4 Q QD2 D 1 QD0 QD1 Q QC1 FSELA FSELB FSELC FSELD OE (PULLDOWN) The MPC9351 requires an external RC filter for the analog power supply pin VCCA. Please see application section for details. Figure 1. MPC9351 Logic Diagram VCCO VCCO GND 24 GND QB VCCO QA GND TCLK PLL_EN REF_SEL 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 GND 17 16 15 14 QD2 VCCO QD3 GND QD4 VCCO OE PCLK 13 12 11 10 9 8 PCLK QC0 QC1 QD0 MPC9351 2 3 4 5 6 VCCA EXT_FB FSELA FSELB FSELC FSELD Figure 2. Pinout: 32-Lead Package Pinout (Top View) 104 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GND QD1 7 MPC9351 Table 1. Pin Descriptions Number PCLK, PCLK TCLK EXT_FB REF_SEL FSELA FSELB FSELC FSELD OE QA QB QC0, QC1 QD0 - QD4 VCCA VCC GND Input Input Input Input Input Input Input Input Input Output Output Output Output Supply Supply Supply Name Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VCC VCC Ground Description Differential clock reference Low voltage positive ECL input Single ended reference clock signal or test clock Feedback signal input, connect to a QA, QB, QC, QD output Selects input reference clock Output A divider selection Output B divider selection Outputs C divider selection Outputs D divider selection Output enable/disable Bank A clock output Bank B clock output Bank C clock outputs Bank D clock outputs Positive power supply for the PLL Positive power supply for I/O and core Negative power supply Table 2. Function Table Control REF_SEL PLL_EN OE FSELA FSELB FSELC FSELD Default 0 1 0 0 0 0 0 0 Selects PCLK as reference clock Test mode with PLL disabled. The input clock is directly routed to the output dividers Outputs enabled QA = VCO / 2 QB = VCO / 4 QC = VCO / 4 QD = VCO / 4 1 Selects TCLK as reference clock PLL enabled. The VCO output is routed to the output dividers Outputs disabled, PLL loop is open VCO is forced to its minimum frequency QA = VCO / 4 QB = VCO / 8 QC = VCO / 8 QD = VCO / 8 Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -55 Characteristics Min -0.3 -0.3 -0.3 Max 4.6 VCC+0.3 VCC+0.3 20 50 150 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD (Machine Model) ESD (Human Body Model) Latch-Up Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 105 MPC9351 Table 5. DC Characteristics (VCC = 3.3V 5%, TA = -40 to 85C) Symbol VIH VIL VPP VCMR VOH VOL ZOUT IIN ICCA ICCQ 1 Characteristics Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage Output Impedance Input Leakage Current Maximum PLL Supply Current Maximum Quiescent Supply Current PCLK, PCLK PCLK, PCLK Min 2.0 250 1.0 2.4 Typ Max VCC + 0.3 0.8 VCC - 0.6 Unit V V mV V V Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -24 mA2 IOL = 24 mA IOL = 12 mA VIN = VCC or GND VCCA Pin All VCC Pins 0.55 0.30 14 -17 200 3.0 5.0 1.0 V V A mA mA 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9351 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. Table 6. AC Characteristics (VCC = 3.3V 5%, TA = -40 to 85C)1 Symbol fref Characteristics Input Frequency / 2 feedback / 4 feedback / 8 feedback Static test mode VCO Frequency Maximum Output Frequency / 2 output / 4 output / 8 output PCLK, PCLK PCLK, PCLK Min 100 50 25 0 200 100 50 25 25 500 1.2 Typ Max 200 100 50 300 400 200 100 50 75 1000 VCC - 0.9 1.0 -50 +25 45 47.5 48.75 0.1 50 50 50 +150 +325 150 55 52.5 51.75 1.0 10 10 9.0 -- 20.0 3.0 - 9.5 1.2 - 2.1 10 8.0 4.0 - 17 1.0 Unit MHz MHz MHz MHz MHz MHz MHz MHz % mV V ns ps ps ps % % % ns ns ns MHz -3 db point of MHz PLL transfer characteristic MHz ps RMS value ps ps ms RMS value RMS value LVPECL LVPECL 0.8 to 2.0V PLL locked PLL locked Condition PLL_EN = 1 PLL_EN = 1 PLL_EN = 1 PLL_EN = 0 fVCO fMAX frefDC VPP VCMR tr, tf t() 2 Reference Input Duty Cycle Peak-to-Peak Input Voltage Common Mode Range TCLK Input Rise/Fall Time Propagation Delay (static phase offset) TCLK to EXT_FB PCLK to EXT_FB Output-to-Output Skew Output Duty Cycle 100 - 200 MHz 50 - 100 MHz 25 - 50 MHz tsk(o) DC tr, tf tPLZ, HZ tPZL, ZH BW Output Rise/Fall Time Output Disable Time Output Enable Time / 2 feedback / 4 feedback / 8 feedback Cycle-to-cycle jitter / 4 feedback Single Output Frequency Configuration Period Jitter / 4 feedback Single Output Frequency Configuration I/O Phase Jitter PLL closed loop bandwidth Maximum PLL Lock Time 0.55 to 2.4V tJIT(CC) tJIT(PER) tJIT() tLOCK 22 15 1. AC characteristics apply for parallel output termination of 50 to VTT 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). 106 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9351 Table 7. DC Characteristics (VCC = 2.5V 5%, TA = -40 to 85C) Symbol VIH VIL VPP VCMR VOH VOL ZOUT IIN CIN CPD ICCA ICCQ 1 Characteristics Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage Output Impedance Input Leakage Current Input Capacitance Power Dissipation Capacitance Maximum PLL Supply Current Maximum Quiescent Supply Current PCLK, PCLK PCLK, PCLK Min 1.7 250 1.0 1.8 Typ Max VCC + 0.3 0.7 VCC - 0.6 0.6 Unit V V mV V V V A pF pF Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -15 mA2 IOL = 15 mA VIN = VCC or GND Per Output VCCA Pin All VCC Pins 17 - 20 200 4.0 10 3.0 5.0 1.0 mA mA 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9351 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output. Table 8. AC Characteristics (VCC = 2.5V 5%, TA = -40 to 85C)1 Symbol fref Characteristics Input Frequency / 2 feedback / 4 feedback / 8 feedback VCO Frequency Maximum Output Frequency / 2 output / 4 output / 8 output PCLK, PCLK PCLK, PCLK Min 100 50 25 200 100 50 25 25 500 1.2 Typ Max 200 100 50 400 200 100 50 75 1000 VCC - 0.6 1.0 -100 0 45 47.5 48.75 0.1 50 50 50 +100 +300 150 55 52.5 51.75 1.0 12 12 4.0 - 15.0 2.0 - 7.0 0.7 - 2.0 10 8.0 6.0 - 25 1.0 Unit MHz MHz MHz MHz MHz MHz MHz % mV V ns ps ps ps % % % ns ns ns MHz -3dB point of PLL transfer MHz characteristic MHz ps RMS value ps ps ms RMS value RMS value LVPECL LVPECL 0.7 to 1.7V PLL locked PLL locked Condition fVCO fMAX frefDC VPP VCMR tr, tf t() 2 Reference Input Duty Cycle Peak-to-Peak Input Voltage Common Mode Range TCLK Input Rise/Fall Time Propagation Delay (static phase offset) TCLK to EXT_FB PCLK to EXT_FB Output-to-Output Skew Output Duty Cycle 100 - 200 MHz 50 - 100 MHz 25 - 50 MHz tsk(o) DC tr, tf tPLZ, HZ tPZL, ZH BW Output Rise/Fall Time Output Disable Time Output Enable Time / 2 feedback / 4 feedback / 8 feedback Cycle-to-cycle jitter / 4 feedback Single Output Frequency Configuration Period Jitter / 4 feedback Single Output Frequency Configuration I/O Phase Jitter PLL closed loop bandwidth Maximum PLL Lock Time 0.6 to 1.8V tJIT(CC) tJIT(PER) tJIT() tLOCK 22 15 1. AC characteristics apply for parallel output termination of 50 to VTT 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 107 MPC9351 APPLICATIONS INFORMATION Programming the MPC9351 The MPC9351 clock driver outputs can be configured into several divider modes, in addition the external feedback of the device allows for flexibility in establishing various input to output frequency relationships. The output divider of the four output groups allows the user to configure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even dividers ensures that the output duty cycle is always 50%. Table 9 illustrates the various output configurations, the table describes the outputs using the input clock frequency CLK as a reference. The output division settings establish the output relationship, in addition, it must be ensured that the VCO will be stable given the frequency of the outputs desired. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL supports output frequencies from 25 MHz to 200 MHz while the VCO frequency range is specified from 200 MHz to 400 MHz and should not be exceeded for stable operation. Table 9. Output Frequency Relationship1 for an Example Configuration Inputs FSELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA 2 * CLK 2 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK 4 * CLK 4 * CLK CLK CLK 2 * CLK 2 * CLK CLK CLK 2 * CLK 2 * CLK QB CLK CLK 2 * CLK 2 * CLK CLK / 2 CLK / 2 CLK CLK CLK CLK 2 * CLK 2 * CLK CLK / 2 CLK / 2 CLK CLK Outputs QC CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK QD CLK CLK / 2 2* CLK CLK CLK CLK / 2 2 * CLK CLK CLK CLK / 2 2 * CLK CLK CLK CLK / 2 2 * CLK CLK 1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB. More frequency ratios are available by the connection of QA to the feedback input (EXT_FB). Using the MPC9351 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9351. For these applications the MPC9351 offers a differential LVPECL clock input pair as a PLL reference. This allows for the use of differential LVPECL primary clock distribution devices such as the Motorola MC100EP111 or MC10EP222, taking advantage of its superior low-skew performance. Clock trees using LVPECL for clock distribution and the MPC9351 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9351 PLL allows for its use as a zero-delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. The remaining insertion delay (skew error) of the MPC9351 in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset (SPO or t()), I/O jitter (tJIT(), phase or long-term jitter), feedback path delay and the output-to-output skew (tSK(O) relative to the feedback output. fref = 100 MHz TCLK REF_SEL PLL_EN FSELA FSELB FSELC FSELD Ext_FB MPC9351 100 MHz (Feedback) QA QB QC0 QC1 QD0 QD1 QD2 QD3 QD4 2 x 100 MHz 2 x 100 MHz 1 1 1 0 0 0 4 x 100 MHz Figure 3. MPC9351 Zero-Delay Configuration (Feedback of QD4) 108 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9351 Calculation of Part-to-Part Skew The MPC9351 zero-delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (TCLK or PCLK) of two or more MPC9351 are connected together, the maximum overall timing uncertainty from the common TCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() * CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Above equation uses the maximum I/O jitter number shown in the AC characteristic table for VCC = 3.3 V (17 ps RMS). I/O jitter is frequency dependant with a maximum at the lowest VCO frequency (200 MHz for the MPC9351). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in Figure 5 and Figure 6 can be used to derive a smaller I/O jitter number at the specific VCO frequency, resulting in tighter timing limits in zero-delay mode and for part-to-part skew (tSK(PP)). Max. I/O Jitter versus Frequency 30 TCLKCommon --t(y) QFBDevice 1 25 tJIT() [ps] ms tPD,LINE(FB) 20 15 10 5 +tSK(O) +t() QFBDevice2 tJIT() 0 75 225 250 275 300 325 350 375 400 VCO Frequency [MHz] tJIT() Any QDevice 1 Figure 5. Maximum I/O Jitter (RMS) versus frequency for VCC=2.5 V Max. I/O Jitter versus Frequency Any QDevice 2 Max. skew +tSK(O) tJIT() [ps] ms tSK(PP) 30 25 20 15 10 5 0 75 225 250 275 300 325 350 375 400 VCO Frequency [MHz] Figure 4. MPC9351 Maximum Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 10. Table 10. Confidence Factor CF CF 1 2 3 4 5 6 Probability of Clock Edge within the Distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 Figure 6. Maximum I/O Jitter (RMS) versus frequency for VCC=3.3 V Power Supply Filtering The MPC9351 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9351 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment, where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9351. Figure 7. VCCA Power Supply Filter illustrates a typical power supply filter The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation, an I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -251 ps to 351 ps relative to TCLK (VCC = 3.3 V and fVCO = 400 MHz): tSK(PP) = [-50 ps...150 ps] + [-150 ps...150 ps] + [(17ps * -3)...(17ps *3)] + tPD, LINE(FB) tSK(PP) = [-251 ps...351 ps] + tPD, LINE(FB) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 109 MPC9351 scheme. The MPC9351 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor (RF). From the data sheet, the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325 V (VCC = 3.3 V or VCC = 2.5 V) must be maintained on the VCCA pin. The resistor RF shown in Figure 7 must have a resistance of 270 (VCC = 3.3 V) or 9-10 (VCC = 2.5 V) to meet the voltage drop criteria. RF = 270 for VCC = 3.3 V RF = 9-10 for VCC = 2.5 V VCC RF CF 10 nF CF = 1 F for VCC = 3.3 V CF = 22 F for VCC = 2.5 V VCCA MPC9351 VCC 33...100 nF MPC9351 OUTPUT BUFFER IN 14 used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC / 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9351 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 8 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9351 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9351 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 Figure 7. VCCA Power Supply Filter The minimum values for RF and the and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 7, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9351 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC9351 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be RS = 36 Figure 8. Single versus Dual Transmission Lines The waveform plots in Figure 9. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9351 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9351. The output waveform in Figure 9 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18 + 17 + 25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 110 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9351 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 VOLTAGE (V) Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 10 should be used. In this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9351 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 Figure 9. Single versus Dual Waveforms 14 + 22 || 22 = 50 || 50 25 = 25 Figure 10. Optimized Dual Line Termination MPC9351 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 11. TCLK MPC9351 AC Test Reference for Vcc = 3.3 V and Vcc = 2.5 V Differential Pulse Generator Z = 50 ZO = 50 MPC9351 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 12. PCLK MPC9351 AC Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 111 MPC9351 PCLK PCLK VCMR VCMR VCC VCC / 2 GND t() t() TCLK VCC VCC / 2 GND Ext_FB VCC VCC / 2 GND Ext_FB Figure 13. Propagation Delay (tPD, static phase offset) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 14. Propagation Delay (tPD) Test Reference VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 15. Output Duty Cycle (DC) Figure 16. Output-to-Output Skew tSK(O) TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 17. Cycle-to-Cycle Jitter Figure 18. Period Jitter TCLK (CLK) VCC = 3.3 V 2.4 TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles tF tR 0.55 VCC = 2.5 V 1.8 V 0.6 V Ext_FB Figure 19. I/O Jitter Figure 20. Transition Time Test Reference 112 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC93H51 Rev 3, 08/2004 Low Voltage PLL Clock Drive The MPC93H51 is a 3.3V compatible, PLL based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 240 MHz and a maximum output skew of 150 ps the MPC93H51 is an ideal solution for the most demanding clock tree designs. The device offers 9 low skew clock outputs, each is configurable to support the clocking needs of the various high-performance microprocessors including the PowerQuicc II integrated communication microprocessor. The devices employs a fully differential PLL design to minimize cycle-to-cycle and long-term jitter. Features * * * * * * * * * * * * * * 9 outputs LVCMOS PLL clock generator 25 - 240 MHz output frequency range Fully integrated PLL Compatible to various microprocessors such as PowerQuicc II Supports networking, telecommunications and computer applications Configurable outputs: divide-by-2, 4 and 8 of VCO frequency LVPECL and LVCMOS compatible inputs External feedback enables zero-delay configurations Output enable/disable and static test mode (PLL enable/disable) Low skew characteristics: maximum 150 ps output-to-output 32-lead LQFP package 32-lead Pb-free Package Available Ambient Temperature Range 0C to +70C Pin & Function Compatible with the MPC951 MPC93H51 LOW VOLTAGE 3.3 V PLL CLOCK GENERATOR FA SUFFIX LQFP PACKAGE CASE 873A-03 Functional Description The MPC93H51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation of the MPC93H51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8 the internal VCO of the MPC93H51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK). The MPC93H51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC93H51 is 3.3V compatible and requires no external loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC93H51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm2 32-lead LQFP package. Application Information The fully integrated PLL of the MPC93H51 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 113 MPC93H51 PCLK PCLK TCLK REF_SEL EXT_FB (pullup) (pulldown) (pulldown) (pulldown) 0 1 Ref PLL 0 1 /2 /4 /8 0 D 1 Q QA FB 200-480 MHz 0 D 1 Q QB PLL_EN (pullup) 0 QC0 D 1 QD0 0 D 1 Q QD1 QD2 QD3 QD4 Q QC1 FSELA FSELB FSELC FSELD (pulldown) (pulldown) (pulldown) (pulldown) OE (pulldown) The MPC93H51 requires an external RC filter for the analog power supply pin VCCA. Please see APPLICATIONS INFORMATION for details. Figure 1. MPC93H51 Logic Diagram VCCO VCCO GND 24 GND QB VCCO QA GND TCLK PLL_EN REF_SEL 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 GND 17 16 15 14 QD2 VCCO QD3 GND QD4 VCCO OE PCLK 13 12 11 10 9 8 PCLK QC0 QC1 QD0 MPC93H51 2 3 4 5 6 VCCA FSELA FSELB FSELC EXT_FB FSELD Figure 2. Pinout: 32-Lead LQFP Package Pinout (Top View) 114 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GND QD1 7 MPC93H51 Table 1. Pin Description Pin PCLK, PCLK TCLK EXT_FB REF_SEL FSELA FSELB FSELC FSELD OE QA QB QC0, QC1 QD0 - QD4 VCCA VCC GND Input Input Input Input Input Input Input Input Input Output Output Output Output Supply Supply Supply I/O Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VCC VCC Ground Differential clock reference Low voltage positive ECL input Single ended reference clock signal or test clock Feedback signal input, connect to a QA, QB, QC, QD output Selects input reference clock Output A divider selection Output B divider selection Outputs C divider selection Outputs D divider selection Output enable/disable Bank A clock output Bank B clock output Bank C clock outputs Bank D clock outputs1.5 Positive power supply for the PLL Positive power supply for I/O and core Negative power supply Function Table 2. Function Table Control REF_SEL PLL_EN OE FSELA FSELB FSELC FSELD Default 0 1 0 0 0 0 0 0 Selects PCLK as reference clock Test mode with PLL disabled. The input clock is directly routed to the output dividers Outputs enabled QA = VCO / 2 QB = VCO / 4 QC = VCO / 4 QD = VCO / 4 1 Selects TCLK as reference clock PLL enabled. The VCO output is routed to the output dividers Outputs disabled, PLL loop is open VCO is forced to its minimum frequency QA = VCO / 4 QB = VCO / 8 QC = VCO / 8 QD = VCO / 8 Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 150 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 115 MPC93H51 Table 4. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD (Machine Model) ESD (Human Body Model) Latch-Up Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 5. DC Characteristics (VCC = 3.3 V 5%, TA = 0 to 70C) Symbol VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICCA ICCQ Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage Output Impedance Input Leakage Current Maximum PLL Supply Current Maximum Quiescent Supply Current 6.0 10.0 7 - 10 150 12.0 14.0 PCLK, PCLK PCLK, PCLK 250 1.0 2.4 0.55 0.30 VCC-0.6 Characteristics Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V mV V V V V A mA mA VIN = VCC or GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -24 mA2 IOL = 24 mA IOL = 12 mA 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC93H51 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 116 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93H51 Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = 0 to 70C)1 Symbol fref Input Frequency 2 Characteristics / 4 feedback / 8 feedback Static test mode Min 50 25 0 200 / 2 output / 4 output / 8 output 100 50 25 25 PCLK, PCLK PCLK, PCLK 500 1.2 Typ Max 120 60 300 480 240 120 60 75 1000 VCC-0.9 1.0 Unit MHz MHz MHz MHz MHz MHz MHz % mV V ns ps ps ps % % % ns ns ns MHz MHz Condition PLL_EN = 1 PLL_EN = 1 PLL_EN = 0 fVCO fMAX VCO Frequency Maximum Output Frequency2 frefDC VPP VCMR tr, tf4 t() 3 Reference Input Duty Cycle Peak-to-Peak Input Voltage Common Mode Range TCLK Input Rise/Fall Time Propagation Delay (static phase offset) TCLK to EXT_FB PCLK to EXT_FB Output-to-Output Skew Output Duty Cycle 100 - 240 MHz 50 - 120 MHz 25 - 60 MHz LVPECL LVPECL 0.8 to 2.0 V PLL locked PLL locked -150 0 +150 +250 300 tsk(o) DC 45 47.5 48.75 0.1 50 50 50 55 52.5 51.75 1.0 7.0 6.0 tr, tf tPLZ, HZ tPZL, ZH BW Output Rise/Fall Time Output Disable Time Output Enable Time PLL closed loop bandwidth / 2 feedback / 4 feedback / 8 feedback / 4 feedback / 4 feedback 0.55 to 2.4 V 9.0 - 20.0 3.0 - 9.5 1.2 - 2.1 40 25 30 5 -3 db point of PLL transfer characteristic RMS value RMS value RMS value tJIT(CC) tJIT(PER) tJIT() tLOCK Cycle-to-cycle jitter Single Output Frequency Configuration Period Jitter Single Output Frequency Configuration I/O Phase Jitter Maximum PLL Lock Time ps ps ps ms 1. AC characteristics apply for parallel output termination of 50 to VTT 2. The PLL will be unstable with a divide by 2 feedback ratio. 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). 4. The MPC93H51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), can only be guaranteed if tr/tf are within the specified range. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 117 MPC93H51 APPLICATIONS INFORMATION Programming the MPC93H51 The MPC93H51 clock driver outputs can be configured into several divider modes, in addition the external feedback of the device allows for flexibility in establishing various input to output frequency relationships. The output divider of the four output groups allows the user to configure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even dividers ensure that the output duty cycle is always 50%. Table 7 illustrates the various output configurations, the table describes the outputs using the input clock frequency CLK as a reference. The output division settings establish the output relationship, in addition, it must be ensured that the VCO will be stable given the frequency of the outputs desired. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL supports output frequencies from 25 MHz to 240 MHz while the VCO frequency range is specified from 200 MHz to 480 MHz and should not be exceeded for stable operation. Table 7. Output Frequency Relationship1 for an Example Configuration Inputs FSELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA 2 * CLK 2 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK 4 * CLK 4 * CLK CLK CLK 2 * CLK 2 * CLK CLK CLK 2 * CLK 2 * CLK QB CLK CLK 2 * CLK 2 * CLK CLK / 2 CLK / 2 CLK CLK CLK CLK 2 * CLK 2 * CLK CLK / 2 CLK / 2 CLK CLK Outputs QC CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK QD CLK CLK / 2 2* CLK CLK CLK CLK / 2 2 * CLK CLK CLK CLK / 2 2 * CLK CLK CLK CLK / 2 2 * CLK CLK 1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB. Using the MPC93H51 in Zero-Delay Applications Nested clock trees are typical applications for the MPC93H51. For these applications the MPC93H51 offers a differential LVPECL clock input pair as a PLL reference. This allows for the use of differential LVPECL primary clock distribution devices such as the Motorola MC100EP111 or MC10EP222, taking advantage of its superior low-skew performance. Clock trees using LVPECL for clock distribution and the MPC93H51 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC93H51 PLL allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. The remaining insertion delay (skew error) of the MPC93H51 in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset (SPO or t()), I/O jitter (tJIT(), phase or long-term jitter), feedback path delay and the output-to-output skew (tSK(O) relative to the feedback output. fref = 100 MHz TCLK REF_SEL PLL_EN FSELA FSELB FSELC FSELD Ext_FB MPC93H51 100 MHz (Feedback) QA QB QC0 QC1 QD0 QD1 QD2 QD3 QD4 2 x 100 MHz 2 x 100 MHz 1 1 1 0 0 0 4 x 100 MHz Figure 3. MPC93H51 Zero-Delay Configuration (Feedback of QD4) 118 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93H51 Calculation of Part-to-Part Skew The MPC93H51 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (TCLK or PCLK) of two or more MPC93H51 are connected together, the maximum overall timing uncertainty from the common TCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() * CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: TCLKCommon --t() QFBDevice 1 Above equation uses the maximum I/O jitter number shown in the AC characteristic table for VCC = 3.3 V (17 ps RMS). I/O jitter is frequency dependant with a maximum at the lowest VCO frequency (200 MHz for the MPC93H51). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in Figure 5 can be used to derive a smaller I/O jitter number at the specific VCO frequency, resulting in tighter timing limits in zero-delay mode and for part-to-part skew tSK(PP). Max. I/O Jitter versus Frequency 30 25 tPD,LINE(FB) tJIT() [ps] rms +tSK(O) +t() 20 15 10 5 0 200 tJIT() Any QDevice 1 225 250 275 300 325 350 375 400 VCO frequency [MHz] QFBDevice2 tJIT() Figure 5. Maximum I/O Jitter (RSM) versus Frequency for VCC = 3.3 V Power Supply Filtering The MPC93H51 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC93H51 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC93H51. Figure 6. VCCA Power Supply Filter illustrates a typical power supply filter scheme. The MPC93H51 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 6 mA (12 mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin. The resistor RF shown in Figure 6 must have a resistance of 5-15 to meet the voltage drop criteria. Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 4. MPC93H51 Maximum Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. Table 8. Confidence Factor CF CF 1 2 3 4 5 6 Probability of Clock Edge within the Distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -251 ps to 351 ps relative to TCLK (VCC = 3.3 V and fVCO = 400 MHz): tSK(PP) = tSK(PP) = [-50ps...150ps] + [-150ps...150ps] + [(17ps @ -3)...(17ps @ 3)] + tPD, LINE(FB) [-251ps...351ps] + tPD, LINE(FB) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 119 MPC93H51 RF VCC 22 F 0.01 F MPC93H51 VCC 0.01 F MPC93H51 OUTPUT BUFFER IN 10 RS = 36 ZO = 50 OutB1 RS = 36 ZO = 50 IN VCCA MPC93H51 OUTPUT BUFFER 10 RS = 36 ZO = 50 OutA Figure 6. VCCA Power Supply Filter As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC93H51 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC93H51 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC / 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC93H51 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 7 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC93H51 clock driver is effectively doubled due to its capability to drive multiple lines. OutB0 Figure 7. Single versus Dual Transmission Lines The waveform plots in Figure 8. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC93H51 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC93H51. The output waveform in Figure 8 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18 + 17 + 25) = 1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 9. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. 120 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93H51 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (nS) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 MPC93H51 OUTPUT BUFFER 10 RS = 22 ZO = 50 VOLTAGE (V) RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 9. Optimized Dual Line Termination Figure 8. Single versus Dual Waveforms MPC93H51 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 10. TCLK MPC93H51 AC Test Reference for VCC = 3. 3V Differential Pulse Generator Z = 50 ZO = 50 MPC93H51 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 11. PCLK MPC93H51 AC Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 121 MPC93H51 PCLK PCLK VCMR VCMR VCC VCC/2 GND t() t() TCLK VCC VCC/2 GND Ext_FB VCC VCC/2 GND Ext_FB Figure 12. Propagation Delay (tPD, status phase offset) Test Reference Figure 13. Propagation Delay (tPD) Test Reference VCC VCC/2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage tSK(O) VCC VCC/2 GND VCC VCC/2 GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 14. Output Duty Cycle (DC) Figure 15. Output-to-Output Skew tSK(O) TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(P) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 16. Cycle-to-Cycle Jitter Figure 17. Period Jitter TCLK (PCLK) Ext_FB TJIT() = |T0-T1mean| tF The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles tR VCC = 3.3 V 2.4 0.55 Figure 18. I/O Jitter Figure 19. Transition Time Test Reference 122 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC93R51 Rev 2, 08/2004 Low Voltage PLL Clock Driver The MPC93R51 is a 3.3V compatible, PLL based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 240 MHz and a maximum output skew of 150 ps the MPC93R51 is an ideal solution for the most demanding clock tree designs. The device offers 9 low skew clock outputs, each is configurable to support the clocking needs of the various high-performance microprocessors including the PowerQuicc II integrated communication microprocessor. The devices employs a fully differential PLL design to minimize cycle-to-cycle and long-term jitter. Features * * * * * * * * * * * * * * * 9 outputs LVCMOS PLL clock generator 25 - 240 MHz output frequency range Fully integrated PLL Compatible to various microprocessors such as PowerQuicc II Supports networking, telecommunications and computer applications Configurable outputs: divide-by-2, 4 and 8 of VCO frequency LVPECL and LVCMOS compatible inputs External feedback enables zero-delay configurations Output enable/disable and static test mode (PLL enable/disable) Low skew characteristics: maximum 150 ps output-to-output Cycle-to-cycle jitter max. 22 ps RMS 32-lead LQFP package 32-lead Pb-free Package Available Ambient Temperature Range 0C to +70C Pin & Function Compatible with the MPC951 MPC93R51 LOW VOLTAGE 3.3V PLL CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8 the internal VCO of the MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK). The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC93R51 is 3.3V compatible and requires no external loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC93R51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm2 32-lead LQFP package. Application Information The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 123 MPC93R51 PCLK PCLK TCLK REF_SEL EXT_FB (PULLUP) (PULLDOWN) (PULLDOWN) (PULLDOWN) 0 Ref 1 PLL 0 /2 0 D 1 Q QA 1 /4 /8 FB 200 - 480 MHz 0 D 1 Q QB PLL_EN (PULLUP) QC0 0 (PULLDOWN) (PULLDOWN) (PULLDOWN) (PULLDOWN) 0 D 1 QD3 QD4 Q QD2 D 1 QD0 QD1 Q QC1 FSELA FSELB FSELC FSELD OE (PULLDOWN) The MPC93R51 requires an external RC filter for the analog power supply pin VCCA. Please see application section for details. Figure 1. MPC93R51 Logic Diagram VCCO VCCO GND 24 GND QB VCCO QA GND TCLK PLL_EN REF_SEL 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 GND 17 16 15 14 QD2 VCCO QD3 GND QD4 VCCO OE PCLK 13 12 11 10 9 8 PCLK QC0 QC1 QD0 MPC93R51 2 3 4 5 6 VCCA EXT_FB FSELA FSELB FSELC FSELD Figure 2. Pinout: 32-Lead Package Pinout (Top View) 124 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GND QD1 7 MPC93R51 Table 1. Pin Description Number PCLK, PCLK TCLK EXT_FB REF_SEL FSELA FSELB FSELC FSELD OE QA QB QC0, QC1 QD0 - QD4 VCCA VCC GND Input Input Input Input Input Input Input Input Input Output Output Output Output Supply Supply Supply Name Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VCC VCC Ground Description Differential clock reference Low voltage positive ECL input Single ended reference clock signal or test clock Feedback signal input, connect to a QA, QB, QC, QD output Selects input reference clock Output A divider selection Output B divider selection Outputs C divider selection Outputs D divider selection Output enable/disable Bank A clock output Bank B clock output Bank C clock outputs Bank D clock outputs Positive power supply for the PLL Positive power supply for I/O and core Negative power supply Table 2. Function Table Control REF_SEL PLL_EN OE FSELA FSELB FSELC FSELD Default 0 1 0 0 0 0 0 0 Selects PCLK as reference clock Test mode with PLL disabled. The input clock is directly routed to the output dividers Outputs enabled QA = VCO / 2 QB = VCO / 4 QC = VCO / 4 QD = VCO / 4 1 Selects TCLK as reference clock PLL enabled. The VCO output is routed to the output dividers Outputs disabled, PLL loop is open VCO is forced to its minimum frequency QA = VCO / 4 QB = VCO / 8 QC = VCO / 8 QD = VCO / 8 Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Characteristics Min -0.3 -0.3 -0.3 Max 4.6 VCC+0.3 VCC+0.3 20 50 -55 150 Unit V V V mA mA C Condition Table 4Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 125 MPC93R51 Table 5. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD (Machine Model) ESD (Human Body Model) Latch-Up Power Dissipation Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 6. DC Characteristics (VCC = 3.3V 5%, TA = 0 to 70C) Symbol VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICCA ICCQ Characteristics Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage Output Impedance Input Leakage Current Maximum PLL Supply Current Maximum Quiescent Supply Current 3.0 7.0 14 -17 150 5.0 10 PCLK, PCLK PCLK, PCLK 250 1.0 2.4 0.55 0.30 VCC-0.6 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V mV V V V V A mA mA VIN = VCC or GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL IOH=-24 mA2 IOL= 24 mA IOL= 12 mA 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC93R51 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 126 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93R51 Table 7. AC Characteristics (VCC = 3.3V 5%, TA = 0 to 70C)1 Symbol fref Characteristics Input Frequency 2 Min 50 25 0 200 / 2 output / 4 output / 8 output 100 50 25 25 PCLK, PCLK PCLK, PCLK 500 1.2 Typ Max 120 60 300 480 240 120 60 75 1000 VCC-0.9 1.0 Unit Condition / 4 feedback / 8 feedback Static test mode MHz PLL_EN = 1 MHz PLL_EN = 1 MHz PLL_EN = 0 MHz MHz MHz MHz % mV V ns LVPECL LVPECL 0.8 to 2.0V fVCO fMAX VCO Frequency Maximum Output Frequency2 frefDC VPP VCMR3 tr, tf4 t() Reference Input Duty Cycle Peak-to-Peak Input Voltage Common Mode Range TCLK Input Rise/Fall Time Propagation Delay (static phase offset) TCLK to EXT_FB PCLK to EXT_FB Output-to-Output Skew Output Duty Cycle 100 - 240 MHz 50 - 120 MHz 25 - 60 MHz -50 +25 +150 +325 150 ps ps ps % % % ns ns ns PLL locked PLL locked tsk(o) DC 45 47.5 48.75 0.1 50 50 50 55 52.5 51.75 1.0 7.0 6.0 tr, tf tPLZ, HZ tPZL, ZH BW tJIT(CC) tJIT(PER) tJIT() tLOCK Output Rise/Fall Time Output Disable Time Output Enable Time PLL closed loop bandwidth / 4 feedback / 8 feedback 0.55 to 2.4V 3.0 - 9.5 1.2 - 2.1 10 8.0 4.0 - 17 1.0 22 15 MHz -3 db point of MHz PLL transfer characteristic ps ps ps ms RMS value RMS value RMS value Cycle-to-cycle jitter / 4 feedback Single Output Frequency Configuration Period Jitter / 4 feedback Single Output Frequency Configuration I/O Phase Jitter Maximum PLL Lock Time 1. AC characteristics apply for parallel output termination of 50 to VTT 2. The PLL will be unstable with a divide by 2 feedback ratio 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). 4. The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), can only be guaranteed if tr/tf are within the specified range. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 127 MPC93R51 APPLICATIONS INFORMATION Programming the MPC93R51 The MPC93R51 clock driver outputs can be configured into several divider modes, in addition the external feedback of the device allows for flexibility in establishing various input to output frequency relationships. The output divider of the four output groups allows the user to configure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even dividers ensure that the output duty cycle is always 50%. Table 8. Output Frequency Relationship for an Example Configuration illustrates the various output configurations, the table describes the outputs using the input clock frequency CLK as a reference. The output division settings establish the output relationship, in addition, it must be ensured that the VCO will be stable given the frequency of the outputs desired. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL supports output frequencies from 25 MHz to 240 MHz while the VCO frequency range is specified from 200 MHz to 480 MHz and should not be exceeded for stable operation. Outputs FSELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA 2 * CLK 2 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK 4 * CLK 4 * CLK CLK CLK 2 * CLK 2 * CLK CLK CLK 2 * CLK 2 * CLK QB CLK CLK 2 * CLK 2 * CLK CLK / 2 CLK / 2 CLK CLK CLK CLK 2 * CLK 2 * CLK CLK / 2 CLK / 2 CLK CLK QC CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK QD CLK CLK / 2 2* CLK CLK CLK CLK / 2 2 * CLK CLK CLK CLK / 2 2 * CLK CLK CLK CLK / 2 2 * CLK CLK Table 8. Output Frequency Relationship1 for an Example Configuration Inputs FSELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB. Using the MPC93R51 in zero-delay applications Nested clock trees are typical applications for the MPC93R51. For these applications the MPC93R51 offers a differential LVPECL clock input pair as a PLL reference. This allows for the use of differential LVPECL primary clock distribution devices such as the Motorola MC100EP111 or MC10EP222, taking advantage of its superior low-skew performance. Clock trees using LVPECL for clock distribution and the MPC93R51 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC93R51 PLL allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. The remaining insertion delay (skew error) of the MPC93R51 in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset (SPO or t()), I/O jitter (tJIT(), phase or long-term jitter), feedback path delay and the output-to-output skew (tSK(O) relative to the feedback output. fref = 100 MHz TCLK REF_SEL PLL_EN FSELA FSELB FSELC FSELD QA QB QC0 QC1 QD0 QD1 QD2 QD3 2 x 100 MHz 2 x 100 MHz 1 1 1 0 0 0 4 x 100 MHz QD4 Ext_FB MPC93R51 100 MHz (Feedback) Figure 3. MPC93R51 Zero-Delay Configuration (Feedback of QD4) 128 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93R51 Calculation of part-to-part skew The MPC93R51 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (TCLK or PCLK) of two or more MPC93R51 are connected together, the maximum overall timing uncertainty from the common TCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() * CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Above equation uses the maximum I/O jitter number shown in the AC characteristic table for VCC=3.3V (17 ps RMS). I/O jitter is frequency dependant with a maximum at the lowest VCO frequency (200 MHz for the MPC93R51). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in Figure 5 can be used to derive a smaller I/O jitter number at the specific VCO frequency, resulting in tighter timing limits in zero-delay mode and for part-to-part skew tSK(PP). Max. I/O Jitter versus frequency TCLKCommon --t() QFBDevice 1 tPD,LINE(FB) tJIT() [ps] ms 30 25 20 15 10 5 0 75 225 250 275 300 325 350 375 400 VCO frequency [MHz] tJIT() +tSK(O) +t() Any QDevice 1 QFBDevice2 tJIT() Any QDevice 2 Max. skew Figure 5. Max. I/O Jitter (RMS) Versus Frequency for VCC=3.3V Power Supply Filtering The MPC93R51 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC93R51 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC93R51. Figure 6. VCCA Power Supply Filter illustrates a typical power supply filter scheme. The MPC93R51 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin. The resistor RF shown in Figure 6 must have a resistance of 5-15 to meet the voltage drop criteria. +tSK(O) tSK(PP) Figure 4. MPC93R51 Max. Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 9. Table 9. Confidence Factor CF CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -251 ps to 351 ps relative to TCLK (VCC=3.3V and fVCO = 400 MHz): tSK(PP) = [-50ps...150ps] + [-150ps...150ps] + [(17ps * -3)...(17ps *3)] + tPD, LINE(FB) tSK(PP) = [-251ps...351ps] + tPD, LINE(FB) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 129 MPC93R51 RF 22 pF 0.1 F VCC VCCA MPC93R51 VCC 0.1 F IN MPC93R51 OUTPUT BUFFER 14 RS = 36 ZO = 50 OutA Figure 6. VCCA Power Supply Filter As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC93R51 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC93R51 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC93R51 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 7. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC93R51 clock driver is effectively doubled due to its capability to drive multiple lines. IN MPC93R51 OUTPUT BUFFER 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 7. Single versus Dual Transmission Lines The waveform plots in Figure 8. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC93R51 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC93R51. The output waveform in Figure 8 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+17+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 130 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93R51 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 MPC93R51 OUTPUT BUFFER 14 OutA tD = 3.8956 OutB tD = 3.9386 VOLTAGE (V) Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 9. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. RS = 22 ZO = 50 RS = 22 ZO = 50 Figure 8. Single versus Dual Waveforms 14 + 22 || 22 = 50 || 50 25 = 25 Figure 9. Optimized Dual Line Termination MPC93R51 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 10. TCLK MPC93R51 AC Test Reference for VCC = 3.3V Differential Pulse Generator Z = 50 ZO = 50 MPC93R51 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 11. PCLK MPC9R351 AC Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 131 MPC93R51 PCLK PCLK VCMR VCMR VCC VCC / 2 GND t() t() TCLK VCC VCC / 2 GND Ext_FB VCC VCC / 2 GND Ext_FB Figure 12. Propagation Delay (tPD, Static Phase Offset) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 13. Propagation Delay (tPD) Test Reference VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 14. Output Duty Cycle (DC) Figure 15. Output-to-Output Skew tSK(O) TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 16. Cycle-to-Cycle Jitter Figure 17. Period Jitter TCLK (PCLK) VCC=3.3V 2.4 TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles tF tR 0.55 Ext_FB Figure 18. I/O Jitter Figure 19. Transition Time Test Reference 132 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9352 Rev 4, 08/2004 3.3V/2.5V 1:11 LVCMOS Zero Delay Clock Generator The MPC9352 is a 3.3V or 2.5V compatible, 1:11 PLL based clock generator targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews lower than 200 ps the device meets the needs of most demanding clock applications. Features * Configurable 11 outputs LVCMOS PLL clock generator * Fully integrated PLL * Wide range of output clock frequency of 16.67 MHz to 200 MHz * Multiplication of the input reference clock frequency by 3, 2, 1, 3 / 2, 2 / 3, 1 / 3 and 1 / 2 * 2.5V and 3.3V LVCMOS compatible * Maximum output skew of 200 ps * Supports zero-delay applications * Designed for high-performance telecom, networking and computing applications * 32-lead LQFP package * 32-lead Pb-free Package Available * Ambient Temperature Range -40C to +85C MPC9352 LOW VOLTAGE 3.3V/2.5V LVCMOS 1:11 CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC9352 is a fully 3.3V or 2.5V compatible PLL clock generator and clock driver. The device has the capability to generate output clock signals of 16.67 to 200 MHz from external clock sources. The internal PLL optimized for its frequency range and does not require external look filter components. One output of the MPC9352 has to be connected to the PLL feedback input FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multiplication factor. This multiplication factor, F_RANGE and the reference clock frequency must be selected to situate the VCO in its specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx pins supporting systems with different but phase-aligned clock frequencies. The PLL of the MPC9352 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50 transmission lines. Alternatively, each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22. The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The MPC9352 is packaged in a 32 ld LQFP. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 133 MPC9352 CCLK CCLK Ref BANK A 1 /2 1 0 /6 /4 /2 1 0 QA0 QA1 VCO 0 FB_IN FB PLL QA2 QA3 QA4 BANK B QB0 QB1 PLL_EN 1 0 F_RANGE FSELA FSELB QB2 QB3 BANK C 1 FSELC 0 MR/OE (All input resistors have a value of 25k) QC0 QC1 Figure 1. MPC9352 Logic Diagram GND 24 VCC QB2 QB3 GND GND QC0 QC1 VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 GND 17 16 15 14 VCC QA2 QA1 GND QA0 VCC VCCA PLL_EN 13 12 11 10 9 8 FB_IN QB1 QB0 QA4 6 CCLK MPC9352 2 3 4 5 FSELB F_RANGE FSELC FSELA It is recommended to use an external RC filter for the analog power supply pin VCCA. Please see application section for details. Figure 2. MPC9352 32-Lead Package Pinout (Top View) 134 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MR/OE GND QA3 7 VCC VCC MPC9352 ] Table 1. Pin Configuration Pin CCLK FB_IN F_RANGE FSELA FSELB FSELC PLL_EN MR/OE QA0-4, QB0-3, QC0-1 GND VCCA Input Input Input Input Input Input Input Input Output Supply Supply I/O Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC PLL reference clock signal PLL feedback signal input, connect to an output PLL frequency range select Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCCA. Please see applications section for details. Positive power supply for I/O and core Function VCC Supply VCC Table 2. Function Table Control Default 0 1 F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios. See Table 9 and Table 10 for supported frequency ranges and output to input frequency ratios. F_RANGE FSELA FSELB FSELC MR/OE 0 0 0 0 0 VCO / 1 (High input frequency range) Output divider / 4 Output divider / 4 Output divider / 2 Outputs enabled (active) VCO / 2 (Low input frequency range) Output divider / 6 Output divider / 2 Output divider / 4 Outputs disabled (high-impedance state) and reset of the device. During reset, the PLL feedback loop is open and the VCO is operating at its lowest frequency. The MPC9352 requires reset at power-up and after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than two reference clock cycles (CCLK). Test mode with PLL disabled. CCLK is substituted for the internal VCO output. MPC9352 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. PLL_EN 0 Normal operation mode with PLL enabled. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 135 MPC9352 Table 3. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 3.3V 5%, TA = -40 to 85C) Symbol VIH VIL VOH VOL ZOUT IIN ICCA ICCQ3 Input high voltage Input low voltage Output High Voltage Output Low Voltage Output impedance Input Current2 Maximum PLL Supply Current Maximum Quiescent Supply Current 3.0 2.4 0.55 0.30 14 - 17 200 5.0 1.0 Characteristics Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V V V A mA mA VIN=VCC or VIN=GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS IOH=-24 mA1 IOL= 24 mA IOL= 12 mA 1. The MPC9352 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. Inputs have pull-down resistors affecting the input current. 3. ICCQ is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open. 136 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9352 Table 6. AC Characteristics (VCC = 3.3V 5%, TA = -40 to 85C)1 Symbol fref Characteristics Input reference frequency in PLL mode 2 Min /4 feedback /6 feedback /8 feedback /12 feedback 50.0 33.3 25.0 16.67 Typ Max 100.0 66.6 50.0 33.3 250.0 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % ns ps ps ps ps ps ps % ns ns ns ps ps ps ps ps ps ps ps ps ps MHz MHz MHz MHz Condition Input reference frequency in PLL bypass mode3 fVCO fMAX VCO lock frequency range4 Output Frequency /2 output5 /4 output /6 output /8 output /12 output 200 100 50 33.3 25 16.67 25 400 200 100 66.6 50 33.3 75 1.0 frefDC tr, tf t() tsk(O) Reference Input Duty Cycle CCLK Input Rise/Fall Time Propagation Delay CCLK to FB_IN (static phase offset) Output-to-output Skew6 fref > 40 MHz fref < 40 MHz 0.8 to 2.0V PLL locked -50 -200 +150 +150 200 200 100 100 all outputs, any frequency within QA output bank within QB output bank within QC output bank 47 0.1 50 DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) Output duty cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter output frequencies mixed outputs are in any /4 and /6 combination all outputs same frequency Period Jitter output frequencies mixed outputs are in any /4 and /6 combination all outputs same frequency /4 feedback divider RMS (1 )7 /6 feedback divider RMS (1 ) /8 feedback divider RMS (1 ) /12 feedback divider RMS (1 ) /4 feedback /6 feedback /8 feedback /12 feedback 53 1.0 8 10 400 250 100 200 150 75 0.55 to 2.4V tJIT(PER) tJIT() I/O Phase Jitter 15 20 18 - 20 25 3.0 - 10.0 1.5 - 6.0 1.0 - 3.5 0.5 - 2.0 10 BW PLL closed loop bandwidth8 tLOCK 1. 2. 3. 4. 5. 6. 7. 8. Maximum PLL Lock Time ms AC characteristics apply for parallel output termination of 50 to VTT. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a /2 divider for feedback. In PLL bypass mode, the MPC9352 divides the input reference clock. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO / FB. See Table 9 and Table 10 for output divider configurations. See application section for part-to-part skew calculation. See application section for a jitter calculation for other confidence factors than 1 . -3 dB point of PLL transfer characteristics. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 137 MPC9352 Table 7. DC Characteristics (VCC = 2.5V 5%, TA = -40 to 85C) Symbol VIH VIL VOH VOL ZOUT IIN ICCA ICCQ2 Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current Maximum PLL Supply Current Maximum Quiescent Supply Current 2.0 17 - 20 200 5.0 1.0 Min 1.7 -0.3 1.8 0.6 Typ Max VCC + 0.3 0.7 Unit V V V V A mA mA VIN = VCC or GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS IOH=-15 mA1 IOL= 15mA 1. The MPC9352 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output. 2. ICCQ is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open. 138 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9352 Table 8. AC Characteristics (VCC = 2.5V 5%, TA = -40 to 85C)1 Symbol fref Characteristics Input reference frequency in PLL mode 2 Min /4 feedback /6 feedback /8 feedback /12 feedback 50.0 33.3 25.0 16.67 Typ Max 100.0 66.6 50.0 33.3 250.0 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % ns ps ps ps ps ps ps % ns ns ns ps ps ps ps ps ps ps ps ps ps MHz MHz MHz MHz Condition Input reference frequency in PLL bypass mode3 fVCO fMAX VCO lock frequency Output Frequency range4 /2 output /4 output /6 output /8 output /12 output 5 200 100 50 33.3 25 16.67 25 400 200 100 66.6 50 33.3 75 1.0 frefDC tr, tf t() tsk(O) Reference Input Duty Cycle CCLK Input Rise/Fall Time Propagation Delay CCLK to FB_IN (static phase offset) Output-to-output Skew6 fref > 40 MHz fref < 40 MHz 0.8 to 2.0V PLL locked -50 -200 +150 +150 200 200 100 100 all outputs, any frequency within QA output bank within QB output bank within QC output bank 47 0.1 50 DC tr, tf tPLZ, HZ tPZL, ZH tJIT(CC) Output duty cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter output frequencies mixed RMS (1 ) outputs are in any /4 and /6 combination RMS (1 ) all outputs same frequency RMS (1 ) Period Jitter output frequencies mixed RMS (1 ) outputs are in any /4 and /6 combination RMS (1 ) all outputs same frequency RMS (1 ) I/O Phase Jitter /4 feedback divider RMS (1 )7 /6 feedback divider RMS (1 ) /8 feedback divider RMS (1 ) /12 feedback divider RMS (1 ) /4 feedback /6 feedback /8 feedback /12 feedback 53 1.0 8 10 400 250 100 200 150 75 0.6 to 1.8V tJIT(PER) tJIT() 15 20 18 - 20 25 1.0 - 8.0 0.7 - 3.0 0.5 - 2.5 0.4 - 1.0 10 BW PLL closed loop bandwidth8 tLOCK 1. 2. 3. 4. 5. 6. 7. 8. Maximum PLL Lock Time ms AC characteristics apply for parallel output termination of 50 to VTT. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a /2 divider for feedback. In PLL bypass mode, the MPC9352 divides the input reference clock. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO / FB. See Table 9 and Table 10 for output divider configurations. See application section for part-to-part skew calculation. See application section for a jitter calculation for other confidence factors than 1 . -3 dB point of PLL transfer characteristics. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 139 MPC9352 APPLICATIONS INFORMATION Programming the MPC9352 The MPC9352 supports output clock frequencies from 16.67 to 200 MHz. Different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. The feedback frequency and divider should be used to situate the VCO in the frequency lock range between 200 and 400 MHz for stable and optimal operation. The FSELA, FSELB, FSELC pins select the desired output clock frequencies. Possible frequency ratios of the reference clock input to the outputs are 1:1, 1:2, 1:3, 3:2 as well as 2:3, 3:1 and 2:1. Table 9 and Table 10 illustrates the various output configurations and frequency ratios supported by the MPC9352. See also Figure 3. MPC9352 Default Configuration to Figure 6. MPC9352 Zero Delay Buffer Configuration 2 for further reference. A /2 output divider cannot be used for feedback. Table 9. MPC9352 Example Configuration (F_RANGE = 0) PLL Feedback VCO / 42 fref1 [MHz] 50-100 FSELA 0 0 1 1 VCO / 63 33.3-66.67 1 1 1 1 FSELB 0 0 0 0 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 QA[0:4]:fref ratio fref fref (50-100 MHz) (50-100 MHz) QB[0:3]:fref ratio fref fref fref fref (50-100 MHz) (50-100 MHz) (50-100 MHz) (50-100 MHz) QC[0:1]:fref ratio fref * 2 (100-200 MHz) fref (50-100 MHz) fref * 2/3 (33-66 MHz) fref * 2/3 (33-66 MHz) fref fref fref fref (33-66 MHz) (33-66 MHz) (33-66 MHz) (33-66 MHz) fref * 2 (100-200 MHz) fref (50-100 MHz) fref * 3/2 (50-100 MHz) fref * 3/2 (50-100 MHz) fref * 3 (100-200 MHz) fref * 3 (100-200 MHz) fref * 3 (100-200 MHz) fref * 3/2 (50-100 MHz) fref * 3 (100-200 MHz) fref * 3/2 (50-100 MHz) 1. fref is the input clock reference frequency (CCLK) 2. QAx connected to FB_IN and FSELA=0 3. QAx connected to FB_IN and FSELA=1 Table 10. MPC9352 Example Configurations (F_RANGE = 1) PLL Feedback VCO / 82 fref1 [MHz] 25-50 FSELA 0 0 1 1 VCO / 123 16.67-33.3 1 1 1 1 FSELB 0 0 0 0 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 QA[0:4]:fref ratio fref fref fref * 2/3 fref * 2/3 fref fref fref fref (25-50 MHz) (25-50 MHz) (16-33 MHz) (16-33 MHz) (16-33 MHz) (16-33 MHz) (16-33 MHz) (16-33 MHz) QB[0:3]:fref ratio fref fref fref fref fref * 3/2 fref * 3/2 fref * 3 fref * 3 (25-50 MHz) (25-50 MHz) (25-50 MHz) (25-50 MHz) (25-50 MHz) (25-50 MHz) (50-100 MHz) (50-100 MHz) QC[0:1]:fref ratio fref * 2 fref fref * 2 fref fref * 3 (50-100 MHz) (25-50 MHz) (50-100 MHz) (25-50 MHz) (50-100 MHz) fref * 3/2 (25-50 MHz) fref * 3 (50-100 MHz) fref * 3/2 (25-50 MHz) 1. fref is the input clock reference frequency (CCLK) 2. QAx connected to FB_IN and FSELA=0 3. QAx connected to FB_IN and FSELA=1 140 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9352 Example Configurations for the MPC9352 fref = 100 MHz fref = 62.5 MHz 100 MHz FB_IN FSELA FSELB FSELC F_RANGE MPC9352 QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QC0 QC1 CCLK FB_IN FSELA FSELB FSELD F_RANGE QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QC0 QC1 CCLK 62.5 MHz 100 MHz VCC 62.5 MHz 62.5 MHz MPC9352 100 MHz (Feedback) 200 MHz 62.5 MHz (Feedback) MPC9352 default configuration (feedback of QB0 = 100 MHz). All control pins are left open. Frequency Range Input QA outputs QB outputs QC outputs Min 50 MHz 50 MHz 50 MHz 100 MHz Max 100 MHz 10 MHz 100 MHz 200 MHz MPC9352 zero-delay (feedback of QB0 = 62.5 MHz). All control pins are left open except FSELC = 1. All outputs are locked in frequency and phase to the input clock. Frequency Range Input QA outputs QB outputs QC outputs Min 50 MHz 50 MHz 50 MHz 50 MHz Max 100 MHz 10 MHz 100 MHz 100 MHz Figure 3. MPC9352 Default Configuration Figure 4. MPC9352 Zero Delay Buffer Configuration fref = 33.3 MHz CCLK FB_IN VCC VCC VCC FSELA FSELB FSELC F_RANGE MPC9352 QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QC0 QC1 fref = 33.3 MHz 33.3 MHz CCLK FB_IN FSELA FSELB FSELC F_RANGE MPC9352 QA0 QA1 QA2 QA3 QQ4 QB0 QB1 QB2 QB3 QC0 QC1 33.3 MHz 50 MHz 100 MHz VCC VCC 33.3 MHz 33.3 MHz 33.3 MHz (Feedback) 33.3 MHz (Feedback) MPC9352 configuration to multiply the reference frequency by 3, 3 / 2 and 1. PLL feedback of QA4 = 33.3 MHz. Frequency Range Input QA outputs QB outputs QC outputs Min 25 MHz 50 MHz 50 MHz 100 MHz Max 50 MHz 10 MHz 100 MHz 200 MHz MPC9352 zero-delay (feedback of QB0 = 33.3 MHz). Equivalent to Table 2 except F_RANGE = 1 enabling a lower input and output clock frequency. Frequency Range Input QA outputs QB outputs QC outputs Min 25 MHz 25 MHz 25 MHz 25 MHz Max 50 MHz 50 MHz 50 MHz 50 MHz Figure 5. MPC9352 Default Configuration Figure 6. MPC9352 Zero Delay Buffer Configuration 2 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 141 MPC9352 Power Supply Filtering The MPC9352 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9352 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9352. Figure 7. VCCA Power Supply Filter illustrates a typical power supply filter scheme. The MPC9352 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the VCCA pin. The resistor RF shown in Figure 7. VCCA Power Supply Filter should have a resistance of 5-15 (VCC=3.3V) or 9-10 (VCC=2.5V) to meet the voltage drop criteria. RF = 5-15 for VCC = 3.3V RF = 9-10 for VCC = 2.5V VCC RF CF 10 nF CF = 22 F for VCC = 3.3V CF = 22 F for VCC = 2.5V VCCA MPC9352 VCC 33...100 nF CCLKCommon --t() tPD,LINE(FB) supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9352 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9352. Designs using the MPC9352 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9352 clock driver allows for its use as a zero delay buffer. One example configuration is to use a /4 output as a feedback to the PLL and configuring all other outputs to a divide-by-4 mode. The propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC9352 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9352 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() * CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Figure 7. VCCA Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 7. VCCA Power Supply Filter, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9352 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power QFBDevice 1 tJIT() +tSK(O) +t() Any QDevice 1 QFBDevice2 tJIT() Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 8. MPC9352 max. device-to-device skew 142 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9352 Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 11. Table 11. Confidence Factor CF CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 IN MPC9352 OUTPUT BUFFER 14 This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9352 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 10. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9352 clock driver is effectively doubled due to its capability to drive multiple lines. The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -445 ps to 395 ps relative to CCLK: tSK(PP) = [-200ps...150ps] + [-200ps...200ps] + [(15ps * -3)...(15ps * 3)] + tPD, LINE(FB) tSK(PP) = [-445ps...395ps] + tPD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 9. Max. I/O Jitter versus Frequency can be used for a more precise timing performance analysis. Max. I/O Jitter versus frequency 30 25 tJIT() [ps] ms 20 15 10 5 0 200 225 250 275 300 325 350 375 400 VCO frequency [MHz] RS = 36 ZO = 50 OutA MPC9352 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 10. Single versus Dual Transmission Lines The waveform plots in Figure 11. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9352 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9352. The output waveform in Figure 11. Single versus Dual Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+17+25)) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). Figure 9. Max. I/O Jitter versus Frequency Driving Transmission Lines The MPC9352 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 143 MPC9352 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 MPC9352 OUTPUT BUFFER 14 OutA tD = 3.8956 OutB tD = 3.9386 VOLTAGE (V) Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 12. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. RS = 22 ZO = 50 RS = 22 ZO = 50 Figure 11. Single versus Dual Waveforms 14 + 22 || 22 = 50 || 50 25 = 25 Figure 12. Optimized Dual Line Termination MPC9352 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 13. CCLK MPC9352 AC Test Reference for VCC = 3.3V and VCC = 2.5V 144 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9352 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device FB_IN t() CCLK VCC VCC / 2 GND VCC VCC / 2 GND Figure 14. Output-to-Output Skew tSK(O) Figure 15. Propagation Delay (t(), static phase offset) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage FB_IN TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles CCLK Figure 16. Output Duty Cycle (DC) Figure 17. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 18. Cycle-to-Cycle Jitter Figure 19. Period Jitter VCC=3.3V 2.4 0.55 tF tR VCC=2.5V 1.8V 0.6V Figure 20. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 145 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC93H52 Rev 3, 08/2004 3.3V 1:11 LVCMOS Zero Delay Clock Generator The MPC93H52 is a 3.3V compatible, 1:11 PLL based clock generator targeted for high performance clock tree applications. With output frequencies up to 240 MHz and output skews lower than 200 ps the device meets the needs of most demanding clock applications. Features * * * * * * * * * * * * Configurable 11 outputs LVCMOS PLL clock generator Fully integrated PLL Wide range of output clock frequency of 16.67 MHz to 240 MHz Multiplication of the input reference clock frequency by 3, 2, 1, 3/2, 2/3, 1/3 and 1/2 3.3V LVCMOS compatible Maximum output skew of 200 ps Supports zero-delay applications Designed for high-performance telecom, networking and computing applications 32-lead LQFP package 32-lead Pb-free Package Available Ambient Temperature Range -- 0C to +70C Pin and function compatible to the MPC952 MPC93H52 LOW VOLTAGE 3.3V LVCMOS 1:11 CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC93H52 is a fully 3.3 V compatible PLL clock generator and clock driver. The device has the capability to generate output clock signals of 16.67 to 240 MHz from external clock sources. The internal PLL optimized for its frequency range and does not require external look filter components. One output of the MPC93H52 has to be connected to the PLL feedback input FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multiplication factor. This multiplication factor, F_RANGE and the reference clock frequency must be selected to situate the VCO in its specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx pins supporting systems with different but phase-aligned clock frequencies. The PLL of the MPC93H52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50 transmission lines. Alternatively, each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22. The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The MPC93H52 is package in a 32-lead LQFP. 146 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93H52 CCLK CCLK Ref Bank A 1 /2 1 0 /6 /4 /2 1 0 QA0 QA1 PLL FB_IN FB 200 - 480 MHz PLL_EN VCO 0 QA2 QA3 QA4 Bank B QB0 QB1 F_RANGE 1 0 FSELA FSELB QB2 QB3 Bank C 1 FSELC POWER-ON RESET MR/OE (all input resistors have a value of 25 k) 0 QC0 QC1 Figure 1. MPC93H52 Logic Diagram GND GND 17 16 15 14 VCC QA2 QA1 GND QA0 VCC VCCA PLL_EN 13 12 11 10 9 1 2 3 4 5 6 7 8 FB_IN QB1 QB0 QA4 19 CCLK QA3 18 GND VCC 21 FSELA 24 VCC QB2 QB3 GND GND QC0 QC1 VCC 25 26 27 28 29 30 31 32 23 22 MPC93H52 F_RANGE FSELC FSELB It is recommended to use an external RC filter for the analog power supply pin VCCA. Please see APPLICATIONS INFORMATION for details. Figure 2. MPC93H52 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MR/OE VCC 20 147 MPC93H52 Table 1. Pin Configuration Pin CCLK FB_IN F_RANGE FSELA FSELB FSELC PLL_EN MR/OE QA0-4, QB0-3, QC0-1 GND VCCA Input Input Input Input Input Input Input Input Output Supply Supply I/O Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC PLL reference clock signal PLL feedback signal input, connect to an output PLL frequency range select Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCCA. Please see applications section for details. Positive power supply for I/O and core Function VCC Supply VCC Table 2. Function Table Control Default 0 1 F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios. See Table 7 and Table 8 for supported frequency ranges and output to input frequency ratios. F_RANGE FSELA FSELB FSELC MR/OE 0 0 0 0 0 VCO / 1 (High input frequency range) Output divider / 4 Output divider / 4 Output divider / 2 Outputs enabled (active) VCO / 2 (Low input frequency range) Output divider / 6 Output divider / 2 Output divider / 4 Outputs disabled (high-impedance state) and reset of the device. During reset, the PLL feedback loop is open and the VCO is operating at its lowest frequency. The MPC93H52 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than two reference clock cycles (CCLK). The device is reset by the internal power-on reset (POR) circuitry during power-up. Test mode with PLL disabled. CCLK is substituted for the internal VCO output. MPC93H52 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. PLL_EN 0 Normal operation mode with PLL enabled. 148 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93H52 Table 3. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD (Machine Model) ESD (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 3.3 V 5%, TA = 0 to 70C) Symbol VIH VIL VOH VOL ZOUT IIN ICCA ICCQ3 Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current2 Maximum PLL Supply Current Maximum Quiescent Supply Current 8 10 7 - 10 200 12 16 2.4 0.55 0.30 Characteristics Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V V V A mA mA VIN = VCC or VIN = GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS IOH = -24 mA1 IOL = 24 mA IOL = 12 mA 1. The MPC93H52 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. Inputs have pull-down resistors affecting the input current. 3. ICCQ is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 149 MPC93H52 Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = 0 to 70C)1 Symbol fref in PLL mode2 3 Characteristics Input reference frequency /4 feedback /6 feedback /8 feedback /12 feedback Min 50.0 33.3 25.0 16.67 50.0 200 /2 output6 /4 output /6 output /8 output /12 output 7 Typ Max 120.0 80.0 60.0 40.0 250.0 480 240 120 80 60 40 1.0 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns ns ps ps ps ps ps ps % ns ns ns ps ps ps ps ps ps ps ps MHz MHz MHz MHz Condition Input reference frequency in PLL bypass mode4 fVCO fMAX VCO lock frequency range5 Output Frequency 100 50 33.3 25 16.67 2.0 tPWMIN tr, tf t() tsk(O) Minimum Reference Input Pulse Width CCLK Input Rise/Fall Time 0.8 to 2.0V PLL locked Propagation Delay CCLK to FB_IN (static phase offset) Output-to-output Skew8 (fref = 50MHz) -200 +200 300 200 200 100 all outputs, any frequency within QA output bank within QB output bank within QC output bank 45 0.1 50 DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) Output duty cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter output frequencies mixed all outputs same frequency output frequencies mixed all outputs same frequency /4 feedback divider RMS (1 ) /6 feedback divider RMS (1 ) /8 feedback divider RMS (1 ) /12 feedback divider RMS (1 ) /4 feedback /6 feedback /8 feedback /12 feedback 55 1.0 8 10 150 25 75 20 0.55 to 2.4V RMS RMS RMS RMS tJIT(PER) Period Jitter tJIT() I/O Phase Jitter9 40 40 40 40 2.0-8.0 1.0-4.0 0.8-2.5 0.6-1.5 10 BW PLL closed loop bandwidth10 tLOCK 1. 2. 3. 4. 5. 6. 7. Maximum PLL Lock Time ms AC characteristics apply for parallel output termination of 50 to VTT PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. The PLL may be unstable with a divide by 2 feedback ratio. In PLL bypass mode, the MPC93H52 divides the input reference clock. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO / FB. See Table 7 and Table 8 for output divider configurations. The MPC93H52 will operate with input rise and fall times up to 3.0 ns, but the AC characteristics, specifically t(), can only be guaranteed if tr/tf are within the specified range. 8. See application section for part-to-part skew calculation. 9. See application section for a jitter calculation for other confidence factors than 1 . 10. -3 dB point of PLL transfer characteristics. 150 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93H52 APPLICATIONS INFORMATION Programming the MPC93H52 The MPC93H52 supports output clock frequencies from 16.67 to 240 MHz. Different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. The feedback frequency and divider should be used to situate the VCO in the frequency lock range between 200 and 480 MHz for stable and optimal operation. The FSELA, FSELB, FSELC pins select the desired Table 7. MPC93H52 Example Configuration (F_RANGE = 0) PLL Feedback VCO / 42 fref1 [MHz] 50-120 FSELA 0 0 1 1 VCO / 6 3 output clock frequencies. Possible frequency ratios of the reference clock input to the outputs are 1:1, 1:2, 1:3, 3:2 as well as 2:3, 3:1 and 2:1. Table 7 illustrates the various output configurations and frequency ratios supported by the MPC93H52. See also Table 8 and to Figure 6. MPC93H52 Zero Delay Buffer Configuration 2 for further reference. A /2 output divider cannot be used for feedback. FSELB 0 0 0 0 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 fref fref QA[0:4]:fref ratio (50-120 MHz) (50-120 MHz) (33-80 MHz) (33-80 MHz) (33-80 MHz) (33-80 MHz) (33-80 MHz) (33-80 MHz) fref fref fref fref QB[0:3]:fref ratio (50-120 MHz) (50-120 MHz) (50-120 MHz) (50-120 MHz) (50-120 MHz) (50-120 MHz) (100-240 MHz) (100-240 MHz) QC[0:1]:fref ratio fref 2 fref fref 2 fref fref 3 fref 3/2 fref 3 fref 3/2 (100-240 MHz) (50-120 MHz) (100-240 MHz) (50-120 MHz) (100-240 MHz) (50-120 MHz) (100-240 MHz) (50-120 MHz) fref 2/3 fref 2/3 fref fref fref fref 33.3-80 1 1 1 1 fref 3/2 fref 3/2 fref 3 fref 3 1. fref is the input clock reference frequency (CCLK) 2. fref is the input clock reference frequency (CCLK) 3. fref is the input clock reference frequency (CCLK) Table 8. MPC93H52 Example Configurations (F_RANGE = 1) PLL Feedback VCO / 82 fref1 [MHz] 25-60 FSELA 0 0 1 1 VCO / 12 3 FSELB 0 0 0 0 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 fref fref QA[0:4]:fref ratio (25-60 MHz) (25-60 MHz) fref fref QB[0:3]:fref ratio (25-60 MHz) (25-60 MHz) (25-60 MHz) QC[0:1]:fref ratio fref 2 fref fref (50-120 MHz) (25-60 MHz) (50-120 MHz) (25-60 MHz) (50-120 MHz) (25-60 MHz) (50-120 MHz) (25-60 MHz) fref 2/3 fref 2/3 fref fref fref fref (16-40 MHz) fref (16-40 MHz) fref (16-40 MHz) (16-40 MHz) (16-40 MHz) fref 3/2 fref 3 fref 3 (16-40 MHz) fref 3/2 (25-60 MHz) fref 2 (25-60 MHz) fref 3 (25-60 MHz) fref 3/2 (50-120 MHz) fref 3 (50-120 MHz) fref 3/2 16.67-40 1 1 1 1 1. fref is the input clock reference frequency (CCLK) 2. QAx connected to FB_IN and FSELA=0 3. QAx connected to FB_IN and FSELA=1 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 151 MPC93H52 Example Configurations for the MPC93H52 fref = 100 MHz CCLK QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QC0 QC1 fref = 62.5 MHz 100 MHz FB_IN 100 MHz FSELA FSELB FSELC F_RANGE MPC93H52 CCLK QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QC0 QC1 62.5 MHz FB_IN FSELA FSELB FSELD F_RANGE MPC93H52 VCC 62.5 MHz 200 MHz 62.5 MHz 100 MHz (Feedback) 62.5 MHz (Feedback) MPC93H52 default configuration (feedback of QB0 = 100 MHz). All control pins are left open. Frequency range Input QA outputs QB outputs QC outputs Min 50 MHz 50 MHz 50 MHz 100 MHz Max 120 MHz 120 MHz 120 MHz 240 MHz MPC93H52 zero-delay (feedback of QB0 = 62.5 MHz). All control pins are left open except FSELC = 1. All outputs are locked in frequency and phase to the input clock. Frequency range Input QA outputs QB outputs QC outputs Min 50 MHz 50 MHz 50 MHz 50 MHz Max 120 MHz 120 MHz 120 MHz 120 MHz Figure 3. MPC93H52 Default Configuration Figure 4. MPC93H52 Default Configuration fref = 33.3 MHz CCLK FB_IN VCC VCC VCC FSELA FSELB FSELC F_RANGE MPC93H52 QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QC0 QC1 fref = 33.3 MHz 33.3 MHz CCLK FB_IN 50 MHz FSELA FSELB FSELC F_RANGE MPC93H52 QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QC0 QC1 33.3 MHz VCC VCC 33.3 MHz 100 MHz 33.3 MHz 33.3 MHz (Feedback) 33.3 MHz (Feedback) MPC93H52 configuration to multiply the reference frequency by 3, 3/2 and 1. PLL feedback of QA4 = 33.3 MHz. Frequency range Input QA outputs QB outputs QC outputs Min 25 MHz 50 MHz 50 MHz 100 MHz Max 60 MHz 120 MHz 120 MHz 240 MHz MPC93H52 zero-delay (feedback of QB0 = 33.3 MHz). Equivalent to Table 2 except F_RANGE = 1 enabling a lower input and output clock frequency. Frequency range Input QA outputs QB outputs QC outputs Min 25 MHz 25 MHz 25 MHz 25 MHz Max 60 MHz 60 MHz 60 MHz 60 MHz Figure 5. MPC93H52 Default Configuration Figure 6. MPC93H52 Zero Delay Buffer Configuration 2 152 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93H52 Power Supply Filtering The MPC93H52 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC93H52 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC93H52. Figure 7. VCCA Power Supply Filter illustrates a typical power supply filter scheme. The MPC93H52 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 8 mA (12 mA maximum), assuming that a minimum of 2.98V must be maintained on the VCCA pin. The resistor RF shown in Figure 7. VCCA Power Supply Filter should have a resistance of 5-25 to meet the voltage drop criteria. RF = 5-25 VCC RF CF CF = 22 mF VCCA 10 nF MPC93H52 VCC 33...100 nF adequate to eliminate power supply noise related problems in most designs. Using the MPC93H52 in Zero-Delay Applications Nested clock trees are typical applications for the MPC93H52. Designs using the MPC93H52 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC93H52 clock driver allows for its use as a zero delay buffer. One example configuration is to use a /4 output as a feedback to the PLL and configuring all other outputs to a divide-by-4 mode. The propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC93H52 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC93H52 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() * CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Figure 7. VCCA Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 7. VCCA Power Supply Filter, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC93H52 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be CCLKCommon --t() QFBDevice 1 tPD,LINE(FB) tJIT() Any QDevice 1 +tSK(O) +t() QFBDevice2 tJIT() Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 8. MPC93H51 Maximum Device-to-Device Skew FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 153 MPC93H52 Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 9. Table 9. Confidence Factor CF CF 1 2 3 4 5 6 Probability of Clock Edge within the Distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 IN MPC93H52 OUTPUT BUFFER 10 RS = 40 ZO = 50 OutB1 RS =40 ZO = 50 IN MPC93H52 OUTPUT BUFFER 10 RS =40 ZO = 50 OutA OutB0 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -445 ps to 395 ps relative to CCLK: tSK(PP) = tSK(PP) = [-200ps...150ps] + [-200ps...200ps] + [(15ps * -3)...(15ps * 3)] + tPD, LINE(FB) [-445ps...395ps] + tPD, LINE(FB) Figure 9. Single versus Dual Transmission Lines The waveform plots in Figure 10. Single versus Dual Waveforms and Figure 11. Optimized Dual Line Termination show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC93H51 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC93H51. The output waveform in Figure 10. Single versus Dual Waveforms and Figure 11. Optimized Dual Line Termination shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 40 || 40 R0 = 10 VL = 3.0 (25 / (20 + 10 + 25) = 1.36 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.7 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 11. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. Driving Transmission Lines The MPC93H52 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC93H52 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 9. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC93H52 clock driver is effectively doubled due to its capability to drive multiple lines. 154 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93H52 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (nS) 10 12 14 OutA tD = 3.8956 MPC93H52 OUTPUT BUFFER OutB tD = 3.9386 10 RS = 30 ZO = 50 RS = 30 ZO = 50 VOLTAGE (V) 10 + 30 || 30 = 50 || 50 25 = 25 Figure 11. Optimized Dual Line Termination Figure 10. Single versus Dual Waveforms Pulse Generator Z = 50 ZO = 50 MPC93H52 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 12. CCLK MPC93H52 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 155 MPC93H52 VCC VCC/2 GND VCC VCC/2 GND tSK(O) t() The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device FB_IN CCLK VCC VCC/2 GND VCC VCC/2 GND Figure 13. Output-to-Output Skew tSK(O) Figure 14. Propagation Delay (t(), status phase offset) Test Reference VCC VCC/2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage CCLK FB_IN TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 15. Output Duty Cycle (DC) Figure 16. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(P) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 17. Cycle-to-Cycle Jitter Figure 18. Period Jitter VCC=3.3V 2.4 0.55 tF tR Figure 19. Output Transition Time Test Reference 156 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC93R52 Rev 3, 08/2004 3.3V 1:11 LVCMOS Zero Delay Clock Generator The MPC93R52 is a 3.3V compatible, 1:11 PLL based clock generator targeted for high performance clock tree applications. With output frequencies up to 240 MHz and output skews lower than 200 ps the device meets the needs of most demanding clock applications. Features * * * * * * * * * * * * Configurable 11 outputs LVCMOS PLL clock generator Fully integrated PLL Wide range of output clock frequency of 16.67 MHz to 240 MHz Multiplication of the input reference clock frequency by 3, 2, 1, 3 / 2, 2 / 3, 1 / 3, and 1 / 2 3.3V LVCMOS compatible Maximum output skew of 200 ps Supports zero-delay applications Designed for high-performance telecom, networking and computing applications 32-lead LQFP package 32-lead Pb-free package available Ambient Temperature Range - 0C to +70C Pin and function compatible to the MPC952 MPC93R52 LOW VOLTAGE 3.3V LVCMOS 1:11 CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC93R52 is a fully 3.3V compatible PLL clock generator and clock driver. The device has the capability to generate output clock signals of 16.67 to 240 MHz from external clock sources. The internal PLL optimized for its frequency range and does not require external look filter components. One output of the MPC93R52 has to be connected to the PLL feedback input FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multiplication factor. This multiplication factor, F_RANGE and the reference clock frequency must be selected to situate the VCO in its specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx pins supporting systems with different but phase-aligned clock frequencies. The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50 transmission lines. Alternatively, each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22. The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The MPC93R52 is package in a 32 ld LQFP. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 157 MPC93R52 CCLK CCLK Ref FB PLL BANK A 1 /2 1 0 /6 /4 /2 1 0 QA0 QA1 VCO 0 QA2 QA3 QA4 BANK B QB0 QB1 FB_IN PLL_EN 200 - 480 MHz F_RANGE 1 0 FSELA FSELB QB2 QB3 BANK C 1 FSELC POWER-ON RESET MR/OE (All input resistors have a value of 25k) 0 QC0 QC1 Figure 1. MPC93R52 Logic Diagram GND 24 VCC QB2 QB3 GND GND QC0 QC1 VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 GND 17 16 15 14 VCC QA2 QA1 GND QA0 VCC VCCA PLL_EN 13 12 11 10 9 8 FB_IN QB1 QB0 QA4 6 CCLK MPC93R52 2 3 4 5 F_RANGE FSELB FSELC FSELA It is recommended to use an external RC filter for the analog power supply pin VCCA. Please see application section for details. Figure 2. Pinout: 32-Lead Package Pinout (Top View) 158 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MR/OE GND QA3 7 VCC VCC MPC93R52 ] Table 1. Pin Configuration Pin CCLK FB_IN F_RANGE FSELA FSELB FSELC PLL_EN MR/OE QA0-4, QB0-3, QC0-1 GND VCCA Input Input Input Input Input Input Input Input Output Supply Supply I/O Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC PLL reference clock signal PLL feedback signal input, connect to an output PLL frequency range select Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCCA. Please see applications section for details. Positive power supply for I/O and core Function VCC Supply VCC Table 2. Function Table Control Default 0 1 F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios. See Table 7 and Table 8 for supported frequency ranges and output to input frequency ratios. F_RANGE FSELA FSELB FSELC MR/OE 0 0 0 0 0 VCO / 1 (High input frequency range) Output divider / 4 Output divider / 4 Output divider / 2 Outputs enabled (active) VCO / 2 (Low input frequency range) Output divider / 6 Output divider / 2 Output divider / 4 Outputs disabled (high-impedance state) and reset of the device. During reset, the PLL feedback loop is open and the VCO is operating at its lowest frequency. The MPC93R52 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than two reference clock cycles (CCLK). The device is reset by the internal power-on reset (POR) circuitry during power-up. Test mode with PLL disabled. CCLK is substituted for the internal VCO output. MPC93R52 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. PLL_EN 0 Normal operation mode with PLL enabled. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 159 MPC93R52 Table 3. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 3.3V 5%, TA = 0 to 70C) Symbol VIH VIL VOH VOL ZOUT IIN ICCA ICCQ3 Input high voltage Input low voltage Output High Voltage Output Low Voltage Output impedance Input Current2 Maximum PLL Supply Current Maximum Quiescent Supply Current 3.0 7.0 2.4 0.55 0.30 14 - 17 200 5.0 1.0 Characteristics Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V V V A mA mA VIN=VCC or VIN=GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS IOH=-24 mA1 IOL= 24 mA IOL= 12 mA 1. The MPC93R52 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. Inputs have pull-down resistors affecting the input current. 3. ICCQ is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open. 160 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93R52 Table 6. AC Characteristics (VCC = 3.3V 5%, TA = 0 to 70C)1 Symbol fref Characteristics Input reference frequency in PLL mode2, 3 /4 feedback /6 feedback /8 feedback /12 feedback Input reference frequency in PLL bypass mode4 fVCO fMAX VCO lock frequency range5 Output Frequency /2 output6 /4 output /6 output /8 output /12 output Min 50.0 33.3 25.0 16.67 50.0 200 100 50 33.3 25 16.67 2.0 1.0 fref > 50 MHz -100 +200 150 100 100 50 47 0.1 50 53 1.0 8 10 output frequencies mixed all outputs same frequency Period Jitter I/O Phase Jitter9 output frequencies mixed all outputs same frequency /4 feedback divider RMS (1 ) /6 feedback divider RMS (1 ) /8 feedback divider RMS (1 ) /12 feedback divider RMS (1 ) /4 feedback /6 feedback /8 feedback /12 feedback 40 50 60 80 2.0 - 8.0 1.0 - 4.0 0.8 - 2.5 0.6 - 1.5 10 400 100 450 100 Typ Max 120.0 80.0 60.0 40.0 250.0 480 240 120 80 60 40 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns ns ps ps ps ps ps % ns ns ns ps ps ps ps ps ps ps ps MHz MHz MHz MHz ms 0.55 to 2.4V 0.8 to 2.0V PLL locked Condition tPWMIN tr, tf t() tsk(O) Minimum Reference Input Pulse Width CCLK Input Rise/Fall Time7 Propagation Delay CCLK to FB_IN (static phase offset) Output-to-output Skew8 all outputs, any frequency within QA output bank within QB output bank within QC output bank DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) Output duty cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter tJIT(PER) tJIT() BW PLL closed loop bandwidth10 tLOCK 1. 2. 3. 4. 5. 6. 7. Maximum PLL Lock Time AC characteristics apply for parallel output termination of 50 to VTT. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. The PLL may be unstable with a divide by 2 feedback ratio. In PLL bypass mode, the MPC93R52 divides the input reference clock. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO / FB. See Table 7 and Table 8 for output divider configurations. The MPC93R52 will operate with input rise and fall times up to 3.0 ns, but the AC characteristics, specifically t(), can only be guaranteed if tr/tf are within the specified range. 8. See application section for part-to-part skew calculation. 9. See application section for jitter calculation for other confidence factors with 1 . 10. -3 dB point of PLL transfer characteristics. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 161 MPC93R52 APPLICATIONS INFORMATION Programming the MPC93R52 The MPC93R52 supports output clock frequencies from 16.67 to 240 MHz. Different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. The feedback frequency and divider should be used to situate the VCO in the frequency lock range between 200 and 480 MHz for stable and optimal operation. The FSELA, FSELB, FSELC pins select the desired output clock frequencies. Possible frequency ratios of the reference clock input to the outputs are 1:1, 1:2, 1:3, 3:2 as well as 2:3, 3:1, and 2:1. Table 7 and Table 8 illustrate the various output configurations and frequency ratios supported by the MPC93R52. See also Figure 3. MPC93R52 Default Configuration to Figure 6. MPC93R52 Zero Delay Buffer Configuration 2 for further reference. A /2 output divider cannot be used for feedback. Table 7. MPC93R52 Example Configuration (F_RANGE = 0) PLL Feedback VCO / 42 fref1 [MHz] 50-120 FSELA 0 0 1 1 VCO / 63 33.3-80 1 1 1 1 FSELB 0 0 0 0 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 QA[0:4]:fref ratio fref fref (50-120 MHz) (50-120 MHz) QB[0:3]:fref ratio fref fref fref fref (50-120 MHz) (50-120 MHz) (50-120 MHz) (50-120 MHz) QC[0:1]:fref ratio fref 2 (100-240 MHz) fref (50-120 MHz) fref 2/3 (33-80 MHz) fref 2/3 (33-80 MHz) fref fref fref fref (33-80 MHz) (33-80 MHz) (33-80 MHz) (33-80 MHz) fref 2 (100-240 MHz) fref (50-120 MHz) fref 3/2 (50-120 MHz) fref 3/2 (50-120 MHz) fref 3 (100-240 MHz) fref 3 (100-240 MHz) fref 3 (100-240 MHz) fref 3/2 (50-120 MHz) fref 3 (100-240 MHz) fref 3/2 (50-120 MHz) 1. fref is the input clock reference frequency (CCLK) 2. QAx connected to FB_IN and FSELA=0 3. QAx connected to FB_IN and FSELA=1 Table 8. MPC93R52 Example Configurations (F_RANGE = 1) PLL Feedback VCO / 82 fref1 [MHz] 25-60 FSELA 0 0 1 1 VCO / 123 16.67-40 1 1 1 1 FSELB 0 0 0 0 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 QA[0:4]:fref ratio fref fref (25-60 MHz) (25-60 MHz) QB[0:3]:fref ratio fref fref fref fref (25-60 MHz) (25-60 MHz) (25-60 MHz) (25-60 MHz) QC[0:1]:fref ratio fref 2 (50-120 MHz) fref (25-60 MHz) fref 2/3 (16-40 MHz) fref 2/3 (16-40 MHz) fref fref fref fref (16-40 MHz) (16-40 MHz) (16-40 MHz) (16-40 MHz) fref 2 (50-120 MHz) fref (25-60 MHz) fref 3/2 (25-60 MHz) fref 3/2 (25-60 MHz) fref 3 (50-120 MHz) fref 3 (50-120 MHz) fref 3 (50-120 MHz) fref 3/2 (25-60 MHz) fref 3 (50-120 MHz) fref 3/2 (25-60 MHz) 1. fref is the input clock reference frequency (CCLK) 2. QAx connected to FB_IN and FSELA=0 3. QAx connected to FB_IN and FSELA=1 162 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93R52 Example Configurations for the MPC93R52 fref = 100 MHz CCLK QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QC0 QC1 fref = 62.5 MHz 100 MHz CCLK QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QC0 QC1 62.5 MHz FB_IN FSELA FSELB FSELC F_RANGE FB_IN FSELA FSELB FSELC F_RANGE 100 MHz VCC 62.5 MHz 62.5 MHz MPC93R52 100 MHz (Feedback) 200 MHz MPC93R52 62.5 MHz (Feedback) MPC93R52 default configuration (feedback of QB0 = 100 MHz). All control pins are left open. Frequency range Input QA outputs QB outputs QC outputs Min 50 MHz 50 MHz 50 MHz 100 MHz Max 120 MHz 12 MHz 120 MHz 240 MHz MPC93R52 zero-delay (feedback of QB0 = 62.5 MHz). All control pins are left open except FSELC = 1. All outputs are locked in frequency and phase to the input clock. Frequency range Input QA outputs QB outputs QC outputs Min 50 MHz 50 MHz 50 MHz 50 MHz Max 120 MHz 120 MHz 120 MHz 120 MHz Figure 3. MPC93R52 Default Configuration Figure 4. MPC93R52 Zero Delay Buffer Configuration QA0 QA1 QA2 QA3 QQ4 QB0 QB1 QB2 QB3 QC0 QC1 fref = 33.3 MHz CCLK FB_IN VCC VCC VCC FSELA FSELB FSELC F_RANGE MPC93R52 QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QC0 QC1 fref = 33.3 MHz 33.3 MHz CCLK 33.3 MHz FB_IN FSELA FSELB FSELC F_RANGE MPC93R52 50 MHz 100 MHz VCC VCC 33.3 MHz 33.3 MHz 33.3 MHz (Feedback) 33.3 MHz (Feedback) MPC93R52 configuration to multiply the reference frequency by 3, 3 / 2 and 1. PLL feedback of QA4 = 33.3 MHz. Frequency range Input QA outputs QB outputs QC outputs Min 25 MHz 50 MHz 50 MHz 100 MHz Max 60 MHz 120 MHz 120 MHz 240 MHz MPC93R52 zero-delay (feedback of QB0 = 33.3 MHz). Equivalent to Table 2 except F_RANGE = 1 enabling a lower input and output clock frequency. Frequency range Input QA outputs QB outputs QC outputs Min 25 MHz 25 MHz 25 MHz 25 MHz Max 60 MHz 60 MHz 60 MHz 60 MHz Figure 5. MPC93R52 Default Configuration Figure 6. MPC93R52 Zero Delay Buffer Configuration 2 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 163 MPC93R52 Power Supply Filtering The MPC93R52 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC93R52 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC93R52. Figure 7. VCCA Power Supply Filter illustrates a typical power supply filter scheme. The MPC93R52 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.98V must be maintained on the VCCA pin. The resistor RF shown in Figure 7. VCCA Power Supply Filter should have a resistance of 5-25 to meet the voltage drop criteria. RF = 5-25 RF CF = 22 F VCCA CF 10 nF MPC93R52 VCC 33...100 nF CCLKCommon --t() QFBDevice 1 tPD,LINE(FB) adequate to eliminate power supply noise related problems in most designs. Using the MPC93R52 in Zero-Delay Applications Nested clock trees are typical applications for the MPC93R52. Designs using the MPC93R52 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC93R52 clock driver allows for its use as a zero delay buffer. One example configuration is to use a /4 output as a feedback to the PLL and configuring all other outputs to a divide-by-4 mode. The propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC93R52 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC93R52 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() * CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: VCC Figure 7. VCCA Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 7. VCCA Power Supply Filter, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC93R52 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be tJIT() +tSK(O) +t() Any QDevice 1 QFBDevice2 tJIT() Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 8. MPC93R52 Max. Device-to-Device Skew 164 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93R52 Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 9. Table 9. Confidence Factor CF CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 IN MPC93R52 OUTPUT BUFFER 14 This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC93R52 clock driver. For the series terminated case however, there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 10. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC93R52 clock driver is effectively doubled due to its capability to drive multiple lines. The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -445 ps to 395 ps relative to CCLK: tSK(PP) = [-200ps...150ps] + [-200ps...200ps] + [(15ps * -3)...(15ps * 3)] + tPD, LINE(FB) tSK(PP) = [-445ps...395ps] + tPD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 9. Max. I/O Jitter versus Frequency, can be used for a more precise timing performance analysis. Max. I/O Jitter versus frequency 30 25 tJIT() [ps] rms 20 15 10 5 0 200 225 250 275 300 325 350 375 400 VCO frequency [MHz] RS = 36 ZO = 50 OutA MPC93R52 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 10. Single versus Dual Transmission Lines The waveform plots in Figure 11. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC93R52 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC93R52. The output waveform in Figure 11. Single versus Dual Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+17+25)) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). Figure 9. Max. I/O Jitter versus Frequency Driving Transmission Lines The MPC93R52 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 165 MPC93R52 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 MPC93R52 OUTPUT BUFFER 14 OutA tD = 3.8956 OutB tD = 3.9386 VOLTAGE (V) Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 12. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. RS = 22 ZO = 50 RS = 22 ZO = 50 Figure 11. Single versus Dual Waveforms 14 + 22 || 22 = 50 || 50 25 = 25 Figure 12. Optimized Dual Line Termination MPC93R52 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 13. CCLK MPC93R52 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V 166 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC93R52 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device FB_IN t() CCLK VCC VCC / 2 GND VCC VCC / 2 GND Figure 14. Output-to-Output Skew tSK(O) Figure 15. Propagation Delay (t(), static phase offset) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage FB_IN TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles CCLK Figure 16. Output Duty Cycle (DC) Figure 17. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 18. Cycle-to-Cycle Jitter Figure 19. Period Jitter VCC=3.3V 2.4 0.55 tF tR Figure 20. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 167 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9600 Rev 3, 08/2004 Product Preview Low Voltage 2.5 V and 3.3 V CMOS PLL Clock Driver The MPC9600 is a low voltage 2.5 V or 3.3 V compatible, 1:21 PLL based clock driver and fanout buffer. With output frequencies up to 200 MHz and output skews of 150 ps, the device meets the needs of the most demanding clock tree applications. Features MPC9600 3.3 V OR 2.5 V LOW VOLTAGE CMOS PLL CLOCK DRIVER Multiplication of input frequency by 2, 3, 4, and 6 Distribution of output frequency to 21 outputs organized in three output banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable * Fully integrated PLL FA SUFFIX * Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz 48-LEAD LQFP PACKAGE * Selectable input frequency range is 16.67 to 33 MHz and 25 to 50 MHz CASE 932-03 * LVCMOS outputs * Outputs disable to high impedance (except QFB) * LVCMOS or LVPECL reference clock options * 48-lead QFP packaging * 48-lead Pb-free Package Available * 50 ps cycle-to-cycle jitter * 150 ps maximum output-to-output skew * 200 ps maximum static phase offset window The MPC9600 is a fully LVCMOS 2.5 V or 3.3 V compatible PLL clock driver. The MPC9600 has the capability to generate clock signals of 50 to 200 MHz from clock sources of 16.67 to 50 MHz. The internal PLL is optimized for this frequency range and does not require external loop filter components. QFB provides an output for the external feedback path to the feedback input FB_IN. The QFB divider ratio is configurable and determines the PLL frequency multiplication factor when QFB is directly connected to FB_IN. The MPC9600 is optimized for minimizing the propagation delay between the clock input and FB_IN. Three output banks of 7 outputs each bank can be individually configured to divide the VCO frequency by 2 or by 4. Combining the feedback and output divider ratios, the MPC9600 is capable to multiply the input frequency by 2, 3, 4, and 6. The reference clock is selectable either LVPECL or LVCMOS. The LVPECL reference clock feature allows the designer to use LVPECL fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCMOS compatible levels. The outputs provide low impedance LVCMOS outputs capable of driving parallel terminated 50 transmission to VTT = VCC/2. For series terminated lines the MPC9600 can drive two lines per output giving the device an effective total fanout of 1:42. With guaranteed maximum output-to-output skew of 150 ps, the MPC9600 PLL clock driver meets the synchronization requirements of the most demanding systems. The VCCA analog power pin doubles as a PLL bypass select line for test purpose. When the VCCA is driven to GND the reference clock will bypass the PLL. The device is packaged in a 48-lead LQFP package to provide optimum combination of board density and performance. SCALE 2:1 * * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. 168 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9600 VCCA VCC 7 (PULLDOWN) (PULLDOWN) 1 FB (PULLUP) (PULLUP) VCC/2 200 - 400 MHz CCLK PCLK PCLK 0 Ref PLL 0 /2 1 /4 /8 /12 0 1 BANK A D Q QA0 QA1 QA2 QA3 QA4 QA5 REF_SEL FB_IN FSELA (PULLDOWN) 0 1 FSELB (PULLUP) 0 1 FSELC (PULLUP) 0 1 FSEL_FB OE (PULLUP) (PULLDOWN) 8 GND BANK B D Q 7 QA6 QB0-6 BANK C D Q 7 QC0-6 FEEDBACK D Q QFB Figure 1. MPC9600 Logic Diagram FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 169 MPC9600 Table 1. Pin Configuration - 48 LQFP Pin PCLK, PCLK CCLK FB_IN QAn QBn QCn QFB REF_SEL FSELA FSELB FSELC FSEL_FB OE VCCA VCC GND I/O Input Input Input Output Output Output Output Input Input Input Input Input Input Type PECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Power supply Power supply Ground Reference clock input PLL feedback clock input Bank A outputs Bank B outputs Bank C outputs Differential feedback output Reference clock input select Selection of bank A output frequency Selection of bank B output frequency Selection of bank C output frequency Selection of feedback frequency Output enable Analog power supply and PLL bypass. An external VCC filter is recommended for VCCA Core power supply Ground Description Differential reference clock frequency input GND GND QFB QB0 QB1 QB2 QB3 QB4 QB5 QB6 26 VCC 36 VCC QA6 QA5 QA4 GND QA3 QA2 VCC QA1 QA0 FB_IN GND 37 38 39 40 41 42 43 44 45 46 47 48 1 35 34 33 32 31 30 29 28 27 VCC 25 24 23 22 21 20 GND QC0 QC1 QC2 VCC QC3 QC4 GND QC5 QC6 OE VCC 19 18 17 16 15 14 13 12 GND MPC9600 2 3 4 5 6 7 8 9 10 11 REF_SEL FSEL_FB CCLK PCLK PCLK VCCA VCC FSELA FSELB Figure 2. 48-Lead Package Pinout (Top View) 170 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA FSELC GND MPC9600 Table 2. Function Table (Controls) Control Pin REF_SEL VCCA OE FSELA FSELB FSELC FSEL_FB 0 CCLK PLL Bypass 1 1 PCLK PLL Power Outputs Disabled (except QFB) Output Bank A at VCO/4 Output Bank B at VCO/4 Output Bank C at VCO/4 Feedback Output at VCO/12 Outputs Enabled Output Bank A at VCO/2 Output Bank B at VCO/2 Output Bank C at VCO/2 Feedback Output at VCO/8 1. VCCA = GND, PLL off and bypassed for static test and diagnosis Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TStor Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 -0.3 Max 4.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol VTT MM HBM CDM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 400 4000 1500 200 10 4.0 Min Typ VCC / 2 Max Unit V V V V mA pF pF Per output Inputs Condition FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 171 MPC9600 Table 5. DC Characteristics (VCC = 3.3 V 5%, TA = - 40C to +85C) Symbol VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICCA ICCQ Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage (DC) Common Mode Range (DC) Output High Voltage Output Low Voltage Output Impedance Input Leakage Current Maximum PLL Supply Current Maximum Quiescent Supply Current 2.0 14 - 17 150 5.0 1.0 PCLK, PCLK PCLK, PCLK 250 1.0 2.4 0.55 0.30 VCC - 0.6 Characteristics Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V mV V V V V W A mA mA VIN = VCC or GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -24 mA2 IOL = 24mA IOL = 12mA 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9600 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. Table 6. DC Characteristics (VCC = 2.5 V 5%, TA = - 40C to +85C) Symbol VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICCA ICCQ Input High Voltage Input Low Voltage Peak-to-Peak input voltage (DC) Common Mode Range (DC) Output High Voltage Output Low Voltage Output Impedance Input Leakage Current Maximum PLL Supply Current Maximum Quiescent Supply Current 3.0 17 - 20 150 5.0 1.0 PCLK, PCLK PCLK, PCLK 250 1.0 1.8 0.6 VCC - 0.6 Characteristics Min 1.7 Typ Max VCC + 0.3 0.7 Unit V V mV V V V W A mA mA VIN = VCC or GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -15 mA2 IOL = 15 mA 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9600 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 172 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9600 Table 7. AC Characteristics - 48 LQFP (VCC = 3.3 V 5% or VCC = 2.5 V 5%, TA = -40C to +85C)1 Symbol fref Input Frequency / 8 feedback (FSEL_FB = 0) / 12 feedback (FSEL_FB = 1) Static test mode (VCCA = GND) fVCO fMAX VCO Frequency Maximum Output Frequency / 2 outputs (FSELx = 0) / 4 outputs (FSELx = 1) Reference Input Duty Cycle Peak-to-Peak Input Voltage 2 Characteristics Min 25 16.67 0 200 100 50 25 PCLK, PCLK 500 1.2 1.2 Typ Max 50 33 500 400 200 100 75 1000 VCC -0.8 VCC -0.6 1.0 Unit MHz MHz MHz MHz MHz MHz % mV V V ns ps ps ps ps ps ps ps % ns ns ns MHz MHz Condition PLL locked PLL locked VCCA = GND PLL locked PLL locked frefDC VPP VCMR LVPECL LVPECL LVPECL see Figure 11 PLL locked PLL locked Measured at coincident rising edge Common Mode Range PCLK, PCLK (VCC = 3.3 V 5%) PCLK, PCLK (VCC = 2.5 V 5%) CCLK Input Rise/Fall Time Propagation Delay (static phase offset) CCLK to FB_IN PECL_CLK to FB_IN Output-to-Output Skew all outputs, single frequency all outputs, multiple frequency within QAx output bank within QBx outputs within QCx outputs 70 70 30 40 30 45 0.1 50 150 150 75 125 75 55 1.0 10 10 1.0 - 10 0.6 - 4.0 -60 +30 +40 +130 +140 +230 tr, tf t() tsk(o) DC tr, tf tPLZ, HZ tPZL, ZH BW Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time PLL Closed Loop Bandwidth / 8 feedback (FSEL_FB=0) / 12 feedback (FSEL_FB=1) Cycle-to-Cycle Jitter3 All outputs in / 2 configuration All outputs in / 4 configuration see Figure 11 -3 dB point of PLL transfer characteristic Refer to application section for other configurations Refer to application section for other configurations RMS value at fVCO = 400 MHz tJIT(CC) 40 40 25 20 130 180 70 100 174 15 3 ps ps ps ps ps ps ms tJIT(PER) Period Jitter3 All outputs in / 2 configuration All outputs in / 4 configuration tJIT() tLOCK I/O Phase Jitter (1 ) Maximum PLL Lock Time VCC = 3.3 V VCC = 2.5 V 5.0 1. AC characteristics are applicable over the entire ambient temperature and supply voltage range and are production tested. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). 3. Cycle-to-cycle and period jitter depends on output divider configuration. 4. See applications section for max I/O phase jitter versus frequency. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 173 MPC9600 APPLICATIONS INFORMATION Programming the MPC9600 The MPC9600 clock driver outputs can be configured into several divider modes. Additionally the external feedback of the device allows for flexibility in establishing various input to output frequency relationships. The selectable feedback divider of the three output groups allows the user to configure the device for 1:2, 1:3, 1:4 and 1:6 input:output frequency ratios. The use of even dividers ensure that the output duty cycle is always 50%. Table 8 illustrates the various output configurations, the table describes the outputs using the input clock frequency CLK as a reference. The feedback divider division settings establish the output relationship, in addition, it must be ensured that the VCO will be stable given the frequency of the outputs desired. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL supports output frequencies from 50 MHz to 200 MHz while the VCO frequency range is specified from 200 MHz to 400 MHz and should not be exceeded for stable operation. Table 8. Output Frequency Relationship1 for QFB Connected to FB_IN Configuration Inputs FSEL_FB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSELA 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSELB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16.67-33.33 25.0-50.0 Input Frequency Range CLK [MHz] Output Frequency Ratio and Range Ratio, QAx [MHz] 4*CLK 4*CLK 4*CLK 4*CLK 2*CLK 2*CLK 2*CLK 6*CLK 6*CLK 6*CLK 6*CLK 3*CLK 3*CLK 3*CLK 3*CLK (100-200) (100-200) (100-200) (100-200) (50.0-100) (50.0-100) (50.0-100) (100-200) (100-200) (100-200) (100-200) (50.0-100) (50.0-100) (50.0-100) (50.0-100) Ratio, QBx [MHz] 4*CLK 4*CLK 2*CLK 2*CLK 4*CLK 4*CLK 2*CLK 2*CLK 6*CLK 6*CLK 3*CLK 3*CLK 6*CLK 6*CLK 3*CLK 3*CLK (100-200) (100-200) (50.0-100) (50.0-100) (100-200) (100-200) (50.0-100) (50.0-100) (100-200) (100-200) (50.0-100) (50.0-100) (100-200) (100-200) (50.0-100) (50.0-100) Ratio, QCx [MHz] 4*CLK 2*CLK 4*CLK 2*CLK 4*CLK 2*CLK 4*CLK 2*CLK 6*CLK 3*CLK 6*CLK 3*CLK 6*CLK 3*CLK 6*CLK 3*CLK (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100) 2*CLK (50.0-100) 1. Output frequency relationship with respect to input reference frequency CLK. The VCO frequency range is always 200-400. 174 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9600 Table 9. Typical and Maximum Period Jitter Specification Device Configuration All output banks in / 2 or / 4 divider / 2 (FSELA = 0 and FESLB = 0 and FSELC = 0) / 4 (FSELA = 1 and FESLB = 1 and FSELC = 1) Mixed / 2// 4 divider configurations2 for output banks in / 2 divider configurations for output banks in / 4 divider configurations configuration1 QA0 to QA6 Typ 25 20 80 25 Max 50 70 130 70 QB0 to QB6 Typ 50 50 100 60 Max 70 100 150 100 QC0 to QC6 Typ 25 20 80 25 Max 50 70 130 70 1. In this configuration, all MPC9600 outputs generate the same clock frequency. See Figure 3 for an example configuration. 2. Multiple frequency generation. Jitter data are specified for each output divider separately. See Figure 7 for an example. Table 10. Typical and Maximum Cycle-to-Cycle Jitter Specification Device Configuration All output banks in / 2 or / 4 divider configuration1 / 2 (FSELA = 0 and FESLB = 0 and FSELC = 0) / 4 (FSELA = 1 and FESLB = 1 and FSELC = 1) Mixed /2// 4 divider configurations2 for output banks in / 2 divider configurations for output banks in / 4 divider configurations QA0 to QA6 Typ 40 40 150 30 Max 90 110 250 110 QB0 to QB6 Typ 80 120 200 120 Max 130 180 280 180 QC0 to QC6 Typ 40 40 150 30 Max 90 110 250 110 1. In this configuration, all MPC9600 outputs generate the same clock frequency. 2. Multiple frequency generation. Jitter data are specified for each output divider separately. fref = 20.833 MHz CCLK QA0-6 QB0-6 7 7 7 125 MHz 125 MHz 125 MHz fref = 33.33 MHz CCLK QA0-6 QB0-6 7 7 7 133.3 MHz 66.67 MHz 66.67 MHz FB_IN 1 0 0 0 FSEL_FB FSELA FSELB FSELC MPC9600 QC0-6 FB_IN 0 0 1 1 FSEL_FB FSELA FSELB FSELC QC0-6 QFB QFB MPC9600 20.833 MHz (Feedback) Frequency Range Input QA outputs QB outputs QC outputs Min 16.67 MHz 100 MHz 100 MHz 100 MHz Max 33.33 MHz 200 MHz 200 MHz 200 MHz 33.33 MHz (Feedback) Frequency Range Input QA outputs QB outputs QC outputs Min 25 MHz 100 MHz 100 MHz 100 MHz Max 50 MHz 200 MHz 200 MHz 200 MHz Figure 3. Configuration for 126 MHz Clocks Figure 4. Configuration for 133.3/66.67 MHz Clocks FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 175 MPC9600 Power Supply Filtering The MPC9600 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9600 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9600. Figure 5 illustrates a typical power supply filter scheme. The MPC9600 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325 V (VCC = 3.3 V or VCC = 2.5 V) must be maintained on the VCCA pin. The resistor RF shown in Figure 5, must have a resistance of 9-10 (VCC = 2.5 V) to meet the voltage drop criteria. The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 5, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. RF = 9-10 for VCC = 2.5 V or VCC = 3.3 V CF = 22 F for VCC = 2.5 V or VCC = 3.3 V RF VCC CF 10 nF MPC9600 VCC 33...100 nF QFBDevice 1 tJIT() VCCA TCLKCommon --t() tPD,LINE(FB) adequate to eliminate power supply noise related problems in most designs. Using the MPC9600 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9600. For these applications the MPC9600 offers a differential LVPECL clock input pair as a PLL reference. This allows for the use of differential LVPECL primary clock distribution devices such as the Motorola MC100ES6111 or MC100ES6226, taking advantage of its superior low-skew performance. Clock trees using LVPECL for clock distribution and the MPC9600 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9600 PLL allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. The remaining insertion delay (skew error) of the MPC9600 in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset (SPO or t()), I/O jitter (tJIT(), phase or long-term jitter), feedback path delay and the output-to-output skew (tSK(O)) relative to the feedback output. Features Calculation of Part-to-Part Skew The MPC9600 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (CCLK or PCLK) of two or more MPC9600 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() * CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Figure 5. VCCA Power Supply Filter As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9600 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be Any QDevice 1 +tSK(O) +t() QFBDevice2 tJIT() Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 6. MPC9600 Maximum Device-to-Device Skew 176 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9600 Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 11. Table 11. Confidence Factor CF CF 1 2 3 4 5 6 Probability of Clock Edge Within the Distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC /2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9600 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 8 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9600 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9600 OUTPUT BUFFER IN 14 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -261 ps to 341 ps relative to CCLK (VCC = 3.3 V and fVCO = 200 MHz): tSK(PP) = [-60 ps...140 ps] + [-150 ps...150 ps] + [(17 ps @ -3)...(17 ps @ 3)] + tPD, LINE(FB) tSK(PP) = [-261 ps...341 ps] + tPD, LINE(FB) Above equation uses the maximum I/O jitter number shown in the AC characteristic table for VCC = 3.3 V (17 ps RMS). I/O jitter is frequency dependant with a maximum at the lowest VCO frequency (200 MHz for the MPC9600). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in Figure 7 can be used to derive a smaller I/O jitter number at the specific VCO frequency, resulting in tighter timing limits in zero-delay mode and for part-to-part skew tSK(PP). Maximum I/O Jitter versus Frequency 18 16 14 12 10 8 6 4 2 0 200 VCC = 3.3 V VCC = 2.5 V RS = 36 ZO = 50 OutA MPC9600 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 8. Single versus Dual Transmission Lines The waveform plots in Figure 9 shows the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9600 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9600. The output waveform in Figure 9 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18 + 17 + 25) = 1.31 V tjit(o) [ps] rms 220 240 260 280 300 320 340 360 380 400 VCO FREQUENCY (MHz) Figure 7. I/O Jitter versus VCO Frequency for VCC = 2.5 V and VCC = 3.3 V Driving Transmission Lines The MPC9600 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 177 MPC9600 At the load end the voltage will double due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 10 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9600 OUTPUT BUFFER 14 RS = 22 ZO = 50 VOLTAGE (V) RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 10. Optimized Dual Line Termination The following figures illustrate the measurement reference for the MPC9600 clock driver circuit. Figure 9. Single versus Dual Waveforms MPC9600 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 11. CCLK MPC9600 AC Test Reference Differential Pulse Generator Z = 50 ZO = 50 MPC9600 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 12. PCLK MPC9600 AC Test Reference 178 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9600 PCLK PCLK VPP VCMR VCC VCC / 2 GND t() t() TCLK VCC VCC / 2 GND FB_IN VCC VCC / 2 GND FB_IN Figure 14. Propagation Delay (tO, status phase offset) Test Reference Figure 15. Propagation Delay (tO) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage tSK(O) VCC VCC / 2 GND VCC VCC / 2 GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 16. Output Duty Cycle (DC) Figure 17. Output-to-Output Skew tSK(O) TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(P) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 18. Cycle-to-Cycle Jitter Figure 19. Period Jitter CCLK (PCLK) FB_IN TJIT() = |T0-T1mean| tF The deviation in T0 for a controlled edge with respect to a T0 mean in a random sample of cycles tR VCC = 3.3 V 2.4 0.55 VCC = 2.5 V 1.8 0.6 Figure 20. I/O Jitter Figure 21. Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 179 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9772 Rev 4, 08/2004 3.3V 1:12 LVCMOS PLL Clock Generator The MPC9772 is a 3.3V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * * * MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR 1:12 PLL based low-voltage clock generator 3.3V power supply Internal power-on reset FA SUFFIX Generates clock signals up to 240 MHz 52-LEAD LQFP PACKAGE Maximum output skew of 250 ps CASE 848D-03 On-chip crystal oscillator clock reference Two LVCMOS PLL reference clock inputs External PLL feedback supports zero-delay capability Various feedback and output dividers (see application section) Supports up to three individual generated output clock frequencies Synchronous output clock stop circuitry for each individual output for power down support Drives up to 24 clock lines Ambient temperature range 0C to +70C Pin and function compatible to the MPC972 52-lead Pb-free Package Available Functional Description The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1, and 8:3. The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-binary factor. The MPC9772 also supports the 180 phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the MPC9772. The MPC9772 has an internal power-on reset. The MPC9772 is fully 3.3V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package. 180 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9772 All input resistors have a value of 25k XTAL_IN XTAL_OUT XTAL VCC CCLK0 CCLK1 CCLK_SEL REF_SEL FB_IN VCO_SEL PLL_EN VCC FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] VCC INV_CLK STOP_DATA STOP_CLK MR/OE 12 POWER-ON RESET 2 2 2 3 0 1 VCC FB PLL 0 1 Ref VCO /2 /1 0 1 0 1 /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 /4, /6, /8, /10 /12, /16, /20 SYNC PULSE QA0 BANK A CLK STOP QA1 QA2 QA3 QB0 BANK B CLK STOP QB1 QB2 QB3 BANK C QC0 CLK STOP 0 1 CLK STOP QC1 QC2 QC3 QFB CLK STOP QSYNC CLOCK STOP Figure 1. MPC9772 Logic Diagram GND QB0 VCC QB1 GND QB2 VCC QB3 FB_IN GND QFB VCC FSEL_FB0 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VCC QA2 GND QA1 VCC QA0 GND VCO_SEL 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 20 46 MPC9772 19 47 18 48 17 49 16 50 15 51 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 GND MR/OE STOP_CLK STOP_DATA FSEL_FB2 PLL_EN REF_SEL CCLK_SEL CCLK0 CCLK1 XTAL_IN XTAL_OUT VCC_PLL FSEL_FB1 QSYNC GND QC0 VCC QC1 FSEL_C0 FSEL_C1 QC2 VCC QC3 GND INV_CLK Figure 2. MPC9772 52-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 181 MPC9772 Table 1. Pin Configuration Pin CCLK0 CCLK1 XTAL_IN, XTAL_OUT FB_IN CCLK_SEL REF_SEL VCO_SEL PLL_EN MR/OE FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] INV_CLK STOP_CLK STOP_DATA QA[0-3] QB[0-3] QC[0-3] QFB QSYNC GND VCC_PLL VCC Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Supply Supply Supply I/O Input Input Type LVCMOS LVCMOS Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock Alternative PLL reference clock Crystal oscillator interface PLL feedback signal input, connect to an QFB LVCMOS clock reference select LVCMOS/PECL reference clock select VCO operating frequency select PLL enable/PLL bypass mode select Output enable/disable (high-impedance tristate) and device reset Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs Frequency divider select for the QFB output Clock phase selection for outputs QC2 and QC3 Clock input for clock stop circuitry Configuration data input for clock stop circuitry Clock outputs (Bank A) Clock outputs (Bank B) Clock outputs (Bank C) PLL feedback output. Connect to FB_IN. Synchronization pulse output Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function Table 2. Function Table (Configuration Controls) Control REF_SEL CCLK_SEL VCO_SEL PLL_EN Default 1 1 1 1 0 Selects CCLKx as the PLL reference clock Selects CCLK0 Selects VCO/2. The VCO frequency is scaled by a factor of 2 (low VCO frequency range). 1 Selects the crystal oscillator as the PLL reference clock Selects CCLK1 Selects VCO/1. (high VCO frequency range) Test mode with the PLL bypassed. The reference clock is substituted for the Normal operation mode with PLL enabled. internal VCO output. MPC9772 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. QC2 and QC3 are in phase with QC0 and QC1 QC2 and QC3 are inverted (180 phase shift) with respect to QC0 and QC1 INV_CLK MR/OE 1 1 Outputs disabled (high-impedance state) and device is reset. During reset/ Outputs enabled (active) output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9772 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power-on reset (POR) circuitry during power-up. VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency ratios. See Table 3 to Table 6 and the APPLICATIONS INFORMATION for supported frequency ranges and output to input frequency ratios. 182 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9772 Table 3. Output Divider Bank A (NA) VCO_SEL 0 0 0 0 1 1 1 1 FSEL_A1 0 0 1 1 0 0 1 1 FSEL_A0 0 1 0 1 0 1 0 1 QA[0:3] VCO/8 VCO/12 VCO/16 VCO/24 VCO/4 VCO/6 VCO/8 VCO/12 Table 5. Output Divider Bank C (NC) VCO_SEL 0 0 0 0 1 1 1 1 FSEL_C1 0 0 1 1 0 0 1 1 FSEL_C0 0 1 0 1 0 1 0 1 QC[0:3] VCO/4 VCO/8 VCO/12 VCO/16 VCO/2 VCO/4 VCO/6 VCO/8 Table 4. Output Divider Bank B (NB) VCO_SEL 0 0 0 0 1 1 1 1 FSEL_B1 0 0 1 1 0 0 1 1 FSEL_B0 0 1 0 1 0 1 0 1 QB[0:3] VCO/8 VCO/12 VCO/16 VCO/20 VCO/4 VCO/6 VCO/8 VCO/10 Table 6. Output Divider PLL Feedback (M) VCO_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSEL_FB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QFB VCO/8 VCO/12 VCO/16 VCO/20 VCO/16 VCO/24 VCO/32 VCO/40 VCO/4 VCO/6 VCO/8 VCO/10 VCO/8 VCO/12 VCO/16 VCO/20 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 183 MPC9772 Table 7. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 12 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 8. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 9. DC Characteristics (VCC = 3.3V 5%, TA = -40 to 85C) Symbol VCC_PLL VIH VIL VOH VOL ZOUT IIN ICC_PLL ICCQ Characteristics PLL Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current2 Maximum PLL Supply Current Maximum Quiescent Supply Current 3.0 14 - 17 200 5.0 15 2.4 0.55 0.30 Min 3.0 2.0 Typ Max VCC VCC + 0.3 0.8 Unit V V V V V V W A mA mA VIN = VCC or GND VCC_PLL Pin All VCC Pins Condition LVCMOS LVCMOS LVCMOS IOH=-24 mA1 IOL= 24 mA IOL= 12 mA 1. The MPC9772 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. Inputs have pull-down resistors affecting the input current. 184 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9772 Table 10. AC Characteristics (VCC = 3.3V 5%, TA = -40 to +85C)1, 2 Max Symbol Characteristics Min Typ TA = 0C TA = -40C to +70C to +85C 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 15.0 12.0 250 200 10 /2 output /4 output /6 output /8 output /10 output /12 output /16 output /20 output /24 output 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 240.0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 20 2.0 1.0 480 25 230.00 115.00 76.67 57.50 46.00 38.33 28.75 23.00 19.16 115.00 76.67 57.50 46.00 38.33 28.75 23.00 19.16 14.37 11.50 250 460 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns ns ps ps ps ps ps ps ns ns ns ps ps 0.55 to 2.4V 0.8 to 2.0V PLL locked -3 -4 -166 +3 +4 +166 100 100 100 250 (T/2) - 200 0.1 T/2 (T/2) + 200 1.0 8 8 150 200 150 PLL locked PLL locked Unit Condition fREF Input reference frequency /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00 Input reference frequency in PLL bypass mode3 fVCO fXTAL fMAX VCO frequency range4 Crystal interface frequency range4 Output Frequency PLL bypass fSTOP_CLK Serial interface clock frequency tPW,MIN tR, tF t() Input Reference Pulse Width5 CCLKx Input Rise/Fall Time6 Propagation Delay (static phase offset)7 CCLK to FB_IN 6.25 MHz < fREF < 65.0 MHz 65.0 MHz < fREF < 125 MHz fREF=50 MHz and feedback=/8 Output-to-output Skew8 within QA outputs within QB outputs within QC outputs all outputs tSK(O) DC tR, tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) Output Duty Cycle9 Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle Jitter10 Period Jitter11 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 185 MPC9772 Table 10. AC Characteristics (VCC = 3.3V 5%, TA = -40 to +85C)1, 2 (Continued) Max Symbol Characteristics Min Typ TA = 0C TA = -40C to +70C to +85C 11 86 13 88 16 19 21 22 27 30 1.20 - 3.50 0.70 - 2.50 0.50 - 1.80 0.45 - 1.20 0.30 - 1.00 0.25 - 0.70 0.20 - 0.55 0.17 - 0.40 0.12 - 0.30 0.11 - 0.28 10 ps ps ps ps ps ps ps ps ps ps MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz (VCO=400 MHz) Unit Condition tJIT() I/O Phase Jitter RMS (1 )12 /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback BW PLL closed loop bandwidth13 tLOCK 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Maximum PLL Lock Time ms AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9772 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF= fVCO / (M VCO_SEL). The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio: fXTAL(min, max) = fVCO(min, max) / (M VCO_SEL) and 10 MHz fXTAL 25 MHz. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF, MIN. The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. Static phase offset depends on the reference frequency. t() [s] = t() [] / (fREF 360). Excluding QSYNC output. See application section for part-to-part skew calculation. Output duty cycle is DC = (0.5 200 ps fOUT) 100%. E.g. the DC range at fOUT = 100 MHz is 48% FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9772 APPLICATIONS INFORMATION MPC9772 Configurations Configuring the MPC9772 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: fOUT = fREF M / N fREF PLL /VCO_SEL /N fOUT frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and output divider: fQA[0:3] = fVCO / (VCO_SEL NA) fQB[0:3] = fVCO / (VCO_SEL NB) fQC[0:3] = fVCO / (VCO_SEL NC) Table 11. MPC9772 Divider /M Divider M Function PLL feedback FSEL_FB[0:3] Bank A Output Divider FSEL_A[0:1] Bank B Output Divider FSEL_B[0:1] Bank C Output Divider FSEL_C[0:1] VCO_SEL /1 /2 /1 /2 /1 /2 /1 /2 Values 4, 6, 8, 10, 12, 16 8, 12, 16, 20, 24, 32, 40 4, 6, 8, 12 8, 12, 16, 24 4, 6, 8, 10 8, 12, 16, 20 2, 4, 6, 8 4, 8, 12, 16 where fREF is the reference frequency of the selected input clock source (CCLKO, CCLK1 or XTAL interface), M is the PLL feedback divider and N is a output divider. The PLL feedback divider is configured by the FSEL_FB[2:0] and the output dividers are individually configured for each output bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0] inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 480 MHz in order to achieve stable PLL operation: fVCO,MIN (fREF VCO_SEL M) fVCO,MAX The PLL post-divider VCO_SEL is either a divide-by-one or a divide-by-two and can be used to situate the VCO into the specified frequency range. This divider is controlled by the VCO_SEL pin. VCO_SEL effectively extends the usable input NA NB NC Table 11 shows the various PLL feedback and output dividers and Figure 3. Example Configuration and Figure 4. Example Configuration display example configurations for the MPC9772: Figure 4. Example Configuration Figure 3. Example Configuration CCLK0 CCLK1 CCLK_SEL 1 VCO_SEL FB_IN 11 00 00 101 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0] MPC9772 fref = 33.3 MHz QA[3:0] QB[3:0] QC[3:0] QFB 33.3 MHz 100 MHz 200 MHz fref = 25 MHz CCLK0 CCLK1 CCLK_SEL 1 VCO_SEL FB_IN 00 00 00 011 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0] MPC9772 QA[3:0] QB[3:0] QC[3:0] QFB 62.5 MHz 62.5 MHz 125 MHz 33.3 MHz (Feedback) 25 MHz (Feedback) MPC9772 example configuration (feedback of QFB = 33.3 MHz, fVCO=400 MHz, VCO_SEL=/1, M=12, NA=12, NB=4, NC=2). Frequency Range TA = 0C to +70C TA = -40C to +85C Input QA Outputs QA Outputs QC Outputs 16.6 - 40 MHz 16.6 - 40 MHz 50 - 120 MHz 100 - 240 MHz 16.6 - 38.33 MHz 16.6 - 38.33 MHz 50 - 115 MHz 100 - 230 MHz MPC9772 example configuration (feedback of QFB = 25 MHz, fVCO=250 MHz, VCO_SEL=/1, M=10, NA=4, NB=4, NC=2). Frequency Range TA = 0C to +70C TA = -40C to +85C Input QA Outputs QA Outputs QC Outputs 20 - 48 MHz 50 - 120 MHz 50 - 120 MHz 100 - 240 MHz 20 - 46 MHz 50 - 115 MHz 50 - 115 MHz 100 - 230 MHz FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 187 MPC9772 MPC9772 Individual Output Disable (Clock Stop) Circuitry The individual clock stop (output enable) control of the MPC9772 allows designers, under software control, to implement power management into the clock distribution design. A simple serial interface and a clock stop control logic provides a mechanism through which the MPC9772 clock outputs can be individually stopped in the logic `0' state: The clock stop mechanism allows serial loading of a 12-bit serial input register. This register contains one programmable clock stop bit for 12 of the 14 output clocks. The QC0 and QFB outputs cannot be stopped (disabled) with the serial port. The user can program an output clock to stop (disable) by writing logic `0' to the respective stop enable bit. Likewise, the user may programmably enable an output clock by writing logic `1' to the respective enable bit. The clock stop logic enables or disables clock outputs during the time when the output would be in normally in logic low state, eliminating the possibility of short or `runt' clock pulses. The user can write to the serial input register through the STOP_DATA input by supplying a logic `0' start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free--running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC9772 can sample each STOP_DATA bit with the rising edge of the free--running STOP_CLK signal. (See Figure 5. Clock Stop Circuit Programming.) STOP_CLK STOP_DATA START QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC Figure 5. Clock Stop Circuit Programming 188 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9772 SYNC Output Description The MPC9772 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9772 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the fVCO 1:1 Mode QA QC QSYNC 2:1 Mode QA QC QSYNC 3:1 Mode QC(/2) QA(/6) QSYNC 3:2 Mode QA(/4) QC(/6) QSYNC 4:1 Mode QC(/2) QA(/8) QSYNC 4:3 Mode QA(/6) QC(/8) QSYNC 6:1 Mode QA(/12) QC(/2) QSYNC coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse is dependent QA and QC output frequencies: the QSYNC pulse width is equal to the period of the higher of the QA and QC output frequencies. Figure 6. QSYNC Timing Diagram shows various waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank C outputs. Figure 6. QSYNC Timing Diagram FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 189 MPC9772 Power Supply Filtering The MPC9772 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9772 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA_PLL pin for the MPC9772. Figure 7. VCC_PLL Power Supply Filter illustrates a typical power supply filter scheme. The MPC9772 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 3.0V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 7. VCC_PLL Power Supply Filter must have a resistance of 5-10 to meet the voltage drop criteria. RF = 5-10 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9772 CCLKCommon VCC 33...100 nF QFBDevice 1 -t() tPD,LINE(FB) supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9772 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9772. Designs using the MPC9772 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9772 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC9772 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9772 are connected together, the maximum overall timing uncertainty from the common CCLKx input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: tJIT() +tSK(O) +t() Figure 7. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 7. VCC_PLL Power Supply Filter, the filter cut-off frequency is around 4.5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9772 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power Any QDevice 1 QFBDevice2 tJIT() Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 8. MPC9772 Maximum Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12. Confidence Factor CF. 190 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9772 Table 12. Confidence Factor CF CF 1 2 3 4 5 6 Probability of Clock Edge within the Distribution 0.68268948 tjit() [ps] RMS 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 120 100 80 60 40 20 0 200 FB=/12 FB=/6 FB=/24 Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 250 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. Due to the frequency dependence of the static phase offset and I/O jitter, using Figure 9. MPC9772 I/O Jitter to Figure 11. MPC9772 I/O Jitter to predict a maximum I/O jitter and the specified t() parameter relative to the input reference frequency results in a precise timing performance analysis. In the following example calculation an I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from the common input reference clock to any output of -455 ps to +455 ps relative to CCLK (PLL feedback = /8, reference frequency = 50 MHz, VCO frequency = 400 MHz, I/O jitter = 13 ps rms max., static phase offset t() = 166 ps): tSK(PP) = tSK(PP) = [-166ps...166ps] + [-250ps...250ps] + [(13ps @ -3)...(13ps @ 3)] + tPD, LINE(FB) [-455ps...455ps] + tPD, LINE(FB) 300 350 400 VCO Frequency [MHz] 450 480 Figure 10. MPC9772 I/O Jitter Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 140 120 tjit() [ps] RMS 100 80 60 40 20 0 200 FB=/10 FB=/40 FB=/20 250 300 350 400 VCO Frequency [MHz] 450 480 Figure 11. MPC9772 I/O Jitter Driving Transmission Lines The MPC9772 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9772 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 12. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9772 clock driver is effectively doubled due to its capability to drive multiple lines. Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 160 140 FB=/32 120 100 FB=/16 80 FB=/8 60 40 20 FB=/4 0 200 250 300 350 400 VCO Frequency [MHz] tjit() [ps] RMS 450 480 Figure 9. MPC9772 I/O Jitter FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 191 MPC9772 quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 3.0 RS = 36 ZO = 50 OutA 2.5 2.0 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 0.5 VOLTAGE (V) In 1.5 1.0 OutA tD = 3.8956 OutB tD = 3.9386 MPC9772 OUTPUT BUFFER IN 14 MPC9772 OUTPUT BUFFER IN 14 RS = 36 Figure 12. Single versus Dual Transmission Lines The waveform plots in Figure 13. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9772 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9772. The output waveform in Figure 13. Single versus Dual Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+17+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the 0 2 4 6 8 TIME (ns) 10 12 14 Figure 13. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 14. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9772 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 14. Optimized Dual Line Termination MPC9772 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 15. CCLK MPC9772 AC Test Reference 192 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9772 VCC VCC/2 GND VCC VCC/2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t() CCLKx VCC VCC/2 GND FB_IN VCC VCC/2 GND Figure 16. Output-to-Output Skew tSK(O) VCC VCC/2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 17. Propagation Delay (t(), Static Phase Offset) Test Reference CCLKx FB_IN TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 18. Output Duty Cycle (DC) Figure 19. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 20. Cycle-to-Cycle Jitter Figure 21. Period Jitter VCC=3.3V 2.4 0.55 tF tR Figure 22. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 193 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9773 Rev 4, 08/2004 3.3 V 1:12 LVCMOS PLL Clock Generator The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted for high-performance low-skew clock distribution in mid-range to high-performance networking, computing, and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * * * MPC9773 3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR 1:12 PLL based low-voltage clock generator 3.3 V power supply Internal power-on reset FA SUFFIX Generates clock signals up to 240 MHz 52-LEAD LQFP PACKAGE Maximum output skew of 250 ps CASE 848D-03 Differential PECL reference clock input Two LVCMOS PLL reference clock inputs External PLL feedback supports zero-delay capability Various feedback and output dividers (refer to Application Section) Supports up to three individual generated output clock frequencies Synchronous output clock stop circuitry for each individual output for power down support Drives up to 24 clock lines Ambient temperature range 0C to +70C Pin and function compatible to the MPC973 52-lead Pb-free Package Available Functional Description The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3. The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-binary factor. The MPC9773 also supports the 180 phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the MPC9773. The MPC9773 has an internal power-on reset. The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package. 194 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9773 All input resistors have a value of 25 k PCLK PCLK VCC CCLK0 CCLK1 CCLK_SEL REF_SEL FB_IN VCO_SEL PLL_EN VCC FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] VCC INV_CLK STOP_DATA STOP_CLK MR/OE 12 POWER-ON RESET 2 2 2 3 0 1 VCC FB PLL 200-480 MHz 1 0 Ref VCO /2 /1 0 1 0 1 /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 /4, /6, /8, /10 /12, /16, /20 SYNC PULSE QA0 BANK A CLK STOP QA1 QA2 QA3 QB0 BANK B CLK STOP QB1 QB2 QB3 BANK C CLK STOP 0 1 CLK STOP QC0 QC1 QC2 QC3 QFB CLK STOP QSYNC CLOCK STOP Figure 1. MPC9773 Logic Diagram GND QB0 VCC QB1 GND QB2 VCC QB3 FB_IN GND QFB VCC FSEL_FB0 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VCC QA2 GND QA1 VCC QA0 GND VCO_SEL 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 MPC9773 20 46 19 47 18 48 17 49 16 50 15 51 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 GND MR/OE STOP_CLK STOP_DATA FSEL_FB2 PLL_EN REF_SEL CCLK_SEL CCLK0 CCLK1 VCC_PLL PCLK PCLK FSEL_FB1 QSYNC GND QC0 VCC QC1 FSEL_C0 FSEL_C1 QC2 VCC QC3 GND INV_CLK Figure 2. MPC9773 52-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 195 MPC9773 Table 1. Pin Configuration Pin CCLK0 CCLK1 PCLK, PCLK FB_IN CCLK_SEL REF_SEL VCO_SEL PLL_EN MR/OE FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] INV_CLK STOP_CLK STOP_DATA QA[0-3] QB[0-3] QC[0-3] QFB QSYNC GND VCC_PLL VCC I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Supply Supply Supply Type LVCMOS LVCMOS LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock Alternative PLL reference clock Differential LVPECL reference clock PLL feedback signal input, connect to an QFB LVCMOS clock reference select LVCMOS/PECL reference clock select VCO operating frequency select PLL enable/PLL bypass mode select Output enable/disable (high-impedance tristate) and device reset Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs Frequency divider select for the QFB output Clock phase selection for outputs QC2 and QC3 Clock input for clock stop circuitry Configuration data input for clock stop circuitry Clock outputs (Bank A) Clock outputs (Bank B) Clock outputs (Bank C) PLL feedback output. Connect to FB_IN. Synchronization pulse output Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please refer to applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function Table 2. Function Table (Configuration Controls) Control REF_SEL CCLK_SEL VCO_SEL PLL_EN Default 1 1 1 1 0 Selects CCLKx as the PLL reference clock Selects CCLK0 Selects VCO / 2. The VCO frequency is scaled by a factor of 2 (low VCO frequency range). 1 Selects the LVPECL inputs as the PLL reference clock Selects CCLK1 Selects VCO / 1 (high VCO frequency range) Test mode with the PLL bypassed. The reference clock is substituted for the Normal operation mode with PLL enabled. internal VCO output. MPC9773 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. QC2 and QC3 are in phase with QC0 and QC1 QC2 and QC3 are inverted (180 phase shift) with respect to QC0 and QC1 INV_CLK MR/OE 1 1 Outputs disabled (high-impedance state) and device is reset. During reset/ Outputs enabled (active) output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9773 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power-on reset (POR) circuitry during power-up. VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency ratios. See Table 3 to Table 6 and the Applications Section for supported frequency ranges and output to input frequency ratios. 196 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9773 Table 3. Output Divider Bank A (NA) VCO_SEL 0 0 0 0 1 1 1 1 FSEL_A1 0 0 1 1 0 0 1 1 FSEL_A0 0 1 0 1 0 1 0 1 QA[0:3] VCO / 8 VCO / 12 VCO / 16 VCO / 24 VCO / 4 VCO / 6 VCO / 8 VCO / 12 Table 5. Ouput Divider Bank (NC) VCO_SEL 0 0 0 0 1 1 1 1 FSEL_C1 0 0 1 1 0 0 1 1 FSEL_C0 0 1 0 1 0 1 0 1 QC[0:3] VCO / 4 VCO / 8 VCO / 12 VCO / 16 VCO / 2 VCO / 4 VCO / 6 VCO / 8 Table 4. Output Divider Bank (NB) VCO_SEL 0 0 0 0 1 1 1 1 FSEL_B1 0 0 1 1 0 0 1 1 FSEL_B0 0 1 0 1 0 1 0 1 QB[0:3] VCO / 8 VCO / 12 VCO / 16 VCO / 20 VCO / 4 VCO / 6 VCO / 8 VCO / 10 Table 6. Output Divider PLL Feedback (M) VCO_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSEL_FB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QFB VCO / 8 VCO / 12 VCO / 16 VCO / 20 VCO / 16 VCO / 24 VCO / 32 VCO / 40 VCO / 4 VCO / 6 VCO / 8 VCO / 10 VCO / 8 VCO / 12 VCO / 16 VCO / 20 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 197 MPC9773 Table 7. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 12 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 8. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 9. DC Characteristics (VCC = 3.3 V 5%, TA = 0C to 70C) Symbol VCC_PLL PLL Supply Voltage VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICC_PLL ICCQ Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage Output Impedance Input Current3 Maximum PLL Supply Current Maximum Quiescent Supply Current 8.0 14 - 17 200 13.5 35 PCLK, PCLK PCLK, PCLK 250 1.0 2.4 0.55 0.30 VCC - 0.6 Characteristics Min 3.0 2.0 Typ Max VCC VCC + 0.3 0.8 Unit V V V mV V V V V A mA mA VIN = VCC or GND VCC_PLL Pin All VCC Pins Condition LVCMOS LVCMOS LVCMOS LVPECL LVPECL IOH = -24 mA2 IOL = 24 mA IOL = 12 mA 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9773 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 3. Inputs have pull-down resistors affecting the input current. 198 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9773 Table 10. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to 70C)1, 2 Symbol fREF Characteristics Input Reference Frequency / 4 feedback / 6 feedback / 8 feedback / 10 feedback / 12 feedback / 16 feedback / 20 feedback / 24 feedback / 32 feedback / 40 feedback Min 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00 Typ Max 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 15.0 12.0 250 200 / 2 output / 4 output / 6 output / 8 output / 10 output / 12 output / 16 output / 20 output / 24 output 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 480 240.0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 20 PCLK, PCLK PCLK, PCLK 400 1.2 2.0 1.0 -3 -4 -166 +3 +4 +166 100 100 100 250 (T/2) -200 0.1 T/2 (T/2) +200 1.0 8.0 8.0 150 200 150 / 4 feedback / 6 feedback / 8 feedback / 10 feedback / 12 feedback / 16 feedback / 20 feedback / 24 feedback / 32 feedback / 40 feedback 11 86 13 88 16 19 21 22 27 30 1000 VCC - 0.9 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz mV V ns ns ps ps ps ps ps ps ns ns ns ps ps ps ps ps ps ps ps ps ps ps ps (VCO = 400 MHz) 0.55 to 2.4 V 0.8 to 2.0 V PLL locked LVPECL LVPECL PLL locked Condition PLL locked PLL bypass Input Reference Frequency in PLL Bypass Mode fVCO fMAX VCO Frequency Range Output Frequency 3 fSTOP_CLK VPP VCMR4 tPW,MIN tR, tF t() Serial Interface Clock Frequency Peak-to-Peak Input Voltage Common Mode Range Input Reference Pulse Width4 CCLKx Input Rise/Fall Time5 Propagation Delay (static phase offset)6 6.25 MHz < fREF < 65.0 MHz 65.0 MHz < fREF < 125 MHz fREF = 50 MHz and feedback = /8 Output-to-Output Skew7 within QA outputs within QB outputs within QC outputs all outputs tSK(O) DC tR, tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() Output Duty Cycle8 Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter9 Period Jitter10 I/O Phase Jitter RMS (1 )11 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 199 MPC9773 Table 10. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to 70C)1, 2 Symbol BW Characteristics PLL Closed Loop Bandwidth 12 Min / 4 feedback / 6 feedback / 8 feedback / 10 feedback / 12 feedback / 16 feedback / 20 feedback / 24 feedback / 32 feedback / 40 feedback Typ 1.20 - 3.50 0.70 - 2.50 0.50 - 1.80 0.45 - 1.20 0.30 - 1.00 0.25 - 0.70 0.20 - 0.55 0.17 - 0.40 0.12 - 0.30 0.11 - 0.28 Max Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Condition tLOCK Maximum PLL Lock Time 10 ms 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The input reference frequency must match the VCO lock range divided by the feedback divider ratio: fREF = fVCO / (M VCO_SEL). 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). 4. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF,MIN. 5. The MPC9773 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. 6. CCLKx or PCLK to FB_IN. Static phase offset depends on the reference frequency. t() [s] = t() [] / (fREF 360). 7. Excluding QSYNC output. Refer to application section for part-to-part skew calculation. 8. Output duty cycle is DC = (0.5 200 ps fOUT) 100%. E.g., the DC range at fOUT = 100 MHz is 48% < DC < 52%. T = output period. 9. Cycle jitter is valid for all outputs in the same divider configuration. Refer to APPLICATIONS INFORMATION for more details. 10. Period jitter is valid for all outputs in the same divider configuration. Refer to APPLICATIONS INFORMATION for more details. 11. I/O jitter is valid for a VCO frequency of 400 MHz. Refer to APPLICATIONS INFORMATION for I/O jitter vs. VCO frequency. 12. -3 dB point of PLL transfer characteristics. 200 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9773 APPLICATIONS INFORMATION MPC9773 Configurations Configuring the MPC9773 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: fOUT = fREF M / N fREF PLL /VCO_SEL /N fOUT specified frequency range. This divider is controlled by the VCO_SEL pin. VCO_SEL effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and output divider: fQA[0:3] = fVCO / (VCO_SEL NA) fQB[0:3] = fVCO / (VCO_SEL NB) fQC[0:3] = fVCO / (VCO_SEL NC) Table 11. MPC9773 Divider Divider Function PLL Feedback FSEL_FB[0:3] Bank A Output Divider FSEL_A[0:1] Bank B Output Divider FSEL_B[0:1] Bank C Output Divider FSEL_C[0:1] VCO_SEL /1 /2 /1 /2 /1 /2 /1 /2 Values 4, 6, 8, 10, 12, 16 8, 12, 16, 20, 24, 32, 40 4, 6, 8, 12 8, 12, 16, 24 4, 6, 8, 10 8, 12, 16, 20 2, 4, 6, 8 4, 8, 12, 16 M NA NB NC /M where fREF is the reference frequency of the selected input clock source (CCLKO, CCLK1 or PCLK), M is the PLL feedback divider and N is a output divider. The PLL feedback divider is configured by the FSEL_FB[2:0] and the output dividers are individually configured for each output bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0] inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 480 MHz in order to achieve stable PLL operation: fVCO,MIN (fREF VCO_SEL M) fVCO,MAX The PLL post-divider VCO_SEL is either a divide-by-one or a divide-by-two and can be used to situate the VCO into the Figure 3. Example Configuration fREF = 33.3 MHz CCLK0 CCLK1 CCLK_SEL 1 VCO_SEL FB_IN 11 00 00 101 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0] MPC9773 Table 11 shows the various PLL feedback and output dividers and Figure 3 and Figure 4 display example configurations for the MPC9773. Figure 4. Example Configuration QA[3:0] QB[3:0] QC[3:0] QFB 33.3 MHz 100 MHz 200 MHz fREF = 25 MHz CCLK0 CCLK1 CCLK_SEL 1 VCO_SEL FB_IN 00 00 00 011 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0] MPC9773 QA[3:0] QB[3:0] QC[3:0] QFB 62.5 MHz 62.5 MHz 125 MHz 33.3 MHz (Feedback) 25 MHz (Feedback) MPC9773 example configuration (feedback of QFB = 33.3 MHz, fVCO = 400 MHz, VCO_SEL = /1, M = 12, NA = 12, NB = 4, NC = 2). Frequency Range Input QA outputs QB outputs QC outputs Min 16.6 MHz 16.6 MHz 50 MHz 100 MHz Max 40 MHz 40 MHz 120 MHz 240 MHz MPC9773 example configuration (feedback of QFB = 25 MHz, fVCO = 250 MHz, VCO_SEL = /1, M = 10, NA = 4, NB = 4, NC = 2). Frequency Range Input QA outputs QB outputs QC outputs Min 20 MHz 50 MHz 50 MHz 100 MHz Max 48 MHz 120 MHz 120 MHz 240 MHz FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 201 MPC9773 MPC9773 Individual Output Disable (Clock Stop) Circuitry The individual clock stop (output enable) control of the MPC9773 allows designers, under software control, to implement power management into the clock distribution design. A simple serial interface and a clock stop control logic provides a mechanism through which the MPC9773 clock outputs can be individually stopped in the logic `0' state: The clock stop mechanism allows serial loading of a 12-bit serial input register. This register contains one programmable clock stop bit for 12 of the 14 output clocks. The QC0 and QFB outputs cannot be stopped (disabled) with the serial port. The user can program an output clock to stop (disable) by writing logic `0' to the respective stop enable bit. Likewise, the user may programmably enable an output clock by writing logic `1' to the respective enable bit. The clock stop logic enables or disables clock outputs during the time when the output would be in normally in logic low state, eliminating the possibility of short or `runt' clock pulses. The user can write to the serial input register through the STOP_DATA input by supplying a logic `0' start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC9773 can sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. (See Figure 5.) STOP_CLK STOP_DATA START QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC Figure 5. Clock Stop Circuit Programing 202 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9773 SYNC Output Description The MPC9773 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9773 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the fVCO 1:1 Mode QA QC QSYNC 2:1 Mode QA QC QSYNC 3:1 Mode QC(/2) QA(/6) QSYNC 3:2 Mode QA(/4) QC(/6) QSYNC 4:1 Mode QC(/2) QA(/8) QSYNC 4:3 Mode QA(/6) QC(/8) QSYNC 6:1 Mode QA(/12) QC(/2) QSYNC coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse is dependent QA and QC output frequencies: the QSYNC pulse width is equal to the period of the higher of the QA and QC output frequencies. Figure 6 shows various waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank C outputs. Figure 6. QSYNC Timing Diagram FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 203 MPC9773 Power Supply Filtering The MPC9773 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9773 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA_PLL pin for the MPC9773. Figure 7 illustrates a typical power supply filter scheme. The MPC9773 frequency and phase stability is most susceptible to noise with spectral content in the 100-kHz to 20-MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 8 mA (13.5 mA maximum), assuming that a minimum of 3.0 V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 7 must have a resistance of 5-10 to meet the voltage drop criteria. RF = 5-10 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9773 VCC 33...100 nF QFBDevice 1 tJIT() +tSK(O) +t() QFBDevice2 tJIT() CCLKCommon tPD,LINE(FB) Using the MPC9773 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9773. Designs using the MPC9773 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9773 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC9773 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9773 are connected together, the maximum overall timing uncertainty from the common CCLKx input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay, and I/O (phase) jitter: -t() Any QDevice 1 Figure 7. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 7, the filter cut-off frequency is around 4.5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9773 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 8. MPC9773 Maximum Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12. 204 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9773 Table 12. Confidence Factor CF CF 1 2 3 4 5 6 Probability of Clock Edge within the Distribution 0.68268948 tjit[] [ps] RMS 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 120 100 80 60 40 20 0 200 250 300 350 400 450 480 VCO frequency [MHz] FB = /12 FB = /6 FB = /24 Maximum I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. Due to the frequency dependence of the static phase offset and I/O jitter, using Figure 9 to Figure 11 to predict a maximum I/O jitter and the specified t() parameter relative to the input reference frequency results in a precise timing performance analysis. In the following example calculation an I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst-case timing uncertainty from the common input reference clock to any output of -455 ps to +455 ps relative to CCLK (PLL feedback = /8, reference frequency = 50 MHz, VCO frequency = 400 MHz, I/O jitter = 13 ps RMS max., static phase offset t() = 166 ps): tSK(PP) = [-166ps...166ps] + [-250ps...250ps] + [(13ps -3)...(13ps 3)] + tPD, LINE(FB) tSK(PP) = [-455ps...455ps] + tPD, LINE(FB) Maximum I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 160 140 120 100 80 60 40 20 0 200 Figure 10. MPC9772 I/O Jitter Maximum I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 140 120 tjit[] [ps] RMS 100 80 60 40 20 0 200 FB = /10 FB = /40 FB = /20 250 300 350 400 450 480 VCO frequency [MHz] Figure 11. MPC9772 I/O Jitter Driving Transmission Lines The MPC9773 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high-performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50- resistance to VCC / 2. FB = /32 FB = /16 FB = /8 tjit[] [ps] RMS FB =/4 250 300 350 400 VCO frequency [MHz] 450 480 Figure 9. MPC9772 I/O Jitter FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 205 MPC9773 This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9773 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 12 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9773 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9773 OUTPUT BUFFER IN 14 At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 1. Final skew data pending specification. 3.0 2.5 2.0 In 1.5 1.0 OutA tD = 3.8956 OutB tD = 3.9386 RS = 36 ZO = 50 OutA MPC9773 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 VOLTAGE (V) 0.5 0 2 4 6 8 TIME (ns) 10 12 14 RS = 36 Figure 13. Single versus Dual Waveforms Figure 12. Single versus Dual Transmission Lines The waveform plots in Figure 13 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9773 output buffer is more than sufficient to drive 50- transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9773. The output waveform in Figure 13 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36- series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+17+25) = 1.31 V Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 14 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9773 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 14. Optimized Dual Line Termination 206 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9773 MPC9773 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 15. CCLK MPC9773 AC Test Reference Differential Pulse Generator Z = 50 ZO = 50 MPC9773 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 16. PCLK MPC9773 AC Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 207 MPC9773 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device CCLKx VCC VCC / 2 GND FB_IN VCC VCC / 2 GND t() Figure 17. Output-to-Output Skew tSK(O) VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 18. Propagation Delay (t(), Static Phase Offset) Test Reference CCLKx FB_IN TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 19. Output Duty Cycle (DC) Figure 20. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 21. Cycle-to-Cycle Jitter Figure 22. Period Jitter VCC = 3.3 V 2.4 0.55 tF tR Figure 23. Output Transition Time Test Reference 208 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC97H73 Rev 1, 08/2004 3.3V 1:12 LVCMOS PLL Clock Generator The MPC97H73 is a 3.3V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * * * MPC97H73 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR 1:12 PLL based low-voltage clock generator 3.3V power supply Internal power-on reset FA SUFFIX Generates clock signals up to 240 MHz 52 LEAD LQFP PACKAGE Maximum output skew of 250 ps CASE 848D-03 Differential PECL reference clock input Two LVCMOS PLL reference clock inputs External PLL feedback supports zero-delay capability Various feedback and output dividers (see application section) Supports up to three individual generated output clock frequencies Synchronous output clock stop circuitry for each individual output for power down support Drives up to 24 clock lines Ambient temperature range 0C to +70C Pin and function compatible to the MPC973 52-lead Pb-free Package Available Functional Description The MPC97H73 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC97H73 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC97H73 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1, and 8:3. The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non--binary factor. The MPC97H73 also supports the 180 phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the MPC97H73. The MPC97H73 has an internal power-on reset. The MPC97H73 is fully 3.3V compatible and requires no external loop filter components. All inputs (except PCLK) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC97H73 outputs can drive one or two traces giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 209 MPC97H73 All input resistors have a value of 25k PCLK PCLK VCC CCLK0 CCLK1 CCLK_SEL REF_SEL FB_IN VCO_SEL PLL_EN VCC FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] VCC INV_CLK STOP_DATA STOP_CLK MR/OE 12 POWER-ON RESET 2 2 2 3 0 1 VCC FB PLL 200-480 MHz 1 0 Ref VCO /2 /1 0 1 0 1 /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 /4, /6, /8, /10 /12, /16, /20 SYNC PULSE QA0 BANK A CLK STOP QA1 QA2 QA3 QB0 BANK B CLK STOP QB1 QB2 QB3 BANK C QC0 CLK STOP 0 1 CLK STOP QC1 QC2 QC3 QFB CLK STOP QSYNC CLOCK STOP Figure 1. MPC97H73 Logic Diagram GND QB0 VCC QB1 GND QB2 VCC QB3 FB_IN GND QFB VCC FSEL_FB0 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VCC QA2 GND QA1 VCC QA0 GND VCO_SEL 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 20 46 MPC97H73 19 47 18 48 17 49 16 50 15 51 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 MR/OE STOP_CLK STOP_DATA FSEL_FB2 PLL_EN REF_SEL CCLK_SEL CCLK0 CCLK1 VCC_PLL PCLK PCLK GND FSEL_FB1 QSYNC GND QC0 VCC QC1 FSEL_C0 FSEL_C1 QC2 VCC QC3 GND INV_CLK Figure 2. MPC97H73 52-Lead Package Pinout (Top View) 210 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H73 Table 1. Pin Configuration Pin CCLK0 CCLK1 PCLK, PCLK FB_IN CCLK_SEL REF_SEL VCO_SEL PLL_EN MR/OE FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] INV_CLK STOP_CLK STOP_DATA QA[0-3] QB[0-3] QC[0-3] QFB QSYNC GND VCC_PLL VCC I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Supply Supply Supply Type LVCMOS LVCMOS LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock Alternative PLL reference clock Differential LVPECL reference clock PLL feedback signal input, connect to an QFB LVCMOS clock reference select LVCMOS/PECL reference clock select VCO operating frequency select PLL enable/PLL bypass mode select Output enable/disable (high-impedance tristate) and device reset Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs Frequency divider select for the QFB output Clock phase selection for outputs QC2 and QC3 Clock input for clock stop circuitry Configuration data input for clock stop circuitry Clock outputs (Bank A) Clock outputs (Bank B) Clock outputs (Bank C) PLL feedback output. Connect to FB_IN. Synchronization pulse output Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function Table 2. Function Table (Configuration Controls) Control REF_SEL CCLK_SEL VCO_SEL PLL_EN Default 1 1 1 1 0 Selects CCLKx as the PLL reference clock Selects CCLK0 Selects VCO/2. The VCO frequency is scaled by a factor of 2 (low VCO frequency range). 1 Selects the LVPECL inputs as the PLL reference clock Selects CCLK1 Selects VCO/1. (high VCO frequency range) Test mode with the PLL bypassed. The reference clock is substituted for the Normal operation mode with PLL enabled. internal VCO output. MPC97H73 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. QC2 and QC3 are in phase with QC0 and QC1 QC2 and QC3 are inverted (180 phase shift) with respect to QC0 and QC1 INV_CLK MR/OE 1 1 Outputs disabled (high-impedance state) and device is reset. During reset/ Outputs enabled (active) output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC97H73 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power-on reset (POR) circuitry during power-up. VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency ratios. See Table 3 to Table 6 and the APPLICATIONS INFORMATION for supported frequency ranges and output to input frequency ratios. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 211 MPC97H73 Table 3. Output Divider Bank A (NA) VCO_SEL 0 0 0 0 1 1 1 1 FSEL_A1 0 0 1 1 0 0 1 1 FSEL_A0 0 1 0 1 0 1 0 1 QA[0:3] VCO/8 VCO/12 VCO/16 VCO/24 VCO/4 VCO/6 VCO/8 VCO/12 Table 4. Output Divider Bank B (NB) VCO_SEL 0 0 0 0 1 1 1 1 FSEL_B1 0 0 1 1 0 0 1 1 FSEL_B0 0 1 0 1 0 1 0 1 QB[0:3] VCO/8 VCO/12 VCO/16 VCO/20 VCO/4 VCO/6 VCO/8 VCO/10 Table 5. Output Divider Bank C (NC) VCO_SEL 0 0 0 0 1 1 1 1 FSEL_C1 0 0 1 1 0 0 1 1 FSEL_C0 0 1 0 1 0 1 0 1 QC[0:3] VCO/4 VCO/8 VCO/12 VCO/16 VCO/2 VCO/4 VCO/6 VCO/8 Table 6. Output Divider PLL Feedback (M) VCO_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSEL_FB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QFB VCO/8 VCO/12 VCO/16 VCO/20 VCO/16 VCO/24 VCO/32 VCO/40 VCO/4 VCO/6 VCO/8 VCO/10 VCO/8 VCO/12 VCO/16 VCO/20 212 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H73 Table 7. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 12 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 8. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 9. DC Characteristics (VCC = 3.3V 5%, TA = 0 to 70C) Symbol VCC_PLL VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICC_PLL ICCQ Characteristics PLL Supply Voltage Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage Output Impedance Input Current 3 Min 3.0 2.0 Typ Max VCC VCC + 0.3 0.8 Unit V V V mV Condition LVCMOS LVCMOS LVCMOS LVPECL LVPECL IOH=-24 mA2 IOL= 24 mA IOL= 12 mA PCLK, PCLK PCLK, PCLK 250 1.0 2.4 0.55 0.30 8 - 11 200 8.0 13.5 35 VCC - 0.6 V V V V A mA mA VIN = VCC or GND VCC_PLL Pin All VCC Pins Maximum PLL Supply Current Maximum Quiescent Supply Current 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC97H73 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 3. Inputs have pull-down resistors affecting the input current. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 213 MPC97H73 Table 10. AC Characteristics (VCC = 3.3V 5%, TA = 0 to +70C)1 2 Symbol fREF Characteristics Input Reference Frequency /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback Min 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00 Typ Max 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 15.0 12.0 250 200 /2 output /4 output /6 output /8 output /10 output /12 output /16 output /20 output /24 output 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 480 240.0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 20 PCLK, PCLK PCLK, PCLK 400 1.2 2.0 1.0 -3 -4 -166 +3 +4 +166 100 100 100 250 (T/2) - 200 0.1 T/2 (T/2) +200 1.0 8.0 8.0 150 200 150 1000 VCC-0.9 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz mV V ns ns 0.8 to 2.0V PLL locked LVPECL LVPECL PLL locked Condition PLL locked Input Reference Frequency in PLL Bypass Mode fVCO fMAX VCO Frequency Range3 Output Frequency PLL bypass fSTOP_CLK Serial Interface Clock Frequency VPP VCMR tPW,MIN tR, tF t() Peak-to-Peak Input Voltage Common Mode Range Input Reference Pulse Width4 CCLKx Input Rise/Fall Time5 Propagation Delay (static phase offset)6 6.25 MHz < fREF < 65.0 MHz 65.0 MHz < fREF < 125 MHz fREF=50 MHz and feedback=/8 Output-to-Output Skew7 within QA outputs within QB outputs within QC outputs all outputs ps ps ps ps ps ps ns ns ns ps ps 0.55 to 2.4V tSK(O) DC tR, tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) Output Duty Cycle8 Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle jitter9 Period Jitter10 214 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H73 Table 10. AC Characteristics (VCC = 3.3V 5%, TA = 0 to +70C)1 2 (Continued) Symbol tJIT() Characteristics I/O Phase Jitter RMS (1 )11 /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback 1.20 - 3.50 0.70 - 2.50 0.50 - 1.80 0.45 - 1.20 0.30 - 1.00 0.25 - 0.70 0.20 - 0.55 0.17 - 0.40 0.12 - 0.30 0.11 - 0.28 10 Min Typ Max 11 86 13 88 16 19 21 22 27 30 Unit ps ps ps ps ps ps ps ps ps ps MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ms Condition (VCO=400 MHz) BW PLL Closed Loop Bandwidth12 tLOCK Maximum PLL Lock Time 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The input reference frequency must match the VCO lock range divided by the feedback divider ratio: fREF= fVCO / (M VCO_SEL). 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). 4. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF, MIN. 5. The MPC97H73 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. 6. CCLKx or PCLK to FB_IN. Static phase offset depends on the reference frequency. t() [s] = t() [] / (fREF 360). 7. Excluding QSYNC output. See application section for part-to-part skew calculation. 8. Output duty cycle is DC = (0.5 200 ps fOUT) 100%. E.g. the DC range at fOUT=100MHz is 48% 215 MPC97H73 APPLICATIONS INFORMATION MPC97H73 Configurations Configuring the MPC97H73 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: fOUT = fREF M / N fREF PLL /VCO_SEL /N fOUT frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and output divider: fQA[0:3] = fVCO / (VCO_SEL NA) fQB[0:3] = fVCO / (VCO_SEL NB) fQC[0:3] = fVCO / (VCO_SEL NC) Table 11. MPC97H73 Divider /M Divider M Function PLL feedback FSEL_FB[0:3] Bank A Output Divider FSEL_A[0:1] Bank B Output Divider FSEL_B[0:1] Bank C Output Divider FSEL_C[0:1] VCO_SEL /1 /2 /1 /2 /1 /2 /1 /2 Values 4, 6, 8, 10, 12, 16 8, 12, 16, 20, 24, 32, 40 4, 6, 8, 12 8, 12, 16, 24 4, 6, 8, 10 8, 12, 16, 20 2, 4, 6, 8 4, 8, 12, 16 where fREF is the reference frequency of the selected input clock source (CCLKO, CCLK1 or PCLK), M is the PLL feedback divider and N is a output divider. The PLL feedback divider is configured by the FSEL_FB[2:0] and the output dividers are individually configured for each output bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0] inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 480 MHz in order to achieve stable PLL operation: fVCO,MIN (fREF VCO_SEL M) fVCO,MAX The PLL post-divider VCO_SEL is either a divide-by-one or a divide-by-two and can be used to situate the VCO into the specified frequency range. This divider is controlled by the VCO_SEL pin. VCO_SEL effectively extends the usable input fref = 33.3 MHz CCLK0 CCLK1 CCLK_SEL 1 VCO_SEL FB_IN 11 00 00 101 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0] QA[3:0] QB[3:0] QC[3:0] QFB 33.3 MHz 100 MHz 200 MHz NA NB NC Table 11 shows the various PLL feedback and output dividers and Figure 3. Example Configuration and Figure 4. Example Configuration display example configurations for the MPC97H73: fref = 25 MHz CCLK0 CCLK1 CCLK_SEL 1 VCO_SEL FB_IN 00 00 00 011 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0] QA[3:0] QB[3:0] QC[3:0] QFB 62.5 MHz 62.5 MHz 125 MHz MPC97H73 33.3 MHz (Feedback) MPC97H73 25 MHz (Feedback) MPC97H73 example configuration (feedback of QFB = 33.3 MHz, fVCO=400 MHz, VCO_SEL=/1, M=12, NA=12, NB=4, NC=2). Frequency Range Input QA Outputs QA Outputs QC Outputs Min 16.6 MHz 16.6 MHz 50 MHz 100 MHz Max 40 MHz 40 MHz 120 MHz 240 MHz MPC97H73 example configuration (feedback of QFB = 25 MHz, fVCO=250 MHz, VCO_SEL=/1, M=10, NA=4, NB=4, NC=2). Frequency Range Input QA Outputs QA Outputs QC Outputs Min 20 MHz 50 MHz 50 MHz 100 MHz Max 48 MHz 120 MHz 120 MHz 240 MHz Figure 3. Example Configuration Figure 4. Example Configuration 216 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H73 MPC97H73 Individual Output Disable (Clock Stop) Circuitry The individual clock stop (output enable) control of the MPC97H73 allows designers, under software control, to implement power management into the clock distribution design. A simple serial interface and a clock stop control logic provides a mechanism through which the MPC97H73 clock outputs can be individually stopped in the logic `0' state: The clock stop mechanism allows serial loading of a 12-bit serial input register. This register contains one programmable clock stop bit for 12 of the 14 output clocks. The QC0 and QFB outputs cannot be stopped (disabled) with the serial port. The user can program an output clock to stop (disable) by writing logic `0' to the respective stop enable bit. Likewise, the user may programmably enable an output clock by writing logic `1' to the respective enable bit. The clock stop logic enables or disables clock outputs during the time when the output would be in normally in logic low state, eliminating the possibility of short or `runt' clock pulses. The user can write to the serial input register through the STOP_DATA input by supplying a logic `0' start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC97H73 can sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. (See Figure 5. Clock Stop Circuit Programming.) STOP_CLK STOP_DATA START QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC Figure 5. Clock Stop Circuit Programming FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 217 MPC97H73 SYNC Output Description The MPC97H73 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC97H73 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the fVCO 1:1 Mode QA QC QSYNC 2:1 Mode QA QC QSYNC 3:1 Mode QC(/2) QA(/6) QSYNC 3:2 Mode QA(/4) QC(/6) QSYNC 4:1 Mode QC(/2) QA(/8) QSYNC 4:3 Mode QA(/6) QC(/8) QSYNC 6:1 Mode QA(/12) QC(/2) QSYNC coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse is dependent QA and QC output frequencies: the QSYNC pulse width is equal to the period of the higher of the QA and QC output frequencies. Figure 6. QSYNC Timing Diagram shows various waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank C outputs. Figure 6. QSYNC Timing Diagram 218 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H73 Power Supply Filtering The MPC97H73 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC97H73 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA_PLL pin for the MPC97H73. Figure 7. VCC_PLL Power Supply Filter illustrates a typical power supply filter scheme. The MPC97H73 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 3.0V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 7. VCC_PLL Power Supply Filter must have a resistance of 5-10 to meet the voltage drop criteria. RF = 5-10 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC97H73 VCC 33...100 nF QFBDevice 1 tJIT() +tSK(O) +t() QFBDevice2 tJIT() CCLKCommon -t() tPD,LINE(FB) adequate to eliminate power supply noise related problems in most designs. Using the MPC97H73 in Zero-Delay Applications Nested clock trees are typical applications for the MPC97H73. Designs using the MPC97H73 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC97H73 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC97H73 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC97H73 are connected together, the maximum overall timing uncertainty from the common CCLKx input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Figure 7. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 7. VCC_PLL Power Supply Filter, the filter cut-off frequency is around 4.5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC97H73 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be Any QDevice 1 Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 8. MPC97H73 Maximum Device-to-Device Skew FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 219 MPC97H73 Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12. Table 12. Confidence Factor CF tjit() [ps] RMS CF 1 2 3 4 5 6 Probability of Clock Edge within the Distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 120 100 80 60 40 20 0 200 FB=/12 FB=/6 FB=/24 250 300 350 400 VCO Frequency [MHz] 450 480 Figure 10. MPC97H73 I/O Jitter Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 140 120 tjit() [ps] RMS 100 80 60 40 20 0 200 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. Due to the frequency dependence of the static phase offset and I/O jitter, using Figure 9. MPC97H73 I/O Jitter to Figure 11. MPC97H73 I/O Jitter to predict a maximum I/O jitter and the specified t() parameter relative to the input reference frequency results in a precise timing performance analysis. In the following example calculation an I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from the common input reference clock to any output of -455 ps to +455 ps relative to CCLK (PLL feedback = /8, reference frequency = 50 MHz, VCO frequency = 400 MHz, I/O jitter = 13 ps rms max., static phase offset t() = 166 ps): tSK(PP) = tSK(PP) = [-166ps...166ps] + [-250ps...250ps] + [(13ps @ -3)...(13ps @ 3)] + tPD, LINE(FB) [-455ps...455ps] + tPD, LINE(FB) FB=/10 FB=/40 FB=/20 250 300 350 400 VCO Frequency [MHz] 450 480 Figure 11. MPC97H73 I/O Jitter Driving Transmission Lines The MPC97H73 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC97H73 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 12. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC97H73 clock driver is effectively doubled due to its capability to drive multiple lines. Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 160 140 FB=/32 120 100 FB=/16 80 FB=/8 60 40 20 FB=/4 0 200 250 300 350 400 VCO Frequency [MHz] tjit() [ps] RMS 450 480 Figure 9. MPC97H73 I/O Jitter 220 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H73 MPC97H73 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA 2.5 2.0 In RS = 36 VOLTAGE (V) ZO = 50 OutB0 ZO = 50 OutB1 0.5 1.5 1.0 1. Final skew data pending specification 3.0 OutA tD = 3.8956 OutB tD = 3.9386 MPC97H73 OUTPUT BUFFER IN 14 RS = 36 Figure 12. Single versus Dual Transmission Lines The waveform plots in Figure 13. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC97H73 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC97H73. The output waveform in Figure 13. Single versus Dual Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+17+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 0 2 4 6 8 TIME (ns) 10 12 14 Figure 13. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 14. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC97H73 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 14. Optimized Dual Line Termination FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 221 MPC97H73 MPC97H73 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 15. CCLK MPC97H73 AC Test Reference Differential Pulse Generator Z = 50 ZO = 50 MPC97H73 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 16. PCLK MPC97H73 AC Test Reference 222 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H73 VCC VCC/2 GND VCC VCC/2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t() CCLKx VCC VCC/2 GND FB_IN VCC VCC/2 GND Figure 16. Output-to-Output Skew tSK(O) VCC VCC/2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 17. Propagation Delay (t(), Static Phase Offset) Test Reference CCLKx FB_IN TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 18. Output Duty Cycle (DC) Figure 19. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 20. Cycle-to-Cycle Jitter Figure 21. Period Jitter VCC=3.3V 2.4 0.55 tF tR Figure 22. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 223 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9774 Rev 3, 08/2004 3.3 V 1:14 LVCMOS PLL Clock Generator The MPC9774 is a 3.3V compatible, 1:14 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 125 MHz and output skews less than 175 ps the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * 1:14 PLL based low-voltage clock generator 3.3 V power supply Internal power-on reset Generates clock signals up to 125 MHz Maximum output skew of 175 ps Two LVCMOS PLL reference clock inputs External PLL feedback supports zero-delay capability Various feedback and output dividers (see APPLICATIONS INFORMATION) Supports up to three individual generated output clock frequencies Drives up to 28 clock lines Ambient temperature range 0C to +70C Pin and function compatible to the MPC974 52-lead Pb-free Package Available MPC9774 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR FA SUFFIX 52-LEAD LQFP PACKAGE CASE 848D-03 Functional Description The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate configurable feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL pin provides an extended PLL input reference frequency range. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The MPC9774 has an internal power-on reset. The MPC9774 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package. 224 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9774 All input resistors have a value of 25 k VCC CCLK0 CCLK1 CCLK_SEL 0 1 0 Ref PLL 200-500 MHz VCC VCO 1 /2 /4 QA0 BANK A QA1 QA2 QA3 QA4 BANK B QB0 QB1 0 1 / 2, / 4 / 2, / 4 / 4, / 6 / 4, / 6, / 8, / 12 CLK STOP FB_IN PLL_EN VCO_SEL FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] FB CLK STOP QB2 QB3 QB4 2 BANK C CLK STOP QC0 QC1 QC2 QC3 VCC CLK_STOP VCC MR/OE POWER-ON RESET QFB Figure 1. MPC9774 Logic Diagram GND QB1 VCC QB2 GND QB3 VCC QB4 FB_IN GND QFB VCC NC QB0 VCC NC GND QC3 VCC QC2 GND QC1 VCC QC0 GND VCO_SEL 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 MPC9774 20 46 19 47 18 48 17 49 16 50 15 51 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 GND MR/OE CLK_STOP FSEL_B FSEL_C PLL_EN FSEL_A CCLK_SEL CCLK0 CCLK1 NC VCC VCC_PLL VCC QA0 GND QA1 VCC QA2 FSEL_FB1 GND QA3 VCC QA4 GND FSEL_FB0 Figure 2. MPC9774 52-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 225 MPC9774 Table 1. Pin Configuration Pin CCLK0 CCLK1 FB_IN CCLK_SEL VCO_SEL PLL_EN MR/OE CLK_STOP FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] QA[4:0] QB[4:0] QC[3:0] QFB GND VCC_PLL VCC I/O Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Supply Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock Alternative PLL reference clock PLL feedback signal input, connect to QFB LVCMOS clock reference select VCO operating frequency select PLL enable/PLL bypass mode select Output enable/disable (high-impedance tristate) and device reset Output enable/clock stop (logic low state) Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs Frequency divider select for the QFB output Clock outputs (Bank A) Clock outputs (Bank B) Clock outputs (Bank C) PLL feedback output. Connect to FB_IN. Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function Table 2. Function Table (Configuration Controls) Control CCLK_SEL VCO_SEL Default 0 0 0 Selects CCLK0 as PLL references signal input Selects VCO / 2. The VCO frequency is scaled by a factor of 2 (high input frequency range) 1 Selects CCKL1 as PLL reference signal input Selects VCO / 4. The VCO frequency is scaled by a factor of 4 (low input frequency range). PLL_EN 1 Test mode with the PLL bypassed. The reference clock is substituted for the Normal operation mode with PLL enabled. internal VCO output. MPC9774 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Outputs enabled (active) QA, QB an QC outputs disabled in logic low state. QFB is not affected by CLK_STOP. CLK_STOP deassertion may cause the initial output clock pulse to be distorted. Outputs enabled (active) Outputs disabled (high-impedance state) and reset of the device. During reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9774 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power-on reset (POR) circuitry during power-up. CLK_STOP 1 MR/OE 1 VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios. See Table 3 and Table 4 for the device frequency configuration. Table 3. Function Table (Output Dividers Bank A, B, and C) VCO_SEL 0 0 1 1 FSEL_A 0 1 0 1 QA[4:0] VCO / 4 VCO / 8 VCO / 8 VCO / 16 VCO_SEL 0 0 1 1 FSEL_B 0 1 0 1 QB[4:0] VCO / 4 VCO / 8 VCO / 8 VCO / 16 VCO_SEL 0 0 1 1 FSEL_C 0 1 0 1 QC[3:0] VCO / 8 VCO / 12 VCO / 16 VCO / 24 226 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9774 Table 4. Function Table (QFB) VCO_SEL 0 0 0 0 1 1 1 1 FSEL_B1 0 0 1 1 0 0 1 1 FSEL_B0 0 1 0 1 0 1 0 1 QFB VCO / 8 VCO / 16 VCO / 12 VCO / 24 VCO / 16 VCO / 32 VCO / 24 VCO / 48 Table 5. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD protection (Machine Model) ESD protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 12 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 6. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 7. DC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C) Symbol VCC_PLL VIH VIL VOH VOL ZOUT IIN ICC_PLL ICCQ Characteristics PLL Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current2 5.0 14 - 17 200 7.5 8.0 2.4 0.55 0.30 Min 3.02 2.0 Typ Max VCC VCC + 0.3 0.8 Unit V V V V V V A mA mA VIN = VCC or GND VCC_PLL Pin All VCC Pins Condition LVCMOS LVCMOS LVCMOS IOH = -24 mA1 IOL = 24 mA IOL = 12 mA Maximum PLL Supply Current Maximum Quiescent Supply Current 1. The MPC9774 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. Inputs have pull-down or pull-up resistors affecting the input current. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 227 MPC9774 Table 8. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C)1 Symbol fREF Characteristics Input Reference Frequency / 8 feedback / 12 feedback / 16 feedback / 24 feedback / 32 feedback / 48 feedback Min 25.0 16.6 12.5 8.33 6.25 4.16 Typ Max 62.5 41.6 31.25 20.83 15.625 10.41 250 200 / 4 output / 8 output / 12 output / 16 output / 24 output 50.0 25.0 16.6 12.5 8.33 2.0 1.0 offset)5 -250 +100 100 125 100 175 47 0.1 50 53 1.0 10 10 7 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns ns ps ps ps ps ps % ns ns ns ps ps ps ps ps ps ps ps MHz MHz MHZ MHz MHz MHz Condition PLL locked PLL bypass Input Reference Frequency in PLL Bypass Mode2 fVCO fMAX VCO Frequency Range3 Output Frequency 500 125.0 62.5 41.6 31.25 20.83 PLL locked tPW,MIN tR, tF t() tSK(O) Input Reference Pulse Width4 CCLKx Input Rise/Fall Time Propagation Delay (static phase CCLKx to FB_IN (FB = / 8 and fREF = 50 MHz) Output-to-Output Skew6 within QA bank within QB bank within QC bank any output 0.8 to 2.0V PLL locked DC tR, tF tPLZ, HZ tPZL tJIT(CC) tJIT(PER) tJIT() Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle Jitter Period Jitter6 I/O Phase Jitter RMS (1 )8 FB = / 8 FB = / 12 FB = / 16 FB = / 24 FB = / 32 FB = / 48 FB = / 8 FB = / 12 FB = / 16 FB = / 24 FB = / 32 FB = / 48 0.55 to 2.4V 90 90 15 49 18 22 26 34 0.50 - 1.80 0.30 - 1.00 0.25 - 0.70 0.17 - 0.40 0.12 - 0.30 0.07 - 0.20 10 BW PLL Closed Loop Bandwidth9 tLOCK 1. 2. 3. 4. 5. 6. 7. 8. 9. Maximum PLL Lock Time ms AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9774 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio (FB): fREF = fVCO / (M VCO_SEL). Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF,MIN. E.g. at fREF = 62.5 MHz the input duty cycle range is 12.5% < DC < 87.5%. Static phase offset depends on the reference frequency: t() = +50 ps (1/(120 fREF)) for any reference frequency. Refer to Application section for part-to-part skew calculation. Valid for all outputs at the same frequency. I/O jitter for fVCO = 400 MHz. Refer to APPLICATIONS INFORMATION for I/O jitter at other frequencies and for a jitter calculation for confidence factors other than 1 . -3 dB point of PLL transfer characteristics. 228 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9774 APPLICATIONS INFORMATION MPC9774 Configurations Configuring the MPC9774 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: fOUT = fREF M / N fREF PLL / VCO_SEL /N fOUT VCO_SEL pin. VCO_SEL effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and output divider: fQA[4:0] = fVCO / (VCO_SEL NA) fQB[4:0] = fVCO / (VCO_SEL NB) fQC[3:0] = fVCO / (VCO_SEL NC) Table 9. MPC9774 Divider /M Divider M NA NB NC Function PLL Feedback FSEL_FB[0:1] Bank A Output Divider FSEL_A Bank B Output Divider FSEL_B Bank C Output Divider FSEL_C VCO_SEL /2 /4 /2 /4 /2 /4 /2 /4 Values 8, 12, 16, 24 16, 24, 32, 48 4, 8 8, 16 4, 8 8, 16 8, 12 16, 24 where fREF is the reference frequency of the selected input clock source (CCLK0 or CCLK1), M is the PLL feedback divider and N is a output divider. M is configured by the FSEL_FB[0:1] and N is individually configured for each output bank by the FSEL_A, FSEL_B and FSEL_C inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 500 MHz in order to achieve stable PLL operation: fVCO,MIN (fREF VCO_SEL M) fVCO,MAX The PLL post-divider VCO_SEL is either a divide-by-two or a divide-by-four and can be used to situate the VCO into the specified frequency range. This divider is controlled by the Figure 3. Example Configuration fREF = 20.83 MHz CCLK0 CCLK1 0 CCLK_SEL 0 VCO_SEL FB_IN 0 1 0 11 FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] QA[4:0] QB[4:0] QC[3:0] QFB 125 MHz 62.5 MHz 62.5 MHz Table 9 shows the various PLL feedback and output dividers. The output dividers for the three output banks allow the user to configure the outputs into 1:1, 2:1, 3:2, and 3:2:1 frequency ratios. Figure 3 and Figure 4 display example configurations for the MPC9774. Figure 4. Example Configuration fREF = 25 MHz CCLK0 CCLK1 0 CCLK_SEL 0 VCO_SEL FB_IN 0 1 1 01 FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] QA[4:0] QB[4:0] QC[3:0] QFB 100 MHz 50 MHz 33.3 MHz MPC9774 MPC9774 20.83 MHz (Feedback) 25 MHz (Feedback) MPC9774 example configuration (feedback of QFB = 20.83 MHz, VCO_SEL = / 2, M = 12, NA = 2, NB = 4, NC = 4, fVCO = 500 MHz). Frequency Range Input QA outputs QB outputs QC outputs Min 8.33 MHz 50 MHz 25 MHz 25 MHz Max 20.83 MHz 125 MHz 62.5 MHz 62.5 MHz MPC9774 example configuration (feedback of QFB = 25 MHz, VCO_SEL = / 2, M = 8, NA = 2, NB = 4, NC = 6, fVCO = 400 MHz). Frequency Range Input QA outputs QB outputs QC outputs Min 20 MHz 50 MHz 50 MHz 100 MHz Max 48 MHz 120 MHz 120 MHz 200 MHz FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 229 MPC9774 Using the MPC9774 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9774. Designs using the MPC9774 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback of the MPC9774 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC9774 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9774 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Table 10. Confidence Factor CF CF 1 2 3 4 5 6 Probability of Clock Edge within the Distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 Due to the frequency dependence of the static phase offset and I/O jitter, using Figure 6 and Figure 7 to predict a maximum I/O jitter and the specified t() parameter relative to the input reference frequency results in a precise timing performance analysis. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from the common input reference clock to any output of -470 ps to +320 ps relative to CCLK (PLL feedback = / 8, reference frequency = 50 MHz, VCO frequency = 400 MHz, I/O jitter = 15 ps RMS max., static phase offset t() = -250 ps to +100 ps): tSK(PP) = [-250 ps...+100 ps] + [-175 ps...175 ps] + [(15 ps * -3)...(15 ps * 3)] + tPD, LINE(FB) tSK(PP) = [-470 ps...+320 ps] + tPD, LINE(FB) Maximum I/O Phase Jitter (RMS) versus Frequency Parameter: PLL Feedback Divider FB 100 tjit[] [ps] RMS CCLKCommon -t() tPD,LINE(FB) 80 60 40 20 FB = / 8 FB = / 32 FB = / 16 QFBDevice 1 tJIT() tSK(O) +t() Any QDevice 1 0 200 250 300 350 400 450 500 VCO Frequency [MHz] QFBDevice2 Figure 6. MPC9774 I/O Jitter tJIT() Maximum I/O Phase Jitter (RMS) versus Frequency Parameter: PLL Feedback Divider FB 160 140 FB = / 12 120 100 80 FB = / 48 60 40 FB = / 24 20 0 200 250 300 350 400 VCO Frequency [MHz] Any QDevice 2 Max. skew tSK(O) tjit[] [ps] RMS tSK(PP) Figure 5. MPC9774 Maximum Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 10. The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. 450 500 Figure 7. MPC9774 I/O Jitter 230 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9774 Driving Transmission Lines The MPC9774 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC / 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9774 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 8 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9774 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9774 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18 + 17 + 25) = 1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 VOLTAGE (V) MPC9774 OUTPUT BUFFER IN 14 Figure 9. Single versus Dual Waveforms RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 10 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9774 OUTPUT BUFFER 14 RS = 22 ZO = 50 Figure 8. Single versus Dual Transmission Lines The waveform plots in Figure 9 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9774 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9774. The output waveform in Figure 9 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match ZO = 50 RS = 22 14 + 22 || 22 = 50 || 50 25 = 25 Figure 10. Optimized Dual Line Termination FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 231 MPC9774 Power Supply Filtering The MPC9774 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9774 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9774. Figure 11 illustrates a typical power supply filter scheme. The MPC9774 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 5 mA (7.5 mA maximum), assuming that a minimum of 3.02 V (VCC_PLL, min) must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 11 must have a resistance of 5-15 to meet the voltage drop criteria. The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example, RC filter shown in Figure 11, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. RF = 5-15 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9774 VCC 33...100 nF Figure 11. VCC_PLL Power Supply Filter As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9774 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. MPC9774 DUT Pulse Generator Z = 50 Z = 50 Z = 50 RT = 50 VTT RT = 50 VTT Figure 12. CCLK MPC9774 AC Test Reference 232 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9774 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device CCLKx VCC VCC / 2 GND FB_IN VCC VCC / 2 GND t() Figure 13. Output-to-Output Skew tSK(O) VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 14. Propagation Delay (t(), Static Phase Offset) Test Reference CCLKx FB_IN TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 15. Output Duty Cycle (DC) Figure 16. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 17. Cycle-to-Cycle Jitter Figure 18. Period Jitter VCC = 3.3 V 2.4 0.55 tF tR Figure 19. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 233 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC97H74 Rev 3, 08/2004 3.3 V 1:14 LVCMOS PLL Clock Generator The MPC97H74 is a 3.3 V compatible, 1:14 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 125 MHz and output skews less than 175 ps the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * 1:14 PLL based low-voltage clock generator 3.3 V power supply Internal power-on reset Generates clock signals up to 125 MHz Maximum output skew of 175 ps Two LVCMOS PLL reference clock inputs External PLL feedback supports zero-delay capability Various feedback and output dividers (see application section) Supports up to three individual generated output clock frequencies Drives up to 28 clock lines Ambient temperature range 0C to +70C Pin and function compatible to the MPC974 52-lead Pb-free Package Available MPC97H74 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR FA SUFFIX 52-LEAD LQFP PACKAGE CASE 848D-03 Functional Description The MPC97H74 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC97H74 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC97H74 features frequency programmability between the three output bank outputs as well as the output to input relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2, and 3:2:1 can be realized. Additionally, the device supports a separate configurable feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL pin provides an extended PLL input reference frequency range. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The MPC97H74 has an internal power-on reset. The MPC97H74 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC97H74 outputs can drive one or two traces giving the devices an effective fanout of 1:28. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package. 234 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H74 All input resistors have a value of 25 k VCC CCLK0 CCLK1 CCLK_SEL 0 1 Ref VCO PLL 200-500 MHz VCC 0 1 /2 /4 0 1 / 2, / 4 / 2, / 4 / 4, / 6 / 4, / 6, / 8, / 12 Bank A QA0 QA1 CLK STOP QA2 QA3 QA4 Bank B QB0 QB1 FB_IN PLL_EN VCO_SEL FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] FB CLK STOP QB2 QB3 QB4 2 Bank C CLK STOP QC0 QC1 QC2 QC3 VCC CLK_STOP VCC MR/OE POWER-ON RESET QFB Figure 1. MPC97H74 Logic Diagram FB_IN GND GND GND QFB QB1 QB2 QB3 QB4 VCC VCC VCC QB0 VCC NC GND QC3 VCC QC2 GND QC1 VCC QC0 GND VCO_SEL 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 41 42 43 44 45 46 47 48 49 50 51 52 1 2 MR/OE 3 CLK_STOP 4 FSEL_B 5 FSEL_C 6 PLL_EN 7 FSEL_A 8 CCLK_SEL 9 10 11 12 13 CCLK0 CCLK1 NC VCC 25 24 23 22 21 NC VCC QA0 GND QA1 VCC QA2 FSEL_FB1 GND QA3 VCC QA4 GND FSEL_FB0 MPC97H74 20 19 18 17 16 15 14 Figure 2. MPC97H74 52-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA VCC_PLL GND 235 MPC97H74 Table 1. Pin Configuration Pin CCLK0 CCLK1 FB_IN CCLK_SEL VCO_SEL PLL_EN MR/OE CLK_STOP FSEL_A FSEL_B FSEL_C QA[4:0] QB[4:0] QC[3:0] QFB GND VCC_PLL VCC I/O Input Input Input Input Input Input Input Input Input Input Input Type LVCMOS PLL reference clock LVCMOS Alternative PLL reference clock LVCMOS PLL feedback signal input, connect to QFB LVCMOS LVCMOS clock reference select LVCMOS VCO operating frequency select LVCMOS PLL enable/PLL bypass mode select LVCMOS Output enable/disable (high-impedance tristate) and device reset LVCMOS Output enable/clock stop (logic low state) LVCMOS Frequency divider select for bank A outputs LVCMOS Frequency divider select for bank B outputs LVCMOS Frequency divider select for bank C outputs LVCMOS Frequency divider select for the QFB output Function FSEL_FB[1:0] Input Output LVCMOS Clock outputs (bank A) Output LVCMOS Clock outputs (bank B) Output LVCMOS Clock outputs (bank C) Output LVCMOS PLL feedback output. Connect to FB_IN. Supply Ground Supply VCC Supply VCC Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 2. Function Table (MPC97H74 Configuration Controls) Control CCLK_SEL VCO_SEL PLL_EN Default 0 0 1 0 Selects CCLK0 as PLL reference signal input Selects VCO / 2. The VCO frequency is scaled by a factor of 2 (high input frequency range) Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC97H74 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. QA, QB an QC outputs disabled in logic low state. QFB is not affected by CLK_STOP. CLK_STOP deassertion may cause the initial output clock pulse to be distorted. 1 Selects CCKL1 as PLL reference signal input Selects VCO / 4. The VCO frequency is scaled by a factor of 4 (low input frequency range). Normal operation mode with PLL enabled. CLK_STOP 1 Outputs enabled (active) MR/OE 1 Outputs disabled (high-impedance state) and reset of the device. Outputs enabled (active) During reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC97H74 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power-on reset (POR) circuitry during power-up. VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios. Refer to Table 3 and Table 4 for the device frequency configuration. Table 3. Function Table (Output Dividers Bank A, B, and C) VCO_SEL 0 0 1 1 FSEL_A 0 1 0 1 QA[4:0] VCO / 4 VCO / 8 VCO / 8 VCO / 16 VCO_SEL 0 0 1 1 FSEL_B 0 1 0 1 QB[4:0] VCO / 4 VCO / 8 VCO / 8 VCO / 16 VCO_SEL 0 0 1 1 FSEL_C 0 1 0 1 QC[3:0] VCO / 8 VCO / 12 VCO / 16 VCO / 24 236 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H74 Table 4. Function Table (QFB) VCO_SEL 0 0 0 0 1 1 1 1 FSEL_B1 0 0 1 1 0 0 1 1 FSEL_B0 0 1 0 1 0 1 0 1 QFB VCO / 8 VCO / 16 VCO / 12 VCO / 24 VCO / 16 VCO / 32 VCO / 24 VCO / 48 Table 5. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD protection (Machine Model) ESD protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 12 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 6. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 7. DC Characteristics (VCC = 3.3V 5%, TA = 0C to +70C) Symbol VCC_PLL VIH VIL VOH VOL ZOUT IIN ICC_PLL ICCQ Characteristics PLL Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current2 Maximum PLL Supply Current Maximum Quiescent Supply Current 5.0 8 - 11 200 7.5 8.0 2.4 0.55 0.30 Min 3.02 2.0 Typ Max VCC VCC + 0.3 0.8 Unit V V V V V V A mA mA VIN = VCC or GND VCC_PLL Pin All VCC Pins Condition LVCMOS LVCMOS LVCMOS IOH = -24 mA1 IOL = 24 mA IOL = 12 mA 1. The MPC97H74 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. Inputs have pull-down or pull-up resistors affecting the input current. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 237 MPC97H74 Table 8. AC CHARACTERISTICS (VCC = 3.3 V 5%, TA = 0C to +70C)1 Symbol fREF Characteristics Input Reference Frequency / 8 feedback / 12 feedback / 16 feedback / 24 feedback / 32 feedback / 48 feedback Min 25.0 16.6 12.5 8.33 6.25 4.16 Typ Max 62.5 41.6 31.25 20.83 15.625 10.41 250 200 / 4 output / 8 output / 12 output / 16 output / 24 output 50.0 25.0 16.6 12.5 8.33 2.0 1.0 -250 +100 100 125 100 175 47 0.1 50 53 1.0 10 10 90 90 8 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns ns ps ps ps ps ps % ns ns ns ps ps ps ps ps ps ps ps MHz MHz MHZ MHz MHz MHz Condition PLL locked Input Reference Frequency in PLL Bypass Mode2 fVCO fMAX VCO Frequency Range Output Frequency 3 PLL bypass 500 125.0 62.5 41.6 31.25 20.83 PLL locked tPW,MIN tR, tF t() tSK(O) Input Reference Pulse Width4 CCLKx Input Rise/Fall Time Propagation Delay (static phase offset)5 CCLKx to FB_IN (FB = / 8 and fREF = 50 MHz) Output-to-output Skew6 within QA bank within QB bank within QC bank any output 0.8 to 2.0V PLL locked DC tR, tF tPLZ, HZ tPZL tJIT(CC) tJIT(PER) tJIT() Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle Period Jitter 6 0.55 to 2.4V Jitter7 I/O Phase Jitter RMS (1 ) FB = / 8 FB = / 12 FB = / 16 FB = /24 FB = / 32 FB = / 48 FB = / 8 FB = / 12 FB = / 16 FB = / 24 FB = / 32 FB = / 48 0.50 - 1.80 0.30 - 1.00 0.25 - 0.70 0.17 - 0.40 0.12 - 0.30 0.07 - 0.20 15 49 18 22 26 34 BW PLL Closed Loop Bandwidth9 tLOCK 1. 2. 3. 4. 5. 6. 7. 8. 9. Maximum PLL Lock Time 10 ms AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC97H74 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio (FB): fREF = fVCO / (M x VCO_SEL). Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN x fREF x 100% and DCREF,MAX = 100% - DCREF, MIN. E.g. at fREF = 62.5 MHz the input duty cycle range is 12.5% < DC < 87.5%. Static phase offset depends on the reference frequency: t() = +50 ps (1 / (120 x fREF)) for any reference frequency. Refer to Application section for part-to-part skew calculation. Valid for all outputs at the same fequency. I/O jitter for fVCO = 400 MHz. Refer to APPLICATIONS INFORMATION for I/O jitter at other frequencies and for a jitter calculation for confidence factors other than 1 . -3 dB point of PLL transfer characteristics. 238 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H74 APPLICATIONS INFORMATION MPC97H74 Configurations Configuring the MPC97H74 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: fOUT = fREF x M / N fREF PLL /VCO_SEL /N fOUT frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and the output divider: fQA[4:0] = fVCO / (VCO_SEL x NA) fQB[4:0] = fVCO / (VCO_SEL x NB) fQC[3:0] = fVCO / (VCO_SEL x NC) Table 9MPC97H74 Dividers Divider Function PLL feedback FSEL_FB[0:1] Bank A Output Divider FSEL_A Bank B Output Divider FSEL_B Bank C Output Divider FSEL_C VCO_SEL /2 /4 /2 /4 /2 /4 /2 /4 Values 8, 12, 16, 24 16, 24, 32, 48 4, 8 8, 16 4, 8 8, 16 8, 12 16, 24 M /M where fREF is the reference frequency of the selected input clock source (CCLKO or CCLK1), M is the PLL feedback divider and N is a output divider. M is configured by the FSEL_FB[0:1] and N is individually configured for each output bank by the FSEL_A, FSEL_B and FSEL_C inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 500 MHz in order to achieve stable PLL operation: fVCO,MIN (fREF x VCO_SEL x M) fVCO,MAX The PLL post-divider VCO_SEL is either a divide-by-two or a divide-by-four and can be used to situate the VCO into the specified frequency range. This divider is controlled by the VCO_SEL pin. VCO_SEL effectively extends the usable input Figure 3. Example Configuration fREF = 20.83 MHz CCLK0 CCLK1 0 CCLK_SEL 0 VCO_SEL FB_IN 0 1 0 11 FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] QA[4:0] QB[4:0] QC[3:0] QFB 125 MHz 62.5 MHz 62.5 MHz NA NB NC Table 9 shows the various PLL feedback and output dividers. The output dividers for the three output banks allow the user to configure the outputs into 1:1, 2:1, 3:2, and 3:2:1 frequency ratios. Figure 3 and Figure 4 display example configurations for the MPC97H74: Figure 4. Example Configuration fREF = 25 MHz CCLK0 CCLK1 0 CCLK_SEL 0 VCO_SEL FB_IN 0 1 1 01 FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] QA[4:0] QB[4:0] QC[3:0] QFB 100 MHz 50 MHz 33.3 MHz MPC97H74 20.83 MHz (Feedback) MPC97H74 25 MHz (Feedback) MPC97H74 example configuration (feedback of QFB = 20.83 MHz, VCO_SEL = / 2, M = 12, NA = 2, NB = 4, NC = 4, fVCO = 500 MHz). Frequency Range Input QA outputs QB outputs QC outputs Min 8.33 MHz 50 MHz 25 MHz 25 MHz Max 20.83 MHz 125 MHz 62.5 MHz 62.5 MHz MPC97H74 example configuration (feedback of QFB = 25 MHz, VCO_SEL = / 2, M = 8, NA = 2, NB = 4, NC = 6, fVCO = 400 MHz). Frequency Range Input QA outputs QB outputs QC outputs Min 20 MHz 50 MHz 50 MHz 100 MHz Max 48 MHz 120 MHz 120 MHz 200 MHz FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 239 MPC97H74 Using the MPC97H74 in Zero-Delay Applications Nested clock trees are typical applications for the MPC97H74. Designs using the MPC97H74 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback of the MPC97H74 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC97H74 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC97H74 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() x CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Table 10. Confidence Factor CF CF 1 2 3 4 5 6 Probability of Clock Edge Within The Distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 Due to the frequency dependence of the static phase offset and I/O jitter, using Figure 6. MPC97H74 I/O Jitter and Figure 7. MPC97H74 I/O Jitter to predict a maximum I/O jitter and the specified t() parameter relative to the input reference frequency results in a precise timing performance analysis. In the following example calculation a I/O jitter confidence factor of 99.7 percent ( 3 ) is assumed, resulting in a worst case timing uncertainty from the common input reference clock to any output of -470 ps to +320 ps relative to CCLK (PLL feedback = /8, reference frequency = 50 MHz, VCO frequency = 400 MHz, I/O jitter = 15 ps rms max., static phase offset t() = -250 ps to +100 ps): tSK(PP) = [-250 ps...+100 ps] + [-175 ps...175 ps] + [(15 ps x -3)...(15 ps x 3)] + tPD, LINE(FB) tSK(PP) = [-470 ps...+320 ps] + tPD, LINE(FB) Maximum I/O Phase Jitter (RMS) versus Frequency Parameter: PLL Feedback Divider FB CCLKCommon 100 tjit() [ps] RMS --t() tPD, LINE(FB) 80 60 40 20 tSK(O) +t() FB = / 8 FB = / 32 FB = / 16 QFBDevice 1 tJIT() Any QDevice 1 0 200 250 300 350 400 VCO Frequency (MHz) 450 500 QFBDevice2 Figure 6. MPC97H74 I/O Jitter tJIT() tSK(O) tjit() [ps] RMS tSK(PP) Maximum I/O Phase Jitter (RMS) versus Frequency Parameter: PLL Feedback Divider FB 160 140 FB = / 12 120 100 FB = / 48 80 60 FB = / 24 40 20 0 200 250 300 350 400 VCO Frequency (MHz) Any QDevice 2 Max. Skew Figure 5. MPC97H74 Max. Device-to-Device Skew Due to the statistical nature of I/O jitter a rms value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 10. The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. 450 500 Figure 7. MPC97H74 I/O Jitter 240 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H74 Driving Transmission Lines The MPC97H74 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC divided by 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC97H74 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 8. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC97H74 clock driver is effectively doubled due to its capability to drive multiple lines. match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 40 || 40 R0 = 10 VL = 3.0 ( 25 / (20 + 10 + 25) = 1.36 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.7 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 3.0 2.5 2.0 VOLTAGE (V) In 1.5 1.0 0.5 0 RS = 40 ZO = 50 OutA 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 MPC97H74 OUTPUT BUFFER IN 10 Figure 9. Single versus Dual Waveforms MPC97H74 OUTPUT BUFFER IN 10 RS = 40 ZO = 50 OutB1 RS = 40 ZO = 50 OutB0 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 10. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC97H74 OUTPUT BUFFER 10 RS = 30 ZO = 50 Figure 8. Single versus Dual Transmission Lines The waveform plots in Figure 9. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC97H74 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC97H74. The output waveform in Figure 9. Single versus Dual Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 40 series resistor plus the output impedance does not RS = 30 ZO = 50 10 + 30 || 30 = 50 || 50 25 = 25 Figure 10. Optimized Dual Line Termination FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 241 MPC97H74 Power Supply Filtering The MPC97H74 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC97H74 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC97H74. Figure 11. VCC_PLL Power Supply Filter illustrates a typical power supply filter scheme. The MPC97H74 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 5 mA (7.5 mA maximum), assuming that a minimum of 3.02 V (VCC_PLL, minimum) must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 11. VCC_PLL Power Supply Filter must have a resistance of 5 - 15 to meet the voltage drop criteria. The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 11. VCC_PLL Power Supply Filter, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. RF = 5-15 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC97H74 VCC 33...100 nF Figure 11. VCC_PLL Power Supply Filter As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC97H74 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. MPC97H74 DUT Pulse Generator Z = 50 Z = 50 Z = 50 RT = 50 VTT RT = 50 VTT Figure 12. CCLK MPC97H74 AC Test Reference 242 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC97H74 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t() CCLKx VCC VCC / 2 GND FB_IN VCC VCC / 2 GND Figure 13. Output-to-Output Skew tSK(O) Figure 14. Propagation Delay (t(), Static Phase Offset) Test Reference VCC VCC / 2 tP t0 DC = tP/t0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage GND CCLKx FB_IN tJIT(y) = |t0 - t1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 15. Output Duty Cycle (DC) Figure 16. I/O Jitter tN tN+1 tJIT(CC) = |tN - tN + 1| t0 tJIT(PER) = |tN - (1 / f0)| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 17. Cycle-to-Cycle Jitter Figure 18. Period Jitter VCC = 3.3 V 2.4 0.55 tF tR Figure 19. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 243 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC992 Rev 2, 08/2001 Low Voltage PECL PLL Clock Driver The MPC992 is a 3.3V compatible, PLL based PECL clock generator and distributor. The fully differential design ensures optimum skew and PLL jitter performance. The performance of the device makes the MPC992 ideal for workstations, main frame computer, telecommunication and instrumentation applications. The device offers a crystal oscillator or a differential PECL reference clock input to provide flexibility in the reference clock interface. All of the control signals to the MPC992 are LVTTL compatible inputs. Features * * * * * * * Fully Integrated PLL Output Frequency of up to 400MHz PECL Clock Inputs and Outputs Operates from a 3.3V VCC Supply Output Frequency Configurable 32-Lead TQFP Packaging 25ps Cycle-Cycle Jitter MPC992 LOW VOLTAGE PLL CLOCK DRIVER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC992 offers two banks of outputs which can be configured into four different relationships. The output banks can be configured into 2:1, 3:1, 3:2 and 5:2 ratios to provide a wide variety of potential frequency outputs. In addition to these two banks of outputs a synchronization output is also offered. The SYNC output will provide information as to the time when the two output banks will transition positively in phase. This information can be important when the odd ratios are used as it provides for a baseline point in the system timing. The SYNC output will pulse high for one Qa clock period, centered on the rising Qa clock edge four edges prior to the Qb synchronous edge. The relationship is illustrated in the timing diagrams in the data sheet. The MPC992 offers several features to aid in system debug and test. The PECL reference input pins can be interfaced to a test signal and the PLL can be bypassed to allow the designer to drive the MPC992 outputs directly. This allows for single stepping in a system functional debug mode. In addition an overriding reset is provided which will force all of the Q outputs LOW upon assertion. The MPC992 is packaged in a 32-lead TQFP package to optimize both performance and board density. PLL_EN VCO_SEL XTAL_SEL XTAL1 XTAL2 PECL_CLK PECL_CLK FSEL0 FSEL1 POR Reset XTAL OSC x2 1 0 Integrated PLL 0 1 0 1 Qan Frequency Generator Qan Qbn Qbn (x4) (x3) SYNC (x1) SYNC Figure 1. MPC992 Logic Diagram 244 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC992 VCCO1 24 Qa1 Qa1 Qa0 Qa0 GND VCCA Reset VCCI 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 VCCO2 17 16 15 14 Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 PLL_EN GNDI 13 12 11 10 9 8 XTAL2 SYNC 6 PCKL_CLK MPC992 2 3 4 5 PCLK_CLK FSEL0 VCO_SEL FSEL1 XTAL_SEL Figure 2. MPC992 32-Lead Package Pinout (Top View) Table 1. Function Table 1 FSEL0 0 0 1 1 FSEL1 0 1 0 1 Qa VCO/4 VCO/2 VCO/4 VCO/2 Qb VCO/6 VCO/4 VCO/10 VCO/6 Feedback VCO/24 VCO/16 VCO/40 VCO/24 Ratio 3:2 2:1 5:2 3:1 Table 3. Function Table 2 Control Signal Reset XTAL_SEL PLL_EN VCO_SEL Qb 4 (fref) 4 (fref) 4 (fref) 4 (fref) Internal Feedback fref fref fref fref Logic `0' Outputs Enabled PECL REF Disabled High Frequency Logic `1' Outputs Disabled XTAL REF Enabled Low Frequency Table 2. Input vs Output Frequency FSEL0 0 0 1 1 FSEL1 0 1 0 1 Qa 6 (fref) 8 (fref) 10 (fref) 12 (fref) Table 4. Pin Description Pin Name VCO_SEL PLL_EN XTAL_SEL XTAL1:2 PECL_CLK PECL_CLK FSELn RESET Function VCO range select pin (Int Pullup) PLL bypass select pin (Int Pullup) Input reference source select pin (Int Pullup) Crystal interface pins for the internal oscillator True PECL reference clock input (Int Pulldown) Compliment PECL reference clock input (Int Pullup) Internal divider select pins (Int Pullup) Internal flip-flop reset, true outputs go LOW (Int Pulldown) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA XTAL1 SYNC 7 Qa2 Qa2 Qa3 Qa3 245 MPC992 2:1 Mode Qa Qb SYNC 3:1 Mode Qa Qb SYNC 3:2 Mode Qa Qb SYNC 5:2 Mode Qa Qb SYNC Figure 3. Output Waveforms Table 5. Absolute Maximum Ratings1 Symbol VCC VI IOUT TStor Supply Voltage Input Voltage Output Current Storage Temperature Range Continuous Surge -40 Parameter Min -0.3 -0.3 Max 4.6 VDD + 0.3 50 100 125 Unit V V mA C 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. 246 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC992 Table 6. DC Characteristics (TA = 0 to 70C, VCC = 3.3V 5%) Symbol VIH VIL VOH VOL IIN ICCI ICCA Characteristic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage1 Output LOW Voltage1 Input Current Maximum Quiescent Supply Current Maximum PLL Supply Current PECL_CLK Other 1 Min 2.15 2.0 1.5 0 1.8 1.2 -120 Typ Max 2.4 VCC 1.8 0.8 2.4 1.7 120 Unit V V V V A mA mA Condition VCC = 3.3V VCC = 3.3V VCC = 3.3V VCC = 3.3V PECL_CLK1 Other 130 15 150 20 1. DC levels will vary 1:1 with VCC. Table 7. AC Characteristics (TA = 0 to 70C, VCC = 3.3V 5%) Symbol tr, tf tpw1 tpw2 fref tos fVCO fmax Characteristic Output Rise/Fall Time Output Duty Cycle SYNC Output Duty Cycle Input Reference Frequency Output-to-Output Skew PLL VCO Lock Range Maximum Output Frequency Qa (/2) Qa,Qb (/4) Qb (/6) Qb (/10) 25 XTAL FREF Qa, Qb Qa (-) to SYNC (+) 200 400 Min 200 49 0.95 10 Note1 Typ Max 850 51 1.05 20 Note1 100 300 440 750 375 187.5 125 75 50 10 ps MHz MHz VCO_SEL = 1 VCO_SEL = 0 Note2 Unit ps % % MHz PCLK Period Condition 20% to 80% tjitter tlock Cycle-to-Cycle Jitter (Peak-to-Peak) Maximum PLL Lock Time ps ms Note3 1. ECLK and XTAL input reference limited by the feedback divide and the guaranteed VCO lock range. 2. At 400MHz the output swing will be less than the nominal value. 3. Guaranteed by characterization. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 247 MPC992 APPLICATIONS INFORMATION Using the On-Board Crystal Oscillator The MPC992 features an on-board crystal oscillator to allow for seed clock generation as well as final distribution. The on-board oscillator is completely self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC992 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are recommended, but not required. The oscillator circuit is a series resonant circuit as opposed to the more common parallel resonant circuit, this eliminates the need for large on-board capacitors. Because the design is a series resonant design, for optimum frequency accuracy a series resonant crystal should be used (see specification table below). Unfortunately most off the shelf crystals are characterized in a parallel resonant mode. However a parallel resonant crystal is physically no different than a series resonant crystal, a parallel resonant crystal is simply a crystal which has been characterized in its parallel resonant mode. Therefore in the majority of cases a parallel specified crystal can be used with the MPC992 with just a minor frequency error due to the actual series resonant frequency of the parallel resonant specified crystal. Typically a parallel specified crystal used in a series resonant mode will exhibit an oscillatory frequency a few hundred ppm lower than the specified value. For most processor implementations a few hundred ppm translates into kHz inaccuracies, a level which does not represent a major issue. Figure 4 shows an optional series capacitor in the crystal oscillator interface. The on-board oscillator introduces a small phase shift in the overall loop which causes the oscillator to operate at a frequency slightly slower than the specified crystal. The series capacitor is used to compensate the loop and allow the oscillator to function at the specified crystal frequency. If a 100ppm type error is not important, the capacitor can be left off the PCB. For more detailed information, order Motorola Application Note AN1579/D. MPC992 XTAL1 Table 8. Crystal Specifications Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance* 75ppm at 25C 150ppm 0 to 70C 0 to 70C 5-7pF 50 to 80 max 100 5ppm/Yr (First 3 Years) XTAL2 CTUNE (Optional) Figure 4. Recommended Crystal Interface Power Supply Filtering The MPC992 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC992 provides separate power supplies for the digital circuitry (VCCI) and the internal PLL (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC992. Figure 5 illustrates a typical power supply filter scheme. The MPC992 is most susceptible to noise with spectral content in the 10kHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC992. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 5 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. 248 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC992 3.3V RS=10-15 VCCA MPC992 VCC 0.01F 0.01F 22F Figure 5. Power Supply Filter A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000H choke will show a significant impedance at 10KHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCCA pin a low DC resistance inductor is required (less than 15). Generally the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. The MPC992 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. The important aspect of the layout for the MPC992 is low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC992 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. No active signal lines should pass below the crystal interface to the MPC992. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. In addition, the crystal interface circuitry will be adversely affected by activity on the PECL_CLK inputs. Therefore, it is recommended that the PECL input signals be static when the crystal oscillator circuitry is being used. Although the MPC992 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 249 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9992 Rev 4, 08/2004 3.3V Differential ECL/PECL PLL Clock Generator The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using SiGe technology and a fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC9992 makes the device ideal for workstation, mainframe computer and telecommunication applications. With output frequencies up to 400 MHz and output skews less than 100 ps the device meets the needs of the most demanding clock applications. The MPC9992 offers a differential PECL input and a crystal oscillator interface. All control signals are LVCMOS compatible. Features * * * * * * * * * * * 7 differential outputs, PLL based clock generator SiGe technology supports minimum output skew (max. 100 ps) Supports up to two generated output clock frequencies with a maximum clock frequency up to 400 MHz Selectable crystal oscillator interface and PECL compatible clock input SYNC pulse generation PECL compatible differential clock inputs and outputs Single 3.3V (PECL) supply Ambient temperature range 0C to +70C Standard 32 lead LQFP package Pin and function compatible to the MPC992 32-lead Pb-free Package Available MPC9992 3.3V DIFFERENTIAL ECL/PECL CLOCK GENERATOR FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback frequency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input reference frequency range. The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC generator output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between output frequencies. The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted. Assertion of the reset signal forces all outputs to the logic low state. The MPC9992 is fully 3.3V compatible and requires no external loop filter components. The differential clock input (PCLK) is PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels with the capability to drive terminated 50 transmission lines. The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package. 250 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9992 VCC XTAL_IN XTAL_OUT PCLK PCLK All input resistors have a value of 50k BANK A QA0 QA0 QA1 QA1 QA2 QA2 QA3 QA3 XTAL 1 0 Ref VCO /4 /2 1 0 0 1 /2, /4 /4, /6, /10 /16, /24, /40 SYNC PULSE BANK B VCC REF_SEL VCC VCO_SEL PLL_EN FSEL[1:0] PLL 800-1600 MHz FB QB0 QB0 QB1 QB1 QB2 QB2 VCC 2 SYNC QSYNC QSYNC MR/STOP Figure 1. MPC9992 Logic Diagram QSYNC QSYNC 18 QA2 QA2 QA3 QA3 VCC 24 QA1 QA1 QA0 QA0 GND VCC_PLL MR/STOP VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 VCC 17 16 15 14 QB0 QB0 QB1 QB1 QB2 QB2 PLL_EN GND 13 12 11 10 9 8 XTAL_OUT MPC9992 2 3 4 5 6 7 PCLK REF_SEL Figure 2. MPC9992 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA VCO_SEL XTAL_IN FSEL0 FSEL1 PCKL 251 MPC9992 Table 1. MPC9992 PLL Configurations VCO_SEL 0 0 0 0 1 1 1 1 FSEL_0 0 0 1 1 0 0 1 1 FSEL_1 0 1 0 1 0 1 0 1 fREF (MHz) 16.6-33.3 25-50 10-20 16.6-33.3 8.3-16.6 12.5-25 5-10 8.3-16.6 QA[3:0] (NA) VCO/8 (6 fREF) VCO/4 (8 fREF) VCO/8 (10 fREF) VCO/4 (12 fREF) VCO/16 (6 fREF) VCO/8 (8 fREF) VCO/16 (10 fREF) VCO/8 (12 fREF) QB[2:0] (NB) VCO/12 (4 fREF) VCO/8 (4 fREF) VCO/20 (4 fREF) VCO/12 (4 fREF) VCO/24 (4 fREF) VCO/16 (4 fREF) VCO/40 (4 fREF) VCO/24 (4 fREF) Frequency Ratio QA to QB 3/2 2/1 5/2 3/1 3/2 2/1 5/2 3/1 Internal Feedback (M VCO_SEL) VCO/48 VCO/32 VCO/80 VCO/48 VCO/96 VCO/64 VCO/160 VCO/96 Table 2. Function Table (Configuration Controls) Control REF_SEL VCO_SEL PLL_EN Default 1 1 1 0 Selects PCLK, PCLK as PLL references signal input Selects VCO/2. The VCO frequency is scaled by a factor of 2 (high input frequency range) Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC9992 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Normal operation 1 Selects the crystal oscillator as PLL reference signal input Selects VCO/4. The VCO frequency is scaled by a factor of 4 (low input frequency range). Normal operation mode with PLL enabled. MR/STOP 0 Reset of the device and output disable (output clock stop). The outputs are stopped in logic low state: Qx=L, Qx=H. The minimum reset period should be greater than one reference clock cycle. VCO_SEL and FSEL[1:0] control the operating PLL frequency range and input/output frequency ratios. See Table 1 for the device frequency configuration. Table 3. Pin Configuration Pin PCLK, PCLK XTAL_IN, XTAL_OUT VCO_SEL PLL_EN REF_SEL MR/STOP FSEL[1:0] QA[0-3], QA[0-3] QB[0-2], QB[0-2] QSYNC, QSYNC GND VCC VCC_PLL Input Input Input Input Input Output Output Output Supply Supply Supply I/O Input Type PECL Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS PECL PECL PECL GND VCC VCC Differential reference clock signal input Crystal oscillator interface VCO operating frequency select PLL Enable/Bypass mode select PLL reference signal input select Device reset and output clock disable (stop in logic low state) Output and PLL feedback frequency divider select Differential clock outputs (bank A) Differential clock outputs (bank B) Differential clock outputs (bank C) Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details Function 252 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9992 Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. General Specifications Symbol VTT MM HBM CDM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Input Capacitance Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 175 2000 1000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2 Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC TJ Thermal Resistance Junction to Case Operating Junction Temperature1 (continuous operation) MTBF = 9.1 years 0 110 C 1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MPC9992 to be used in applications requiring industrial temperature range. It is recommended that users of the MPC9992 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 253 MPC9992 Table 6. DC Characteristics (VCC = 3.3V 5%, GND = 0V, TA = 0C to 70C) Symbol Characteristics 1 Min Typ Max Unit Condition Differential PECL Clock Inputs (PCLK, PCLK) VPP VCMR IIN VIH VIL IIN VOH VOL VCC_PLL ICC_PLL IGND 5 AC Differential Input Voltage2 Differential Cross Point Voltage3 Input Current4 Input High Voltage Input Low Voltage Input Current 4 0.2 1.0 1.3 VCC-0.3 120 V V A Differential operation Differential operation VIN = VCC or GND LVCMOS LVCMOS VIN = VCC or GND LVCMOS Control Inputs (VCO_SEL, PLL_EN, MR/STOP, REF_SEL, FSEL[1:0]) 2.0 VCC + 0.3 0.8 120 V V A PECL Clock Outputs (QA[3:0], QA[3:0], QB[2:0], QB[2:0], QSYNC, QSYNC) Output High Voltage Output Low Voltage VCC-1.025 VCC-1.920 2.955 9.0 80 VCC-0.880 VCC-1.620 VCC 12 110 V V IOH = -30 mA IOL = -5 mA VCC_PLL pin VCC_PLL pin GND pins Supply Current and Voltage PLL Supply Voltage Maximum PLL Supply Current Maximum Supply Current V mA mA 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Inputs have pull-down resistors affecting the input current. 4. Equivalent to a termination of 50 to VTT. 5. Does not include output drive current which is dependant on output termination methods. 254 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9992 Table 7. AC Characteristics (VCC = 3.3V 5%, GND = 0V, TA = 0C to +70C)1 Symbol fref Characteristics Input Reference Frequency /32 feedback /48 feedback /64 feedback /80 feedback /96 feedback /160 feedback Min 25.0 16.67 12.5 10.0 8.33 5.0 Typ Max 50.0 33.3 25.0 20.0 16.67 10.0 400 10 800 /4 output /8 output /12 output /16 output /20 output /24 output /48 output 200.0 100.0 66.6 50.0 40.0 33.3 16.6 0.3 (PCLK) (PCLK) 1.2 0.6 2.0 100 48 50 30 43 RMS (1 )10 /32 feedback /48 feedback /64 feedback /80 feedback /96 feedback /160 feedback 86 0.60-1.5 0.40-1.2 0.30-1.0 0.30-0.8 0.20-0.7 0.15-0.4 10 0.05 1.0 52 79 106 212 0.8 20 1600 400.0 200.0 133.3 100.0 80.0 66.6 33.3 1.3 VCC-0.3 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz V V V ns ps % ps ps ps MHz MHz MHz MHz MHz MHz ms ns 20% to 80% PLL locked Condition PLL locked Input Reference Frequency in PLL Bypass Mode2 fXTAL fVCO fMAX Crystal Interface Frequency Range VCO Frequency Range Output Frequency 4 3 PLL bypass VPP VCMR VO(P-P) tPW,MIN tsk(O) DC tJIT(CC) tJIT(PER) tJIT() BW Differential Input Voltage5 (peak-to-peak) Differential Input Crosspoint Voltage6 Differential Output Voltage (peak-to-peak) Input Reference Pulse Width7 Output-to-Output Skew Output Duty Cycle8 Cycle-to-Cycle Jitter9 Period Jitter9 I/O Phase Jitter9 PLL Closed Loop Bandwidth11 tLOCK tr, tf Maximum PLL Lock Time Output Rise/Fall Time 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. In bypass mode, the MPC9992 divides the input reference clock. 3. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio: fXTAL(min, max) = fVCO(min, max) / (M VCO_SEL) and 10 MHz fXTAL 20 MHz. 4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO / (M VCO_SEL) 5. VPP is the minimum differential input voltage swing required to maintain AC characteristics. 6. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. 7. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF, MIN. E.g. at fREF = 50 MHz the input duty cycle range is 10% < DC < 90%. 8. Output duty cycle for QAx and QBx outputs. The pulse width for the QSYNC output is equal to one QAx output period tQA 5%. 9. Jitter data is valid fref = 25 MHz. 10. See application section for a jitter calculation for other confidence factors than 1 . 11. -3 dB point of PLL transfer characteristics. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 255 MPC9992 APPLICATIONS INFORMATION SYNC Output Description The MPC9992 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9992 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic high) one QA period in duration. The placement of the pulse is dependent on the QA and QB output frequencies ratio. Figure 3 shows the waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank B outputs. 2:1 Mode Qa Qb QSYNC 3:1 Mode Qa Qb QSYNC 3:2 Mode Qa Qb QSYNC 5:2 Mode Qa Qb QSYNC Figure 3. QSYNC Timing Diagram 256 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9992 Power Supply Filtering The MPC9992 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9992 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9992. Figure 4 illustrates a typical power supply filter scheme. The MPC9992 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 9 mA (12 mA maximum), assuming that a minimum of 2.955V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 4 must have a resistance of 10-15 to meet the voltage drop criteria. RF = 10 - 15 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9992 VCC 33...100 nF Figure 4. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 4, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9992 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Differential Pulse Generator Z = 50 Z = 50 Z = 50 RT = 50 VTT MPC9992 DUT RT = 50 VTT Figure 5. MPC9992 AC Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 257 MPC9992 END 258 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Chapter Three QUICCClock Generator Data Sheets QUICCClock Generator Device Index Device Number Page MPC9817 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 MPC9850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 MPC9855 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 259 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9817 Rev 0, 07/2004 Advance Information Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers The MPC9817 is a PLL-based clock generator specifically designed for Motorola Microprocessor and Microcontroller applications including the PowerPC and PowerQUICC. This device generates the microprocessor input clock and other microprocessor system and bus clocks at any one of four output frequencies. These frequencies include the popular 33- and 66-MHz PCI bus frequencies. The device offers five low-skew clock outputs plus three reference outputs. The clock input reference is 25 MHz and may be derived from an external source or by the addition of a 25-MHz crystal to the on-chip crystal oscillator. The extended temperature range of the MPC9817 supports telecommunication and networking requirements. Features * 5 LVCMOS outputs for processor and other system circuitry * 3 Buffered 25-MHz reference clock outputs * Crystal oscillator or external reference input * 25-MHz input reference frequency * Selectable output frequencies include: 25, 33, 50, or 66 MHz * Low cycle-to-cycle and period jitter * Package: 20-lead SSOP * 3.3-V supply * Supports computing, networking, and telecommunications applications * Ambient temperature range: -40C to +85C MPC9817 MICROPROCESSOR CLOCK GENERATOR SCALE 2:1 SD SUFFIX 20 SSOP PACKAGE CASE 1461-01 Functional Description The MPC9817 uses a PLL with a 25-MHz input reference frequency to generate a single bank of five configurable LVCMOS output clocks. The output frequency of this bank is configurable to either 25, 33, 50, or 66 MHz by two FSEL pins. The 25-MHz reference may be either an external frequency source or a 25-MHz crystal. The 25-MHz crystal is directly connected to the XTAL_IN and XTAL_OUT pins with no additional components required. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating. The input reference, whether provided by a crystal or an external input, is also directly buffered to a second bank of three LVCMOS outputs. These outputs may be used as the clock source for processor I/O applications such as an Ethernet PHY. When FSEL0 and FSEL1 are both configured low, the QA outputs are directly fed from the input reference providing a total of eight low-skew 25-MHz outputs. For all other combinations of FSEL0 and FSEL1 the single-ended LVCMOS outputs provide five low-skew outputs for use in driving a microprocessor or microcontroller clock input as well as other system components. The MPC9817 is packaged in a 20-lead SSOP package. This document contains certain information on a new product. Specifications and information herein are subject to change without notice. 260 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9817 QA0 XTAL_IN OSC XTAL_OUT Ref PLL 400 MHz QA1 33,50,66 MHz QA2 QA3 FSEL0 FSEL1 Data Generator 25 MHz QA4 QREF0 QREF1 QREF2 MR/OE Figure 1. MPC9817 Logic Diagram Table 1. Pin Configuration Pin QA0, QA1, QA2, QA3, QA4 QREF0, QREF1, QREF2 XTAL_IN XTAL_OUT FSEL0, FSEL1 MR/OE VDD GND I/O Output Output Input Output Input Input -- -- Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS -- -- Clock Outputs Reference Output (25 MHz) Crystal Oscillator Input Pin Crystal Oscillator Output Pin Configures Bank A Clock Output Frequency (pull-up) Enables All Outputs (pull-down) 3.3-V Supply Ground Function Table 2. Function Table Control FSEL0,FSEL1 Default 11 00 25 MHz fed directly from reference input, PLL disabled 01 33 MHz 10 50 MHz 11 66 MHz FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 261 MPC9817 XTAL_IN XTAL_OUT FSEL0 VDD FSEL1 QREF2 GND QREF1 QREF0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD QA4 QA3 GND QA2 QA1 VDD QA0 MR/OE GND Figure 2. MPC9817 20-Lead SSOP Package Pinout (Top View) MPC9817 OPERATION Crystal Oscillator The MPC9817 features a fully integrated Pierce oscillator to minimize system implementation costs. Other than the addition of a 25-MHz crystal, no external components are required.The crystal selection should be: 25 MHz, parallel resonant type with a load specification of CL = 20 pF. The crystal should be located as close to the MPC9817 XTAL_IN and XTAL_OUT pins as possible to avoid any board level parasitic. Power Supply Bypassing The MPC9817 should have all VDD pins bypassed with 0.01 capacitors and a minimum of one 1.0 capacitor for the overall package. All capacitors should be located as close to the SSOP pins as possible. External Clock Source An external reference source of 25 MHz may be applied to the XTAL_IN pin. In this mode of operation, the XTAL_OUT pin should be left floating. 262 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9817 Table 3. Absolute Maximum Ratings1 Symbol VDD IIN IOUT TS Supply Voltage DC Input Current DC Output Current Storage Temperature Characteristics Min -0.3 -- -- -65 Max 3.8 20 75 125 Unit V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol VTT MM HBM LU CIN JC TC Characteristics Output Termination Voltage ESD Protection (machine model) ESD Protection (human body model) Latch-Up Immunity Input Capacitance Thermal Resistance (junction-to-ambient, junction-toboard, junction-to-case) Ambient Temperature Min -- 200 2000 200 -- -- -40 Typ VDD / 2 -- -- -- 4 TBD Max -- -- -- -- -- -- 85 Unit V V V ma pF C/W C Inputs Condition Table 5. DC Characteristics (VDD = 3.3 V 5%, TA= -40C to +85C) Symbol VIH VIH VIL IIN VOH VOL ZOUT IDD Characteristics Input High Voltage (XTAL_IN) Input High Voltage Input Low Voltage Input Current1 Output High Voltage Output Low Voltage Output Impedance Maximum Quiescent Supply Current Min 2.4 2.0 -- -- 2.4 -- -- -- Typ -- -- -- -- -- -- 14 TBD Max VDD + 0.3 VDD + 0.3 0.8 150 -- 0.4 -- TBD Unit V V V A V V mA VDD pins LVCMOS VIN = VDDL or GND IOH = -24 mA IOL = 24 mA Condition Input threshold = VDD/2 1. Inputs have pull-down resistors affecting the input current. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 263 MPC9817 Table 6. AC Characteristics1 2 (VDD = 3.3 V 5%, TA= -40C to +85C) Symbol Characteristics Min Typ Max Unit Condition Input and Output Timing Specification fref fVCO fMCX Input Reference Frequency VCO Frequency Range Output Frequency (QAx) FSEL0, FSEL1 = 00 FSEL0, FSEL1 = 01 FSEL0, FSEL1 = 10 FSEL0, FSEL1 = 11 TBD 47.5 Crystal3 External Reference TBD 0 25 MHz Input XTAL Input TBD TBD -- 25 25 400 25 33 50 66 25 -- 50 -- -- TBD TBD -- -- -- -- -- -- -- 52.5 TBD 0 MHz MHz MHz MHz MHz MHz MHz MHz ps % ppm ppm PLL locked Output Frequency (QREFx) frefPW DC fout Reference Input Pulse Width Output Duty Cycle Output Frequency Accuracy PLL Specifications BW tLOCK PLL Closed Loop Bandwidth4 Maximum PLL Lock Time 500 10 kHz ms Skew and Jitter Specifications tsk(O) tsk(O) tJIT(CC) tJIT(PER) tJIT(O) tr, tf 1. 2. 3. 4. Output-to-Output Skew (within a bank) Output-to-Output Skew (between bank A and bank Ref) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Output Rise/Fall Time TBD TBD 100 200 150 175 TBD 1 ps ps ps ns 20% to 80% ps FSEL0, FSEL1 = 00 AC characteristics are design targets and pending characterization AC characteristics apply for parallel output termination of 50 to VTT Based upon recommended crystal specifications as outlined in operation section -3 dB point of PLL transfer characteristics Pulse Generator Z = 50 Z = 50 Z = 50 RT = 50 VTT DUT MPC9817 RT = 50 VTT Figure 3. MPC9817 AC Test Reference (LVCMOS Outputs) 264 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9817 Table 7. MPC9817 Pin List Pin 1 2 3 4 5 6 7 8 9 10 Description XTAL_IN XTAL_OUT FSEL0 VDD FSEL1 QREF2 GND QREF1 QREF0 VDD Pin 11 12 13 14 15 16 17 18 19 20 Description GND MR/OE QA0 VDD QA1 QA2 GND QA3 QA4 VDD FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 265 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9850 Rev 3, 07/2004 Preliminary Information Clock Generator for PowerQUICC III The MPC9850 is a PLL based clock generator specifically designed for Motorola Microprocessor And Microcontroller applications including the PowerQUICC III. This device generates a microprocessor input clock plus the 500 MHz Rapid I/O clock. The microprocessor clock is selectable in output frequency to any of the commonly used microprocessor input and bus frequencies. The Rapid I/O outputs are LVDS compatible. The device offers eight low skew clock outputs organized into two output banks, each configurable to support different clock frequencies. The extended temperature range of the MPC9850 supports telecommunication and networking requirements. Features * 8 LVCMOS outputs for processor and other circuitry * 2 differential LVDS outputs for Rapid I/O interface * Crystal oscillator or external reference input * 25 or 33 MHz Input reference frequency * Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66, 50, 33 or 16 MHz * Buffered reference clock output * Rapid I/O (LVDS) Output = 500, 250 or 125 MHz * Low cycle-to-cycle and period jitter * 100-lead PBGA package * 100-lead Pb-free Package Available * 3.3V supply with 3.3V or 2.5V output LVCMOS drive * Supports computing, networking, telecommunications applications * Ambient temperature range -40C to +85C MPC9850 MICROPROCESSOR CLOCK GENERATOR SCALE 2:1 VF SUFFIX VM SUFFIX (Pb-FREE) 100 MAPBGA PACKAGE CASE 1462-01 Functional Description The MPC9850 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60 or 120 to produce output frequencies of 200, 166, 133, 125, 111, 100, 83 66 50 33 or 16 MHz. The single-ended LVCMOS outputs are divided into two banks of 4 low skew outputs each, for use in driving a microprocessor or microcontroller clock input as well as other system components. The 2 GHz PLL output frequency is also divided to produce a 125, 250 or 500 MHz clock output for Rapid I/O applications such as found on the PowerQUICC III communications processor. The input reference, either crystal or external input is also buffered to a separate output that my be used as the clock source for a Gigabit Ethernet PHY if desired. The reference clock may be provided by either an external clock input of 25 MHz or 33 MHz. An internal oscillator requiring a 25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or external clock input is selected via the input pin of REF_SEL. Other than the crystal, no external components are required for crystal oscillator operation. The REF_33MHz configuration pins is used to select between a 33 and 25 MHz input frequency. The MPC9850 is packaged in a 100 lead MAPBGA package to optimize both performance and board density. 266 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9850 CLK PCLK PCLK REF_CLK_SEL XTAL_IN XTAL_OUT REF_SEL 0 1 0 1 Ref PLL 2000 MHz OSC 1 /N 0 QA1 QA2 QA3 /N QB0 QB1 QB2 QB3 /4, 8, 16, 40 QA0 PLL_BYPASS REF_33MHz CLK_A[0:5] CLK_B[0:5] RIO_C[0:1] MR QC0 QC0 QC1 QC1 REF_OUT Figure 1. MPC9850 Logic Diagram Table 1. Pin Configurations Pin CLK PCLK, PCLK QA0, QA1, QA2, QA3 QB0, QB1, QB2, QB3 REF_OUT XTAL_IN XTAL_OUT REF_CLK_SEL REF_SEL REF_33MHz MR PLL_BYPASS CLK_A[0:5] 1 I/O Input Input Output Output Output Input Output Input Input Input Input Input Input Input Input Type Function LVCMOS PLL Reference Clock Input (pull-down) PLL Reference Clock Input (PCLK - pull-down, PCLK - pull-up and pull-down) LVCMOS Bank A Outputs LVCMOS Bank B Outputs LVDS Bank C Outputs LVCMOS Reference Output (25 MHz or 33 MHz) LVCMOS Crystal Oscillator Input Pin LVCMOS Crystal Oscillator Output Pin LVCMOS Select between CLK and PCLK Input (pull-down) LVCMOS Selects 33MHz Input (pull-down) LVCMOS Master Reset (pull-up) LVCMOS Select PLL or static test mode (pull-down) LVCMOS Configures Bank A clock output frequency (pull-up) LVCMOS Configures Bank B clock output frequency (pull-up) LVCMOS Configures Bank C clock output frequency (pull-down) 3.3 V Supply Analog Supply Supply for Output Bank A Supply for Output Bank B Ground LVPECL Supply VDD VDD VDDOA VDDOB VDDOC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Active/State QC0, QC1, QC0, QC1 Output High High High Low High High High LVCMOS Select between External Input and Crystal Oscillator Input (pull-down) VDD CLK_B[0:5]2 RIO_C [0:1] VDD VDDA VDDOA VDDOB GND 1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) 2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) PowerPC bit ordering (bit 0 = msb, bit 1 = lsb) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 267 MPC9850 Table 2. Function Table Control REF_CLK_SEL REF_SEL PLL_BYPASS REF_33MHz MR Default 0 0 0 0 1 0 CLK CLK or PCLK Normal Selects 25 MHz Reference Reset 1 PCLK XTAL Bypass Selects 33 MHz Reference Normal CLK_A, CLK_B, and RIO_C control output frequencies. See Table 3 and Table 4 for specific device configuration Table 3. Output Configurations (Banks A & B) CLK_x[0:5]1 111111 111100 101000 011110 010100 001111 001100 001010 001001 001000 000111 000110 000101 000100 CLK_x[0] (msb) 1 1 1 0 0 0 0 0 0 0 0 0 0 0 CLK_x[1] 1 1 0 1 1 0 0 0 0 0 0 0 0 0 CLK_x[2] 1 1 1 1 0 1 1 1 1 1 0 0 0 0 CLK_x[3] 1 1 0 1 1 1 1 0 0 0 1 1 1 1 CLK_x[4] 1 0 0 1 0 1 0 1 0 0 1 1 0 0 CLK_x[5] (lsb) 1 0 0 0 0 1 0 0 1 0 1 0 1 0 N 126 120 80 60 40 30 24 20 18 16 15 12 10 8 2 Frequency (MHz) 15.87 16.67 25.00 33.33 50.00 66.67 83.33 100.00 111.11 125.00 133.33 166.67 200.00 250 1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) 2. Minimum value for N Table 4. Output Configurations (Bank C) RIO_C[0:1] 00 01 10 11 Frequency (MHz) 50 (test output) 125 250 500 268 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9850 OPERATION INFORMATION Output Frequency Configuration The MPC9850 was designed to provide the commonly used frequencies in PowerQUICC, PowerPC and other microprocessor systems. Table 3 lists the configuration values that will generate those common frequencies. The MPC9850 can generate numerous other frequencies that may be useful in specific applications. The output frequency (fout) of either Bank A or Bank B may be calculated by the following equation. fout = 2000 / N where fout is in MHz and N = 2 * CLK_x[0:5] This calculation is valid for all values of N from 8 to 126. Note that N = 15 is a modified case of the configuration inputs CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to 00111 or 7. Crystal Input Operation TBD Power-Up and MR Operation Figure 2 defines the release time and the minimum pulse length for MR pin. The MR release time is based upon the power supply being stable and within VDD specifications. See Table 11 for actual parameter values. The MPC9850 may be configured after release of reset and the outputs will be stable for use after lock indication is obtained. VDD MR treset_rel treset_pulse Figure 2. MR Operation Power Supply Bypassing The MPC9850 is a mixed analog/digital product. The architecture of the MPC9850 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VDD pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VDD 22 F 15 0.1 F VDD MPC9850 VDDA 0.1 F Figure 3. VCC Power Supply Bypass FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 269 MPC9850 Table 5. Absolute Maximum Ratings1 Symbol VDD VDDA VDDOA VDDOB VIN VOUT IIN IOUT TS Characteristics Supply Voltage (core) Supply Voltage (Analog Supply Voltage) Supply Voltage (LVCMOS output for Bank A) Supply Voltage (LVCMOS output for Bank B) DC Input Voltage DC Output Voltage2 DC Input Current DC Output Current Storage Temperature -65 Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max 3.8 VDD VDD VDD VDD+0.3 VDDx+0.3 20 50 125 V V mA mA C Unit V V V Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 2. VDDx references power supply pin associated with specific output pin. Table 6. General Specifications Symbol VTT MM HBM CDM LU CIN CPD JC TA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Input Capacitance Power Dissipation Capacitance Thermal Resistance (junction-to-ambient) Ambient Temperature -40 200 2000 500 200 4 10 54.5 85 Min Typ VDD / 2 Max Unit V V V V mA pF pF C/W C Inputs Per Output Air Flow = 0 Condition 270 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9850 Table 7. DC Characteristics (TA = -40C to 85C) Symbol Characteristics Min Typ Max Unit Condition Supply Current for VDD = 3.3 V 5%, VDDOA = 3.3 V 5%, = VDDOB = 3.3 V 5% IDD + IDDA Maximum Quiescent Supply Current (Core) + IDDOC IDDA IDDOA IDDOB Maximum Quiescent Supply Current (Analog Supply) Maximum Bank A Supply Current Maximum Bank B Supply Current 100 15 50 50 mA mA mA mA VDD + VDDA + VDDOC pins VDDIN pins VDDOA pins VDDOB pins Supply Current for VDD = 3.3 V 5%, VDDOA = 2.5 V 5%, VDDOB = 2.5 V 5% IDD + IDDA Maximum Quiescent Supply Current (Core) + IDDOC IDDA IDDOA IDDOB Maximum Quiescent Supply Current (Analog Supply) Maximum Bank A Supply Current Maximum Bank B Supply Current 100 15 40 40 mA mA mA mA VDD + VDDA + VDDOC pins VDDIN pins VDDOA pins VDDOA and VDDOB pins Table 8. LVDS DC Characteristics (TA = -40C to 85C) Symbol Characteristics Min Typ Max Unit Condition Differential LVDS clock outputs (QC0, QC0 and QC1, QC1) for VDD = 3.3 V 5% and VDDOC = 3.3 V 5% VPP VOS Output Differential Voltage1 (peak-to-peak) Output Offset Voltage (LVDS) (LVDS) 250 1125 400 1275 mV mV 1. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. Table 9. LVPECL DC Characteristics (TA = -40C to 85C)1 Symbol Characteristics Min Typ Max Unit Condition Differential LVPECL clock inputs (CLK1, CLK1) for VDD = 3.3 V 0.5% VPP VCMR Differential Voltage2 (peak-to-peak) Differential Input Crosspoint Voltage3 (LVPECL) (LVPECL) 250 1.0 VDD - 0.6 mV V 1. AC characteristics are design targets and pending characterization. 2. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 271 MPC9850 Table 10. LVCMOS I/O DC Characteristics (TA = -40C to 85C) Symbol LVCMOS for VDD = 3.3 V 5% VIH VIL IIN Input High Voltage Input Low Voltage Input Current1 2.0 VDD + 0.3 0.8 200 V V A LVCMOS LVCMOS VIN = VDDL or GND Characteristics Min Typ Max Unit Condition LVCMOS for VDD = 3.3 V 5%, VDDOA = 3.3 V 5%, VDDOB = 3.3 V 5% VOH VOL ZOUT Output High Voltage Output Low Voltage Output Impedance 14 - 17 2.4 0.4 V V IOH = -24 mA IOL = 24 mA LVCMOS for VDD = 3.3 V 5%, VDDOA = 2.5 V 5%, VDDOB = 2.5 V 5% VOH VOL ZOUT Output High Voltage Output Low Voltage Output Impedance 18 - 22 1.9 0.4 V V IOH = -15 mA IOL = 15 mA 1. Inputs have pull-down resistors affecting the input current. 272 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9850 Table 11. AC Characteristics (VDD = 3.3 V 5%, VDDOA = 3.3 V 5%, VDDOB = 3.3 V 5%, TA = -40C to +85C)1 2 Symbol fref Characteristics Input Reference Frequency (25 MHz input) Input Reference Frequency (33 MHz input) XTAL Input Input Reference Frequency in PLL Bypass Mode3 fVCO fMCX VCO Frequency Range Output Frequency 4 Min Typ 25 33 25 Max Unit MHz MHz MHz MHz MHz Condition Input and Output Timing Specification 250 2000 PLL bypass Bank A Output Bank B output Bank C output 15.87 15.87 50 2 200 200 500 MHz MHz MHz ns PLL locked frefPW frefCcc tr, tf DC Reference Input Pulse Width Input Frequency Accuracy Output Rise/Fall Time Output Duty Cycle 100 150 47.5 45 50 50 500 52.5 55 1 10 10 10 ppm ns % 20% to 80% 3.3 V operation 2.5 V operation PLL Specifications BW tLOCK treset_ref treset_pulse tsk(O) tsk(O) tJIT(CC) tJIT(PER) tJIT() 1. 2. 3. 4. 5. PLL Closed Loop Bandwidth5 Maximum PLL Lock Time MR Hold Time on Power Up MR Hold Time MHz ms ns ns Skew and Jitter Specifications Output-to-Output Skew (within a bank) Output-to-Output Skew (across banks A and B) Cycle-to-cycle jitter Period Jitter I/O Phase Jitter RMS (1 ) 50 100 100 80 100 80 15 15 ps ps ps ps ps VDDOA = 3.3 V VDDOB = 3.3 V Bank A and B Back C Bank A and B Back C Bank A and B Back C AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9850 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = (fVCO / M) N. -3 dB point of PLL transfer characteristics. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 273 MPC9850 Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 100 RT = 50 VTT DUT MPC9850 Figure 4. MPC9850 AC Test Reference (LVDS Outputs) Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT DUT MPC9850 RT = 50 VTT Figure 5. MPC9850 AC Test Reference (LVCMOS Outputs) 274 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9850 Table 12. MPC9850 Pin Diagram (Top View) 1 A B C D E F G H J K VDDOA VDDOA RSVD VDDA REF_SEL PCLK REF_CLK_SEL XTAL_IN VDDOB VDDOB 2 VDDOA VDDOA RSVD VDDA CLK PCLK REF_33MHz XTAL_OUT VDDOB VDDOB 3 CLKA[1] CLKA[0] VDD VDD VDD VDD VDD VDD CLKB[0] CLKB[1] 4 CLKA[3] CLKA[2] VDD GND GND GND GND VDD CLKB[2] CLKB[3] 5 CLKA[5] CLKA[4] VDD GND GND GND GND VDD CLKB[4] CLKB[5] 6 VDD QA0 VDD GND GND GND GND VDD QB0 VDD 7 QA1 VDDOA VDD GND GND GND GND VDD VDDOB QB1 8 QA2 QA3 VDD VDD VDD VDD VDD VDD QB3 QB2 9 VDDOA VDDOA VDD QC0 VDDOC QC1 PLL_BYPASS RIO_C[1] VDDOB VDDOB 10 VDDOA VDDOA REF_OUT QC0 GND QC1 MR RIO_C[0] VDDOB VDDOB Table 13. MPC9850 Pin List Signal VDDOA VDDOA CLKA[1] CLKA[3] CLKA[5] VDD QA1 QA2 VDDOA VDDOA VDDOA VDDOA CLKA[0] CLKA[2] CLKA[4] QA0 VDDOA QA3 VDDOA VDDOA 100 Pin MAPBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Signal RSVD1 RSVD VDD VDD VDD VDD VDD VDD VDD REF_OUT VDDA VDDA VDD GND GND GND GND VDD QC0 QC0 1 100 Pin MAPBGA C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Signal REF_SEL CLK VDD GND GND GND GND VDD VDDOC GND PCLK PCLK VDD GND GND GND GND VDD QC1 QC1 100 Pin MAPBGA E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Signal REF_CLK_SEL REF_33MHz VDD GND GND GND GND VDD PLL_BYPASS MR XTAL_IN XTAL_OUT VDD VDD VDD VDD VDD VDD RIO_C[1] RIO_C[0] 100 Pin MAPBGA G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 Signal VDDOB VDDOB CLKB[0] CLKB[2] CLKB[4] QB0 VDDOB QB3 VDDOB VDDOB VDDOB VDDOB CLKB[1] CLKB[3] CLKB[5] VDD QB1 QB2 VDDOB VDDOB 100 Pin MAPBGA J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 1. RSVD pins must be left open. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 275 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9855 Rev 1, 07/2004 Preliminary Information Clock Generator for PowerQUICC and PowerPC Microprocessors The MPC9855 is a PLL based clock generator specifically designed for Motorola Microprocessor and Microcontroller applications including the PowerPC and PowerQUICC. This device generates a microprocessor input clock. The microprocessor clock is selectable in output frequency to any of the commonly used microprocessor input and bus frequencies. The device offers eight low skew clock outputs in two banks, each configurable to support different clock frequencies. The extended temperature range of the MPC9855 supports telecommunication and networking requirements. Features * 8 LVCMOS outputs for processor and other circuitry * Crystal oscillator or external reference input * 25 or 33 MHz Input reference frequency * Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66, 50, 33, or 16 MHz * Buffered reference clock output (2 copies) * Low cycle-to-cycle and period jitter * 100-lead PBGA package * 100-lead Pb-free Package Available * 3.3 V supply with 3.3 V or 2.5 V LVCMOS output supplies * Supports computing, networking, telecommunications applications * Ambient temperature range -40C to +85C * 100-lead PBGA package * 100-lead Pb-free Package Available MPC9855 MICROPROCESSOR CLOCK GENERATOR SCALE 2:1 VF SUFFIX VM SUFFIX (Pb-FREE) 100 MAPBGA PACKAGE CASE 1462-01 Functional Description The MPC9855 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60, or 120 to produce output frequencies of 200, 166, 133, 125, 111, 100, 83, 66, 50, 33, or 16 MHz. The single-ended LVCMOS outputs provide 8 low skew outputs for use in driving a microprocessor or microcontroller clock input as well as other system components. The input reference, either crystal or external input is also buffered to a separate dual outputs that my be used as the clock source for a Ethernet PHY if desired. The reference clock may be provided by either an external clock input of 25 or 33 MHz. An internal oscillator requiring a 25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or external clock input is selected via the input pin of XTAL_SEL. Other than the crystal, no external components are required for crystal oscillator operation. The REF_33 MHz configuration pin is used to select between a 33 and 25 MHz input frequency. The MPC9855 is packaged in a 100 lead MAPBGA package to optimize both performance and board density. 276 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9855 CLK PCLK PCLK CLK_SEL XTAL_IN XTAL_OUT XTAL_SEL 0 1 0 Ref 1 PLL OSC 2000 MHz 1 /N 0 QA1 QA2 QA3 /N QB0 QB1 QB2 QB3 QA0 PLL_BYPASS REF_33 MHz CLK_A[0:5] CLK_B[0:5] REF_OUT0 MR REF_OUT1 REF_OUT1_E Figure 1. MPC9855 Logic Diagram FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 277 MPC9855 Table 1. Pin Configurations Pin CLK PCLK, PCLK QA0, QA1, QA2, QA3 QB0, QB1, QB2, QB3 REF_OUT0 REF_OUT1 XTAL_IN XTAL_OUT CLK_SEL XTAL_SEL REF_33 MHz REF_OUT1_E MR PLL_BYPASS CLK_A[0:5]1 CLK_B[0:5]1 VDD VDDA VDDOA VDDOB GND I/O Input Input Output Type Function Supply VDD VDD VDDOA Active/State -- -- -- LVCMOS PLL reference clock input (pull-down) LVPECL PLL reference clock input (PCLK -- pull-down, PCLK -- pull-up and pull-down) LVCMOS Clock Outputs Output Input Output Input Input Input Input Input Input Input Input -- -- -- -- -- LVCMOS Reference Output (25 MHz or 33 MHz) LVCMOS Crystal Oscillator Input Pin LVCMOS Crystal Oscillator Output Pin LVCMOS Select between CLK and PCLK input (pull-down) LVCMOS Select between External Input and Crystal Oscillator Input (pull-down) LVCMOS Selects 33MHz input (pull-down) LVCMOS Enables REF_OUT! output (pull-down) LVCMOS Master Reset (pull-up) LVCMOS Select PLL or static test mode (pull-up) LVCMOS Configures Bank A clock output frequency (pull-up) LVCMOS Configures Bank B clock output frequency (pull-up) -- -- -- -- -- 3.3 V Supply Analog Supply Output Supply -- Bank A Output Supply -- Bank B Ground VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD -- -- -- -- -- -- -- -- High High High High Low High -- -- -- -- -- -- -- 1. Power PC bit ordering (bit 0 = msb, bit 5 = lsb). Table 2. Function Table Control CLK_SEL XTAL_SEL PLL_BYPASS REF_OUT1_E REF_33 MHz MR Default 0 0 0 0 0 1 0 CLK CLKx Normal Disables REF_OUT1 Selects 25 MHz Reference Reset 1 PCLK XTAL Bypass Enables REF_OUT1 Selects 33 MHz Reference Normal CLK_A and CLK_B control output frequencies. Refer to Table 3 for specific device configuration 278 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9855 Table 3. Output Configurations (Banks A & B) CLK_x[0:5]1 111111 111100 101000 011110 010100 001111 001100 001010 001001 001000 000111 000110 000101 000100 CLK_x[0] (msb) 1 1 1 0 0 0 0 0 0 0 0 0 0 0 CLK_x[1] 1 1 0 1 1 0 0 0 0 0 0 0 0 0 CLK_x[2] 1 1 1 1 0 1 1 1 1 1 0 0 0 0 CLK_x[3] 1 1 0 1 1 1 1 0 0 0 1 1 1 1 CLK_x[4] 1 0 0 1 0 1 0 1 0 0 1 1 0 0 CLK_x[5] (lsb) 1 0 0 0 0 1 0 0 1 0 1 0 1 0 N 126 120 80 60 40 30 24 20 18 16 15 12 10 82 Frequency (MHz) 15.87 16.67 25.00 33.33 50.00 66.67 83.33 100.00 111.11 125.00 133.33 166.67 200.00 250 1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) 2. Minimum value for N. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 279 MPC9855 OPERATION INFORMATION Output Frequency Configuration The MPC9855 was designed to provide the commonly used frequencies in PowerQUICC, PowerPC and other microprocessor systems. Table 3 lists the configuration values that will generate those common frequencies. The MPC9855 can generate numerous other frequencies that may be useful in specific applications. The output frequency (fout) may be calculated by the following equation. fout = 2000 / N where fout is in MHz and N = 2 * CLK_x[0:5] This calculation is valid for all values of N from 8 to 126. Note that N = 15 is a modified case of the configuration inputs CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to 00111 or 7. Crystal Input Operation TBD Power-Up and MR Operation Figure 2 defines the release time and the minimum pulse length for MR pin. The MR release time is based upon the power supply being stable and within VDD specifications. See Table 10 for actual parameter values. The MPC9855 may be configured after release of reset and the outputs will be stable for use after lock indication is obtained. VDD MR treset_rel treset_pulse Figure 2. MR Operation Power Supply Bypassing The MPC9855 is a mixed analog/digital product. The architecture of the XC9855 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VDD pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VDD 22 F 15 0.1 F VDD MPC9855 VDDA 0.1 F Figure 3. VCC Power Supply Bypass 280 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9855 Table 4. Absolute Maximum Ratings1 Symbol VDD VDDA VDDOA VDDOB VIN VOUT IIN IOUT TS Characteristics Supply Voltage (core) Supply Voltage (Analog Supply Voltage) Supply Voltage (LVCMOS output for Bank A) Supply Voltage (LVCMOS output for Bank B) DC Input Voltage DC Output Voltage2 DC Input Current DC Output Current Storage Temperature -65 Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max 3.8 VDD VDD VDD VDD+0.3 VDDx+0.3 20 50 125 V V mA mA C Unit V V V Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 2. VDDx references power supply pin associated with specific output pin. Table 5. General Specifications Symbol VTT MM HBM CDM LU CIN CPD JC TA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Input Capacitance Power Dissipation Capacitance Thermal Resistance (junction-to-ambient) Ambient Temperature -40 200 2000 500 200 4 10 54.5 85 Min Typ VDD / 2 Max Unit V V V V mA pF pF C/W C Inputs Per Output Air Flow = 0 Condition Table 6. DC Characteristics (TA = -40C to 85C) Symbol Characteristics Min Typ Max Unit Condition Supply Current for VDD = 3.3 V 5%, VDDOA = 3.3 V 5%, = VDDOB = 3.3 V 5% IDD + IDDA Maximum Quiescent Supply Current (Core) + IDDOC IDDA IDDOA IDDOB Maximum Quiescent Supply Current (Analog Supply) Maximum Bank A Supply Current Maximum Bank B Supply Current 100 15 50 50 mA mA mA mA VDD + VDDA + VDDOC pins VDDIN pins VDDOA pins VDDOB pins Supply Current for VDD = 3.3 V 5%, VDDOA = 2.5 V 5%, VDDOB = 2.5 V 5% IDD + IDDA Maximum Quiescent Supply Current (Core) + IDDOC IDDA IDDOA IDDOB Maximum Quiescent Supply Current (Analog Supply) Maximum Bank A Supply Current Maximum Bank B Supply Current 100 15 40 40 mA mA mA mA VDD + VDDA + VDDOC pins VDDIN pins VDDOA pins VDDOA and VDDOB pins FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 281 MPC9855 Table 7. LVPECL DC Characteristics (TA = -40C to 85C)1 Symbol Characteristics Min Typ Max Unit Condition Differential LVPECL clock inputs (CLK1, CLK1) for VDD = 3.3 V 0.5% VPP VCMR Differential Voltage2 (peak-to-peak) Differential Input Crosspoint Voltage3 (LVPECL) (LVPECL) 250 1.0 VDD - 0.6 mV V 1. AC characteristics are design targets and pending characterization. 2. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. Table 8. LVCMOS I/O DC Characteristics (TA = -40C to 85C) Symbol LVCMOS for VDD = 3.3 V 5% VIH VIL IIN Input High Voltage Input Low Voltage Input Current1 2.0 VDD + 0.3 0.8 200 V V A LVCMOS LVCMOS VIN = VDDL or GND Characteristics Min Typ Max Unit Condition LVCMOS for VDD = 3.3 V 5%, VDDOA = 3.3 V 5%, VDDOB = 3.3 V 5% VOH VOL ZOUT Output High Voltage Output Low Voltage Output Impedance 14 - 17 2.4 0.4 V V IOH = -24 mA IOL = 24 mA LVCMOS for VDD = 3.3 V 5%, VDDOA = 2.5 V 5%, VDDOB = 2.5 V 5% VOH VOL ZOUT Output High Voltage Output Low Voltage Output Impedance 18 - 22 1.9 0.4 V V IOH = -15 mA IOL = 15 mA 1. Inputs have pull-down resistors affecting the input current. 282 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9855 Table 9. AC Characteristics (VDD = 3.3 V 5%, VDDOA = 3.3 V 5%, VDDOB = 3.3 V 5%, TA = -40C to +85C)1 2 Symbol fref Characteristics Input Reference Frequency (25 MHz input) Input Reference Frequency (33 MHz input) XTAL Input Input Reference Frequency in PLL Bypass Mode3 fVCO fMCX VCO Frequency Range Output Frequency 4 Min Typ 25 33 25 Max Unit MHz MHz MHz MHz MHz Condition Input and Output Timing Specification 250 2000 PLL bypass Bank A output Bank B output Bank C output 15.87 15.87 50 2 200 200 500 MHz MHz MHz ns PLL locked frefPW frefCcc tr, tf DC Reference Input Pulse Width Input Frequency Accuracy Output Rise/Fall Time Output Duty Cycle 100 150 47.5 45 50 50 500 52.5 55 1 10 10 10 ppm ns % 20% to 80% 3.3 V operation 2.5 V operation PLL Specifications BW tLOCK treset_ref treset_pulse tsk(O) tsk(O) tJIT(CC) tJIT(PER) tJIT() 1. 2. 3. 4. 5. PLL Closed Loop Bandwidth5 Maximum PLL Lock Time MR Hold Time on Power Up MR Hold Time MHz ms ns ns Skew and Jitter Specifications Output-to-Output Skew (within a bank) Output-to-Output Skew (across banks A and B) Cycle-to-cycle jitter Period Jitter I/O Phase Jitter RMS (1 ) 50 100 100 80 100 80 15 15 ps ps ps ps ps VDDOA = 3.3 V VDDOB = 3.3 V Bank A and B Back C Bank A and B Back C Bank A and B Back C AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9855 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = (fVCO / M) N. -3 dB point of PLL transfer characteristics. Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT DUT MPC9855 RT = 50 VTT Figure 4. MPC9855 AC Test Reference (LVCMOS Outputs) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 283 MPC9855 Table 10. MPC9855 Pin Diagram (Top View) 1 A B C D E F G H J K VDDOA VDDOA RSVD VDDA XTAL_SEL PCLK CLK_SEL XTAL_IN VDDOB VDDOB 2 VDDOA VDDOA RSVD VDDA CLK PCLK REF_33MHz XTAL_OUT VDDOB VDDOB 3 CLKA[1] CLKA[0] VDD VDD VDD VDD VDD VDD CLKB[0] CLKB[1] 4 CLKA[3] CLKA[2] VDD GND GND GND GND VDD CLKB[2] CLKB[3] 5 CLKA[5] CLKA[4] VDD GND GND GND GND VDD CLKB[4] CLKB[5] 6 VDD QA0 VDD GND GND GND GND VDD QB0 VDD 7 QA1 VDDOA VDD GND GND GND GND VDD VDDOB QB1 8 QA2 QA3 VDD VDD VDD VDD VDD VDD QB3 QB2 9 VDDOA VDDOA VDD RSVD VDD RSVD PLL_BYPASS RSVD VDDOB VDDOB 10 VDDOA VDDOA REF_OUT[0] REF_OUT[1] GND RSVD MR REF_OUT1E VDDOB VDDOB Table 11. MPC9855 Pin List Signal VDDOA VDDOA CLKA[1] CLKA[3] CLKA[5] VDD QA1 QA2 VDDOA VDDOA VDDOA VDDOA CLKA[0] CLKA[2] CLKA[4] QA0 VDDOA QA3 VDDOA VDDOA 100 Pin MAPBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Signal RSVD RSVD VDD VDD VDD VDD VDD VDD VDD REF_OUT[0] VDDA VDDA VDD GND GND GND GND VDD RSVD REF_OUT[1] 100 Pin MAPBGA C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Signal XTAL_SEL CLK VDD GND GND GND GND VDD VDD GND PCLK PCLK VDD GND GND GND GND VDD RSVD RSVD 100 Pin MAPBGA E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Signal CLK_SEL REF_33MHz VDD GND GND GND GND VDD PLL_BYPASS MR XTAL_IN XTAL_OUT VDD VDD VDD VDD VDD VDD RSVD REF_OUT1E 100 Pin MAPBGA G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 Signal VDDOB VDDOB CLKB[0] CLKB[2] CLKB[4] QB0 VDDOB QB3 VDDOB VDDOB VDDOB VDDOB CLKB[1] CLKB[3] CLKB[5] VDD QB1 QB2 VDDOB VDDOB 100 Pin MAPBGA J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 284 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Chapter Four Failover or Redundant Clock Data Sheets Failover or Redundant Clock Device Index Device Number Page Device Number Page MPC9892 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 MPC9893 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 MPC9894 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 MPC9895 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 MPC9993 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 MPC99J93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 285 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9892 Rev 0, 12/2002 Product Preview Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC9892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 4x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance. Features * * * * * * * Fully Integrated PLL Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3 V Operation 32-Lead LQFP Packaging SiGe technology supports near-zero output skew MPC9892 FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC9892 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section). PLL_En Clk_Selected Inp1bad Inp0bad Man_Override Alarm_Reset Sel_Clk CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR OR Dynamic Switch Logic Qb0 Qb0 Qb1 Qb1 /4 PLL 800 - 1600 MHz /16 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 Figure 1. Block Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. 286 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9892 Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 18 VCC 24 Qa1 Qa1 Qa0 Qa0 VCC VCC_PLL Man_Override PLL_En 25 26 27 28 29 30 31 32 1 23 22 21 20 19 VCC 17 16 15 14 VCC Inp0bad Inp1bad Clk_Selected GND Ext_FB Ext_FB GND 13 12 11 10 9 8 Pin Definition GND MPC9892 2 3 4 5 6 7 Alarm_Reset MR CLK0 CLK0 CLK1 Figure 2. 32-Lead Pinout (Top View) Table 1. Pin Descriptions Pin Name CLK0, CLK0 CLK1, CLK1 Ext_FB, Ext_FB Qa0:1, Qa0:1 Qb0:2, Qb0:2 Inp0bad Inp1bad Clk_Selected Alarm_Reset Sel_Clk Manual_Override PLL_En MR VCCA VCC GNDA GND I/O LVPECL Input LVPECL Input LVPECL Input LVPECL Output LVPECL Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input Power Supply Power Supply Power Supply Power Supply Differential PLL clock reference (CLK0 pulldown, CLK0 pullup) Differential PLL clock reference (CLK1 pulldown, CLK1 pullup) Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup) Differential 1x output pairs Differential 4x output pairs Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted `0' if clock 0 is selected, `1' if clock 1 is selected `0' will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is "one-shotted" (50 k pullup) `0' selects CLK0, `1' selects CLK1 (50 k pulldown) `1' disables internal clock switch circuitry (50 k pulldown) `0' bypasses selected input reference around the phase-locked loop (50 k pullup) `0' resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50 k pullup) PLL power supply Digital power supply PLL Digital ground FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Sel_Clk CLK1 287 MPC9892 Table 2. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. General Specifications Symbol VTT MM HBM CDM LU CIN JA Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model Latch-up Immunity Input Capacitance Thermal resistance junction to ambient JESD 51-3, single layer test board TBD TBD TBD 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 JC Thermal resistance junction to case Operating junction temperature1 (continuous operation) MTBF = 9.1 years 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 110 Min Typ VCC - 2 Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board 1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6226 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6226 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. 288 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9892 Table 4. DC Characteristics (VCC = 3.3 V 5%, TA = -40 to +85C)1 Symbol Characteristics Min Typ Max Unit Condition LVCMOS control inputs (OE, FSEL0, FSEL1, MR) VIL VIH IIN Input Voltage Low Input Voltage High Input Current2 2.0 TBD 0.8 V V A VIN = VCC or VIN = GND LVPECL clock inputs (CLK, CLK)3 VPP VCMR VIH VIL IIN AC Differential Input Voltage4 Differential Cross Point Voltage5 Input High Voltage Input Low Voltage Input Current 0.1 1.0 TBD TBD 1.3 VCC-0.3 TBD TBD TBD A VIN = TBD or VIN = TBD V V Differential operation Differential operation LVPECL clock outputs (QA0-4, QA0-4, QB0-4, QB0-4) VOH VOL Output High Voltage Output Low Voltage TBD TBD VCC-1.005 VCC-1.705 TBD TBD V V Termination 50 to VTT Termination 50 to VTT ICC ICCA 1. 2. 3. 4. 5. Maximum Power Supply Maximum PLL Power Supply VCC pins VCC_PLL pin TBD TBD mA mA AC characterisitics are design targets and pending characterization. Input have internal pullup/pulldown resistors which affect the input current. Clock inputs driven by LVPECL compatible signals. VPP is the minimum differential input voltage swing required to maintain AC characteristic. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 289 MPC9892 Table 5. AC Characteristics (TA = -40C to 85C, VCC = 3.3 V 5%)1 Symbol fVCO tpwi tpd VPP VCMR tr/tf tskew pe per/cycle PLL VCO Lock Range Input Pulse Width Propagation Delay2 Differential Input Voltage Differential Input Crosspoint Voltage Output Rise/Fall Time Output Skew Maximum Phase Error Deviation Within Bank All Outputs CLKn to Q (Bypass) CLKn to Ext_FB (Locked3) (peak-to-peak) 0.3 Parameter Min 800 25 Typ Max 1600 75 TBD TBD 1.3 VCC-0.3 TBD 35 50 TBD4 TBD5 Rate of Change of Periods 75 MHz Output2, 4 300 MHz Output 2, 4 Unit MHz % ns ps V V ps ps ps 75 MHz Output2, 4 300 MHz Output2, 4 tpw tjitter tlock 1. 2. 3. 4. Output Duty Cycle Cycle-to-Cycle Jitter, Standard Deviation (RMS)2 Maximum PLL Lock Time 45 20 10 200 100 50 25 400 200 55 20 10 ps/cycle % ps ms PECL output termination is 50 ohms to VCC - 2.0 V. Guaranteed, not production tested. Static phase offset between the selected reference clock and the feedback signal. Specification holds for a clock switch between two signals no greater than 400 ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. (See Applications Information for more detail) 5. Specification holds for a clock switch between two signals no greater than out of phase. Delta period change per cycle is averaged over the clock switch excursion. 290 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9892 APPLICATIONS INFORMATION The MPC9892 is a dual clock PLL with on-chip Intelligent Dynamic Clock Switch (IDCS) circuitry. Definitions primary clock: The input CLK selected by Sel_Clk. secondary clock: The input CLK NOT selected by Sel_Clk. PLL reference signal: The CLK selected as the PLL reference signal by Sel_Clk or IDCS. (IDCS can override Sel_Clk). Status Functions Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as the PLL reference signal. Clk_Selected (H) indicates CLK1 is selected as the PLL reference signal. INP_BAD: Latched (H) when it's CLK is stuck (H) or (L) for at least one Ext_FB period (Pos to Pos or Neg to Neg). Cleared (L) on assertion of Alarm_Reset. Control Functions Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock. Alarm_Reset: Asserted by a negative edge. Generates a one-shot reset pulse that clears INPUT_BAD latches and Clk_Selected latch. PLL_En: While (L), the PLL reference signal is substituted for the VCO output. MR: While (L), internal dividers are held in reset which holds all Q outputs LOW. Man Override (H) (IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be the CLK selected by Sel_Clk. The status function INP_BAD is active in Man Override (H) and (L). Man Override (L) (IDCS is enabled, PLL functions enhanced). The first CLK to fail will latch it's INP_BAD (H) status flag and select the other input as the Clk_Selected for the PLL reference clock. Once latched, the Clk_Selected and INP_BAD remain latched until assertion of Alarm_Reset which clears all latches (INP_BADs are cleared and Clk_Selected = Sel_Clk). NOTE: If both CLKs are bad when Alarm_Reset is asserted, both INP_BADs will be latched (H) after one Ext_FB period and Clk_Selected will be latched (L) indicating CLK0 is the PLL reference signal. While neither INP_BAD is latched (H), the Clk_Selected can be freely changed with Sel_Clk. Whenever a CLK switch occurs, (manually or by IDCS), following the next negative edge of the newly selected PLL reference signal, the next positive edge pair of Ext_FB and the newly selected PLL reference signal will slew to alignment. To calculate the overall uncertainty between the input CLKs and the outputs from multiple MPC9892's, the following procedure should be used. Assuming that the input CLKs to all MPC9892's are exactly in phase, the total uncertainty will be the sum of the static phase offset, max I/O jitter, and output to output skew. During a dynamic switch, the output phase between two devices may be increased for a short period of time. If the two input CLKs are 400 ps out of phase, a dynamic switch of an MPC9892 will result in an instantaneous phase change of 400 ps to the PLL reference signal without a corresponding change in the output phase (due to the limited response of the PLL). As a result, the I/O phase of a device, undergoing this switch, will initially be 400 ps and diminish as the PLL slews to its new phase alignment. This transient timing issue should be considered when analyzing the overall skew budget of a system. Hot Insertion and Withdrawal In PECL applications, a powered up driver will experience a low impedance path through an MPC9892 input to its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input pins to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input signals. Acquiring Frequency Lock 1. While the MPC9892 is receiving a valid CLK signal, assert Man_Override HIGH. 2. The PLL will phase and frequency lock within the specified lock time. 3. Apply a HIGH to LOW transition to Alarm_Reset to reset Input Bad flags. 4. De-assert Man_Override LOW to enable Intelligent Dynamic Clock Switch mode. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 291 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9893 Rev 4, 08/2004 3.3V 1:10 LVCMOS PLL Clock Generator The MPC9893 is a 2.5V and 3.3V compatible, PLL based intelligent dynamic clock switch and generator specifically designed for redundant clock distribution systems. The device receives two LVCMOS clock signals and generates 12 phase aligned output clocks. The MPC9893 is able to detect a failing reference clock signal and to dynamically switch to a redundant clock signal. The switch from the failing clock to the redundant clock occurs without interruption of the output clock signal (output clock slews to alignment). The phase bump typically caused by a clock failure is eliminated. The device offers 12 low skew clock outputs organized into two output banks, each configurable to support the different clock frequencies. The extended temperature range of the MPC9893 supports telecommunication and networking requirements. The device employs a fully differential PLL design to minimize jitter. Features * 12-output LVCMOS PLL clock generator * 2.5V and 3.3V compatible * IDCS - on-chip intelligent dynamic clock switch * Automatically detects clock failure * Smooth output phase transition during clock failover switch * 7.5 - 200 MHz output frequency range * LVCMOS compatible inputs and outputs * External feedback enables zero-delay configurations * Supports networking, telecommunications and computer applications * Output enable/disable and static test mode (PLL bypass) * Low skew characteristics: maximum 50 ps output-to-output (within bank) * 48-lead LQFP package * 48-lead Pb-free package available * Ambient operating temperature range of -40 to 85C MPC9893 LOW VOLTAGE 2.5V AND 3.3V IDCS AND PLL CLOCK GENERATOR SCALE 2:1 FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932-03 Functional Description The MPC9893 is a 3.3V or 2.5V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by one, two, three, four or eight. The frequency-multiplied clock drives six bank A outputs. Six bank B outputs can run at either the same frequency than bank A or at half of the bank A frequency. Therefore, bank B outputs additionally support the frequency multiplication of the input reference clock by 3/2 and 1/2. Bank A and bank B outputs are phase-aligned(1). Due to the external PLL feedback, the clock signals of both output banks are also phase-aligned1 to the selected input reference clock, providing virtually zero-delay capability. The integrated IDCS continuously monitors both clock inputs and indicates a clock failure individually for each clock input. When a false clock signal is detected, the MPC9893 switches to the redundant clock input, forcing the PLL to slowly slew to alignment and not produce any phase bumps at the outputs. Both clock inputs are interchangeable, also supporting the switch to a failed clock that was restored. The MPC9893 also provides a manual mode that allows for user-controlled clock switches. The PLL bypass of the MPC9893 disables the IDCS and PLL-related specifications do not apply. In PLL bypass mode, the MPC9893 is fully static in order to distribute low-frequency clocks for system test and diagnosis. Outputs of the MPC9893 can be disabled (high-impedance tristate) to isolate the device from the system. Applying output disable also resets the MPC9893. On power-up this reset function needs to be applied for correct operation of the circuitry. Please see the application section for power-on sequence recommendations. The device is packaged in a 7x7 mm2 48-lead LQFP package. 1. At coincident rising edges. 292 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9893 QA0 CLK0 CLK1 FB REF_SEL MAN/A ALARM_RST (PULLDOWN) (PULLDOWN) (PULLDOWN) 0 Ref 1 PLL 200 - 400 MHz FB IDCS (PULLDOWN) (PULLUP) (PULLUP) 0 1 D Q QA1 QA2 QA3 QA4 QA5 QB0 QB1 D Q QB2 QB3 PLL_EN FSEL[0:3] (PULLDOWN) (PULLDOWN) DATA GENERATOR D Q QB4 QB5 QFB ALARM0 ALARM1 OE/MR (PULLDOWN) CLK_IND Figure 1. MPC9893 Logic Diagram ALARM_RST REF_SEL PLL_EN FSEL0 FSEL1 FSEL2 FSEL3 GND GND VCC GND QA0 QA1 VCC GND QA2 QA3 VCC GND QA4 QA5 VCC 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 39 40 41 42 43 44 45 46 47 48 1 2 QFB 3 FB 4 MAN/A 5 VCC 6 CLK0 7 CLK1 8 VCC_PLL 23 22 21 20 19 18 17 16 15 14 13 9 10 11 12 CLK_IND ALARM0 ALARM1 GND VCC OE GND QB0 QB1 VCC GND QB2 QB3 VCC GND QB4 QB5 VCC It is recommended to use an external RC filter for the analog power supply pin VCC_PPL. Please see application section for details. MPC9893 Figure 2. MPC9893 48-Lead Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GND 293 MPC9893 Table 1. Pin Configurations Number CLK0, CLK1 FB REF_SEL MAN/A ALARM_RST PLL_EN FSEL[0:3] OE/MR QA[0:5] QB[0:5] QFB ALARM0 ALARM1 CLK_IND GND VCC_PLL Name Input Input Input Input Input Input Input Input Output Output Output Output Output Output Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC PLL reference clock inputs PLL feedback signal input, connect directly to QFB output Selects the primary reference clock Selects automatic switch mode or manual reference clock selection Reset of alarm flags and selected reference clock Select PLL or static test mode Clock frequency selection and configuration of clock divider modes Output enable/disable and device reset Bank A clock outputs Bank B clock outputs Clock feedback output. QFB must be connected to FB for correct operation Indicates clock failure on CLK0 Indicates clock failure on CLK1 Indicates currently selected input reference clock Negative power supply Positive power supply for the PLL (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see the application section for details. Positive power supply for I/O and core Description VCC Supply VCC Table 2. Function Table Control Inputs PLL_EN 0 PLL enabled. The input to output frequency relationship is that according to Table 3 if the PLL is frequency locked. PLL bypassed and IDCS disabled. The VCO output is replaced by the reference clock signal fref. The MPC9893 is in manual mode. Default 0 1 MAN/A 1 Manual clock switch mode. IDCS disabled. Clock failure Automatic clock switch mode. IDCS enabled. Clock failure detection and output flags ALARM0, ALARM1, CLK_IND are detection and output flags ALARM0, ALARM1, CLK_IND are enabled. enabled. IDCS overrides REF_SEL on a clock failure. IDCS operation requires PLL_EN = 0. ALARM0, ALARM1 and CLK_IND flags are reset: ALARM0=H, ALARM1=H and CLK_IND=REF_SEL. ALARM_RST is a one-shot function. Selects CLK0 as the primary clock source ALARM0, ALARM1 and CLK_IND active ALARM_RST 1 REF_SEL FSEL[0:3] OE/MR 0 0000 0 Selects CLK1 as the secondary clock source See Table 3 Outputs enabled (active) Outputs disabled (high impedance tristate), reset of data generators and output dividers. The MPC9893 requires reset at power-up and after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than two reference clock cycles (CLK0,1). OE/MR does not tristate the QFB output. Outputs (ALARM0, ALARM1, CLK_IND are valid if PLL is locked) ALARM0 ALARM1 CLK_IND CLK0 failure CLK1 failure CLK0 is the reference clock CLK1 is the reference clock 294 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9893 Table 3. Clock Frequency Configuration Name M8 M82 M4 M42 M3 M32 M2M M22M M2H M22H M1L M12L M1M M12M M1H M12H FSEL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSEL1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSEL2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSEL3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fREF range [MHz] 15-25 QAx Ratio fREF * 8 fREF * 4 fREF * 3 fREF * 2 fREF * 2 fREF fREF fREF fQAX [MHz] 120-200 Ratio fREF * 8 fREF * 4 fREF * 4 fREF * 2 fREF * 3 fREF * 3 / 2 fREF * 2 fREF fREF * 2 fREF fREF fREF / 2 fREF fREF / 2 fREF fREF / 2 QBx fQBX[MHz] 120-200 60-100 120-200 60-100 120-200 60-100 60-100 30-50 120-200 60-100 15-25 7.5-12.5 30-50 15-25 60-100 30-50 QFB fREF fREF fREF fREF fREF fREF fREF fREF FB1 16 30-50 120-200 8 40-66.6 120-200 6 30-50 60-100 8 60-100 120-200 4 15-25 15-25 16 30-50 30-50 8 60-100 60-100.0 4 1. FB: Internal PLL feedback divider Table 4. General Specifications Symbol VTT MM HBM CDM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 1500 200 10 4.0 Min Typ VCC / 2 Max Unit V V V V mA pF pF Per output Inputs Condition Table 5. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 295 MPC9893 Table 6. DC Characteristics (VCC = 3.3V 5%, TA = -40 to 85C) Symbol VIH VIL VOH VOL ZOUT IIN ICC_PLL ICC VTT Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current Maximum PLL Supply Current Maximum Quiescent Supply Current Output Termination Voltage VCC/2 2.0 14-17 200 5.0 4.0 2.4 0.55 0.30 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V V V A mA mA V VIN=VCC or GND VCC_PLL Pin All VCC Pins Condition LVCMOS LVCMOS IOH=-24 mA1 IOL= 24 mA IOL= 12 mA 1. The MPC9893 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. Table 7. DC Characteristics (VCC = 2.5V 5%, TA = -40 to 85C) Symbol VIH VIL VOH VOL ZOUT IIN ICC_PLL ICC VTT Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current Maximum PLL Supply Current Maximum Quiescent Supply Current Output Termination Voltage VCC/2 2.0 17-20 200 5.0 4.0 1.8 0.6 Min 1.7 Typ Max VCC + 0.3 0.7 Unit V V V V A mA mA V VIN=VCC or GND VCC_PLL Pin All VCC Pins Condition LVCMOS LVCMOS IOH=-15 mA1 IOL= 15 mA 1. The MPC9893 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50W series terminated transmission lines per output. 296 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9893 Table 8. AC Characteristics (VCC = 3.3V 5% or VCC = 2.5V 5%, TA = -40 to 85C)1 Symbol fref Input Frequency FSEL=000x FSEL=001x FSEL=010x FSEL=011x FSEL=100x FSEL=101x FSEL=110x FSEL=111x Maximum Output Frequency FSEL=000x FSEL=001x FSEL=010x FSEL=011x FSEL=100x FSEL=101x FSEL=110x FSEL=111x Reference Input Duty Cycle CLK0, 1 Input Rise/Fall Time Propagation Delay (static phase offset, CLKx to FB) VCC=3.3V5% and FSEL[0:2]=111 VCC=3.3V5% VCC=2.5V5% and FSEL[0:2]=111 VCC=2.5V5% Rate of Period Change (phase slew rate) QAx outputs QBx outputs (FSEL=xxx0) QBx outputs (FSEL=xxx1) Output-to-Output Skew2 (within bank) (bank-to-bank) (any output to QFB) 45 0.1 50 -60 -200 -125 -400 60.0 60.0 60.0 30.0 60.0 7.5 15.0 30.0 40 200.0 200.0 200.0 100.0 200.0 25.0 50.0 100.0 60 1.0 +50 +100 +25 +100 150 150 300 150 100 125 55 1.0 10 10 FSEL3=0 FSEL3=1 FSEL3=0 FSEL3=1 RMS (1 ) RMS (1 ) RMS (1 ) RMS (1 ) FSEL=111x 0.8-4.0 10 225 425 150 250 40 50 55 70 MHz MHz MHz MHz MHz MHz MHz MHz % ns ps ps ps ps Failover switch ps/cycle 0.8 to 2.0V PLL locked 15.0 30.0 40.0 30.0 60.0 15.0 30.0 60.0 25.0 50.0 66.6 50.0 100.0 12.5 50.0 100.0 MHz MHz MHz MHz MHz MHz MHz MHz PLL locked Characteristics Min Typ Max Unit Condition PLL locked fMAX frefDC tr, tf t() t tsk(O) ps ps ps % ns ns ns ps ps ps ps ps ps ps ps MHz ms See applications section See applications section See applications section 0.55 to 2.4V DCO tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle Jitter3 Period Jitterc I/O Phase Jitter4 FB=4: FSEL[0:2]=100 or 111 FB=6: FSEL[0:2]=010 FB=8: FSEL[0:2]=001, 011, or 110 FB=16: FSEL[0:2]=000 or 101 PLL Closed Loop Bandwidth5 Maximum PLL Lock Time BW tLOCK 1. 2. 3. 4. AC characteristics apply for parallel output termination of 50 to VTT. See application section for part-to-part skew calculation. Cycle-to-cycle and period jitter depend on the VCO frequency and output configuration. See the application section. I/O jitter depends on the VCO frequency and internal PLL feedback divider FB. See FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 297 MPC9893 APPLICATIONS INFORMATION Definitions IDCS: Intelligent Dynamic Clock Switch. The IDCS monitors both primary and secondary clock signals. Upon a failure of the primary clock signal, the IDCS switches to a valid secondary clock signal and status flags are set. Reference clock signal fref: The clock signal that is selected by the IDCS or REF_SEL as the input reference to the PLL. Manual mode: The reference clock frequency is selected by REF_SEL. Automatic mode: The reference clock frequency is determined by the internal IDCS logic. Primary clock: The input clock signal selected by REF_SEL. The primary clock may or may not be the reference clock, depending on switch mode and IDCS status. Secondary clock: The input clock signal not selected by REF_SEL Selected clock: The CLK_IND flag indicates the reference clock signal: CLK_IND = 0 indicates CLK0 is the clock reference signal, CLK_IND =1 indicates CLK1 is the reference clock signal. Clock failure: A valid clock signal that is stuck (high or low) for at least one input clock period. The primary clock and the secondary clock is monitored for failure. Valid clock signals must be within the AC and DC specification for the input reference clock. A loss of clock is detected if as well as the loss of both clocks. In the case of both clocks lost, the MPC9893 will set the alarm flags and the PLL will stall. The MPC9893 does not monitor and detect changes in the input frequency. Automatic Mode and IDCS Commanded Clock Switch MAN/A = 1, IDCS enabled: Both primary and secondary clocks are monitored. The first clock failure is reported by its ALARMx status flag (clock failure is indicated by a logic low). The ALARMx status is flag latched and remains latched until reset by assertion of ALARM_RST. If the clock failure occurs on the primary clock, the IDCS attempts to switch to the secondary clock. The secondary clock signal needs to be valid for a successful switch. Upon a successful switch, CLK_IND indicates the reference clock, which may now be different as that originally selected by REF_SEL. Manual Mode MAN/A = 0, IDCS disabled: PLL functions normally and both clocks are monitored. The reference clock signal will always be the clock signal selected by REF_SEL and will be indicated by CLK_IND. Clock Output Transition A clock switch, either in automatic or manual mode, follows the next negative edge of the newly selected reference clock signal. The feedback and newly selected reference clock edge will start to slew to alignment at the next positive edge of both signals. Output runt pulses are eliminated. Reset ALARM_RST is asserted by a negative edge. It generates a one-shot reset pulse that clears both ALARMx latches and the CLK_IND latch. If both CLK0 and CLK1 are invalid or fail when ALARM_RST is asserted, both ALARMx flags will be latched after one FB signal period and CLK_IND will be latched (L) indicating CLK0 is the reference signal. While neither ALARMx flag is latched (ALARMx = H), the CLK_IND can be freely changed with REF_SEL. OE/MR: Reset the data generator and output disable. Does not reset the IDCS flags. Acquiring Frequency Lock at Startup 1. On startup, OE/MR must be asserted to reset the output dividers. The IDCS should be disabled (MAN/A=0) during startup to select the manual mode and the primary clock. 2. The PLL will attempt to gain lock if the primary clock is present on startup. PLL lock requires the specified lock time. 3. Applying a high to low transition to ALARM_RST will clear the alarm flags. 4. Enable the IDCS (MAN/A=1) to enable to IDCS. Power Supply Filtering The MPC9893 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9893 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9893. Figure 3 illustrates a typical power supply filter scheme. The MPC9893 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 2 mA (5 mA maximum), assuming that a minimum of 2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 3 must have a resistance of 9-10 to meet the voltage drop criteria. 298 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9893 RF = 5-15 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9893 TCLKCommon VCC 33...100 nF QFBDevice 1 --t(y) tPD,LINE(FB) This maximum timing uncertainty consist of four components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: tJIT() +tSK(O) +t() Figure 3. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9893 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9893 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9893. Designs using the MPC9893 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9893 clock driver allows for its use as a zero delay buffer. The the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC9893 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9893 are connected together, the maximum overall timing uncertainty from the common CLK0 or CLK1 input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF Any QDevice 1 QFBDevice2 tJIT() Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 4. MPC9893 Max. Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 9. Table 9. Confidence Factor CF CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from the common clock input to any MPC9893 output of -275 ps to +265 ps relative to the reference clock input CLK0/1: tSK(PP) = [-60ps...50ps] + [-125ps...125ps] + [(30ps -3)...(30ps 3)] + tPD, LINE(FB) tSK(PP) = [-275ps...265ps] + tPD, LINE(FB) fref=100 MHz, VCC=3.3V fVCO=400 MHz, FSEL[0:2]=111 Example configuration: FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 299 MPC9893 The I/O (Phase) jitter of the MPC9893 depends on the internal VCO frequency and the PLL feedback divider configuration. A high internal VCO frequency and a low PLL feedback divider result in lower I/O jitter than the jitter limits in the AC characteristics (Table 8). When calculating the part-to-part skew, Table 10 should be used to determine the actual VCO frequency, then use Figure 5 to determine the maximum I/O jitter for the specific VCO frequency and divider configuration. In above example calculation, the internal VCO frequency of 400 MHz corresponds to a maximum I/O jitter of 30 ps (RMS). Table 10. Internal VCO Frequency fVCO MPC9893 Configuration M1H, M12H, M2H, M22H M3, M32 M1M, M12M, M2M, M22M, M4, M42 M1L, M12L, M8, M82 fVCO 4 * fref 6 * fref 8 * fref 16 * fref PLL Feedback Divider FB 4 6 8 16 Period Jitter versus Frequency Parameter: Output Configuration 300 250 tjit(per) [ps] 200 150 100 50 0 240 260 280 300 320 340 VCO frequency [MHz] 360 380 400 PSEL=xxx1 PSEL=xxx0 Figure 7. Max. Period Jitter versus VCO Frequency Driving Transmission Lines The MPC9893 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9893 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 8 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9893 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9893 OUTPUT BUFFER IN 14 I/O Phase Jitter versus Frequency Parameter: PLL/Feedback Configuration FB=16: FSEL[0:2]=000, 101 70 60 tjit() [ps] RMS 50 40 30 20 10 0 240 FB=6: FSEL[0:2}=010 FB=4: FSEL[0:2]=100, 111 260 280 300 320 340 VCO frequency [MHz] 360 380 400 FB=8: FSEL[0:2]=001, 011, 110 Figure 5. Max. I/O Phase Jitter versus VCO Frequency The cycle-to-cycle jitter and period jitter of the MPC9893 depend on the output configuration and on the frequency of the internal VCO. Using the outputs of bank A and bank B at the same frequency (FSEL3=0) results in a lower jitter than the split output frequency configuration (FSEL3=1). The jitter also decreases with an increasing internal VCO frequency. Figure 5 to Figure 7 represent the maximum jitter of the MPC9893. Cycle-to-Cycle Jitter versus Frequency Parameter: Output Configuration 500 400 tjit(cc) [ps] 300 200 100 0 240 260 280 PSEL3=1 RS = 36 ZO = 50 OutA MPC9893 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 PSEL3=0 RS = 36 300 320 340 VCO frequency [MHz] 360 380 400 Figure 8. Single versus Dual Transmission Lines Figure 6. Max. Cycle-to-Cycle Jitter versus VCO Frequency 300 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9893 The waveform plots in Figure 9 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9893 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9893. The output waveform in Figure 9 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+17+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 10 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9893 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 10. Optimized Dual Line Termination VOLTAGE (V) Figure 9. Single versus Dual Waveforms MPC9893 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 11. CLK0, CLK1 MPC9893 AC Test Reference for VCC = 3.3V and VCC = 2.5V FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 301 MPC9893 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device FB t() CLK0, CLK1 VCC VCC / 2 GND VCC VCC / 2 GND Figure 12. Output-to-Output Skew tSK(O) Figure 13. Propagation Delay (t(), static phase offset) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the noncontrolled edge, divided by the time between PLL controlled edges, expressed as a percentage FB TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles CCLK0, 1 Figure 14. Output Duty Cycle (DC) Figure 15. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 16. Cycle-to-Cycle Jitter Figure 17. Period Jitter VCC=3.3V 2.4 0.55 tF tR VCC=2.5V 1.8 0.6 Figure 18. Output Transition Time Test Reference 302 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9894 Rev 2, 04/2004 Preliminary Information Quad Input Redundant IDCS Clock Generator The MPC9894 is a differential input and output, PLL-based Intelligent Dynamic Clock Switch (IDCS) and clock generator specifically designed for redundant clock distribution systems. The device receives up to four LVPECL clock signals and generates eight phase-aligned output clocks. The MPC9894 is able to detect failing clock signals and to dynamically switch to a redundant clock signal. The switch from the failing clock to the redundant clock occurs without interruption of the output clock signal (output clock slews to alignment). The phase bump typically caused by a clock failure is eliminated. The device offers eight low-skew clock outputs organized into four output banks, each configurable to support the different clock frequencies. The extended temperature range of the MPC9894 supports telecommunication and networking requirements. Features * 8 differential LVPECL output pairs * Quad-redundancy reference clock inputs * IDCS-on-chip intelligent dynamic clock switch * Smooth output phase transition during clock failover switch/* * Automatically detects clock failures * Clock activity monitor * Clock qualifier inputs * Manual clock select and automatic switch modes * 21.25 - 340 MHz output frequency range * Specified frequency and phase slew rate on clock switch * LVCMOS compatible control inputs and outputs * External feedback enables zero-delay configurations * Output enable/disable and static test mode (PLL bypass) * Low-skew characteristics: maximum 50 ps1 output-to-output * I2C interface for device configuration * Low cycle-to-cycle and period jitter * IEEE 1149.1 JTAG Interface * 100-ball MAPBGA package * Supports 2.5 V or 3.3 V supplies with 2.5 V and 3.3 V I/O * Junction temperature range -40C to +110C MPC9894 QUAD INPUT REDUNDANT IDCS CLOCK GENERATOR VF SUFFIX 100-LEAD MAPBGA PACKAGE CASE 1462-01 Functional Description The MPC9894 is a quad differential redundant input clock generator. The device contains logic for clock failure detection and auto switching for clock redundant applications. The generator uses a fully integrated PLL to generate clock signals from any one of four redundant clock sources. The PLL multiplies the frequency of the input reference clock by one, two, four, eight or divides the reference clock by two or four. The frequency-multiplied clock signal drives four banks of two differential outputs. Each bank allows an individual frequency-divider configuration. All outputs are phase-aligned2 to each other. Due to the external PLL feedback, the clock signals of all outputs are also phase-aligned2 to the selected input reference clock, providing virtually zero-delay capability. The integrated IDCS continuously monitors all four clock inputs and indicates a clock failure for each clock input. When a false clock signal is detected on the active clock, the MPC9894 switches to a redundant clock input, forcing the PLL to slowly slew to alignment and not produce any phase bumps at the outputs. The MPC9894 also provides a manual mode that allows for user-controlled clock switches. The device is packaged in a 11x11 mm2 100-ball MAPBGA package. 1. 2. Final specification subject to change. At coincident rising edges. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 303 MPC9894 DEVICE DESCRIPTION CLK0 CLK0 CLK1 CLK1 CLK2 CLK2 CLK3 CLK3 00 01 10 11 fcomp /P Comp PLL 340 - 680 MHz 1 /2, /4, /8, /16 0 QA0 QA0 QA1 QA1 /2, /4, /8, /16 /P FB /2, /4, /8, /16 IDCS QB0 QB0 QB1 QB1 QC0 QC0 QC1 QC1 FB_IN FB_IN EX_FB_SEL CLK_VALID[3:0] CLK_ALARM_RST /2, /4, /8, /16 PLL_BYPASS SCL SDA ADDR[0:2] MBOOT MEDIA PRESET MR JTAG[4:0] PLL_TST[2:0] TPA MSTROUT_EN Control Logic I2C Interface QD0 QD0 QD1 QD1 /M/P QFB QFB LOCK BUSY INT SEL_STAT[1:0] CLK_STAT[3:0] Figure 1MPC9894 Block Diagram Table 1. Pin Configurations Pin CLK0, CLK0 CLK1, CLK1 CLK2, CLK2 CLK3, CLK3 FB_IN, FB_IN I/O Input Type LVPECL Function PLL reference clock inputs (differential) (internal pulldown) Supply VDDIC Active State -- Clock Inputs and Outputs Input LVPECL PLL feedback signal input (differential). When configured for external feedback, the QFB output should be connected to FB_IN. (internal pulldown) Bank A differential outputs Bank B differential outputs Bank C differential outputs Bank D differential outputs Differential PLL feedback output. QFB must be connected to FB_IN for correct operation VDDIC -- QA[1:0], QA[1:0] QB[1:0], QB[1:0] QC[1:0], QC[1:0] QD[1:0], QD[1:0] QFB, QFB Output Output Output Output Output LVPECL LVPECL LVPECL LVPECL LVPECL VDDAB VDDAB VDDCD VDDCD VDDCD -- -- -- -- -- 304 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 Table 1. Pin Configurations (Continued) Pin EX_FB_SEL CLK_VALID[3:0]1 CLK_ALARM_RST PLL_BYPASS MEDIA MR LOCK CLK_STAT[3:0] SEL_STAT[1:0] BUSY MBOOT PRESET INT MSTROUT_EN SEL_2P5V I2C Interface SCL SDA ADDR[2:0] IEEE 1149.1 and Test TMS TDI TDO TCK TRST PLL_TEST[2:0] TPA Power and Ground GND VDD VDDAB VDDCD VDDIC VDDA 1. bit order = msb to lsb. Supply Supply Supply Supply Supply Supply Ground -- -- -- -- -- Negative power supply Positive power supply for the device core, output status and control inputs. (3.3 V or 2.5 V) Supply voltage for output banks A and B (QA0 through QB1) (3.3 V or 2.5 V) Supply voltage for output banks C and D (QC0 through QD1) and QFB (3.3 V or 2.5 V) Supply voltage for differential inputs clock inputs CLK0 to CLK3 and FB_IN (3.3 V or 2.5 V) Clean supply for analog portions of the PLL (This voltage is derived via a RC filter from the VDD supply) -- -- -- -- -- -- -- -- -- -- ---- Input Input Output Input Input Input Output LVCMOS JTAG test mode select(10K pullup) LVCMOS JTAG test data input(10K pullup) LVCMOS JTAG test data output LVCMOS JTAG test clock LVCMOS JTAG test reset(10K pullup) LVCMOS PLL_TEST pins (factory use only, MUST BE CONNECTED TO GND) LVCMOS PLL Analog test pin (factory use only, MUST BE CONNECT TO GND) VDDIC VDDIC VDDIC VDDIC VDDIC N/A VDDA -- -- -- -- -- -- -- I/O I/O Input OD OD I2C interface control, clock I2C interface control, data VDD VDD VDD -- -- high I/O Input Input Input Input Input Input Output Output Output Output Input Input Output Input Input Type Function Supply VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Active State high high low high high low low high high low high high low high high Control Inputs and Outputs LVCMOS Selects between external feedback and internal feedback LVCMOS Validates the clock inputs CLK0 to CLK3 (internal pullup) LVCMOS Reset of all four alarm status flags and clock selection status flag (internal pullup) LVCMOS Select static test mode (internal pulldown) LVCMOS Output impedance control LVCMOS Device reset (internal pullup) LVCMOS PLL lock indicator LVCMOS Clock input status indicator LVCMOS Reference clock selection indicator LVCMOS IDCS switching activity indicator LVCMOS Activates I2C boot sequence (internal pulldown) LVCMOS Enables Preset configuration of configuration registers on release of MR (internal pulldown) OD Indicate any status IDCS change LVCMOS Master Enable for all Outputs (internal pulldown) LVCMOS Device core power supply selection for VDD and VDDA LVCMOS I2C interface address lines (10K pullup) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 305 MPC9894 Table 2. Function Table Control Control Inputs PLL_BYPASS 0 PLL enabled. The input to output frequency relationship PLL bypassed and IDCS disabled. The VCO output is is according to Table 9 if the PLL is frequency locked. replaced by the reference clock signal fREF. This is considered to be a test mode and clock monitoring and clock switching are disabled during this operation. The associated clock input is considered to be invalid and usable CLK_STAT[3:0] and SEL_STAT[1:0] flags are reset: CLK_STAT[3:0] = 0000 and SEL_STAT[1:0] = 00. CLK_ALARM_RST is a one-shot function. The associated clock input is considered to be a valid usable clock input CLK_STAT[3:0] and SEL_STAT[1:0] flags are active Default 0 1 CLK_VALID[3:0] CLK_ALARM_RST 0 1 MR 1 Outputs enabled (active) Reset of data generators and output dividers. The MPC9894 requires reset at power-up and after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than two reference clock cycles I2C read/write mode Normal Operation Selects internal feedback path Low output impedance (QA0 to QD1 and QFB) Selects 3.3 V for core VDD All outputs disabled (synchronous with clock being low) I2C boot mode Uses Configuration Register PRESET values on MR Selects external feedback path 50 output impedance (QA0 to QD1 and QFB) Selects 2.5 V for core VDD All outputs enabled MBOOT PRESET EX_FB_SEL MEDIA SEL_2P5V MSTROUT_EN Control Outputs LOCK1 BUSY1 INT CLK_STAT[3:0] SEL_STAT[1:0] 0 0 0 0 0 PLL is locked The IDCS has initiated a clock switch. IDCS status has changed (indicates an assertion of CLK_STAT[3:0] or deassertion of LOCK) Associated clock input not valid Encoded value refer to Table 7 PLL is unlocked No clock switch currently performed No status change Associated clock input valid Encoded value refer to Table 7 1. The combined pins of LOCK = 1 and BUSY = 0 are used to indicate a catastrophic failure. Refer to PLL Out-of-Lock Conditions. 306 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 OPERATING INFORMATION Basic Functional Description The MPC9894 is a quad-redundancy IDCS clock generator. The redundancy feature allows automatic switching from the reference clock source to a secondary clock source on detection of a failed reference clock. The MPC9894 will detect and report a missing clock on any of its four inputs. Based upon the current IDCS mode setting and the qualifier input pins, the MPC9894 will switch to the next qualified secondary clock. The input clock sources, CLK0, CLK1, CLK2, and CLK3, are assumed to be the same frequency(1) but non-phase-related sources. When a clock switch occurs, the phase alignment to the new clock source will occur over an extended time period, eliminating runt clock output pulses. The maximum rate of phase change is specified in the AC parameter Delta Period per Cycle(PER/CYC). The device uses a fully integrated PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by a variety of values, including 0.25, 0.5, 1, 2, 4 or 8. For a complete list refer to Table 9. The frequency multiplied clock signal drives four independent output banks. Each output bank is phase-aligned to the input reference clock phase, providing virtually zero-delay capability(2). The configuration of the MPC9894 series of clock generators is performed through either the I2C interface or by the preset configuration mode. The I2C interface uses a 2 pin interface to transmit clock and data to and from a series of configuration and status registers in the MPC9894. Definitions IDCS: Intelligent Dynamic Clock Switch. The IDCS monitors the clock inputs CLK0, CLK1, CLK2, and CLK3. Upon a failure of the reference clock signal, the IDCS switches to a qualified secondary clock signal and the status flags are set. Reference clock signal: The input clock signal that is selected by the IDCS or IDCS_MODE[2:0] as the input reference to the PLL. Primary clock: The input clock signal selected by IDCS_MODE[2:0]. The primary clock may or may not be the reference clock, depending on IDCS mode and IDCS status. Secondary clock: The input clock signal which will be selected by the IDCS upon an automatic clock switch. Tertiary, Quaternary clocks: The input clock signals that will be selected by the IDCS, in turn, after the current secondary clock. This clock selection is based upon a round robin rotational sequence Manual IDCS mode: The reference clock input is selected by IDCS_MODE[0xx]. Automatic IDCS mode: The reference clock signal is determined by the IDCS. Selected clock: The SEL_STAT[1:0] flags indicate the reference clock signal. Qualified clock: The corresponding CLK_VALID[3:0] signal is logic high, the associated CLK_STAT status bit is logic high and no clock failure is present. Bit Ordering: The bit ordering convention used in this document for both pin and register documentation is NAME[7:0] where bit 7 is the most significant bit and 0 is the least significant bit. 1. Refer to Table 39 for clock frequency specification 2. Using external feedback FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 307 MPC9894 DEVICE CONFIGURATION I2C Configuration and I2C Addressing The MPC9894 is configured via a series of 8-bit registers. The bits in these registers allow a wide range of control over the operation of the MPC9894 clock generator. These registers are accessed via an I2C interface through which a 7-bit address is sent from the I2C master to select the specific I2C slave device being accessed. The address for this clock driver is found in the first of the MPC9894 I2C registers. The format of this address has a fixed most-significant four bits of binary 1101 while the least-significant 3 address bits are read from the 3 ADDR pins. This provides the capability to configure up to 8 clock devices on a single I2C interface. In addition, activation of the MBOOT pin on power-up or reset initiates an automatic boot sequence allowing the clock generators to be initialized from an I2C compatible EEPROM. In Table 3. MPC9894 IDCS Configuration IDCS_MODE [2:0] 000 001 010 011 100 101 110 111 1. For CLK_VALID[3:0] = 1111 and input clock validity Automatic Description Manual Primary Clock CLK0 CLK1 CLK2 CLK3 CLK0 CLK1 CLK2 CLK3 Secondary Clock1 n/a n/a n/a n/a CLK1 CLK2 CLK3 CLK0 Tertiary Clock n/a n/a n/a n/a CLK2 CLK3 CLK0 CLK1 Quaternary Clock n/a n/a n/a n/a CLK3 CLK0 CLK1 CLK2 this case the MPC9894 becomes an I2C master and the configuration bits are filled by the information from the first 6 bytes of the EEPROM. This allows the clock to be configured without a controlling I2C bus master if desired. The PRESET pin allows the device to be configured without a I2C bus master. The detailed register descriptions are found in the section, I2C Interface and configuration/status register. IDCS MODE Configuration Three register bits are used to configure the MPC9894 in either an automatic clock switch mode or into a manual clock select mode. The three mode select bits are defined in Table 3 IDCS modes 000 through 011 allow manual selection between the four clock sources. IDCS modes 100 through 111 enable the automatic mode of the IDCS. Automatic IDCS Mode In the automatic mode, the clock failure detection is enabled and the IDCS overwrites the selected clock on a clock failure. The IDCS operation requires PLL_BYPASS = 0 and IDCS_MODE[2] = 1. The reference clock is handled in a round robin method based upon clock validity and the qualification input CLK_VALID[3:0]: The qualification input is obtained from the four input pins, CLK_VALID[3:0]. If any of the CLK_VALID pins are low the associated clock input will be considered "unqualified" and thus not selected as a reference clock. Alternatively, if a clock input does not have a valid clock signal, it will not be selected and the next qualified and valid clock is selected as the reference clock. For example, if IDCS_MODE[2:0] = 100 (the IDCS is in automatic mode), CLK_VALID[3:0] = 1111 and CLK0, CLK1, CLK2, and CLK3 have valid input clock signals then CLK0 is the primary clock and CLK1 is the secondary clock. The IDCS selects the primary clock as the reference clock and the PLL will phase-lock the clock outputs to the CLK0 input. Upon the failure of CLK0 the IDCS will select CLK1 as the reference clock and initiate a switch, making CLK1 the reference clock and CLK2 the secondary clock. If CLK1 fails, the IDCS will switch to CLK2, etc. A de-asserted CLK_VALID[] pin disables the associated clock input as secondary clock. The associated clock input cannot be selected by the IDCS as secondary clock signal. For instance, if CLK0 is the primary clock and CLK_VALID[3:0] = 1101, the IDCS will select CLK2 upon a 1. See Clock Failure Detection. clock failure of CLK0 (CLK1 is disabled by the CLK_VALID1 input, allowing external logic to control the IDCS switch logic). If a clock is the reference clock signal and its associated CLK_VALID signal is switched from `valid' to `invalid', the IDCS initiates a clock input switch, selecting the next available clock input (secondary clock). An invalid clock(1) signal triggers the associated clock status output (CLK_STAT[3:0]), independent of the primary and reference clock. These pins go set on a clock failure and remain set (sticky) until the CLK_ALARM_RST pin or the individual alarm reset bits (ALARM_RST[3:0]) are asserted. The CLK_STAT[3:0] outputs are mirrored in the device register 4 for I2C bus access. After each successful IDCS-commanded switch, the primary clock as set by IDCS_MODE[1xx] is no longer the reference clock. The user may reset the IDCS flags by asserting the individual ALARM_RST[3:0] bits after each IDCS-commanded switch. Activation of ALARM_RST[3:0] does not change the reference clock. A user-commanded change of the primary clock in automatic mode requires a write command to the IDCS_MODE[2:0] = 0xx bits (the primary clock and SEL_STAT[1:0] can be freely changed by setting IDCS_MODE[2:0] = 1xx). If the reference clock is not the primary clock, a write command to IDCS_MODE[2:0] = 1xx will cause the PLL to lock on the primary clock, given the new primary clock is a qualified clock. 308 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 Table 4. Input Clock Qualifier and Status Flag Input Clock CLK0 CLK1 CLK2 CLK3 Associated Input Qualifier1 CLK_VALID0 CLK_VALID1 CLK_VALID2 CLK_VALID3 Associated Input Clock Status Flag Pin CLK_STAT0 CLK_STAT1 CLK_STAT2 CLK_STAT3 Register location Device register 5, bit 3 Device register 5, bit 4 Device register 5, bit 5 Device register 5, bit 6 1. The input qualifier logic can be enabled or disabled by setting the QUAL_EN bit in register 3. Table 5. Input Clock Status CLK_STAT[3:0] CLK_STAT[] 0 1 Description Clock input failure Clock input signal valid Table 6. Clock Input Qualifier CLK_VALID[3:0] CLK_VALID[] 0 1 Qualified Associated Input Clock Not qualified and will not be selected The SEL_STAT[1:0] pins indicate which of the four input clocks is the current reference clock. In the automatic mode and In the case of the reference clock failure, the SEL_STAT flag will Table 7. SEL_STAT[1:0] SEL_STAT[1:0] 00 01 10 11 indicate a reference clock different from the original primary clock selected by IDCS_MODE[2:0]. The CLK_STAT outputs are mirrored in register 5, bits 1:0 for I2C bus access. Selected clock input CLK0 CLK1 CLK2 CLK3 If all four clock inputs are not qualified the VCO will slew to its lowest frequency. This condition will be indicated by the LOCK pin being de-asserted. The MPC9894 will remain in this state until an input clock is restored and the device is reset via the MR pin. Clock Failure Detection The MPC9894 clock failure detection is performed using an input clock amplitude check combined with an activity detector. The following conditions will trigger a failed clock status (CLK_STATn = 0) on any qualified clock (CLK_VALIDn = 1). These conditions are: 1. Either or both CLKx, CLKx are disconnected from the input clock source and open. 2. CLKx and CLKx are shorted together 3. Either or both CLKx or CLKx are shorted to GND 4. Both CLKx and CLKx are shorted to a power supply 5. Amplitude of CLKx or CLKx is less than VPP, OK (refer to AC specification, Table 39) In addition, the currently selected clock is checked by a phase-frequency detector after the input divider (P). This is triggered by a phase step of mae(). This phase detector will issue a failed clock status (CLK_STATn = 0) within 'P' clock cycles. The IDCS does not detect changes of the reference frequency or the reference frequency being out of the specified input frequency range. This includes errors such as reference frequency drift due to crystal aging etc. Clearing of IDCS Alarm Flags The input clock status flags are set by a clock failure and remain set until manually cleared (sticky). Clearing can be done by either of two methods. All status flags can be cleared by the package pin, CLK_ALARM_RST. Or individual status flags can be cleared via register bits, ALARM_RST[3:0]. The CLK_ALARM_RST pin is activated by a negative edge on the pin. This clears all CLK_STAT[3:0] flags and returns the IDCS to the primary clock source. The SEL_STAT[1:0]-selected clock indicator now reflects the IDCS_MODE[2:0] setting. By using ALARM_RST[3:0] (register 2) individual CLK_STAT[3:0] bits are cleared by writing a logic 0 to the individual bit in this register. It is important to note that this action does not return the IDCS to the primary clock. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 309 MPC9894 IDCS Manual Mode The manual request IDCS mode is selected by IDCS_MODE[2:0] = 0xx. The PLL functions normally and all four inputs clocks are monitored. The reference clock will always be the clock signal selected by IDCS_MODE[1:0] and will be indicated by SEL_STAT[1:0]. A manual-requested clock switch (by changing the IDCS_MODE[0xx] signal) will only be executed if the new clock is valid. The SEL_STAT[1:0] pins/bits should be checked after the manual request to ensure the clock switch occurred. Interrupt Operation The MPC9894 pin, INT, may be used to interrupt a microprocessor or microcontroller. This open drain output pin goes active or low on any of the following occurrences 1. A clock failure as indicated by any of bits 6 thru 3 being set in the status register 2. A out-of-lock condition for the PLL as indicated by either the LOCK pin or bit 2 of the status register. The interrupted processor would then use the I2C interface to read the status register (bit 7) to determine if this MPC9894 generated the interrupt. If the interrupt was caused by this MC9894, the status register would then be analyzed to determine the reason for the interrupt and then the appropriate action taken. In order for interrupts to occur, the INT_E bit must be set in the Device Configuration and Output Clock Enable Register. Once the interrupt flag has been set, reading of the Status Register clears the INT flag. Clock Operation on Power-Up On or after power-up, the MPC9894 must be reset via the MR pin. The MPC9894 may be powered-up in either of three configurations. These configurations are selected by the PRESET pin and MBOOT pin. If PRESET is low, on release of the MR pin, the MPC9894 powers up in a benign mode with all clock outputs disabled. The device is ready to be and must be programmed via the I2C interface prior to operation. If the PRESET pin is high on the release of the MR pin, the MPC9894 powers up in a run state. In this case the IDCS is configured for automatic mode, CLK0 to be the primary clock, a divide by 2 on clock bank A and B outputs, a divide by 8 on clock C and D outputs, all clock output banks enabled and interrupts enabled. If using the preset mode, then at least one of the clock inputs must have the correct input frequency prior to MR going high. Later in this document, tables defining the I2C interface registers describe both configurations. The default (reset) information is for the normal reset operation, while the default (preset) information describes the values for each configuration bit on activation of the PRESET pin. In order to return the MPC9894 to either the preset or reset configuration the MR pin must be activated. Refer to the 310 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 CLOCK OUTPUT TRANSITION An MPC9894 clock switch, either in IDCS manual or IDCS automatic mode, follows the next positive edge of the newly selected reference clock signal. The positive edge of the feedback clock and the newly selected reference clock edge will start to slew to alignment by adjusting the feedback edge placement a small amount of time in each clock cycle. Figure 2. Clock Switch shows a failed primary input clock with the MPC9894 switching to and aligning to the secondary clock. This small amount of additional time in each clock cycle will ensure that the output clock does not have any large phase changes or frequency changes in a short period of time. The alignment will be to either 1) the closest edge, either forward or Primary Clock backward or 2) toward the lagging clock edge. The maximum rate of period change is specified in the AC parameter tables with the parameter of PER/CYC. This parameter implies that the output clock edge will never change more than the specified amount in any one cycle. The busy signal is used to indicate that the MPC9894 is in the process of slewing to the new input clock alignment. The signal is accessed thru the BUSY pin and goes set upon a clock switch. The pin is reset once the phase realignment is completed. During the period that BUSY is active, the configuration register of the MPC9894 should not be written with new configuration data. Secondary Clock Output Clock BUSY BUSY Figure 2. Clock Switch For example, if the current input clock of 62.5 MHz and the secondary clock are 180 degrees out of phase then the minimum clock transition time can be calculated by tcycle = 1 / fcycle = 1 / 62.5 MHz = 16 ns Therefore 180 degree clock difference is tcycle / 2 = 8 ns Assuming a PER/CYC of 40 ps, then 8ns / 40 ps/cycle = 200 cycles. This is the minimum number of cycles that will be required for the alignment to the new clock. The alignment to the new clock phase may occur slower than this but never faster. The alignment on clock failure is selectable between either 1) the closest edge, either forward or backward or 2) toward the lagging clock edge. The selection of the alignment method is selected in the Slew_Control bit (bit 5) of the Device Configuration and Output Enable Register. This selection allows the user to select the alignment method that best suits the application. The characteristics and subsequent advantages and disadvantages of each method are described as follows. 1. Slew to closest edge a. The alignment is either forward toward the lagging edge or backward toward the leading edge. The alignment to the closest edge ensures re-alignment to the new clock input in the minimum time. c. In applications where the input clocks are closely aligned, there is no ambiguity on the direction of clock slew. d. The clock output frequency will either increase or decrease based on direction of clock slew. 2. Slew to lagging edge a. The output frequency always decreases. Thus the clock frequency never violates a maximum frequency specification in the user system. b. When input clocks are closely aligned (within SPO + jitter) the MPC9894 may align to the closest edge or to the lagging edge. In the case of multiple MPC9894s with equivalent clock inputs one MPC9894 may align in one direction while an other MPC9894 may align to the opposite direction. If default values for the Slew_Control is not the configuration desired then the reconfiguration of the slew method should be perform soon after power-up and the configuration should remain fixed from that point. b. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 311 MPC9894 INPUT AND OUTPUT FREQUENCY CONFIGURATION Configuring the MPC9894 input and output frequencies requires programming the internal PLL input, feedback and output dividers. The output frequency is represented by the following formula: fOUT = [(fREF / P) M] / N where fREF is the reference frequency of the selected input clock source (reference input), M is the PLL feedback divider and N is an output divider. The PLL input divider P, the feedback divider M and the output divider are configured by the device registers 1 and 4. The MPC9894 has four output banks (Bank Table 8. Configuration of PLL P, M and N Frequency Dividers Divider PLL Input Divider (P) PLL Feedback Divider (M) PLL Output Divider, Bank A (NA) PLL Output Divider, Bank B (NB) PLL Output Divider, Bank C (NC) PLL Output Divider, Bank D (ND) /8, /12, /16 /2, /4, /8, /16 /2, /4, /8, /16 /2, /4, /8, /16 /2, /4, /8, /16 FSEL_B[1:0], Register 1, bit 7:6 FSEL_B[1:0], Register 1, bit 5:4 FSEL_C[1:0], Register 1, bit 3:2 FSEL_D[1:0], Register 1, bit 1:0 Available Values /1, /2, /3, /4, /5, /6 Configuration Through Input_FB_Div[3:0], Register 4, bit 3:0 A, B, C, and D) and each output bank can be configured individually as shown in Table 8. fREF /P /N fOUT PLL /M Figure 3. PLL Frequency Calculation The reference frequency fREF and the selection of the PLL input divider (P) and feedback-divider (M) is limited by the specified VCO frequency range. fREF, P and M must be configured to match the VCO frequency range of 340 to 680 MHz in order to achieve stable PLL operation: fVCO,MIN (fREF / P M) fVCO,MAX The PLL input divider (P) can be used to situate the VCO in the specified frequency range. The PLL input divider effectively extends the usable input frequency range. The output frequency for each bank can be derived from the VCO frequency and output divider (N): fQA[1:0] = fVCO / NA fQB[1:0] = fVCO / NB fQC[1:0] = fVCO / NC fQD[1:0] = fVCO / ND Table 9 illustrates the possible input clock frequency configurations of the MPC9894. Note that the VCO lock range is always 340 MHz to 680 MHz, setting lower and upper boundaries for the frequency range of the device. Table 9. Input and Output Frequency Ranges Input_FB_Div[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4 6 /8 /12 170.0 - 340.0 170.0 - 340.0 1fREF 1fREF /4 /12 113.32 - 226.64 1.5fREF reserved reserved reserved 0.5fREF 0.5fREF 0.25fREF 0.25fREF 0.125fREF 0.125fREF /2 /3 /4 /8 /12 /16 85.0 - 170.0 85.0 - 170.0 85.0 - 170.0 2fREF 2fREF 2fREF reserved 0.75fREF 0.375fREF 0.1875fREF P /1 /1 /2 /1 /2 M /16 /12 /12 /8 /16 fREF range MHz 21.25 - 42.5 28.33 - 56.67 56.66 - 113.34 42.5 - 85.0 42.5 - 85.0 Output frequency for any bank A, B, C or D (FSEL_x) and ratio to fREF N=2 8fREF 6fREF 3fREF 4fREF 4fREF reserved 1fREF 1fREF 1fREF 0.5fREF 0.5fREF 0.5fREF 0.125fREF 0.125fREF 0.125fREF N=4 4fREF 3fREF 1.5fREF 2fREF 2fREF N=8 2fREF 1.5fREF 0.75fREF 1fREF 1fREF N = 16 fREF 0.75fREF 0.375fREF 0.5fREF 0.5fREF 312 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 I2C INTERFACE AND CONFIGURATION/STATUS REGISTERS The following tables summarize the bit configurations for the registers accessible via the I2C interface. The register values are read or written over the I2C interface by the I2C Master. This sequence starts with the I2C start command, followed by the I2C device address and read/write byte. This is then followed by the address of the register that is to be accessed. In the case of a write, the register address byte is followed by the data to be Table 10. I2C Registers Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Register Table 11. Slave Address (Register 0 -- Read Only) Table 12. Output Configuration Register (Register 1 -- Read/Write) Table 14. Mode Configuration and Alarm Reset Register (Register 2 -- Read/Write) Table 17. Device Configuration and Output Clock Enable Register (Register 3 -- Read/Write) Table 22. Input and Feedback Divider Configuration Register (Register 4 -- Read/Write) Table 24. Status Register (Register 5 -- Read Only) Table 25. Output Power-Up Register (Register 6 -- Read/Write) Table 27. Feedback Power-Up Register (Register 7 -- Read/Write) written to that register. In the case of a read, the device will then respond with the data from that register. At the conclusion of the transfer an I2C Stop command is issued by the Master to terminate the transfer. For a complete description of the I2C protocol refer to the v2.1 I2C specification. Table 10 lists the registers that are accessible via the I2C interface. Boot Mode When the I2C boot mode is activated on power-up or reset via the MBOOT pin, the entire set of writable configuration registers are written with a 6-byte sequence. This sequence starts with the Output Configuration Register, and is followed by the Mode Configuration and Alarm Reset Register, the Device Configuration and Output Clock Enable Register, the Input and Feedback Divider Configuration Register, the Output Power-Up Register and the Feedback Power-Up Register. This equates to ACK Dev Selection Start Byte Addr Write ACK the register sequence of 1, 2, 3, 4, 6, 7. This sequence starts with the start command, the device select and read/write(write) byte, followed by the beginning byte address for reading from the EEPROM. This is then followed by the start command, device select and read/write (read) and four current address read bytes. The device address is the binary 7-bit value of 1010000. This I2C sequence is compatible with industry standard I2C bus EEPROMs such as STMicroelectronics M24C01, or equivalent. ACK Data Out Read Stop NoACK Dev Selection Start Figure 4. Boot Mode Random Access Read Slave Address Register The Slave Address register contains the I2C address that is used to determine if the data on the I2C interface is addressed to this device. The seven-bit address is determined with the Table 11. Slave Address (Register 0 -- Read Only) Bit Description 7 not used 6 ADDR_6 5 ADD_R5 4 ADDR_4 3 ADDR_3 2 ADDR_2 read from ADDR[2] pin 1 ADDR_1 read from ADR[1] pin 0 ADDR_0 read from ADDR[0] pin fixed value of binary 1101 followed by variable bits that are obtained from the three address pins. The three input pins allow for 8 different addresses for a given clock generator, allowing up to 8 clock generators to be addressed on a single I2C interface. Reset default Preset default 1 1 1 1 0 0 1 1 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 313 MPC9894 Output Configuration Register The output configuration register is divided into four, 2 bit-groups with each group selecting the divide ratio for output Bit Description Reset default Preset default 0 0 7 FSEL_A[1:0] 0 0 0 0 6 5 FSEL_B[1:0] 0 0 0 1 4 banks A through bank D, refer to Table 12. For each bank, four output divider settings (/2, /4, /8, /16) are available, refer to Table 12. Table 12. Output Configuration Register (Register 1 -- Read/Write) 3 FSEL_C[1:0] 0 0 0 1 2 1 FSEL_D[1:0] 0 0 0 Table 13. PLL Output Divider N (FSEL_A to FSEL_D) FSEL_x[1:0] 00 01 10 11 Value /2 /4 /8 /16 Mode Configuration Register The mode configuration register, refer to Table 14, is a read/write register and contains the fields for mode selection as well as alarm reset. The mode of the MPC9894 may be changed by writing the three least significant Mode Configuration Register bits to the desired value. The current idcs mode of the MPC9894 may be obtained by reading this register. The alarm reset bits, found in bit positions 6 thru 3, may be used to individually reset the status flags of register 5. Each of Bit Description Reset default Preset default 7 not used n/a n/a n/a n/a 6 5 n/a n/a 4 n/a n/a these flag bits are associated with the four clock inputs pins and indicate a failed clock input. Clearing of a clock status flag is performed by writing a logic 1 to the individual bit (or bits if more than one flag is to be cleared). Care should be taken to insure that the idcs mode information is written to the proper value when resetting the clock status bits. The four alarm reset bits always read as a logic 0. If a clock input status flag is cleared and the clock input is still in a failed state, the status flag will go set within 4 clock cycles after being cleared. Table 14. Mode Configuration and Alarm Reset Register (Register 2 -- Read/Write) 3 n/a n/a 2 0 1 1 1 0 0 1 0 ALARM_RST[3:0] (Refer to Table 15) IDCS_MODE[2:0] (Refer to Table 16) Table 15. Individual Reset of CLK_STAT[x] Bits ALARM_RST[x] 0 1 No action The status flag CLK_STAT[x] is cleared by setting of this bit. (bit always reads as zero) Description Table 16. MPC9894 IDCS Configuration1 IDCS_MODE [2:0] 000 001 010 011 100 101 110 111 1. This is a repeat of Table 8. 2. For CLK_VALID[3:0] = 1111 and input clock validity. Automatic Description Manual Primary clock CLK0 CLK1 CLK2 CLK3 CLK0 CLK1 CLK2 CLK3 Secondary clock2 n/a n/a n/a n/a CLK1 CLK2 CLK3 CLK0 Tertiary clockb n/a n/a n/a n/a CLK2 CLK3 CLK0 CLK1 Quaternary clockb n/a n/a n/a n/a CLK3 CLK0 CLK1 CLK2 314 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 Device Configuration and Output Enable Register The Device Configuration and Output Enable Register is used to individually enable or disable each bank of outputs. Output banks are enabled by setting the corresponding bit to a logic 1 and disabled by setting the bit to a logic 0 as described in Table 21. Output Clock Stop/Enable. The disable logic sets the outputs of the addressed bank synchronously to logic low state (Qx[] = 0 and Qx[] = 1). The clock output enable/stop bits can be set asynchronous to any clock signal without the risk of generating of runt pulses. The PLL feedback output QFB cannot be disabled when MPC9894 is configured for external feedback. The Device Configuration Register, bit 6, QUAL_EN is used to enable or disable all clock input qualifier pins. Asserting this bit enables the Clock Qualifier Input Pins CLK_VALID[3:0]. Deasserting this bit disables these pins such that inputs on CLK_VALID[3:0] are ignored. The INT_E bit, in bit position 7, is used to enable or disable interrupts from occurring on the INT pin. The setting of the interrupt flag (bit 7 of the Status Register) is unaffected by this bit. Table 17. Device Configuration and Output Clock Enable Register (Register 3 -- Read/Write) Bit Description Reset default Preset default 7 INT_E 0 1 6 QUAL_EN 0 1 5 Slew_Control 0 0 4 Enable_QFB 0 0 3 ENABLE_QA 0 1 2 ENABLE_QB 0 1 1 ENABLE_QC 0 1 0 ENABLE_QD 0 1 Table 18. Interrupt Signal (INT) Enable INT_E INT_E 0 1 Interrupt signal INT is enabled Description Interrupt signal INT is disabled Table 19. Input Clock Qualifier Enable QUAL_EN QUAL_EN 0 1 Description CLK_VALID[3:0] are disabled (clock qualifier signals are disabled) CLK_VALID[3:0] are enabled (clocks can be qualified) Table 20. Slew Control Slew_Control 0 1 Description Clock slew direction on clock switch is toward the closest edge Clock slew direction on clock switch is toward the lagging edge Table 21. Output Clock Stop/Enable ENABLE_Qx 0 1 Output bank x is enabled Description Output bank x is disabled (clock stop in logic low state) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 315 MPC9894 Input and Feedback Divider Configuration Register Table 22. Input and Feedback Divider Configuration Register (Register 4 -- Read/Write) Bit Description Reset default Preset default 7 Reserved n/a n/a 6 Reserved n/a n/a 5 Reserved n/a n/a 4 Reserved n/a n/a 0 0 3 2 0 0 1 0 1 0 0 1 Input_FB_Div[3:0] The Input and Feedback Divider Configuration Register is used to select the input divider value and the feedback divider values. The four bits for Input_FB_Div allow 16 combinations of input and feedback divider ratios. Some input and output Table 23. Input_FB_Div[3:0] Input_FB_Div[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 6 4 2 3 4 frequency ranges may overlap allowing a choice of PLL closed loop bandwidths. This selection may be useful when PLL devices are cascaded. Input Divider (P) 1 1 2 1 2 reserved Feedback Divider (M) 16 12 12 8 16 8 12 16 reserved 12 reserved reserved reserved 8 12 Device Status Register The Device Status Register contains a copy of the status SEL_STAT[1:0], LOCK and CLK_STAT[3:0] pins. In addition, bit 7 is an INT flag bit, which is used to indicate a setting of a bit in the CLK_STAT[3:0], a clearing of the LOCK bit and a change in the value of the SEL_STAT[1:0] bits. Table 24. Status Register (Register 5 -- Read Only) Bit Description 7 6 5 4 The CLK_STAT[3:0] bits are sticky and remain set until manually reset through the Mode Configuration Register. The setting of the register INT bit is reflected on the interrupt pin only if interrupts are enabled. Enabling interrupts is done by the setting of the INT_E bit which is located in the Device Configuration Register. Reading of the Status Register clears the INT flag. 3 2 LOCK Inverse of LOCK signal 1 0 CLK_STAT[3:0] INT Inverse of INT Status of CLK3, CLK2, CLK1 and CLK0 (sticky) Copy of CLK_STAT[3:0] signal signal SEL_STAT[1:0] Copy of SEL_STAT[1:0] signal 316 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 Output Power-Up Register The Output Power-Up Register configures each of the 8 LVPECL outputs for either power-up or a power-down state. The use of these bits allows power consumption to be reduced Table 25. Output Power-Up Register (Register 6 -- Read/Write) Bit Description Reset Default Preset Default 7 PWR_QD1 0 1 6 PWR_QD0 0 1 5 PWR_QC1 0 1 4 PWR_QC0 0 1 3 PWR_QB1 0 1 2 PWR_QB01 0 1 1 PWR_QA1 0 1 0 PWR_QA0 0 1 when all of the clock outputs are not used. Placing an output in the power-down condition is not synchronous with the clock edges. Table 26. Clock Output Power-Up Bits PWR_Qxx 0 1 Output Power-Down Output Power-Up Description Feedback Power-Up Register The Feedback Power-Up register bit 0 is used to configure the MPC9894 feedback output in either a power-up state or a power-down state. Note this register bit is valid for internal feed- back configuration only. When external feedback is selected QFB is always enabled and in a power-up state. The remaining bits of this register are unused and read as a logic 0. Table 27. Feedback Power-Up Register (Register 7 -- Read/Write) Bit Description Reset Default Preset Default 7 6 5 4 3 2 1 0 PWR_QFB 0 1 Table 28. Feedback Output Power-Up Bit PWR_QFB 0 1 Feedback Output Power-Down Feedback Output Power-Up Description FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 317 MPC9894 IEEE STD.1149.1(JTAG) This section describes the IEEE Std. 1149.1 compliant Test Access Port (TAP) and Boundary Scan Architecture implementation in the MPC9894. Special private instructions are provided to assist in production test control. These instructions combined with control of the test mode inputs and Table 29. TAP Interface Signals Signal Name TCK TMS TDI TRST_B TDO Description Test Clock Test Mode Select Test Data In Test Reset Bar Test Data Out Function Test logic clock. TAP mode control input. Serial test instruction/data input. Asynchronous test controller reset. Serial test instruction/data output. Direction Input Input Input Input Output Active State -- -- -- -- -- the use of shared inputs and outputs provide for full production test mode access and control. Test Access Port Interface Signals Table 29 lists the TAP interface signals and their descriptions. Instruction Register Table 30. Instruction Register Bit Position Field Capture-IR Value 0 0 4 3 2 IR 0 0 1 1 0 Instructions Table 31 lists the public instructions provided in the implementation and their instruction codes. Public instructions Table 31. TAP Controller Public Instructions Instruction BYPASS CLAMP EXTEST HIGHZ IDCODE SAMPLE are accessible by the customer for board test and may also be used for production chip test. Code 11111 01100 00000 01001 00001 00010 Enabled Serial Test Data Path Bypass Register Bypass Register Boundary Scan Register Bypass Register ID Register Boundary Scan Register Boundary-Scan Register A full description of the boundary scan register may be found in the BSDL file. Device Identification Register (0x0281D01D) Table 32. Device Identification Register Bit Position Field Value 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Version 0 0 0 0 0 1 0 1 0 Part Number 0 0 0 0 0 1 1 1 0 1 0 0 0 9 8 7 6 5 4 3 2 1 0 Manufacturer ID 0 0 0 0 1 1 1 0 1 318 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 POWER SUPPLY CONFIGURATION The MPC9894 operates from either a 3.3 V or 2.5 V voltage supply for the device core. The pin SEL_2P5V is used to logically indicate the core supply voltage. This selection is done by setting the pin to a logic 1 for 2.5 V or logic 0 for 3.3 V operation. The input and output supply voltage may be set for either 3.3 V or 2.5 V and can be individually set for inputs and banks Table 33. Power Supply Configuration Supply Voltage VDD VDDAB VDDCD VDDIC1 VDDA Description Positive power supply for the device core, output status and control inputs. (3.3 V or 2.5 V) Supply voltage for output banks A and B (QA0 through QB1) Supply voltage for output banks A and B (QC0 through QD1) and QFB Supply voltage for differential inputs clock inputs CLK0 to CLK3 and FB_IN Value 3.3 V or 2.5 V 3.3 V or 2.5 V 3.3 V or 2.5 V 3.3 V or 2.5 V of outputs. Table 33. Power Supply Configuration lists the supply pins and what pin or group of pins are associated with each supply. Note, that for output skew and SPO specifications to be valid the input, feedback input and output, and the output bank must all be at the same voltage level. Clean supply for Analog portions of the PLL (This voltage is derived via an RC filter from the VDD supply) Derived from VDD 1. VDDIC (Supply of FB_IN) must be equal to VDDCD (Supply of QFB) to ensure the SPO specification is met. Power Supply Sequencing and MR Operation Figure 5 defines the release time and the minimum pulse length for MR pin. The MR release time is based upon the power supply being stable and within VDD specifications. Refer to Table 39 for actual parameter values. The MPC9894 may be configured after release of reset and the outputs will be stable for use after lock indication is obtained. VDD must ramp up prior to or concurrent with the other power supply pins. It is recommended that the maximum slew rate for the VDD supply not exceed 0.5 V/ms. VDD MR treset_rel treset_pulse Figure 5. MR Operation Clock Outputs VDD VDD The MPC9894 clock outputs are differential LVPECL voltage compatible. The outputs are designed to drive a single 50 TBD TBD impedance load that is properly terminated. The media pin is MPC9894 RS used to select between either of two output termination techniques. VDDA Selection of media = 0 sets all of the outputs to drive up to TBD 50 parallel terminated (to VTT) transmission lines. With media = 1 the outputs are designed to drive 50 transmission line terminated with a single 100 differential load resistor. See Figure 6. VCC Power Supply Bypass Figure 7 and Figure 8 for diagrams of each of these termination techniques. Note, that the traditional output pulldown resistors Power Supply Bypassing for emitter follower biasing are not required for the MPC9894. If The MPC9894 is a mixed analog/digital product. The external feedback is used, the QFB output must be terminated differential architecture of the MPC9894 supports low noise with the same technique as selected with the media pin. Once signal operation at high frequencies. In order to maintain its a termination technique is chosen, that technique must be used superior signal quality, all VCC pins should be bypassed by for all MPC9894 outputs to guarantee output skew timing. high-frequency ceramic capacitors connected to GND. If the The recommended termination technique is media = 1. This spectral frequencies of the internally generated switching noise provides a simpler termination method and also reduces overall on the supply pins cross the series resonant point of an power consumption of the MPC9894. Unused outputs may be individual bypass capacitor, its overall impedance begins to powered-down via the Output Power-Up and Feedback look inductive and thus increases with increasing frequency. Power-Up registers to conserve power. If external feedback is The parallel capacitor combination shown ensures that a low selected the programming of the PWR_QFB bit is ignored. impedance path to ground exists for frequencies well above the noise bandwidth. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 319 MPC9894 Table 34. Absolute Maximum Ratings1 Symbol VDD VDDAB, CD VDDIC VDDA VIN VOUT IIN IOUT TS Characteristics Supply Voltage (core) Supply Voltage (differential outputs) Supply Voltage (differential inputs) Supply Voltage (Analog Supply Voltage) DC Input Voltage2 DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 3 Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max 4.0 4.0 4.0 VDD VDDx+0.3 VDDx+0.3 20 50 125 Unit V V V V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 2. VDDx references power supply pin associated with specific input pin. 3. VDDx references power supply pin associated with specific output pin. Table 35. General Specifications Symbol VTT MM HBM CDM LU CIN JC TJ Characteristics Output Termination Voltage (LVPECL) ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Input Capacitance Thermal Resistance (junction-to-ambient, junction-to-board, junction-to-case) Junction Temperature1 -40 200 2000 500 200 TBD TBD 110 Min Typ VDD - 2 Max Unit V V V V mA pF C/W C Inputs Condition LVPECL outputs 1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (Refer to Application Note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MPC9894 to be used in applications requiring industrial temperature range. It is recommended that users of the MPC9894 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. Table 36. DC Characteristics (TJ = -40C to +110C)1 Symbol IDD IDDAB, CD2 IDDA IDDIC IDD IDDAB, CD IDDA IDDIC 3 Characteristics Maximum Quiescent Supply Current (core) Maximum Quiescent Supply Current, outputs terminated 50 to VTT Maximum Supply Current (Analog Supply) Maximum Quiescent Supply Current (I/O) Maximum Quiescent Supply Current (core) Maximum Quiescent Supply Current, outputs terminated 50 to VTT Maximum Supply Current (Analog Supply) Maximum Quiescent Supply Current (I/O) Min Typ TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD Unit mA mA mA mA mA mA mA mA Condition VDD pins VDDAB and VDDCD pins VDDA pin VDDIC pins VDD pins VDDAB and VDDCD pins VDDIN pins VDDIC pins Supply Current for VDD = 2.5 V5% and VDDAB,CD = 2.5 V5% Supply Current for VDD = 3.3 V5% and VDDAB,CD = 3.3 V5% or VDDAB,CD = 2.5 V5% 1. DC characteristics are design targets and pending characterization. 2. IDDAB, CD includes current through the output resistors (all outputs terminated to VTT). 3. IDDAB, CD includes current through the output resistors (all outputs terminated to VTT). 320 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 Table 37. PECL DC Characteristics (TJ = -40C to +110C)1 Symbol Characteristics Min 2 Typ Max Unit Condition Differential PECL clock inputs (CLKx, CLKx and FB_IN, FB_IN) for VDDIC = 3.3 V 5% or VDDIC = 2.5 V 5% VPKPK VCMR IIN AC Differential Input Voltage3 Differential Cross Point Voltage Input Current1 4 0.2 1.25 1.3 VDD-0.3 100 V V A Differential operation Differential operation VPP = 0.8 V and VCMR = VDDL-0.7 V Termination 50 to VTT Termination 50 to VTT See Figure 7 See Figure 8 Differential PECL clock outputs (QA0 to QD1 and QFB) for VDDAB,CD = 3.3 V 5% or VDDAB,CD = 2.5 V 5% VOH VOL ZOUT 1. 2. 3. 4. Output High Voltage Output Low Voltage Output Impedance MEDIA = 0 MEDIA = 1 TBD TBD VDDAB,CD-1.0 VDDAB,CD-1.7 TBD 50 TBD TBD V V DC characteristics are design targets and pending characterization. Clock inputs driven by PECL compatible signals. VPKPK is the minimum differential input voltage swing required to maintain AC characteristics. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Table 38. LVCMOS I/O DC Characteristics (TJ = -40C to +110C)1 Symbol Characteristics Min Typ Max Unit Condition Single-ended LVCMOS inputs for VDD = 3.3 V 5% VIH VIL VOH VOL ZOUT IIN Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current 2 2.0 VDD + 0.3 0.8 V V V LVCMOS LVCMOS IOH = -6 mA IOL = 6 mA 2.4 0.4 40 62 10 V A VIN = VDDL or GND Single-ended LVCMOS inputs for VDD = 2.5 V 5% VIH VIL VOH VOL ZOUT IIN Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current 2 1.7 VDD + 0.3 0.7 V V V LVCMOS LVCMOS IOH = -6 mA IOL = 6 mA 1.9 0.4 45 70 10 V A VIN = VDDL or GND 1. DC characteristics are design targets and pending characterization. 2. Inputs have pull-down resistors affecting the input current. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 321 MPC9894 Table 39. AC Characteristics (TJ = -40C to +110C)1 2 Symbol Characteristics Min Typ Max Unit Condition VDD = 3.3 V 5%, VDDAB,CD,IC = 3.3 V 5% or VDDAB,CD,IC = 2.5 V 5% Input and output timing specification fREF Input reference frequency 21.25 28.33 56.66 42.5 85.0 113.32 170 42.5 56.67 113.34 85 170 226.68 340 TBD 340 /2 output /4 output /8 output /16 output 170.0 85.0 42.5 21.25 40 680 340.0 170.0 85.0 42.5 60 500 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % ppm ps ps % kHz 20% to 80% PLL locked Input_FB_Div[3:0] = 0 Input_FB_Div[3:0] = 1 Input_FB_Div[3:0] = 2 Input_FB_Div[3:0] = 3,4 Input_FB_Div[3:0] = 6,7,8 Input_FB_Div[3:0] = 10 Input_FB_Div[3:0] = 14,15 PLL bypass Input reference frequency in PLL bypass mode3 fVCO fMAX VCO frequency range Output Frequency 4 fREFDC fREFacc mae() tr, tf DC fI2C VPP VPP, OK VPP, NOK VO(P-P) t() tsk(O) Reference Input Duty Cycle Input Frequency Accuracy5 Misaligned Edge Specification Output Rise/Fall Time Output duty cycle I2C frequency range Differential input voltage6 (peak-to-peak) (PECL) Differential input voltage7 (peak-to-peak) (PECL) Differential input voltage8 (peak-to-peak) (PECL) Differential output voltage (peak-to-peak) (PECL) 600 47.5 50 1600 800 52.5 100 Differential input and output voltages 1.3 TBD TBD TBD 0.8 V V V V PLL and IDCS specifications Propagation Delay (static phase offset) CLKX, CLKX to FB_IN, FB_IN Output-to-output Skew within a bank9 Output-to-output Skew across a bank9 PER/CYC Rate of change of period10 /2 output /4 output /8 output /16 output /2 output /4 output /8 output /16 output +100 -100 50 TBD +40 +80 +120 +160 ps ps slew_control = 1 ps PLL locked with external feedback selected PER/CYC Rate of change of period11 40 80 120 160 10 TBD TBD ps slew_control = 0 Jitter and bandwidth specifications tJIT(CC) tJIT(PER) tJIT(y) BW Cycle-to-cycle jitterRMS (1 ) Period JitterRMS (1 ) I/O Phase JitterRMS (1 ) PLL closed loop bandwidth 12 ps ps ps kHz TBD 322 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 Table 39. AC Characteristics (TJ = -40C to +110C)1 2 Symbol Characteristics (Continued) Min Typ Max Unit Condition VDD = 3.3 V 5%, VDDAB,CD,IC = 3.3 V 5% or VDDAB,CD,IC = 2.5 V 5% MR and PLL Lock tLOCK treset_ref treset_pulse 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Maximum PLL Lock Time MR hold time on power up MR hold time 10 2 100 s ps ns AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9894 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF = (fVCO / M) N. All Input Clock frequencies must be within this value to guarantee smooth phase transition on input clock switch. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VPP, OK is the minimum differential input voltage swing required for a valid clock signal. Above VPP, OK the input will be detected as a good clock (see IDCS). VPP, NOK is the maximum differential input voltage swing for a guaranteed bad clock. Below VPP, NOK the input will be detected as a failed clock (see IDCS). VDDAB = VDDCD Rate of period change is the maximum change of the clock output signal period T per cycle on a IDCS commanded switch. Rate of period change is the maximum change of the clock output signal period T per cycle on a IDCS commanded switch. -3 dB point of PLL transfer characteristics. Differential Pulse Generator Z = 50 Z = 50 Z = 50 RT = 50 VTT DUT MPC9894 RT = 50 VTT Figure 7. MPC9894 AC Test Reference (Media = 0) Differential Pulse Generator Z = 50 Z = 50 Z = 50 RT = 100 RT = 50 VTT DUT MPC9894 Figure 8 . MPC9894 AC Test Reference (Media = 1) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 323 MPC9894 MPC9894 Pin and Package Table 40. MPC9894 Pin Listing Signal Name CLK0 CLK0 CLK1 CLK1 CLK2 CLK2 CLK3 CLK3 FB_IN FB_IN QA0 QA0 QA1 QA1 QB0 QB0 QB1 QB1 QC0 QC0 QC1 QC1 QD0 QD0 QD1 QD1 QFB QFB CLK_VALID3 CLK_VALID2 CLK_VALID1 CLK_VALID0 CLK_ALARM_RST PLL_BYPASS MEDIA SCL SDA Description Clock0 Positive Input Clock0 Negative Input Clock1 Positive Input Clock1 Negative Input Clock2 Positive Input Clock2 Negative Input Clock3 Positive Input Clock3 Negative Input Feedback Clock Positive Input Feedback Clock Negative Input Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Qualifier for clock input CLK3 Qualifier for clock input CLK2 Qualifier for clock input CLK1 Qualifier for clock input CLK0 Reset of all four alarm status flags and clock selection status flag Select PLL of static test mode Output impedance control (high = 50 ) I2C Interface Control, Clock I2C Interface Control, Data Direction Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input I/O I/O Type LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Active State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- High High High High Low High High -- -- Supply VDDIC VDDIC VDDIC VDDIC VDDIC VDDIC VDDIC VDDIC VDDIC VDDIC VDDAB VDDAB VDDAB VDDAB VDDAB VDDAB VDDAB VDDAB VDDCD VDDCD VDDCD VDDCD VDDCD VDDCD VDDCD VDDCD VDDCD VDDCD VDD VDD VDD VDD VDD VDD VDD VDD VDD Pin D1 D2 E3 E2 F3 F2 G1 G2 C1 C2 K4 J4 K5 J5 K7 J7 K6 J6 A7 B7 A6 B6 A4 B4 A5 B5 A3 B3 F10 E10 E9 E8 F8 F9 E7 C9 C10 324 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 Table 40. MPC9894 Pin Listing (Continued) Signal Name ADDR2 ADDR1 ADDR0 MR LOCK CLK_STAT3 CLK_STAT2 CLK_STAT1 CLK_STAT0 SEL_STAT1 SEL_STAT0 BUSY MBOOT INT PRESET TMS TDI TRST TCK TDO SEL_2P5V MSTROUT_EN PLL_TEST2 PLL_TEST1 PLL_TEST0 TPA EX_FB_SEL VDD VDDA VDDAB VDDCD VDDIC GND Description I2C Interface Control, Address 2 (MSB) I2C Interface Control, Address 1 I2C Interface Control, Address 1 (LSB) Device Master Reset PLL Lock Indicator Input CLK3 status indicator Input CLK2 status indicator Input CLK1 status indicator Input CLK0 status indicator Reference Clock Selection Indicator (MSB) Reference Clock Selection Indicator (LSB) IDCS switch activity indicator Activates I2C Boot Sequence Indicates any status IDCS change Sets preset state JTAG Test Mode Select JTAG Test Data Input JTAG Test Reset Bar JTAG Test Clock JTAG Test Data Out Indicate core VDD level, (high = 2.5V, low = 3.3V) Enable all outputs in sync PLL Test Bit 2 PLL Test Bit 1 PLL Test Bit 0 (LSB) PLL Analog Test Pin Select feedback mode (high = external) Control Input, Status Output and Core Supply Analog Supply Supply for A and B bank outputs Supply for C and D bank outputs Supply for input clocks Control Input, Status Output and Core Ground Direction Input Input Input Input Output Output Output Output Output Output Output Output Input Output Input Input Input Input Input Output Input Input Input Input Input Output Input Power Power Power Power Power Ground Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS OD LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Analog LVCMOS -- -- -- -- -- -- Active State -- -- -- Low Low High High High High High High High High n/a High High -- Low -- -- -- High -- -- -- -- -- -- -- -- -- -- -- Supply VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDIC VDDIC VDD VDDIC VDDIC VDD VDD VDDAB VDDAB VDDCD VDDA VDD VDD VDDA VDDAB VDDCD VDDIC GND Pin A9 B8 A8 D10 G10 H9 H10 G8 G9 K8 J8 J10 D8 D9 H7 D3 H1 H2 G3 J3 D7 K9 H4 G5 D5 E4 C7 A10, B9, C3, C8, G7, H8, J9, K10 E1 H6, J2, K2 A1, C4, C6 B2, H3, K1 A2, B1, B10, C5, D4, D6, E5, E6, F1, F4, F5, F6, F7, G4, G6, H5, J1, K3 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 325 MPC9894 Table 41. MPC9894 PIN DIAGRAM 1 2 3 4 5 6 7 8 9 10 A VDDC GND QFB QD0 QD1 QC1 QC0 ADDR0 ADDR2 VDD B GND VDDIC QFB QD0 QD1 QC1 QC0 ADDR1 VDD GND C FB_IN FB_IN VDD VDDCD GND VDDCD EX_FB_SEL VDD SCL SDA D CLK0 CLK0 TMS GND PLL_TEST0 GND SEL_2P5V MBOOT INT MR E VDDA CLK1 CLK1 TPA GND GND MEDIA CLK_ VALID0 CLK_ ALARM_ RST CLK_ STAT1 CLK_ VALID1 PLL_ BYPASS CLK_ STAT0 CLK_ STAT3 CLK_ VALID2 CLK_ VALID3 F GND CLK2 CLK2 GND GND GND GND G CLK3 CLK3 TCK GND PLL_TEST1 GND VDD LOCK H TDI TRST VDDIC PLL_TEST2 GND VDDAB PRESET VDD CLK_ STAT2 J GND VDDAB TDO QA0 QA1 QB1 QB0 SEL_STAT0 VDD BUSY K VDDIC VDDAB GND QA0 QA1 QB1 QB0 SEL_ STAT1 MSTROUT _EN VDD 326 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9894 MPC9894 PROGRAMMING MODEL Table 42. Slave Address (Register 0 -- Read Only) Bit Description 7 not used 6 ADDR_6 5 ADD_R5 4 ADDR_4 3 ADDR_3 2 ADDR_2 read from ADDR[2] pin 1 ADDR_1 read from ADR[1] pin 0 ADDR_0 read from ADDR[0] pin Reset default Preset default x (TBD) x (TBD) x (TBD) x (TBD) x (TBD) x (TBD) x (TBD) x (TBD) Table 43. Output Configuration Register (Register 1 -- Read/Write) Bit Description Reset default Preset default 0 0 7 FSEL_A[1:0] 0 0 0 0 6 5 FSEL_B[1:0] 0 0 0 1 4 3 FSEL_C[1:0] 0 0 0 1 2 1 FSEL_D[1:0] 0 0 0 Table 44. Mode Configuration and Alarm Reset Register (Register 2 -- Read/Write) Bit Description Reset default Preset default 7 not used n/a n/a n/a n/a 6 5 n/a n/a 4 n/a n/a 3 n/a n/a 2 0 1 1 1 0 0 1 0 ALARM_RST[3:0] (See Table 15) IDCS_MODE[2:0] (See Table 16) Table 45. Device Configuration and Output Clock Enable Register (Register 3 -- Read/Write) Bit Description Reset default Preset default 7 INT_E 0 1 6 QUAL_EN 0 1 5 Slew_Control 0 0 4 Enable_QFB 0 0 3 ENABLE_QA 0 1 2 ENABLE_QB 0 1 1 ENABLE_QC 0 1 0 ENABLE_QD 0 1 Table 46I. nput and Feedback Divider Configuration Register (Register 4 -- Read/Write) Bit Description Reset default Preset default 7 Reserved n/a n/a 6 Reserved n/a n/a 5 Reserved n/a n/a 4 Reserved n/a n/a 0 0 3 2 0 0 1 0 1 0 0 1 Input_FB_Div[3:0] Table 47. Status Register (Register 5 -- Read Only) Bit Description 7 INT Inverse of INT signal 6 5 4 3 2 LOCK Inverse of LOCK signal 1 0 CLK_STAT[3:0] Status of CLK3, CLK2, CLK1 and CLK0 (sticky) Copy of CLK_STAT[3:0] signal SEL_STAT[1:0] Copy of SEL_STAT[1:0] signal Table 48. Output Power-Up Register (Register 6 -- Read/Write) Bit Description Reset Default Preset Default 7 PWR_QD1 0 1 6 PWR_QD0 0 1 5 PWR_QC1 0 1 4 PWR_QC0 0 1 3 PWR_QB1 0 1 2 PWR_QB01 0 1 1 PWR_QA1 0 1 0 PWR_QA0 0 1 Table 49. Feedback Power-Up Register (Register 7 -- Read/Write) Bit Description Reset Default Preset Default 7 6 5 4 3 2 1 0 PWR_QFB 0 1 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 327 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9895 Rev 0, 04/2003 Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch The MPC9895 is a 3.3V compatible, PLL based intelligent dynamic clock switch and generator specifically designed for redundant clock distribution systems. The device receives two LVCMOS clock signals and generates 12 phase aligned output clocks. The MPC9895 is able to detect a failing reference clock signal and to dynamically switch to a redundant clock signal. The switch from the failing clock to the redundant clock occurs without interruption of the output clock signal (output clock slews to alignment). The phase bump typically caused by a clock failure is eliminated. The device offers 12 low skew clock outputs organized into two output banks. The extended temperature range of the MPC9895 supports telecommunication and networking requirements. The device employs a fully differential PLL design to minimize jitter. Features * 12 output LVCMOS PLL clock generator * 3.3V compatible * IDCS - on-chip intelligent dynamic clock switch * Automatically detects clock failure * Smooth output phase transition during clock failover switch * 50 - 200 MHz output frequency range * LVCMOS compatible inputs and outputs * External feedback enables zero-delay configurations * Supports networking, telecommunications and computer applications * Output enable/disable and static test mode (PLL bypass) * Low skew characteristics: maximum 150 ps(1) output-to-output * 100 ball MAPBGA package, 1 mm ball pitch * Ambient temperature range -40C to +85C MPC9895 3.3V IDCS AND PLL CLOCK GENERATOR VF SUFFIX 100-LEAD MAPBGA PACKAGE CASE 1462-01 Functional Description The MPC9895 is a 3.3V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by 4, 8, 16 or 32. The frequencymultiplied clock drives six bank A outputs and six bank B outputs. Bank A and bank B outputs are phase-aligned. Due to the external PLL feedback, the clock signals of both output banks are also phase-aligned to the selected input reference clock, providing virtually zero-delay capability. The integrated IDCS continuously monitors both clock inputs and indicates a clock failure individually for each clock input. When a false clock signal is detected, the MPC9895 switches to the redundant clock input, forcing the PLL to slowly slew to alignment and not produce any phase bumps at the outputs. Both clock inputs are interchangeable. The automatic switch operation to a restored (fixed) clock signal is also supported. The MPC9895 also provides a manual mode that allows for user-controlled clock switches. The PLL bypass of the MPC9895 disables the IDCS and PLL-related PLL specifications do not apply. In PLL bypass mode, the MPC9895 is fully static in order to distribute low-frequency clocks for system test and diagnosis. Outputs of the MPC9895 can be disabled (high-impedance state) to isolate the device from the system. Applying output disable also resets the MPC9895. On power-up this reset function needs to be applied for correct operation of the circuitry. Please see 1. Final specification subject to change 328 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9895 QA0 CLK0 CLK1 FB (PULLDOWN) (PULLDOWN) (PULLDOWN) (PULLDOWN) (PULLUP) (PULLUP) (PULLDOWN) D Q 0 Ref 1 PLL 200 - 400 MHz 0 1 D Q QA1 QA2 QA3 QA4 IDCS QA5 QB0 QB1 QB2 QB3 PLL_EN FSEL[0:2] (PULLDOWN) (PULLDOWN) DATA GENERATOR D Q QB4 QB5 QFB ALARM0 ALARM1 OE/MR (PULLDOWN) CLK_IND FB REF_SEL MAN/A ALARM_RST RESTORE Figure 1. MPC9895 Logic Diagram Table 1. Signal Configurations Signal CLK0, CLK1 FB REF_SEL MAN/A ALARM_RST RESTORE PLL_EN FSEL[0:2] OE/MR QA[0:5] QB[0:5] QFB ALARM0 ALARM1 CLK_IND GND VCC_PLL Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Supply Supply I/O Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC PLL reference clock inputs PLL feedback signal input, connect directly to QFB output Selects the primary reference clock Selects switch mode and alarm flag reset Reset of alarm flags and selected reference clock indicator Selects the automatic restore mode Selects PLL or static test mode Clock frequency selection and configuration of clock divider modes Output enable/disable, device reset Bank A clock outputs Bank B clock outputs Clock feedback output. QFB must be connected to FB for correct operation Indicates clock failure on CLK0 Indicates clock failure on CLK1 Indicates currently selected input reference clock Negative power supply Positive power supply for the PLL (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see VCC Supply VCC FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 329 MPC9895 Table 2. Function Table Control Inputs PLL_EN 0 PLL enabled. The input to output frequency relationship is according to Table 3 if the PLL is frequency locked. Manual clock switch mode. IDCS disabled. Clock failure detection and output flags ALARM0, ALARM1, CLK_IND are enabled. Low-to-high transition: ALARM0, ALARM1 and CLK_IND flags are reset: ALARM0=H, ALARM1=H and CLK_IND=REF_SEL. ALARM_RST 1 ALARM0, ALARM1 and CLK_IND flags are reset: ALARM0=H, ALARM1=H and CLK_IND=REF_SEL. ALARM_RST is an one-shot function. RESTORE operation is disabled PLL bypassed and IDCS disabled. The VCO output is replaced by the reference clock signal fref. The MPC9895 is in manual mode. Automatic clock switch mode. IDCS enabled. Clock failure detection and output flags ALARM0, ALARM1, CLK_IND are enabled. IDCS overrides REF_SEL on a clock failure. IDCS operation requires PLL_EN = 0. Default 0 1 MAN/A 1 ALARM0, ALARM1 and CLK_IND active RESTORE 0 The IDCS attempts to automatically restore the primary clock source defined by REF_SEL. This operation requires PLL_EN = 0 and MAN/A=1 Selects CLK1 as the primary clock source REF_SEL FSEL[0:2] OE/MR 0 00 0 Selects CLK0 as the primary clock source See Table 3 Outputs enabled (active) Logic 1: Outputs disabled (high impedance state), reset of data generators and output dividers. The MPC9895 requires reset at power-up and after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than two reference clock cycles (CLK0,1). OE/MR does not affect the QFB output. Outputs (ALARM0, ALARM1, CLK_IND are valid if PLL is locked) ALARM0 ALARM1 CLK_IND CLKO failure CLK1 failure CLKO is the primary clock, CLK1 is the secondary clock CLK1 is the primary clock, CLK0 is the secondary clock Table 3. Clock Frequency Configuration Name M16H M8L M32 M16L M8H M4 FSEL0 0 0 1 1 0 0 1 1 FSEL1 0 1 0 1 0 1 0 1 FSEL2 0 0 0 0 1 1 1 1 fREF range [MHz] 6.25-12.5 6.25-12.5 3.125-6.25 3.125-6.25 12.5-25.0 12.5-25.0 QAx and QBx Ratio fREF 16 fREF 8 fREF 32 fREF 16 fREF 8 fREF 4 fQAX [MHz] 100-200 50-100 100-200 50-100 100-200 50-100 n/a n/a QFB fREF fREF fREF fREF fREF fREF M 32 32 64 64 16 16 N 2 4 2 4 2 4 330 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9895 Table 4. 100 Ball MAPBGA Signal Alignment1 Signal MAN/A QA5 QA4 GND QA3 QA2 VCC QA1 QA0 GND QFB VCC GND VCC VCC GND GND VCC VCC ALARM_RST Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Signal FB GND VCC VCC VCC VCC VCC VCC VCC REF_SEL CLK0 VCC VCC GND GND GND GND VCC GND PLL_EN Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Signal CLK1 VCC VCC GND GND GND GND VCC GND FSEL0 VCC_PLL GND VCC GND GND GND GND VCC GND FSEL1 Ball E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Signal VCC_PLL GND VCC GND GND GND GND VCC GND FSEL2 ALARM0 GND VCC VCC VCC VCC VCC VCC VCC RESTORE Ball G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 Signal ALARM1 VCC GND VCC VCC GND GND VCC VCC OE/MR CLK_IND QB5 QB4 GND QB3 QB2 VCC QB1 QB0 GND Ball J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 1. See Figure 14. MAPBGA Pin Configurations (Bottom View). Table 5. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 6. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 331 MPC9895 Table 7. DC Characteristics (VCC = 3.3V 5%, TA = -40C to +85C) Symbol VIH VIL VOH VOL ZOUT IIN ICC_PLL ICC VTT Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current Maximum PLL Supply Current Maximum Quiescent Supply Current Output Termination Voltage VCC / 2 2 14-17 200 5 4 2.4 0.55 0.30 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V V V A mA mA V VIN = VCC or GND VCC_PLL balls All VCC balls Condition LVCMOS LVCMOS IOH = -24 mA1 IOL = 24 mA IOL = 12 mA 1. The MPC9895 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50W series terminated transmission lines. Table 8. AC Characteristics (VCC = 3.3V 5%, TA = -40C to +85C)1 2 Symbol fref Input Frequency FSEL= 000 FSEL= 010 FSEL= 100 FSEL= 110 FSEL= 001 FSEL= 011 Maximum Output Frequency FSEL= 000 FSEL= 010 FSEL= 100 FSEL= 110 FSEL= 001 FSEL= 011 Reference Input Duty Cycle CLK0, 1 Input Rise/Fall Time Propagation Delay (static phase offset, CLKx to FB) Rate of Period Change (phase slew rate) IDCS Switch Delay3 IDCS Restore Delay4 Output-to-Output Skew5 Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle jitter Period Jitter I/O Phase Jitter PLL Closed Loop Bandwidth6 Maximum PLL Lock Time FSEL=0x FSEL=1x 2 TBD TBD 10 (within bank) (bank-to-bank) 45 0.1 50 FSEL=x0x FSEL=x1x 1 64 50 100 55 1.0 10 10 100 TBD 3 150 300 100 50 100 50 100 50 40 200 100 200 100 200 100 60 1.0 MHz MHz MHz MHz MHz MHz % ns ns 0.8 to 2.0V PLL locked 6.25 6.26 3.125 3.125 12.5 12.5 12.5 12.5 6.25 6.25 25.0 25.0 MHz MHz MHz MHz MHz MHZ PLL locked Characteristics Min Typ Max Unit Condition PLL locked fMAX frefDC tr, tf t() t NF NR tsk(O) DCO tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW tLOCK 1. 2. 3. 4. 5. 6. ps/cycle MAN/A = 1 MAN/A = 1 T T ps ps % ns ns ns ps ps ns MHz MHz ms 0.55 to 2.4V All AC characteristics are design targets and subject to change upon characterization. AC characteristics apply for parallel output termination of 50 to VTT. Number of input clock cycles for clock failure detection. T = period of the feedback clock signal. Number of consecutive, valid clock cycles of an input clock signal. T = period of the feedback clock signal. See application section for part-to-part skew calculation. -3dB point of PLL transfer characteristics. 332 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9895 APPLICATIONS INFORMATION Definitions IDCS: Intelligent Dynamic Clock Switch. The IDCS monitors both primary and secondary clock signals. Upon a failure of the primary clock signal, the IDCS switches to a valid secondary clock signal and status flags are set. Reference clock signal fref: The clock signal that is selected by the IDCS or REF_SEL as the input reference to the PLL. Manual mode: The reference clock frequency is selected by REF_SEL. Automatic mode: The reference clock frequency is selected by the internal IDCS logic. Primary clock: The input clock signal selected by REF_SEL. The primary clock may or may not be the reference clock, depending on switch mode and IDCS status. Secondary clock: The input clock signal not selected by REF_SEL Selected clock: The CLK_IND flag indicates the reference clock signal: CLK_IND = 0 indicates CLK0 is the clock reference signal, CLK_IND =1 indicates CLK1 is the reference clock signal. Clock failure: A valid clock signal that is stuck (high or low) for at least one input clock period (NF>1). The primary clock and the secondary clock is monitored for failure. Valid clock signals must be within the AC and DC specification for the input reference clock. A loss of clock is detected if as well as the loss of both clocks. In the case of both clocks are lost, the MPC9895 will set the alarm flags and the VCO will run at its lowest frequency. The PLL will not be locked. The MPC9895 has to be reset by OE/MR to recover from this situation, it is recommended to re-apply the startup sequence and to use the manual mode (MAN/A=0) to select the primary clock. The MPC9895 does not monitor and detect changes in the input frequency. Automatic Mode and IDCS Commanded Clock Switch MAN/A = 1, IDCS enabled: Both primary and secondary clocks are monitored. The first clock failure is reported by its ALARMx status flag (clock failure is indicated by a logic low). The ALARMx status is flag latched and remains latched until reset by assertion of ALARM_RST (if RESTORE=0) or the input clock is fixed (if RESTORE=1). If the clock failure occurs on the primary clock, the IDCS attempts to switch to the secondary clock. The secondary clock signal needs to be valid for a successful switch. CLK_IND indicates the reference clock signal. Upon a successful switch, CLK_IND indicates the reference clock, which may now be different as that originally selected by REF_SEL. Clock Restore Operation If the RESTORE input is asserted (RESTORE=1, MAN/A = 1) the IDCS attempts to restore the primary clock after a clock failure. After a successful IDCS-commanded clock switch, REF_SEL is not equal to CLK_IND. The IDCS continues to monitor the primary and secondary clock. If the primary clock becomes valid for at least 64 consecutive cycles (NR>64), the IDCS attempts to switch back to the primary clock (restore the primary clock). Upon a successful clock restore operation, the primary clock is the reference clock, CLK_IND will be equal to REF_SEL and the ALARMx flags are cleared. If REF_SEL is equal to the CLK_IND flag (no clock failure occurred) the IDCS does not change the selected input clock. Deassertion of RESTORE disables the clock restore option and the clock selection must be reset manually. Manual Mode MAN/A = 0, IDCS disabled: PLL functions normally and both clocks are monitored. The reference clock signal will always be the clock signal selected by REF_SEL and will be indicated by CLK_IND. The clock restore feature is disabled in manual mode. Clock Output Transition A clock switch, either in automatic or manual mode, follows the next negative edge of the newly selected reference clock signal. The feedback and newly selected reference clock edge will start to slew to alignment at the next positive edge of both signals. Output runt pulses are eliminated. Reset ALARM_RST is asserted by a negative edge. It generates a one-shot reset pulse that clears both ALARMx latches and the CLK_IND latch. If both CLK0 and CLK1 are invalid or fail when ALARM_RST is asserted, both ALARMx flags will be latched after one FB signal period and CLK_IND will be latched (L) indicating CLK0 is the reference signal. While neither ALARMx flag is latched (ALARMx = H), the CLK_IND can be freely changed with REF_SEL. OE/MR: Reset the data generator and output disable. MAN/A: The rising edge of OE/MR resets ALARMx and CLK_IND as ALARM_RST does. Acquiring Frequency Lock (startup sequence) 1. On startup, OE/MR must be asserted to reset the output dividers. The IDCS should be disabled (MAN/A=0) and RESTORE should be logic low (disable restore option) during startup. REF_SEL selects the primary clock. 2. Release OE/MR and the PLL will attempt to gain lock if the primary clock is present. PLL lock requires the specified lock time. 3. Enable the IDCS automatic mode (MAN/A=1). The rising edge of the MAN/A signal clears the alarm flags and CLK_IND. The IDCS will now report clock failures by asserting ALARMx flags. 4. Enable the restore option (RESTORE=1) if needed. Power Supply Filtering The MPC9895 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL (PLL) power supply impacts the device FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 333 MPC9895 characteristics, for instance I/O jitter. The MPC9895 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9895. Figure 2 illustrates a typical power supply filter scheme. The MPC9895 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 3.0V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 2 must have a resistance of 9-10 to meet the voltage drop criteria. RF = 9-10 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9893 VCC 33...100 nF IN Driving Transmission Lines The MPC9895 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9895 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9895 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9895 OUTPUT BUFFER 14 RS = 36 ZO = 50 OutA Figure 2. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 2, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9895 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. IN MPC9895 OUTPUT BUFFER 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9895 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9895. The output waveform in Figure 4 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus 334 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9895 the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+17+25) = 1.31V 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9895 OUTPUT BUFFER 14 RS = 22 ZO = 50 VOLTAGE (V) RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 5. Optimized Dual Line Termination Figure 4. Single versus Dual Waveforms MPC9895 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 6. CLK0, CLK1 MPC9895 AC Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 335 MPC9895 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device FB t() CLK0,1 VCC VCC / 2 GND VCC VCC / 2 GND Figure 7. Output-to-Output Skew tSK(O) Figure 8. Propagation Delay (t(), static phase offset) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage FB TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles CCLK0, 1 Figure 9. Output Duty Cycle (DC) Figure 10. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 11. Cycle-to-Cycle Jitter Figure 12. Period Jitter VCC=3.3V 2.4 0.55 tF tR Figure 13. Output Transition Time Test Reference 336 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9895 1 K CLK_ IND 2 QB5 3 QB4 4 GND 5 QB3 6 QB2 7 VCC 8 QB1 9 QB0 10 GND K J ALAR M1 VCC GND VCC VCC GND GND VCC VCC OE/MR J H ALAR M0 GND VCC VCC VCC VCC VCC VCC VCC REST ORE H G VCC_ PLL GND VCC GND GND GND GND VCC GND FSEL2 G F VCC_ PLL GND VCC GND GND GND GND VCC GND FSEL1 F E CLK1 VCC VCC GND GND GND GND VCC GND FSEL0 E D CLK0 VCC VCC GND GND GND GND VCC GND PLL_ EN D C FB GND VCC VCC VCC VCC VCC VCC VCC REF_ SEL C B QFB VCC GND VCC VCC GND GND VCC VCC ALARM _RST B A MAN/A QA5 QA4 GND QA3 QA2 VCC QA1 QA0 GND A 1 2 3 4 5 6 7 8 9 10 Figure 14. MAPBGA Pin Configurations (Bottom View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 337 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9993 Rev 2, 08/2004 Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. Features * * * * * * * Fully Integrated PLL Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32-Lead LQFP Packaging 32-Lead Pb-Free Package Available MPC9993 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC9993 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section). PLL_En Clk_Selected Inp1bad Inp0bad Man_Override Alarm_Reset OR Qb0 Qb0 Qb1 Qb1 /8 PLL 800 - 1600 MHz /16 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 DYNAMIC SWITCH LOGIC Sel_Clk CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR Figure 1. Block Diagram 338 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9993 Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 18 VCC 24 Qa1 Qa1 Qa0 Qa0 VCC VCC_PLL Man_Override PLL_EN 25 26 27 28 29 30 31 32 1 23 22 21 20 19 VCC 17 16 15 14 VCC Inp0bad Inp1bad Clk_Selected GND Ext_FB Ext_FB GND 13 12 11 10 9 8 GND MPC9993 2 3 4 5 6 7 MR CLK0 CLK0 CLK1 Alarm_Reset Figure 2. 32-Lead Pinout (Top View) Table 1. Pin Descriptions Pin Name CLK0, CLK0 CLK1, CLK1 Ext_FB, Ext_FB Qa0:1, Qa0:1 Qb0:2, Qb0:2 Inp0bad Inp1bad Clk_Selected Alarm_Reset Sel_Clk Manual_Override PLL_En MR VCCA VCC GNDA GND I/O LVPECL Input LVPECL Input LVPECL Input LVPECL Output LVPECL Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input Power Supply Power Supply Power Supply Power Supply Pin Definition Differential PLL clock reference (CLK0 pulldown, CLK0 pullup) Differential PLL clock reference (CLK1 pulldown, CLK1 pullup) Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup) Differential 1x output pairs Differential 2x output pairs Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted `0' if clock 0 is selected, `1' if clock 1 is selected `0' will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is "one-shotted" (50k pullup) `0' selects CLK0, `1' selects CLK1 (50k pulldown) `1' disables internal clock switch circuitry (50k pulldown) `0' bypasses selected input reference around the phase-locked loop (50k pullup) `0' resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50k pullup) PLL power supply Digital power supply PLL ground Digital ground FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Sel_Clk CLK1 339 MPC9993 Table 2. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. General Specifications Symbol VTT MM HBM CDM LU CIN JA Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model Latch-up Immunity Input Capacitance Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 175 1500 1000 100 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 110 Min Typ VCC - 2 Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC TJ Thermal Resistance Junction to Case Operating Junction Temperature1 (continuous operation) MTBF = 9.1 years 1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MPC9993 to be used in applications requiring industrial temperature range. It is recommended that users of the MPC9993 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. 340 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9993 Table 4. DC Characteristics (VCC = 3.3V 5%, TA = - 40 to +85C) Symbol Characteristics Min Typ Max Unit Condition LVCMOS control inputs (MR, PLL_En, Sel_Clk, Man_Override, Alarm_Reset) VIH VIL IIN Input High Voltage Input Low Voltage Input Current1 2.0 VCC + 0.3 0.8 100 V V A VIN = VCC or GND LVCMOS control outputs (Clk_selected, Inp0bad, Inp1bad) VOH VOL Output High Voltage Output Low Voltage 2.0 0.55 V V IOH = -24 mA IOL = 24 mA LVPECL clock inputs (CLK0, CLK1, Ext_FB)2 VPP VCMR IIN DC Differential Input Voltage3 Differential Cross Point Voltage4 Input Current1 0.1 VCC -1.8 1.3 VCC -0.3 100 V V A Differential operation Differential operation VIN = VCC or GND LVPECL clock outputs (QA[1:0], QB[2:0]) VOH VOL Output High Voltage Output Low Voltage VCC -1.20 VCC -1.90 VCC -0.95 VCC -1.75 VCC -0.70 VCC -1.45 V V Termination 50 to VTT Termination 50 to VTT Supply Current IGND ICC_PLL Maximum Power Supply Current Maximum PLL Supply Current 180 15 mA mA GND Pins VCC_PLL Pin 1. Inputs have internal pull-up/pull-down resistors affecting the input current. 2. Clock inputs driven by differential LVPECL compatible signals. 3. VPP is the minimum differential input voltage swing required to maintain AC characteristics. 4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 341 MPC9993 Table 5. AC Characteristics (VCC = 3.3V 5%, TA = -40C to +85C)1 Symbol fref fVCO fMAX frefDC t() VPP VCMR tsk(O) per/cycle Characteristics Input Reference Frequency VCO Frequency Range2 Output Frequency Reference Input Duty Cycle Propagation Delay Differential Input Voltage4 Differential Input Crosspoint Voltage5 Output-to-Output Skew within QA[2:0] or QB[1:0] within device QA[1:0]6 QB[2:0]6 QA[1:0]7 QB[2:0]7 DC tJIT(CC) tLOCK tr, tf 1. 2. 3. 4. Output Duty Cycle Cycle-to-Cycle Jitter Maximum PLL Lock Time Output Rise/Fall Time 0.05 RMS (1 ) 45 20 10 200 100 50 SPO, static phase offset3 CLK0, CLK1 to any Q (peak-to-peak) /16 feedback /16 feedback QA[1:0] QB[2:0] Min 50 800 50 100 25 -2.0 0.9 0.25 VCC-1.7 Typ Max 100 1600 100 200 75 +2.0 1.8 1.3 VCC-0.3 50 80 50 25 400 200 55 47 10 0.70 Unit MHz MHz MHz MHz % ns ns V V ps ps ps ps ps ps % ps ms ns 20% to 80% PLL_EN=1 PLL_EN=0 PLL locked Condition PLL locked Rate of Change of Period AC characteristics apply for parallel output termination of 50 to VCC - 2V. The input reference frequency must match the VCO lock range divided by the feedback divider ratio (FB): fref = fVCO / FB. CLK0, CLK1 to Ext_FB. VPP is the minimum differential input voltage swing required to maintain AC characteristics including SPO and device-to-device skew. Applicable to CLK0, CLK1 and Ext_FB. 5. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the V PP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the SPO, device and part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB. 6. Specification holds for a clock switch between two input signals (CLK0, CLK1) no greater than 400 ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. 7. Specification holds for a clock switch between two input signals (CLK0, CLK1) at any phase difference (180). Delta period change per cycle is averaged over the clock switch excursion. 342 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9993 APPLICATIONS INFORMATION The MPC9993 is a dual clock PLL with on-chip Intelligent Dynamic Clock Switch (IDCS) circuitry. Definitions primary clock: The input CLK selected by Sel_Clk. secondary clock: The input CLK NOT selected by Sel_Clk. PLL reference signal: The CLK selected as the PLL reference signal by Sel_Clk or IDCS. (IDCS can override Sel_Clk). Status Functions Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as the PLL reference signal. Clk_Selected (H) indicates CLK1 is selected as the PLL reference signal. INP_BAD: Latched (H) when it's CLK is stuck (H) or (L) for at least one Ext_FB period (Pos to Pos or Neg to Neg). Cleared (L) on assertion of Alarm_Reset. Control Functions Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock. Alarm_Reset: Asserted by a negative edge. Generates a one-shot reset pulse that clears INPUT_BAD latches and Clk_Selected latch. PLL_En: While (L), the PLL reference signal is substituted for the VCO output. MR: While (L), internal dividers are held in reset which holds all Q outputs LOW. Man Override (H) (IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be the CLK selected by Sel_Clk. The status function INP_BAD is active in Man Override (H) and (L). Man Override (L) (IDCS is enabled, PLL functions enhanced). The first CLK to fail will latch it's INP_BAD (H) status flag and select the other input as the Clk_Selected for the PLL reference clock. Once latched, the Clk_Selected and INP_BAD remain latched until assertion of Alarm_Reset which clears all latches (INP_BADs are cleared and Clk_Selected = Sel_Clk). NOTE: If both CLKs are bad when Alarm_Reset is asserted, both INP_BADs will be latched (H) after one Ext_FB period and Clk_Selected will be latched (L) indicating CLK0 is the PLL reference signal. While neither INP_BAD is latched (H), the Clk_Selected can be freely changed with Sel_Clk. Whenever a CLK switch occurs, (manually or by IDCS), following the next negative edge of the newly selected PLL reference signal, the next positive edge pair of Ext_FB and the newly selected PLL reference signal will slew to alignment. To calculate the overall uncertainty between the input CLKs and the outputs from multiple MPC9993's, the following procedure should be used. Assuming that the input CLKs to all MPC9993's are exactly in phase, the total uncertainty will be the sum of the static phase offset, max I/O jitter, and output to output skew. During a dynamic switch, the output phase between two devices may be increased for a short period of time. If the two input CLKs are 400ps out of phase, a dynamic switch of an MPC9993 will result in an instantaneous phase change of 400ps to the PLL reference signal without a corresponding change in the output phase (due to the limited response of the PLL). As a result, the I/O phase of a device, undergoing this switch, will initially be 400ps and diminish as the PLL slews to its new phase alignment. This transient timing issue should be considered when analyzing the overall skew budget of a system. Hot insertion and withdrawal In PECL applications, a powered up driver will experience a low impedance path through an MPC9993 input to its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input pins to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input signals. Acquiring Frequency Lock 1. While the MPC9993 is receiving a valid CLK signal, assert Man_Override HIGH. 2. The PLL will phase and frequency lock within the specified lock time. 3. Apply a HIGH to LOW transition to Alarm_Reset to reset Input Bad flags. 4. De-assert Man_Override LOW to enable Intelligent Dynamic Clock Switch mode. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 343 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC99J93 Rev 2, 08/2004 Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC99J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. Features * * * * * * * Fully Integrated PLL Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32-Lead LQFP Packaging 32-Lead Pb-Free Package Available MPC99J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section). PLL_En Clk_Selected Inp1bad Inp0bad Man_Override Alarm_Reset OR Qb0 Qb0 Qb1 Qb1 /2 PLL 200 - 360 MHz /4 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 DYNAMIC SWITCH LOGIC Sel_Clk CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR Figure 1. Block Diagram 344 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC99J93 Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 18 VCC 24 Qa1 Qa1 Qa0 Qa0 VCC VCC_PLL Man_Override PLL_EN 25 26 27 28 29 30 31 32 1 23 22 21 20 19 VCC 17 16 15 14 VCC Inp0bad Inp1bad Clk_Selected GND Ext_FB Ext_FB GND 13 12 11 10 9 8 GND MPC99J93 2 3 4 5 6 7 MR CLK0 CLK0 CLK1 Figure 2. Pinout: 32-Lead Pinout (Top View) Table 1. Pin Descriptions Pin Name CLK0, CLK0 CLK1, CLK1 Ext_FB, Ext_FB Qa0:1, Qa0:1 Qb0:2, Qb0:2 Inp0bad Inp1bad Clk_Selected Alarm_Reset Sel_Clk Manual_Override PLL_En MR VCCA VCC GNDA GND I/O LVPECL Input LVPECL Input LVPECL Input LVPECL Output LVPECL Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input Power Supply Power Supply Power Supply Power Supply Pin Definition Differential PLL clock reference (CLK0 pulldown, CLK0 pullup) Differential PLL clock reference (CLK1 pulldown, CLK1 pullup) Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup) Differential 1x output pairs. Connect one QAx pair to Ext_FB. Differential 2x output pairs Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted `0' if clock 0 is selected, `1' if clock 1 is selected `0' will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is "one-shotted" (50k pullup) `0' selects CLK0, `1' selects CLK1 (50k pulldown) `1' disables internal clock switch circuitry (50k pulldown) `0' bypasses selected input reference around the phase-locked loop (50k pullup) `0' resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50k pullup) PLL power supply Digital power supply PLL ground Digital ground FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Alarm_Reset Sel_Clk CLK1 345 MPC99J93 Table 2. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. General Specifications Symbol VTT MM HBM CDM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model Latch-up Immunity Input Capacitance Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 175 1500 1000 100 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 110 MTBF = 9.1 years Min Typ VCC - 2 Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC TJ Thermal Resistance Junction to Case Operating Junction Temperature1 (continuous operation) 1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MPC99J93 to be used in applications requiring industrial temperature range. It is recommended that users of the MPC99J93 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. 346 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC99J93 Table 4. DC Characteristics (VCC = 3.3V 5%, TA = -40 to +85C) Symbol Characteristics Min Typ Max Unit Condition LVCMOS Control Inputs (MR, PLL_En, Sel_Clk, Man_Override, Alarm_Reset) VIH VIL IIN Input High Voltage Input Low Voltage Input Current1 2.0 VCC + 0.3 0.8 100 V V A VIN=VCC or GND LVCMOS Control Outputs (Clk_selected, Inp0bad, Inp1bad) VOH VOL Output High Voltage Output Low Voltage 2.0 0.55 V V IOH=-24 mA IOL= 24 mA LVPECL Clock Inputs (CLK0, CLK1, Ext_FB)2 VPP VCMR IIN DC Differential Input Voltage3 Differential Cross Point Voltage4 Input Current1 0.1 VCC-1.8 1.3 VCC-0.3 100 V V A Differential operation Differential operation VIN=VCC or GND LVPECL Clock Outputs (QA[1:0], QB[2:0]) VOH VOL Output High Voltage Output Low Voltage VCC-1.20 VCC-1.90 VCC-0.95 VCC-1.75 VCC-0.70 VCC-1.45 V V Termination 50 to VTT Termination 50 to VTT Supply Current IGND ICC_PLL 1. 2. 3. 4. Maximum Power Supply Current Maximum PLL Supply Current 180 15 mA mA GND pins VCC_PLL pin Inputs have internal pull-up/pull-down resistors affecting the input current. Clock inputs driven by differential LVPECL compatible signals. VPP is the minimum differential input voltage swing required to maintain AC characteristics. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 347 MPC99J93 Table 5. AC Characteristics (VCC = 3.3V 5%, TA = -40C to +85C)1 Symbol fref fVCO fMAX frefDC t() VPP VCMR tsk(O) per/cycle Characteristics Input Reference Frequency VCO Frequency Range2 Output Frequency Reference Input Duty Cycle Propagation Delay Differential Input Voltage4 Differential Input Crosspoint Voltage5 Output-to-Output Skew Rate of Change of Period within QA[2:0] or QB[1:0] within device QA[1:0]6 QB[2:0]6 QA[1:0]7 QB[2:0]7 DC tJIT(CC) tLOCK tr, tf 1. 2. 3. 4. Output Duty Cycle Cycle-to-Cycle Jitter Maximum PLL Lock Time Output Rise/Fall Time 0.05 RMS (1 ) 45 20 10 200 100 50 25 10 0.70 SPO, static phase offset3 CLK0, CLK1 to any Q (peak-to-peak) /4 feedback /4 feedback QA[1:0] QB[2:0] Min 50 200 50 100 25 -0.15 0.9 0.25 VCC-1.7 Typ Max 90 360 90 180 75 +0.17 1.8 1.3 VCC-0.3 50 80 50 25 400 200 55 Unit MHz MHz MHz MHz % ns ns V V ps ps ps ps ps ps % ps ms ns 20% to 80% PLL_EN=1 PLL_EN=0 PLL locked Condition PLL locked AC characteristics apply for parallel output termination of 50 to VCC - 2V. The input reference frequency must match the VCO lock range divided by the feedback divider ratio (FB): fref = fVCO / FB. CLK0, CLK1 to Ext_FB. VPP is the minimum differential input voltage swing required to maintain AC characteristics including SPO and device-to-device skew. Applicable to CLK0, CLK1 and Ext_FB. 5. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the V PP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the SPO, device and part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB. 6. Specification holds for a clock switch between two input signals (CLK0, CLK1) no greater than 400 ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. 7. Specification holds for a clock switch between two input signals (CLK0, CLK1) at any phase difference (180). Delta period change per cycle is averaged over the clock switch excursion. 348 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC99J93 APPLICATIONS INFORMATION The MPC99J93 is a dual clock PLL with on-chip Intelligent Dynamic Clock Switch (IDCS) circuitry. Definitions primary clock: The input CLK selected by Sel_Clk. secondary clock: The input CLK NOT selected by Sel_Clk. PLL reference signal: The CLK selected as the PLL reference signal by Sel_Clk or IDCS. (IDCS can override Sel_Clk). Status Functions Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as the PLL reference signal. Clk_Selected (H) indicates CLK1 is selected as the PLL reference signal. INP_BAD: Latched (H) when it's CLK is stuck (H) or (L) for at least one Ext_FB period (Pos to Pos or Neg to Neg). Cleared (L) on assertion of Alarm_Reset. Control Functions Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock. Alarm_Reset: Asserted by a negative edge. Generates a one-shot reset pulse that clears INPUT_BAD latches and Clk_Selected latch. PLL_En: While (L), the PLL reference signal is substituted for the VCO output. MR: While (L), internal dividers are held in reset which holds all Q outputs LOW. Man Override (H) (IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be the CLK selected by Sel_Clk. The status function INP_BAD is active in Man Override (H) and (L). Man Override (L) (IDCS is enabled, PLL functions enhanced). The first CLK to fail will latch it's INP_BAD (H) status flag and select the other input as the Clk_Selected for the PLL reference clock. Once latched, the Clk_Selected and INP_BAD remain latched until assertion of Alarm_Reset which clears all latches (INP_BADs are cleared and Clk_Selected = Sel_Clk). NOTE: If both CLKs are bad when Alarm_Reset is asserted, both INP_BADs will be latched (H) after one Ext_FB period and Clk_Selected will be latched (L) indicating CLK0 is the PLL reference signal. While neither INP_BAD is latched (H), the Clk_Selected can be freely changed with Sel_Clk. Whenever a CLK switch occurs, (manually or by IDCS), following the next negative edge of the newly selected PLL reference signal, the next positive edge pair of Ext_FB and the newly selected PLL reference signal will slew to alignment. To calculate the overall uncertainty between the input CLKs and the outputs from multiple MPC99J93's, the following procedure should be used. Assuming that the input CLKs to all MPC9993's are exactly in phase, the total uncertainty will be the sum of the static phase offset, max I/O jitter, and output to output skew. During a dynamic switch, the output phase between two devices may be increased for a short period of time. If the two input CLKs are 400ps out of phase, a dynamic switch of an MPC99J93 will result in an instantaneous phase change of 400ps to the PLL reference signal without a corresponding change in the output phase (due to the limited response of the PLL). As a result, the I/O phase of a device, undergoing this switch, will initially be 400ps and diminish as the PLL slews to its new phase alignment. This transient timing issue should be considered when analyzing the overall skew budget of a system. Hot insertion and withdrawal In PECL applications, a powered up driver will experience a low impedance path through an MPC99J93 input to its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input pins to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input signals. Acquiring Frequency Lock 1. While the MPC99J93 is receiving a valid CLK signal, assert Man_Override HIGH. 2. The PLL will phase and frequency lock within the specified lock time. 3. Apply a HIGH to LOW transition to Alarm_Reset to reset Input Bad flags. 4. De-assert Man_Override LOW to enable Intelligent Dynamic Clock Switch mode. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 349 MPC99J93 END 350 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Chapter Five Clock Synthesizer Data Sheets Clock Synthesizer Device Index Device Number Page Device Number Page MC12429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 MC12430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 MC12439 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 MPC9229 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 MPC9230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 MPC9239 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 MPC92429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 MPC92430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 MPC92432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 MPC92439 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 MPC92459 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 MPC926508 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 MPC9994 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 351 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC12429 Rev 7, 06/2001 High Frequency Clock Synthesizer The MC12429 is a general purpose synthesized clock source. Its internal VCO will operate over a range of frequencies from 200 to 400MHz. The differential PECL output can be configured to be the VCO frequency divided by 1, 2, 4, or 8. With the output configured to divide the VCO frequency by 1, and with a 16.000MHz external quartz crystal used to provide the reference frequency, the output frequency can be specified in 1MHz steps. The PLL loop filter is fully integrated so that no external components are required. The output frequency is configured using a parallel or serial interface. Features * * * * * * * * * * 25 to 400MHz Differential PECL Outputs 25 ps Peak-to-Peak Output Jitter Fully Integrated Phase-Locked Loop Minimal Frequency Over-Shoot Synthesized Architecture Serial 3-Wire Interface Parallel Interface for Power-Up Quartz Crystal Interface 28-Lead PLCC and 32-Lead LQFP Packages Operates from 3.3V or 5.0V Power Supply MC12429 HIGH FREQUENCY PLL CLOCK SYNTHESIZER FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-022 Functional Description The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference oscillator is divided by 16 before being sent to the phase detector. With a 16MHz crystal, this provides a reference frequency of 1MHz. Although this data sheet illustrates functionality only for a 16MHz crystal, any crystal in the 10-25MHz range can be used. The VCO within the PLL operates over a range of 200 to 400MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector. The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock. The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider (N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50 percent duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated in 50 to VCC - 2.0V. The positive reference for the output driver and the internal logic is separated from the power supply for the phase-locked loop to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the application of the chip. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the programming section for more information. FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 352 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12429 VCC 25 S_CLOCK S_DATA S_LOAD PLL_VCC NC NC XTAL1 26 27 28 1 2 3 4 5 XTAL2 6 OE 7 8 9 M[1] 10 M[2] 11 M[3] FOUT FOUT 24 23 GND 22 VCC 21 TEST 20 GND 19 18 17 16 N[1] N[0] M[8] M[7] M[6] M[5] M[4] N[1:0] 00 01 10 11 Output Division 1 2 4 8 28-Lead PLCC 15 14 13 12 P_LOAD M[0] Figure 1. 28-Lead (Top View) VCC S_CLOCK S_DATA S_LOAD PLL-VCC PLL-VCC N/C N/C XTAL1 1 2 3 4 32 FOUT FOUT GND 31 30 29 VCC 28 VCC 27 TEST GND 26 25 24 23 22 21 N/C N[1] N[0] M[8] M[7] M[6] M[5] M[4] 32-Lead LQFP 5 6 7 8 20 19 18 17 9 10 11 12 13 M[1] 14 M[2] 15 M[3] 16 N/C XTAL2 OE P_LOAD M[0] Figure 2. 32-Lead Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 353 MC12429 Table 1. Pin Descriptions Pin Inputs XTAL1, XTAL2 S_LOAD (Int. Pulldown) S_DATA (Int. Pulldown) S_CLOCK (Int. Pulldown) P_LOAD (Int. Pullup) M[8:0] (Int. Pullup) N[1:0] (Int. Pullup) OE (Int. Pullup) Outputs FOUT, FOUT TEST Power VCC PLL_VCC GND This is the positive supply for the internal logic and the output buffer of the chip, and is connected to +3.3V or 5.0V (VCC = PLL_VCC). Current drain through VCC 85mA. This is the positive supply for the PLL, and should be as noise-free as possible for low-jitter operation. This supply is connected to +3.3V or 5.0V (VCC = PLL_VCC). Current drain through PLL_VCC 15mA. These pins are the negative supply for the chip and are normally all connected to ground. These differential positive-referenced ECL signals (PECL) are the output of the synthesizer. The function of this output is determined by the serial configuration bits T[2:0]. These pins form an oscillator when connected to an external series-resonant crystal. This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH, thus the data must be stable on the HIGH-to-LOW transition of S_LOAD for proper operation. This pin acts as the data input to the serial configuration shift registers. This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge. This pin loads the configuration latches with the contents of the parallel inputs.The latches will be transparent when this signal is LOW, thus the parallel data must be stable on the LOW-to-HIGH transition of P_LOAD for proper operation. P_LOAD is state sensitive. These pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB. These pins are used to configure the output divider modulus. They are sampled on the LOW-to-HIGH transition of P_LOAD. Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output. Function 354 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12429 +3.3 or 5.0V PLL_VCC PHASE DETECTOR VCO XTAL1 OSC 5 XTAL2 9-BIT DIV M COUNTER 200-400 MHz DIV N (1, 2, 4, 8) 24 23 FOUT FOUT VCC0 25 1MHz FREF DIV 16 +3.3 or 5.0V 4 16MHz 20 OE S_LOAD P_LOAD 6 28 7 0 27 26 VCC1 21 +3.3 or 5.0V 8, 16 9 M[8:0] 17, 18 2 N[1:0] 22, 19 1 0 1 LATCH LATCH LATCH TEST S_DATA S_CLOCK 9-BIT SR 2-BIT SR 3-BIT SR Figure 3. MC12429 Block Diagram (28-Lead PLCC Pinout) PROGRAMMING INTERFACE Programming the device amounts to properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can by represented by this formula: (1) FOUT = (FXTAL / 16) x M / N Where FXTAL is the crystal frequency, M is the loop divider modulus, and N is the output divider modulus. Note that it is possible to select values of M such that the PLL is unable to achieve loop lock. To avoid this, always make sure that M is selected to be 200 M 400 for a 16MHz input reference. Assuming that a 16MHz reference frequency is used the above equation reduces to: FOUT = M / N Substituting the four values for N (1, 2, 4, 8) yields: Table 2. Output Frequency Range N 1 2 4 8 FOUT M M/2 M/4 M/8 Output Frequency Range 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz 25 - 50 MHz From these ranges the user will establish the value of N required, then the value of M can be calculated based on the appropriate equation above. For example if an output frequency of 131MHz was desired the following steps would be taken to identify the appropriate M and N values. 131MHz falls within the frequency range set by an N value of 2 so N [1:0] = 01. For N = 2 FOUT = M / 2 and M = 2 x FOUT. Therefore M = 131 x 2 = 262, so M[8:0] = 100000110. Following this same procedure a user can generate any whole frequency desired between 25 and 400MHz. Note that for N > 2 fractional values of FOUT can be realized. The size of the programmable frequency steps (and thus the indicator of the fractional output frequencies achievable) will be equal to FXTAL / 16 / N. For input reference frequencies other than 16MHz the set of appropriate equations can be deduced from equation 1. For computer applications another useful frequency base would be 16.666MHz. From this reference one can generate a family of output frequencies at multiples of the 33.333MHz PCI clock. As an example to generate a 133.333MHz clock from a 16.666MHz reference the following M and N values would be used: FOUT = 16.666 / 16 x M / N = 1.0416 x M / N Let N = 2, M = 133.3333 / 1.0416 x 2 = 256 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 355 MC12429 The value for M falls within the constraints set for PLL stability, therefore N[1:0] = 01 and M[8:0] = 10000000. If the value for M fell outside of the valid range a different N value would be selected to try to move M in the appropriate direction. The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[8:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[8:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 14 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 4 illustrates the timing diagram for both a parallel and a serial load of the MC12429 synthesizer. M[8:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the CMOS output may not be able to toggle fast enough for some of the higher output frequencies. The T2, T1 and T0 control bits are preset to `000' when P_LOAD is LOW so that the PECL FOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MC12429 itself. However the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MC12429 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree. Figure 5 shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 250MHz or less. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 125MHz as the minimum divide ratio of the N counter is 2. Note that the M counter output on the TEST output will not be a 50% duty cycle due to the way the divider is implemented. T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 TEST (Pin 20) SHIFT REGISTER OUT HIGH FREF M COUNTER OUT FOUT LOW MCNT FOUT/4 S_CLOCK S_DATA S_LOAD M[8:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 Last Bit Figure 4. Timing Diagram 356 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12429 FREF MCNT SCLOCK M COUNTER PLL 12429 VCO 0 1 SEL_CLK FDIV4 MCNT LOW FOUT MCNT FREF HIGH N DIVIDE (2, 4, 8, 16) FOUT (VIA ENABLE GATE) 7 TEST MUX 0 TEST LATCH SDATA SHIFT REG 14-BIT SLOAD T0 T1 T2 DECODE Reset PLOADB * T2=T1=1, T0=0: Test Mode (PLL bypass) * SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin. Figure 5. Serial Test Clock Block Diagram (PLL bypass) Table 3. DC Characteristics (VCC = 3.3V 5%) Symbol VIH VIL IIN VOH VOL VOH VOL ICC Characteristic Input HIGH Voltage Input LOW Voltage Input Current Output HIGH Voltage Output LOW Voltage Output HIGH Voltage1 TEST TEST FOUT, FOUT FOUT, FOUT VCC PLL_VCC 2.28 1.35 85 15 2.5 0.4 2.60 1.67 100 20 2.32 1.35 85 15 0C Min 2.2 0.8 1.0 2.5 0.4 2.49 1.67 100 20 2.38 1.35 85 15 Typ Max Min 2.2 0.8 1.0 2.5 0.4 2.565 1.70 100 20 25C Typ Max Min 2.2 0.8 1.0 70C Typ Max Unit V V mA V V V V mA IOH = -0.8mA IOL = 0.8mA VCCO = 3.3V2 VCCO = 3.3V2 Condition Output LOW Voltage1 Power Supply Current 1. 50 to VCC - 2.0V termination. 2. Output levels will vary 1:1 with VCC0 variation. Table 4. DC Characteristics (VCC = 5.0V 5%) Symbol VIH VIL IIN VOH VOL VOH VOL ICC Characteristic Input HIGH Voltage Input LOW Voltage Input Current Output HIGH Voltage Output LOW Voltage Output HIGH Voltage 1 0C Min 3.5 0.8 1.0 TEST TEST 2.5 0.4 3.98 3.05 85 15 4.30 3.37 100 20 4.02 3.05 2.5 Typ Max Min 3.5 25C Typ Max 0.8 1.0 2.5 0.4 4.19 3.37 85 15 100 20 4.08 3.05 Min 3.5 70C Typ Max 0.8 1.0 Unit V V mA V 0.4 4.265 3.40 85 15 100 20 V V V mA Condition IOH = -0.8mA IOL = 0.8mA VCCO = 5.0V2 VCCO = 5.0V2 FOUT, FOUT FOUT, FOUT VCC PLL_VCC Output LOW Voltage1 Power Supply Current 1. 50 to VCC - 2.0V termination. 2. Output levels will vary 1:1 with VCC0 variation. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 357 MC12429 Table 5. AC Characteristics (TA = 0 to 70C, VCC = 3.3V to 5.0V 5%) Symbol FMAXI FMAXO tLOCK tjitter ts Characteristic Maximum Input Frequency Maximum Output Frequency Maximum PLL Lock Time Period Deviation (Peak-to-Peak) Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD S_LOAD P_LOAD FOUT 20 20 20 20 20 50 50 300 800 S_CLOCK Xtal Oscillator VCO (Internal) FOUT Min 10 200 25 Max 10 20 400 400 10 25 Unit MHz MHz ms ps ns Note 2, See Applications Section Note 1 Condition Note 2 th tpwMIN tr, tf Hold Time Minimum Pulse Width Output Rise/Fall ns ns ps Note 2 20%-80%, Note 2 1. 10MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as a test clock in TEST_MODE 6. 2. 50 to VCC - 2.0V pulldown. APPLICATIONS INFORMATION Using the On-Board Crystal Oscillator The MC12429 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MC12429 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are recommended, but not required. Because the series resonant design is affected by capacitive loading on the xtal terminals loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance it may be required to place a resistance across the terminals to suppress the third harmonic. Although typically not required it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 and 1K. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately most crystals are characterized in a parallel resonant mode. Fortunately there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result a parallel resonant crystal can be used with the MC12429 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. Table 6 below specifies the performance requirements of the crystals to be used with the MC12429. Table 6. Recommended Crystal Specifications Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance1 75ppm at 25C 150pm 0 to 70C 0 to 70C 5-7pF 50 to 80 100W 5ppm/Yr (First 3 Years) 1. See accompanying text for series versus parallel resonant discussion. Power Supply Filtering The MC12429 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MC12429 provides separate power supplies for the digital ciruitry (VCC) and the internal PLL (PLL_VCC) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a 358 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12429 controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the PLL_VCC pin for the MC12429. Figure 6 illustrates a typical power supply filter scheme. The MC12429 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the PLL_VCC pin of the MC12429. From the data sheet the IPLL_VCC current (the current sourced through the PLL_VCC pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the PLL_VCC pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 6 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. 3.3V or 5.0V 3.3V or 5.0V Figure 7 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the 12429 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. C1 C1 R1 1 C3 C2 R1 = 10-15 C1 = 0.01F C2 = 22F C3 = 0.01F RS=10-15 PLL_VCC MC12429 VCC 0.01F 0.01F 22F L=1000H R=15 Xtal = VCC = GND = Via Figure 7. PCB Board Layout for MC12429 (28 PLCC) Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. Note the provisions for placing a resistor across the crystal oscillator terminals as discussed in the crystal oscillator section of this data sheet. Although the MC12429 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Figure 6. Power Supply Filter A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. Figure 6 shows a 1000H choke, this value choke will show a significant impedance at 10KHz frequencies and above. Because of the current draw and the voltage that must be maintained on the PLL_VCC pin a low DC resistance inductor is required (less than 15). Generally the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. The MC12429 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 7 shows a representative board layout for the MC12429. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 359 MC12429 Jitter Performance of the MC12429 The MC12429 exhibits long term and cycle-to-cycle jitter which rivals that of SAW based oscillators. This jitter performance comes with the added flexibility one gets with a synthesizer over a fixed frequency oscillator. 25 20 RMS Jitter (ps) 15 10 5 RMS Jitter (ps) 0 200 N=1 N=2 N=4 N=8 deviations of the jitter. Care must be taken that the measured edge is the edge immediately following the trigger edge. All of the jitter data reported on the MC12429 was collected in this manner. Figure 9 shows the jitter as a function of the output frequency. For the 12429 this information is probably of more importance. The flat line represents an RMS jitter value that corresponds to an 8 sigma 25ps peak-to-peak long term period jitter. The graph shows that for output frequencies from 87.5 to 400MHz the jitter falls within the 25ps peak-to-peak specification. The general trend is that as the output frequency is decreased the output edge jitter will increase. 25 20 15 10 5 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 Output Frequency (MHz) 6.25ps Reference 250 300 350 VCO Frequency (MHz) 400 Figure 8. RMS PLL Jitter versus VCO Frequency Figure 8 illustrates the RMS jitter performance of the MC12429 across its specified VCO frequency range. Note that the jitter is a function of both the output frequency as well as the VCO frequency, however the VCO frequency shows a much stronger dependence. The data presented has not been compensated for trigger jitter, this fact provides a measure of guardband to the reported data. The typical method of measuring the jitter is to accumulate a large number of cycles, create a histogram of the edge placements and record peak-to-peak as well as standard Figure 9. RMS Jitter versus Output Frequency The jitter data presented should provide users with enough information to determine the effect on their overall timing budget. The jitter performance meets the needs of most system designs while adding the flexibility of frequency margining and field upgrades. These features are not available with a fixed frequency SAW oscillator. 360 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC12430 Rev 6, 08/2004 High Frequency Clock Synthesizer The MC12430 is a general purpose synthesized clock source. Its internal VCO will operate over a range of frequencies from 400 to 800 MHz. The differential PECL output can be configured to be the VCO frequency divided by 1, 2, 4 or 8. With the output configured to divide the VCO frequency by 2, and with a 16.000 MHz external quartz crystal used to provide the reference frequency, the output frequency can be specified in 1 MHz steps. The PLL loop filter is fully integrated so that no external components are required. The synthesizer output frequency is configured using a parallel or serial interface. Features * * * * * * * * * * 50 to 800 MHz Differential PECL Outputs 25 ps Peak-to-Peak Output Jitter Fully Integrated Phase-Locked Loop Minimal Frequency Over-Shoot Synthesized Architecture Serial 3-Wire Interface Parallel Interface for Power-Up Quartz Crystal Interface 28-Lead PLCC and 32-Lead LQFP Packages Operates from 3.3 V or 5.0V Power Supply MC12430 (See Upgrade Product -- MPC9230) HIGH FREQUENCY PLL CLOCK SYNTHESIZER FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 FA SUFFIX 32-LEAD TQFP PACKAGE CASE 873A-03 Functional Description The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference oscillator is divided by 16 before being sent to the phase detector. With a 16 MHz crystal, this provides a reference frequency of 1 MHz. Although this data sheet illustrates functionality only for a 16 MHz crystal, any crystal in the 10-20 MHz range can be used. The VCO within the PLL operates over a range of 400 to 800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The output of this loop divider is applied to the phase detector. The phase detector and loop filter attempt to force the VCO output frequency to be M x 2 times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock. The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider (N divider) is configured through either the serial or the parallel interfaces and can provide one of four division ratios (1, 2, 4 or 8). This divider extends performance of the part while providing a 50 percent duty cycle. The output driver is driven differentially from the output divider and is capable of driving a pair of transmission lines terminated in 50 to VCC - 2.0 V. The positive reference for the output driver and the internal logic is separated from the power supply for the phase-locked loop to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the application of the chip. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the programming section for more information. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 361 MC12430 VCC 25 S_CLOCK S_DATA S_LOAD PLL_VCC FREF_EXT XTAL_SEL XTAL1 26 27 28 1 2 3 4 5 XTAL2 FOUT FOUT 24 23 GND 22 VCC 21 TEST 20 GND 19 18 17 16 N[1] N[0] M[8] M[7] M[6] M[5] M[4] INPUT 0 1 XTAL Enabled N[1:0] 00 01 10 11 Output Division 2 4 8 1 28-Lead PLCC 15 14 13 12 XTEL_SEL FREF_EXT Disabled OE 6 OE 7 8 9 M[1] 10 M[2] 11 M[3] P_LOAD M[0] Figure 1. 28-Lead Pinout (Top View) VCC S_CLOCK S_DATA S_LOAD PLL-VCC PLL-VCC FREF_EXT XTAL_SEL XTAL1 1 2 3 4 32 FOUT FOUT GND 31 30 29 VCC 28 VCC 27 TEST GND 26 25 24 23 22 21 N/C N[1] N[0] M[8] M[7] M[6] M[5] M[4] 32-Lead LQFP 5 6 7 8 20 19 18 17 12 13 M[1] 14 M[2] 15 M[3] 16 N/C 9 10 11 XTAL2 OE P_LOAD M[0] Figure 2. 32-Lead Pinout (Top View) 362 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12430 Table 1. Pin Descriptions Pin Name Inputs XTAL1, XTAL2 S_LOAD (Int. Pulldown) These pins form an oscillator when connected to an external series-resonant crystal. This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH, thus the data must be stable on the HIGH-to-LOW transition of S_LOAD for proper operation. This pin acts as the data input to the serial configuration shift registers. This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge. This pin loads the configuration latches with the contents of the parallel inputs.The latches will be transparent when this signal is LOW, thus the parallel data must be stable on the LOW-to-HIGH transition of P_LOAD for proper operation. P_LOAD is state sensitive. These pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB. These pins are used to configure the output divider modulus. They are sampled on the LOW-to-HIGH transition of P_LOAD. Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output. Function S_DATA S_CLOCK P_LOAD (Int. Pulldown) (Int. Pulldown) (Int. Pullup) M[8:0] N[1:0] OE Outputs FOUT, FOUT TEST Power VCC PLL_VCC GND Other FREF_EXT XTAL_SEL (Int. Pullup) (Int. Pullup) (Int. Pullup) These differential positive-referenced ECL signals (PECL) are the output of the synthesizer. The function of this output is determined by the serial configuration bits T[2:0]. The output is single-ended ECL. This is the positive supply for the internal logic and the output buffer of the chip, and is connected to +3.3V or 5.0V (VCC = PLL_VCC). Current drain through VCC 85mA. This is the positive supply for the PLL, and should be as noise-free as possible for low-jitter operation. This supply is connected to +3.3V or 5.0V (VCC = PLL_VCC). Current drain through PLL_VCC 15mA. These pins are the negative supply for the chip and are normally all connected to ground. (Int. Pulldown) (Int. Pullup) LVCMOS/CMOS input which can be used as the PLL reference. LVCMOS/CMOS input that selects between the crystal and the FREF_EXT source for the PLL reference signal. A HIGH selects the crystal input. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 363 MC12430 +3.3 or 5.0V PLL_VCC PHASE DETECTOR VCO XTAL1 OSC 5 OE S_LOAD P_LOAD 6 28 7 0 27 26 VCC1 21 +3.3 or 5.0V 8:16 9 M[8:0] N[1:0] 17, 18 2 22, 19 1 0 1 LATCH XTAL2 LATCH LATCH 9-BIT DIV M COUNTER DIV N (1, 2, 4, 8) VCCO 25 24 23 FOUT FOUT XTAL_SEL FREF_EXT 3 2 4 DIV 16 1MHz FREF +3.3 or 5.0V 16MHz 200-400 MHz DIV 2 400-800 MHz 20 TEST S_DATA S_CLOCK 9-BIT SR 2-BIT SR 3-BIT SR Figure 3. MC12430 Block Diagram (28-Lead PLCC Pinout) PROGRAMMING INTERFACE Programming the device amounts to properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can by represented by this formula: (1) FOUT = (FXTAL / 16) x M x 2 / N Where FXTAL is the crystal frequency, M is the loop divider modulus, and N is the output divider modulus. Note that it is possible to select values of M such that the PLL is unable to achieve loop lock. To avoid this, always make sure that M is selected to be 200 M 400 for any input reference. Assuming that a 16MHz reference frequency is used the above equation reduces to: FOUT = 2 x M / N Substituting the four values for N (1, 2, 4, 8) yields: Table 2. Output Frequency Range N 1 2 4 8 FOUT 2xM M M/2 M/4 Output Frequency Range 400 - 800 MHz 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz From these ranges the user will establish the value of N required, then the value of M can be calculated based on the appropriate equation above. For example if an output frequency of 131 MHz was desired the following steps would be taken to identify the appropriate M and N values. 131 MHz falls within the frequency range set by an N value of 4 so N [1:0] = 01. For N = 4 FOUT = M / 2 and M = 2 x FOUT. Therefore, M = 131 x 2 = 262, so M[8:0] = 100000110. Following this same procedure a user can generate any whole frequency desired between 50 and 800MHz. Note that for N > 2 fractional values of FOUT can be realized. The size of the programmable frequency steps (and thus the indicator of the fractional output frequencies achievable) will be equal to FXTAL / 8 / N. For input reference frequencies other than 16MHz, the set of appropriate equations can be deduced from equation 1. For computer applications another useful frequency base would be 16.666MHz. From this reference one can generate a family of output frequencies at multiples of the 33.333MHz PCI clock. As an example to generate a 133.333MHz clock from a 16.666MHz reference the following M and N values would be used: FOUT = 16.666 / 16 x M x 2 / N = 1.04166 x M x 2 / N Let N = 4, M = 133.3333 / 1.04166 x 2 = 256 364 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12430 The value for M falls within the constraints set for PLL stability, therefore N[1:0] = 01 and M[8:0} = 10000000. If the value for M fell outside of the valid range a different N value would be selected to try to move M in the appropriate direction. The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[8:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[8:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port, the S_CLOCK signal samples the information on the S_DATA line and loads it into a 14 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two and the M register with the final eight bits of the data stream on the S_DATA input. For each register, the most significant bit is loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 4 illustrates the timing diagram for both a parallel and a serial load of the MC12430 synthesizer. M[8:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. The T2, T1 and T0 control bits are preset to `000' when P_LOAD is LOW so that the PECL FOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MC12430 itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MC12430 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree. Figure 5 shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 250MHz or less. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 250MHz as the minimum divide ratio of the N counter is 1. Note that the M counter output on the TEST output will not be a 50% duty cycle due to the way the divider is implemented. T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 Test (Pin 20) SHIFT REGISTER OUT HIGH FREF M COUNTER OUT/2 FOUT LOW M COUNTER/2 in PLL Bypass Mode FOUT/4 S_CLOCK S_DATA S_LOAD M[8:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 Last Bit Figure 4. Timing Diagram FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 365 MC12430 FREF MCNT SCLOCK M COUNTER PLL 12430 VCO 0 1 SEL_CLK FDIV4 MCNT/2 LOW FOUT MCNT/2 MCNT/2 HIGH N DIVIDE (1, 2, 4, 8) FOUT (VIA ENABLE GATE) 7 TEST MUX 0 TEST LATCH SDATA SHIFT REG 14-BIT SLOAD T0 T1 T2 DECODE Reset PLOADB * T2=T1=1, T0=0: Test Mode (PLL bypass) * SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin. Figure 5. Serial Test Clock Block Diagram Table 3. DC Characteristics (VCC = 3.3V 5%) Symbol VIH VIL IIN VOH VOL VOH VOL ICC Characteristic Input HIGH Voltage Input LOW Voltage Input Current Output HIGH Voltage Output LOW Voltage Output HIGH Voltage 1 0C Min 2.2 0.8 1.0 TEST TEST 2.5 0.4 2.28 1.35 90 15 2.60 1.67 110 20 2.32 1.35 2.5 Typ Max Min 2.2 25C Typ Max 0.8 1.0 2.5 0.4 2.49 1.67 90 15 110 20 2.38 1.35 Min 2.2 70C Typ Max 0.8 1.0 Unit V V mA V 0.4 2.565 1.70 90 15 100 20 V V V mA Condition IOH = -0.8mA IOL = 0.8mA VCCO = 3.3V2 3 VCCO = 3.3V2 3 FOUT, FOUT FOUT, FOUT VCC PLL_VCC Output LOW Voltage1 Power Supply Current 1. See APPLICATIONS INFORMATION for output level versus frequency information. 2. Output levels will vary 1:1 with VCC0 variation. 3. 50 to VCC - 2.0V termination. Table 4. DC Characteristics (VCC = 5.0V 5%) Symbol VIH VIL IIN VOH VOL VOH VOL ICC Characteristic Input HIGH Voltage Input LOW Voltage Input Current Output HIGH Voltage Output LOW Voltage Output HIGH Voltage1 Output LOW Voltage1 Power Supply Current TEST TEST FOUT, FOUT FOUT, FOUT VCC PLL_VCC 3.98 3.05 90 15 2.5 0.4 4.30 3.37 110 20 4.02 3.05 90 15 0C Min 3.5 Typ Max 0.8 1.0 2.5 0.4 4.19 3.37 110 20 4.08 3.05 90 15 Min 3.5 25C Typ Max 0.8 1.0 2.5 0.4 4.265 3.40 100 20 Min 3.5 70C Typ Max 0.8 1.0 Unit V V mA V V V V mA IOH = -0.8mA IOL = 0.8mA VCCO = 5.0V2 3 VCCO = 5.0V2 3 Condition 1. See APPLICATIONS INFORMATION for output level versus frequency information. 2. Output levels will vary 1:1 with VCC0 variation. 3. 50 to VCC - 2.0V termination. 366 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12430 Table 5. AC Characteristics (TA = 0 to 70C, VCC = 3.3V to 5.0V 5%) Symbol FMAXI Characteristic Maximum Input Frequency S_CLOCK Xtal Oscillator FREF_EXT VCO (Internal) FOUT Min 10 10 400 -50 Max 10 20 Note1 800 800 10 25 65 ts Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD S_LOAD P_LOAD FOUT 20 20 20 20 20 50 50 300 800 ns MHz ms ps N = 2, 4, 8: Note3 N = 1; Note3 Note 3 Unit MHz Note 2 Condition FMAXO tLOCK tjitter Maximum Output Frequency Maximum PLL Lock Time Period Deviation (Peak-to-Peak)4 th tpwMIN tr, tf Hold Time Minimum Pulse Width Output Rise/Fall ns ns ps 20%-80%, Note3 1. Maximum frequency on FREF_EXT is a function of the internal M counter limitations. The phase detector can handle up to 100MHz on the input, but the M counter must remain in the valid range of 200 M 400. See the Programming Interface section on page 4 of this data sheet for more details. 2. 10MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as a test clock in TEST_MODE 6. 3. 50 to VCC - 2.0V pulldown. 4. See APPLICATIONS INFORMATION for additional information. APPLICATIONS INFORMATION Using the On-Board Crystal Oscillator The MC12430 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MC12430 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are recommended, but not required. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately, most crystals are characterized in a parallel resonant mode. Fortunately, there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result, a parallel resonant crystal can be used with the MC12430 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application, this level of inaccuracy is immaterial. Table 1 below specifies the performance requirements of the crystals to be used with the MC12430. Table 6. Recommended Crystal Specifications Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance1 75ppm at 25C 150pm 0 to 70C 0 to 70C 5-7pF 50 to 80 100W 5ppm/Yr (First 3 Years) 1. See accompanying text for series versus parallel resonant discussion. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 367 MC12430 Power Supply Filtering The MC12430 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MC12430 provides separate power supplies for the digital ciruitry (VCC) and the internal PLL (PLL_VCC) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the PLL_VCC pin for the MC12430. Figure 6 illustrates a typical power supply filter scheme. The MC12430 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the PLL_VCC pin of the MC12430. From the data sheet, the IPLL_VCC current (the current sourced through the PLL_VCC pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the PLL_VCC pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 6 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. 3.3V or 5.0V resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. The MC12430 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 7 shows a representative board layout for the MC12430. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 7 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the 12430 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. C1 C1 R1 1 C3 C2 R1 = 10-15 C1 = 0.01F C2 = 22F C3 = 0.01F Xtal = VCC = GND = Via RS=10-15 PLL_VCC MC12430 VCC 0.01F 0.01F 22F Figure 7. PCB Board Layout for MC12430 (28 PLCC) Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. Although the MC12430 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded Figure 6. Power Supply Filter A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000H choke will show a significant impedance at 10KHz frequencies and above. Because of the current draw and the voltage that must be maintained on the PLL_VCC pin a low DC resistance inductor is required (less than 15). Generally, the 368 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12430 due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Jitter Performance of the MC12430 The MC12430 exhibits long term and cycle-to-cycle jitter which rivals that of SAW based oscillators. This jitter performance comes with the added flexibility one gets with a synthesizer over a fixed frequency oscillator. 25 20 RMS Jitter (ps) 15 10 5 0 400 N=2 N=4 N=8 that corresponds to an 8 sigma 25ps peak-to-peak long term period jitter. The graph shows that for output frequencies from 87.5 to 400MHz the jitter falls within the 25ps peak-to-peak specification. The general trend is that as the output frequency is decreased the output edge jitter will increase. The jitter data from Figure 8 and Figure 9 do not include the performance of the MC12430 when the output is in the divide by 1 mode. In divide by one mode, the MC12430 output jitter distribution is bimodal. Since a bimodal distribution cannot be accurately represented with an rms value, peak-to-peak values of jitter for the divide by one mode are presented. Figure 10 shows the peak-to-peak jitter of the 12430 output in divide by one mode as a function of output frequency. Notice that as with the other modes the jitter improves with increasing frequency. The 65 ps shown in the data sheet table represents a conservative value of jitter, especially for the higher VCO, and thus output frequencies. 140 Peak-to-Peak Jitter (ps) 120 100 80 60 40 400 500 600 700 Output Frequency (MHz) 800 Spec Limit N=1 500 600 700 VCO Frequency (MHz) 800 Figure 8. RMS PLL Jitter versus VCO Frequency Figure 8 illustrates the RMS jitter performance of the MC12430 across its specified VCO frequency range. Note that the jitter is a function of both the output frequency as well as the VCO frequency, however the VCO frequency shows a much stronger dependence. The data presented has not been compensated for trigger jitter, this fact provides a measure of guardband to the reported data. The typical method of measuring the jitter is to accumulate a large number of cycles, create a histogram of the edge placements and record peak-to-peak as well as standard deviations of the jitter. Care must be taken that the measured edge is the edge immediately following the trigger edge. The oscillator cannot collect adjacent pulses, rather it collects pulses from a very large sample of pulses. 25 RMS Jitter (ps) 20 15 10 5 0 25 50 75 100 125 150 175 200 225 250 275300 325 350 375 400 Output Frequency (MHz) 6.25ps Reference Figure 10. Peak-to-Peak Jitter versus Output Frequency The jitter data presented should provide users with enough information to determine the effect on their overall timing budget. The jitter performance meets the needs of most system designs while adding the flexibility of frequency margining and field upgrades. These features are not available with a fixed frequency SAW oscillator. Output Voltage Swing vs Frequency In the divide by one mode, the output rise and fall times will limit the peak to peak output voltage swing. For a 400 MHz output, the peak to peak swing of the 12430 output will be approximately 700 mV. This swing will gradually degrade as the output frequency increases, at 800 MHz the output swing will be reduced to approximately 500 mV. For a worst case analysis, it would be safe to assume that the 12430 output will always generate at least a 500mV output swing. Note that most high speed ECL receivers require only a few hundred millivolt input swings for reliable operation. As a result, the output generated by the 12430 will, under all conditions, be sufficient for clocking standard ECL devices. Note that if a larger swing is required the MC12430 could drive a clock fanout buffer like the MC100EP111. Figure 9. RMS Jitter versus Output Frequency Figure 9 shows the jitter as a function of the output frequency. For the MC12430 this information is probably of more importance. The flat line represents an RMS jitter value FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 369 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC12439 Rev 6, 09/2001 High Frequency Clock Synthesizer The MC12439 is a general purpose synthesized clock source. Its internal VCO will operate over a range of frequencies from 400 to 800 MHz. The differential PECL output can be configured to be the VCO frequency divided by 1, 2, 4, or 8. With the output configured to divide the VCO frequency by 1, and with a 16.66 MHz external quartz crystal used to provide the reference frequency, the output frequency can be specified in 16.66 MHz steps. The output frequency is configured using a parallel or serial interface. Features * * * * * * * * * 50 to 800 MHz Differential PECL Outputs 25 ps Typical Peak-to-Peak Output Jitter Minimal Frequency Over-Shoot Synthesized Architecture Serial 3-Wire Interface Parallel Interface for Power-Up Quartz Crystal Interface 28-Lead PLCC Package Operates from 3.3 V or 5.0 V Power Supply MC12439 HIGH FREQUENCY PLL CLOCK SYNTHESIZER FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 Functional Description The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference oscillator is divided by 2 before being sent to the phase detector. With a 16.66 MHz crystal, this provides a reference frequency of 8.33 MHz. Although this data sheet illustrates functionality only for a 16 MHz and 16.66 MHz crystal, any crystal in the 10-20 MHz range can be used. In addition to the crystal, an LVCMOS input can also be used as the PLL reference. The reference is selected via the XTAL_SEL input pin. The VCO within the PLL operates over a range of 400 to 800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector. The phase detector and loop filter attempt to force the VCO output frequency to be 2 x M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock. The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider is configured through either the serial or the parallel interfaces and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50 percent duty cycle. The output driver is driven differentially from the output divider and is capable of driving a pair of transmission lines terminated in 50 to VCC - 2.0 V. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs to reduce component count in the application of the chip. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAMMING INTERFACE for more information. The TEST output reflects various internal node values and is controlled by the T[2:0] bits in the serial data stream. See PROGRAMMING INTERFACE for more information. The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments. 370 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12439 VCC 25 S_CLOCK S_DATA S_LOAD PLL_VCC PWR_DOWN FREF_EXT XTAL1 26 27 28 1 2 3 4 5 XTAL2 6 OE 7 8 9 M[1] 10 M[2] 11 M[3] FOUT FOUT 24 23 GND 22 VCC 21 TEST 20 GND 19 18 17 16 15 14 13 12 N[1] N[0] NC XTAL_SEL M[6] M[5] M[4] Input PWR_DOWN XTAL_SEL OE 0 FOUT FREF_EXT Disabled 1 FOUT/16 XTAL Enabled N[1:0] 00 01 10 11 Output Division 2 4 8 1 P_LOAD M[0] Figure 1. 28-Lead Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 371 MC12439 Table 1. Pin Descriptions Pin Name Inputs XTAL1, XTAL2 S_LOAD -- Int. Pulldown These pins form an oscillator when connected to an external series-resonant crystal. This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH, thus the data must be stable on the HIGH-to-LOW transition of S_LOAD for proper operation. This pin acts as the data input to the serial configuration shift registers. This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge. This pin loads the configuration latches with the contents of the parallel inputs.The latches will be transparent when this signal is LOW, thus the parallel data must be stable on the LOW-to-HIGH transition of P_LOAD for proper operation. These pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH transition of P_LOAD. M[6] is the MSB, M[0] is the LSB. These pins are used to configure the output divider modulus. They are sampled on the LOW-to-HIGH transition of P_LOAD. P_LOAD is state sensitive. Active HIGH Output Enable. Type Function S_DATA S_CLOCK P_LOAD Int. Pulldown Int. Pulldown Int. Pullup M[6:0] N[1:0] OE Outputs FOUT, FOUT TEST Power VCC PLL_VCC GND Other PWR_DOWN FREF_EXT XTAL_SEL Int. Pullup Int. Pullup Int. Pullup -- -- These differential positive-referenced ECL signals (PECL) are the output of the synthesizer. The function of this output is determined by the serial configuration bits T[2:0]. -- -- -- This is the positive supply for the chip, and is connected to +3.3 V or 5.0 V (VCC = PLL_VCC). This is the positive supply for the PLL and should be as noise-free as possible for low-jitter operation. This supply is connected to +3.3 V or 5.0 V (VCC = PLL_VCC). These pins are the negative supply for the chip and are normally all connected to ground. Int. Pulldown Int. Pulldown Int. Pullup LVCMOS input that forces the FOUT output to synchronously reduce its frequency by a factor of 16. LVCMOS input which can be used as the PLL reference frequency. LVCMOS input that selects between the XTAL and FREF_EXT PLL reference inputs. A HIGH selects the XTAL input. 372 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12439 XTAL_SEL 15 PWR_DOWN 2 PLL_VCC FREF_EXT 3 +3.3 or 5.0V 0 1 DIV 2 PHASE DETECTOR VCO POWER DOWN +3.3 or 5.0V VCC0 DIV N (1, 2, 4, 8) 25 24 23 FOUT FOUT 4 16.66MHz 5 XTAL1 OSC XTAL2 7-BIT DIV M COUNTER DIV 2 400-800 MHz 20 OE S_LOAD P_LOAD 6 28 7 0 27 26 VCC1 21 +3.3 or 5.0V 8 14 7 M[6:0] 17, 18 2 N[1:0] 22, 19 1 0 1 LATCH LATCH LATCH TEST S_DATA S_CLOCK 7-BIT SR 2-BIT SR 3-BIT SR Figure 2. MC12439 Block Diagram PROGRAMMING INTERFACE Programming the device amounts to properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can by represented by this formula: (1) FOUT = FXTAL x M / N Where FXTAL is the crystal frequency, M is the loop divider modulus, and N is the output divider modulus. Note that it is possible to select values of M such that the PLL is unable to achieve loop lock. To avoid this, always make sure that M is selected to be 25 M 50 for a 16MHz input reference. For input references other than 16MHz, the valid M values can be calculated from the valid VCO range of 400-800MHz. Assuming that a 16MHz reference frequency is used, the above equation reduces to: FOUT = 16 x M / N Substituting the four values for N (1, 2, 4, 8) yields: Table 2. Output Frequency Range N 1 2 4 8 FOUT 16 x M 8xM 4xM 2xM Output Frequency Range 400 - 800 MHZ 200 - 400 MHZ 100 - 200 MHZ 50 - 100 MHZ From these ranges, the user will establish the value of N required, then the value of M can be calculated based on the appropriate equation above. For example, if an output frequency of 384MHz was desired, the following steps would be taken to identify the appropriate M and N values. 384 MHz falls within the frequency range set by an N value of 2, so N [1:0] = 00. For N = 2, FOUT = 8M and M = FOUT / 8. Therefore, M = 384 / 8 = 48, so M[8:0] = 0110000. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 373 MC12439 For input reference frequencies other than 16MHz, the set of appropriate equations can be deduced from equation 1. For computer applications, another useful frequency base would be 16.666MHz. From this reference, one can generate a family of output frequencies at multiples of the 33.333 MHz PCI clock. As an example, to generate a 533.333MHz clock from a 16.666MHz reference, the following M and N values would be used: FOUT = 16.666 x M / N Let N = 1, M = 533.333 / 16.666 = 32 The value for M falls within the constraints set for PLL stability (400/16.666 M 800/16.666; 24 M 48), therefore N[1:0] = 11 and M[6:0} = 0100000. If the value for M fell outside of the valid range, a different N value would be selected to try to move M in the appropriate direction. The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[6:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW, the input latches will be transparent and any changes on the M[6:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port, the S_CLOCK signal samples the information on the S_DATA line and loads it into a 12 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two and the M register with the final eight bits of the data stream on the S_DATA input. For each register, the most significant bit is loaded first (T2, N1 and M6). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 3 illustrates the timing diagram for both a parallel and a serial load of the MC12439 synthesizer. M[6:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the CMOS output may not be able to toggle fast enough for some of the higher output frequencies. The T2, T1 and T0 control bits are preset to `000' when P_LOAD is LOW so that the PECL FOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MC12439 itself. However the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110, the MC12439 is placed in PLL bypass mode. In this mode, the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode, the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree. Figure 4 shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level, the input frequency is limited to 250 MHz or less. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 250 MHz as the minimum divide ratio of the N counter is 1. Note that the M counter output on the TEST output will not be a 50% duty cycle due to the way the divider is implemented. T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 TEST (Pin 20) SHIFT REGISTER OUT HIGH FREF M COUNTER OUT/2 FOUT LOW M COUNTER/2 in PLL Bypass Mode FOUT/4 S_CLOCK S_DATA S_LOAD M[6:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M6 M5 M4 M3 M2 M1 M0 Last Bit Figure 3. Timing Diagram 374 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12439 FREF MCNT SCLOCK M COUNTER Shift Reg. Out LATCH SDATA SHIFT REG 12-BIT SLOAD T0 T1 T2 DECODE Reset PLOAD PLL 12439 VCO 0 1 SEL_CLK FDIV4 MCNT/2 LOW FOUT MCNT/2 FREF HIGH N DIVIDE (1, 2, 4, 8) FOUT (VIA ENABLE GATE) 7 TEST MUX 0 TEST * T2=T1=1, T0=0: Test Mode (PLL bypass) * SCLOCK is selected, MCNT/2 is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin PLOAD acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin. Figure 4. Serial Test Clock Block Diagram Table 3. DC Characteristics (VCC = 3.3 V 5%) Symbol VIH VIL IIN IOH VOH VOL VOH VOL ICC 1. 2. 3. 4. Characteristic Input HIGH Voltage Input LOW Voltage Input Current Output HIGH Current1 Output HIGH Voltage Output LOW Voltage Output HIGH Voltage2 Output LOW Voltage2 Power Supply Current FOUT, FOUT TEST TEST FOUT, FOUT 2.28 FOUT, FOUT 1.35 VCC PLL_VCC 90 15 2.5 0.4 2.60 1.67 110 20 2.32 1.35 90 15 Min 2.0 0C Typ Max 0.8 1.0 50 2.5 0.4 2.49 1.67 110 20 2.38 1.35 90 15 Min 2.0 25C Typ Max 0.8 1.0 50 2.5 0.4 2.565 1.70 110 20 Min 2.0 70C Typ Max 0.8 1.0 50 Unit V V mA mA V V V V mA Continuous IOH = -0.8mA IOL = 0.8mA VCCO = 3.3V3 4 VCCO = 3.3V3 4 Condition Maximum IOH spec implies the device can drive 25 impedance with the PECL outputs. See APPLICATIONS INFORMATION for output level versus frequency information. Output levels will vary 1:1 with VCC variation. 50 to VCC - 2.0V termination. 0C Typ 25C Typ 70C Typ Table 4. DC Characteristics (VCC = 5.0 V 5%) Symbol VIH VIL IIN IOH VOH VOL VOH VOL ICC 1. 2. 3. 4. Characteristic Input HIGH Voltage Input LOW Voltage Input Current Output HIGH Current1 Output HIGH Voltage Output LOW Voltage Output LOW Voltage Power Supply Current 2 Min 3.5 Max 0.8 1.0 Min 3.5 Max 0.8 1.0 50 Min 3.5 Max 0.8 1.0 50 Unit V V mA mA V V V V mA Condition FOUT, FOUT TEST TEST FOUT, FOUT FOUT, FOUT VCC PLL_VCC 50 3.8 0.4 3.98 3.05 90 15 4.30 3.37 110 20 4.02 3.05 90 15 3.8 Continuous IOH = -0.8 mA IOL = 0.8 mA VCCO = 5.0 V3 4 VCCO = 5.0 V3 4 3.8 0.4 4.19 3.37 110 20 4.08 3.05 90 15 0.4 4.265 3.40 110 20 Output HIGH Voltage2 Maximum IOH spec implies the device can drive 25 impedance with the PECL outputs. See APPLICATIONS INFORMATION for output level versus frequency information. Output levels will vary 1:1 with VCC0 variation. 50 to VCC - 2.0V termination. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 375 MC12439 Table 5. AC Characteristics (TA = 0 to 70C; VCC = 3.3 to 5.0V 5%) Symbol FMAXI Characteristic Maximum Input Frequency S_CLOCK Xtal Oscillator FREF_EXT VCO (Internal) FOUT Min 10 10 400 50 1 Max 10 20 Note1 900 800 10 25 65 20 20 20 20 20 50 50 300 800 ps Note2 ns Note2 ns MHz ms ps N = 2,4,8; Note2 N = 1; Note2 ns Note2 Unit MHz Condition FMAXO tLOCK tjitter ts Maximum Output Frequency Maximum PLL Lock Time Period Deviation (Peak-to-Peak)3 Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD th tpwMIN tr, tf Hold Time S_DATA to S_CLOCK M, N to P_LOAD Minimum Pulse Width Output Rise/Fall Time S_LOAD P_LOAD 1. Maximum frequency on FREF_EXT is a function of the internal M counter limitations. The phase detector can handle up to 100 MHz on the input, but the M counter must remain in the valid range of 25 M 50. See PROGRAMMING INTERFACE in this data sheet for more details. 2. 50 to VCC - 2.0 V pulldown. 3. See APPLICATIONS INFORMATION for additional information. 376 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12439 APPLICATIONS INFORMATION Using the On-Board Crystal Oscillator The MC12439 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the MC12439 as possible to avoid any board level parasitics. To facilitate co-location, surface mount crystals are recommended but not required. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately, most crystals are characterized in a parallel resonant mode. Fortunately, there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result, a parallel resonant crystal can be used with the MC12439 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application, this level of inaccuracy is immaterial. Table 6 below specifies the performance requirements of the crystals to be used with the MC12439. Table 6. Crystal Specifications Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance1 75 ppm at 25C 150 pm 0 to 70C 0 to 70C 5-7 pF 50 to 80 100 W 5 ppm/Yr (First 3 Years) PLL_VCC MC12439 VCC 0.01F 0.01F 22F RS=10-15 controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simplest form of isolation is a power supply filter on the PLL_VCC pin for the MC12439. Figure 5 illustrates a typical power supply filter scheme. The MC12439 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the PLL_VCC pin of the MC12439. From the data sheet, the IPLL_VCC current (the current sourced through the PLL_VCC pin) is typically 15mA (20 mA maximum), assuming that a minimum of 3.0 V must be maintained on the PLL_VCC pin very little DC voltage drop can be tolerated when a 3.3 V VCC supply is used. The resistor shown in Figure 5 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. 3.3V or 5.0V Figure 5. Power Supply Filter A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 H choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the PLL_VCC pin, a low DC resistance inductor is required (less than 15 ). Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. The MC12439 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 6 shows a representative board layout for the MC12439. There exist many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 6 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general 1. See accompanying text for series versus parallel resonant discussion. Power Supply Filtering The MC12439 is a mixed analog/digital product, and as such, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MC12439 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (PLL_VCC) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 377 MC12439 purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the 12439 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. C1 C1 25 20 RMS Jitter (ps) 15 10 5 600 700 800 VCO Frequency (MHz) Figure 7. RMS PLL Jitter versus VCO Frequency Figure 7 illustrates the RMS jitter performance of the MC12439 across its specified VCO frequency range. Note that the jitter is a function of both the output frequency as well as the VCO frequency, however the VCO frequency shows a much stronger dependence. The data presented has not been compensated for trigger jitter, this fact provides a measure of guardband to the reported data. The typical method of measuring the jitter is to accumulate a large number of cycles, create a histogram of the edge placements and record peak-to-peak as well as standard deviations of the jitter. Care must be taken that the measured edge is the edge immediately following the trigger edge. The oscilloscope cannot collect adjacent pulses, rather it collects pulses from a very large sample of pulses. 25 RMS Jitter (ps) 20 15 10 5 0 25 50 75 100 125 150 175 200 225 250 275300 325 350 375 400 Output Frequency (MHz) 6.25ps Reference N=2 N=4 N=8 0 400 500 R1 1 C3 C2 R1 = 10-15 C1 = 0.01F C2 = 22F C3 = 0.01F Xtal = VCC = GND = Via Figure 6. PCB Board Layout for MC12439 Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit, and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. Although the MC12439 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Jitter Performance of the MC12439 The MC12439 exhibits long term and cycle-to-cycle jitter which rivals that of SAW based oscillators. This jitter performance comes with the added flexibility one gets with a synthesizer over a fixed frequency oscillator. Figure 8. RMS Jitter versus Output Frequency Figure 8 shows the jitter as a function of the output frequency. For the 12439, this information is probably of more importance. The flat line represents an RMS jitter value that corresponds to an 8 sigma 25 ps peak-to-peak long term period jitter. The graph shows that for output frequencies from 87.5 to 400 MHz the jitter falls within the 25 ps peak-to-peak specification. The general trend is that as the output frequency is decreased, the output edge jitter will increase. The jitter data from Figure 7 does not include the performance of the 12439 when the output is in the divide by 1 mode. In divide by one mode, the MC12439 output jitter distribution is bimodal. Since a bimodal distribution cannot be accurately represented with an rms value, peak-to-peak values of jitter for the divide by one mode are presented. 378 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC12439 Figure 9 shows the peak-to-peak jitter of the 12439 output in divide by one mode as a function of output frequency. Notice that as with the other modes, the jitter improves with increasing frequency. The 65 ps shown in the data sheet table represents a conservative value of jitter, especially for the higher VCO, and thus output frequencies. The jitter data presented should provide users with enough information to determine the effect on their overall timing budget. The jitter performance meets the needs of most system designs while adding the flexibility of frequency margining and field upgrades. These features are not available with a fixed frequency SAW oscillator. Output Voltage Swing vs Frequency In the divide by one mode, the output rise and fall times will limit the peak to peak output voltage swing. For a 400 MHz output, the peak to peak swing of the 12439 output will be approximately 700 mV. This swing will gradually degrade as the output frequency increases, at 800 MHz the output swing will be reduced to approximately 500 mV. For a worst case analysis, it would be safe to assume that the 12439 output will always generate at least a 400mV output swing. Note that most high speed ECL receivers require only a few hundred millivolt input swings for reliable operation. As a result, the output generated by the 12439 will, under all conditions, be sufficient for clocking standard ECL devices. Note that if a larger swing is desired, the MC12439 could drive the clock fanout buffer MC100EP111. 140 Peak-to-Peak Jitter (ps) 120 100 80 60 40 400 500 600 700 Output Frequency (MHz) 800 Spec Limit N=1 Figure 9. Peak-to-Peak versus Output Frequency FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 379 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9229 Rev 2, 05/2004 400 MHz Low Voltage PECL Clock Synthesizer The MPC9229 is a 3.3 V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 25 MHz to 400 MHz and the support of differential PECL output signals the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * * 25 MHz to 400 MHz synthesized clock output signal Differential PECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation 3.3 V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 32-lead LQFP and 20-lead PLCC packaging 32-lead and 20-lead Pb-free Package Available SiGe Technology Ambient temperature range 0C to +70C Pin and function compatible to the MC12429 MPC9229 400 MHz LOW VOLTAGE CLOCK SYNTHESIZER SCALE 2:1 DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-02 FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 4M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC -2.0 V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. Refer to the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. 380 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9229 XTAL_IN XTAL_OUT XTAL 10 - 20 MHz / 16 Ref VCO /4 PLL 800 - 1800 MHz FB / 0 TO / 511 9-BIT M-DIVIDER 9 /1 /2 /4 /8 00 01 10 11 OE fOUT fOUT SYNC TEST 2 N-LATCH 3 T-LATCH TEST VCC P_LOAD S_LOAD LE P/S M-LATCH 0 BITS 5-13 S_DATA S_CLOCK VCC M[0:8] N[1:0] OE 1 BITS 3-4 0 14-BIT SHIFT REGISTER 1 BITS 0-2 Figure 1. MPC9229 Logic Diagram M[8] M[7] M[6] M[5] 18 TEST GND GND fOUT VCC fOUT VCC S_CLOCK S_DATA S_LOAD VCC_PLL NC NC XTAL_IN 25 26 27 28 1 2 3 4 5 XTAL_OUT 24 23 22 21 20 19 18 17 16 24 N[1] N[0] M[8] M[7] M[6] M[5] M[4] GND TEST VCC VCC GND fOUT fOUT VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 M[4] 17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT 13 12 11 10 9 8 XTAL_IN N[1] MPC9229 N[0] 3 NC 15 14 13 12 MPC9229 6 OE 7 P_LOAD 8 M[0] 9 M[1] 10 M[2] 11 M[3] 2 4 5 6 7 S_CLOCK S_DATA NC S_LOAD VCC_PLL Figure 2. MPC9229 28-Lead PLCC Pinout (Top View) Figure 3. MPC9229 32-Lead LQFP Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA VCC_PLL NC 381 MPC9229 Table 1. Pin Configurations Pin XTAL_IN, XTAL_OUT fOUT, fOUT TEST S_LOAD Output Output Input 0 I/O Default Type Analog LVPECL Crystal oscillator interface. Differential clock output. Function LVCMOS Test and device diagnosis output. LVCMOS Serial configuration control input. This inputs controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. LVCMOS Parallel configuration control input. This input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive LVCMOS Serial configuration data input. LVCMOS Serial configuration clock input. LVCMOS Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. LVCMOS Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD LVCMOS Output enable (active high). The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the fOUT output. OE = L low stops fOUT in the logic low state (fOUT = L, fOUT = H) Ground VCC VCC Negative power supply (GND). Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. PLL positive power supply (analog power supply). P_LOAD Input 1 S_DATA S_CLOCK M[0:8] N[1:0] OE Input Input Input Input Input 0 0 1 1 1 GND VCC VCC_PLL Supply Supply Supply Supply Supply Supply Table 2. Output Frequency Range and Pll Post-Divider N N 1 0 0 1 1 0 0 1 0 1 Output Division 1 2 4 8 Output Frequency Range 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz 25 - 50 MHz 382 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9229 Table 3. General Specifications Symbol VTT MM HBM LU CIN JA Characteristics Output Termination Voltage ESD protection (Machine Model) ESD protection (Human Body Model) Latch-Up Immunity Input Capacitance LQFP 32 Thermal resistance junction to ambient JESD 51-3, single layer test board 200 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC -2 Max Unit V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Condition JESD 51-6, 2S2P multilayer test board JC LQFP 32 Thermal resistance junction to case C/W MIL-SPEC 883E Method 1012.1 Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C) Symbol VIH VIL IIN Input High Voltage Input Low Voltage Input Current 1 Characteristics Min 2.0 Typ Max VCC + 0.3 0.8 200 Unit V V A Condition LVCMOS LVCMOS VIN = VCC or GND LVCMOS control inputs (P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1], OE) Differential clock output fOUT2 VOH VOL VOH VOL ICC_PLL ICC Output High Voltage3 Output Low Voltage 3 VCC -1.02 VCC -1.95 2.0 VCC -0.74 VCC -1.60 V V V LVPECL LVPECL IOH = -0.8 mA IOL = 0.8 mA VCC_PLL Pins All VCC Pins Test and diagnosis output TEST Output High Voltage3 Output Low Voltage3 Maximum PLL Supply Current Maximum Supply Current 0.55 20 100 V mA mA Supply current 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 to VTT = VCC -2 V. 3. The MPC9229 TEST output levels are compatible to the MC12429 output levels. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 383 MPC9229 Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C)1 Symbol fXTAL fVCO fMAX Characteristics Crystal interface frequency range VCO frequency range2 N = 00 (/ 1) N = 01 (/ 2) N = 10 (/ 4) N = 11 (/ 8) Min 10 800 200 100 50 25 45 0.05 0 50 20 20 20 20 20 90 130 160 190 70 120 140 170 10 50 Typ Max 20 1600 400 200 100 50 55 0.3 10 Unit MHz MHz MHz MHz MHz MHz % ns MHz ns ns ns ns ns ns ps ps ps ps ps ps ps ps ms 20% to 80% Condition Output Frequency DC tr, tf fS_CLOCK tP,MIN tS Output duty cycle Output Rise/Fall Time Serial interface programming clock frequency3 Minimum pulse width Setup Time (S_LOAD, P_LOAD) S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD N = 00 (/ 1) N = 01 (/ 2) N = 10 (/ 4) N = 11 (/ 8) N = 00 (/ 1) N = 01 (/ 2) N = 10 (/ 4) N = 11 (/ 8) tS tJIT(CC) Hold Time Cycle-to-cycle jitter tJIT(PER) Period Jitter tLOCK Maximum PLL Lock Time 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL M / 4. 3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. Refer to APPLICATIONS INFORMATION for more details. 384 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9229 PROGRAMMING INTERFACE Programming the MPC9229 Programming the MPC9229 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: (1) fOUT = (fXTAL / 16) (4 M) / (4 N) or (2) fOUT = (fXTAL / 16) M / N where fXTAL is the crystal frequency, M is the PLL feedback-divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured Table 7. MPC9229 Frequency Operating Range M 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 510 M[8:0] 010100000 010101010 010110100 010111110 011001000 011010010 011011100 011100110 011110000 011111010 100000100 100001110 100011000 100100010 100101100 100110110 101000000 101001010 101010100 101011110 101101000 101110010 101111100 110000110 110010000 110011010 110100100 110101110 110111000 111000010 111111110 800 825 850 875 900 925 950 975 1000 1025 1050 1075 1100 1125 1275 810 840 870 900 930 960 990 1020 1050 1080 1110 1140 1170 1200 1230 1260 1290 1320 1350 1530 805 840 875 910 945 980 1015 1050 1085 1120 1155 1190 1225 1260 1295 1330 1365 1400 1435 1470 1505 1540 1575 800 840 880 920 960 100 1040 1080 1120 1160 1200 1240 1280 1320 1360 1400 1440 1480 1520 1560 1600 810 855 900 945 990 1035 1080 1125 1170 1215 1260 1305 1350 1395 1440 1485 1530 1575 VCO frequency for a crystal interface frequency of 10 12 14 16 18 20 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1600 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 190 195 200 50 52.5 55 57.5 60 62.5 65 67.5 70 72.5 75 77.5 80 82.5 85 87.5 90 92.5 95 97.5 100 25 26.25 27.50 28.75 30 31.25 32.50 33.75 35 36.25 37.5 38.75 40 41.25 42.5 43.75 45 46.25 47.5 48.75 50 Output frequency for fXTAL = 16 MHz and for N = 1 2 4 16 to match the VCO frequency range of 800 to 1600 MHz in order to achieve stable PLL operation: (3) MMIN = 4 fVCO,MIN / fXTAL and MMAX = 4 fVCO,MAX / fXTAL (4) For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M = 200 and M = 400. Table 7 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation (2) reduces to: fOUT = M / N FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 385 MPC9229 Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 8. Output Frequency Range for fXTAL = 16 MHz N 1 0 0 1 1 0 0 1 0 1 Value 1 2 4 8 fOUT M M/2 M/4 M/8 fOUT Range 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz 25 - 50 MHz fOUT Step 1 MHz 500 kHz 250 kHz 125 kHz Example Frequency Calculation for an 16 MHz Input Frequency If an output frequency of 131 MHz was desired the following steps would be taken to identify the appropriate M and N values. According to Table 8, 131 MHz falls in the frequency set by an value of 2 so N[1:0] = 01. For N = 2 the output frequency is fOUT = M / 2 and M = fOUT x 2. Therefore M = 2 x 131 = 262, so M[8:0] = 100000110. Following this procedure a user can generate any whole frequency between 25 MHz and 400 MHz. Note than for N > 2 fractional values of can be realized. The size of the programmable frequency steps (and thus the indicator of the fractional output frequencies achievable) will be equal to: fSTEP = fXTAL / 16 / N APPLICATIONS INFORMATION Using the Parallel and Serial Interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW-to-HIGH transition will latch the information present on the M[8:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW, the input latches will be transparent and any changes on the M[8:0] and N[1:0] inputs will affect the fOUT output pair. To use the serial port, the S_CLOCK signal samples the information on the S_DATA line and loads it into a 14-bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1, and M8). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH-to-LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 4 illustrates the timing diagram for both a parallel and a serial load of the MPC9229 synthesizer. M[8:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. Using the Test and Diagnosis Output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents fOUT, the CMOS output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. The T2, T1, and T0 control bits are preset to `000' when P_LOAD is LOW so that the PECL fOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC9229 itself. However the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110, the MPC9229 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the fOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving fOUT directly gives the user more control on the test clocks sent through the clock tree. Figure 6 shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level, the input frequency is limited to 200 MHz. This means the fastest the fOUT pin can be toggled via the S_CLOCK is 100 MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle. Table 9. Test and Debug Configuration for TEST T[2:0] T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 TEST Output 14-bit shift register out1 Logic 1 fXTAL / 16 M-Counter out fOUT Logic 0 M-Counter out in PLL-bypass mode fOUT / 4 1. Clocked out at the rate of S_CLOCK Table 10. Debug Configuration for PLL Bypass1 Output fOUT TEST S_CLOCK / N M-Counter out2 Configuration 1. T[2:0] = 110. AC specifications do not apply in PLL bypass mode 2. Clocked out at the rate of S_CLOCK / (4 N) 386 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9229 S_CLOCK S_DATA S_LOAD M[8:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 Last Bit Figure 4. Serial Interface Timing Diagram Power Supply Filtering The MPC9229 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device characteristics. The MPC9229 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC9229. Figure 5 illustrates a typical power supply filter scheme. The MPC9229 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the MPC9229 pin of the MPC9229. From the data sheet the VCC_PLL current (the current sourced through the VCC_PLL pin) is maximum 20 mA, assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. The resistor shown in Figure 5 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 H choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than 15 ). RF = 10-15 CF = 22 F C2 VCC VCC_PLL MPC9229 VCC C1, C2 = 0.01...0.1 F C1 Figure 5. VCC_PLL Power Supply Filter Layout Recommendations The MPC9229 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 6 shows a representative board layout for the MPC9229. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 6 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC9229 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. Although the MPC9229 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 387 MPC9229 PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. C1 C1 1 CF C2 R1 = 10-15 C1 = 0.01 F C2 = 22 F C3 = 0.01 F XTAL = VCC = GND = Via close to the MPC9229 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are recommended, but not required. Because the series resonant design is affected by capacitive loading on the xtal terminals loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance, it may be required to place a resistance across the terminals to suppress the third harmonic. Although typically not required, it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 and 1 K. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately most crystals are characterized in a parallel resonant mode. Fortunately there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result a parallel resonant crystal can be used with the MPC9229 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. Table 11 below specifies the performance requirements of the crystals to be used with the MPC9229. Table 11. Recommended Crystal Specifications Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance1 75 ppm at 25C 150 pm 0 to 70C 0 to 70C 5 - 7pF 50 to 80 100 W 5 ppm/Yr (First 3 Years) Figure 6. PCB Board Layout Recommendation for the PLCC28 Package Using the On-Board Crystal Oscillator The MPC9229 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as 1. Refer to the accompanying text for series versus parallel resonant discussion. 388 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9230 Rev 4, 07/2004 800 MHz Low Voltage PECL Clock Synthesizer The MPC9230 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 50 MHz to 800 MHz(1) and the support of differential PECL output signals the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * * * 50 MHz to 800 MHz1 synthesized clock output signal Differential PECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference clock input 3.3V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 32-lead LQFP and 28-lead PLCC packaging 32-lead and 28-lead Pb-free package available SiGe Technology Ambient temperature range -40C to +85C Pin and function compatible to the MC12430 MPC9230 800 MHz LOW VOLTAGE CLOCK SYNTHESIZER FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 FA SUFFIX 32-LEAD TQFP PACKAGE CASE 873A-03 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz.1 Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 8M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz1). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC - 2.0V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. 1. The VCO frequency range of 800-1600 MHz is available at an ambient temperature range of 0 to 70C. At -40 to +85C, the VCO frequency (output frequency) is limited to max. 1500 MHz (750 MHz) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 389 MPC9230 XTAL_IN XTAL_OUT FREF_EXT XTAL 10 - 20 MHz /16 Ref VCO /2 PLL 800 - 1800 MHz /1 /2 /4 /8 11 00 01 10 OE FOUT FOUT FB VCC XTAL_SEL /0 TO /511 9-BIT M-DIVIDER 9 VCC P_LOAD S_LOAD LE P/S 0 BITS 5-13 S_DATA S_CLOCK VCC 1 BITS 3-4 14-BIT SHIFT REGISTER 0 1 BITS 0-2 M-LATCH /2 2 N-LATCH TEST 3 T-LATCH TEST M[0:8] N[1:0] OE Figure 1. MPC9230 Logic Diagram M[8] M[7] M[6] M[5] 18 FOUT TEST FOUT GND GND VCC VCC S_CLOCK S_DATA S_LOAD VCC_PLL FREF_EXT XTAL_SEL XTAL_IN 26 27 28 1 2 3 4 25 24 23 22 21 20 19 24 18 17 16 N[1] N[0] M[8] M[7] M[6] M[5] M[4] GND TEST VCC VCC GND FOUT FOUT VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 M[4] 17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT 13 12 11 10 9 8 XTAL_IN N[1] 2 N[0] 3 NC MPC9230 15 14 13 12 MPC9230 5 XTAL_OUT 6 OE 7 P_LOAD 8 M[0] 9 M[1] 10 M[2] 11 M[3] 4 5 6 7 S_CLOCK S_DATA S_LOAD FREF_EXT Figure 2. MPC9230 28-Lead PLCC Pinout (Top View) Figure 3. MPC9230 32-Lead Package Pinout (Top View) 390 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA XTAL_SEL VCC_PLL VCC_PLL MPC9230 Table 1. Pin Configurations Pin XTAL_IN, XTAL_OUT FREF_EXT FOUT, FOUT TEST XTAL_SEL S_LOAD Input Output Output Input Input 1 0 0 I/O Default Type Analog LVCMOS LVPECL LVCMOS LVCMOS LVCMOS Crystal oscillator interface Alternative PLL reference input Differential clock output Test and device diagnosis output PLL reference select input Serial configuration control input. This input controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. Parallel configuration control input. This input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive. Serial configuration data input. Serial configuration clock input. Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD. Output enable (active high) The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the FOUT output. Negative power supply (GND). Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. PLL positive power supply (analog power supply). Function P_LOAD Input 1 LVCMOS S_DATA S_CLOCK M[0:8] N[1:0] OE Input Input Input Input Input 0 0 1 1 1 LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS GND VCC VCC_PLL Supply Supply Supply Ground VCC VCC Table 2. Output Frequency Range and PLL Post-Divider N N 1 0 0 1 1 0 0 1 0 1 Output Division 2 4 8 1 Output Frequency Range for TA = 0C to +70C 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz 400 - 800 MHz Output Frequency Range for TA = -40C to +85C 200 - 375 MHz 100 - 187.5 MHz 50 - 93.75 MHz 400 - 750 MHz Table 3. Function Table Input XTAL_SEL OE 0 FREF_EXT Outputs disabled. FOUT is stopped in the logic low state (FOUT = L, FOUT = H) 1 XTAL interface Outputs enabled FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 391 MPC9230 Table 4. General Specifications Symbol VTT MM HBM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Input Capacitance LQFP 32 Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 200 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2 Max Unit V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC LQFP 32 Thermal Resistance Junction to Case Table 5. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Characteristics Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Min -0.3 -0.3 -0.3 Max 4.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 6. DC Characteristics (VCC = 3.3V 5%, TA = 0C to +70C) Symbol Characteristics Min Typ Max Unit V V A Condition LVCMOS LVCMOS VIN = VCC or GND LVCMOS Control Inputs (FREF_EXT, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE) VIH 2.0 VCC + 0.3 Input High Voltage VIL IIN Input Low Voltage Input Current 1 2 0.8 200 Differential Clock Output FOUT VOH Output High Voltage VOL Output Low Voltage Test and Diagnosis Output TEST VOH Output High Voltage VOL Output Low Voltage Supply Current ICC_PLL Maximum PLL Supply Current ICC Maximum Supply Current VCC-1.02 VCC-1.95 VCC-1.02 VCC-1.95 VCC-0.74 VCC-1.60 VCC-0.74 VCC-1.60 20 110 V V V V mA mA LVPECL LVPECL LVPECL LVPECL VCC_PLL Pins All VCC Pins 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 to VTT = VCC - 2V. 392 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9230 Table 7. AC Characteristics (VCC = 3.3V 5%, TA = -40C to +85C) Symbol VIH VIL IIN Characteristics Min 2.0 Typ Max VCC + 0.3 0.8 200 Unit V V A Condition LVCMOS Control Inputs (FREF_EXT, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE) Input High Voltage Input Low Voltage Input Current1 LVCMOS LVCMOS VIN = VCC or GND Differential Clock Output FOUT2 VOH VOL Output High Voltage Output Low Voltage VCC-1.1 VCC-1.95 VCC-0.74 VCC-1.65 V V LVPECL LVPECL Test and Diagnosis Output TEST VOH VOL Output High Voltage Output Low Voltage VCC-1.1 VCC-1.95 VCC-0.74 VCC-1.65 V V LVPECL LVPECL Supply Current ICC_PLL ICC Maximum PLL Supply Current Maximum Supply Current 20 110 mA mA VCC_PLL Pins All VCC Pins 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 to VTT = VCC - 2V. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 393 MPC9230 Table 8. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C)1 Symbol fXTAL fREF fVCO fMAX Characteristics Crystal Interface Frequency Range FREF_EXT Reference Frequency Range VCO Frequency Range3 Output Frequency N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) Min 10 10 800 400 200 100 50 0 50 45 0.05 S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) 20 20 20 20 20 80 90 130 160 60 70 120 140 10 50 55 0.3 Typ Max 20 (fVCO,MAX/M)42 1600 800 400 200 100 10 Unit MHz MHz MHz MHz MHz MHz MHz MHz ns % ns ns ns ns ns ns ps ps ps ps ps ps ps ps ms 20% to 80% Condition fS_CLOCK tP,MIN DC tr, tf tS Serial Interface Programming Clock Frequency4 Minimum Pulse Width Output Duty Cycle Output Rise/Fall Time Setup Time (S_LOAD, P_LOAD) tH tJIT(CC) Hold Time Cycle-to-Cycle Jitter tJIT(PER) Period Jitter tLOCK Maximum PLL Lock Time 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The maximum frequency on FREF_EXT is a function of the max. VCO frequency and the M counter. M should be higher than 160 for stable PLL operation. 3. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL M / 4. 4. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. See APPLICATIONS INFORMATION for more details. 394 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9230 Table 9. AC Characteristics (VCC = 3.3V 5%, TA = -40C to +85C)1 Symbol fXTAL fREF fVCO fMAX Characteristics Crystal Interface Frequency Range FREF_EXT Reference Frequency Range VCO Frequency Range3 Output Frequency N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) Min 10 10 800 400 200 100 50 0 50 45 0.05 S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) 20 20 20 20 20 80 90 130 160 60 70 120 140 10 50 55 0.3 Typ Max 20 (fVCO,MAX/M)*4 1500 750.00 375.00 187.50 93.75 10 2 Unit MHz MHz MHz MHz MHz MHz MHz MHz ns % ns ns ns ns ns ns ps ps ps ps ps ps ps ps ms Condition fS_CLOCK tP,MIN DC tr, tf tS Serial Interface Programming Clock Frequency4 Minimum Pulse Width Output Duty Cycle Output Rise/Fall Time Setup Time (S_LOAD, P_LOAD) 20% to 80% tH tJIT(CC) Hold Time Cycle-to-Cycle Jitter tJIT(CC) Period Jitter tLOCK Maximum PLL Lock Time 1. AC characteristics apply for parallel output termination of 50 to VTT 2. The maximum frequency on FREF_EXT is a function of the max. VCO frequency and the M counter. M should be higher than 160 for stable PLL operation 3. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL M / 4. 4. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. See APPLICATIONS INFORMATION for more details. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 395 MPC9230 PROGRAMMING INTERFACE Programming the MPC9230 Programming the MPC9230 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: (1) FOUT = (fXTAL / 16) (4 M) / (2 N) or (2) FOUT = (fXTAL / 8) M / N where fXTAL is the crystal frequency, M is the PLL feedbackdivider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured to Table 10. MPC9230 Frequency Operating Range VCO frequency for an crystal interface frequency of [MHz] M 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 M[8:0] 010100000 010101010 010110100 010111110 011001000 011010010 011011100 011100110 011110000 011111010 100000100 100001110 100011000 100100010 100101100 100110110 101000000 101001010 101010100 101011110 101101000 101110010 101111100 110000110 110010000 110011010 110100100 110101110 110111000 111000010 800 825 850 875 900 925 950 975 1000 1025 1050 1075 1100 1125 810 840 870 900 930 960 990 1020 1050 1080 1110 1140 1170 1200 1230 1260 1290 1320 1350 805 840 875 910 945 980 1015 1050 1085 1120 1155 1190 1225 1260 1295 1330 1365 1400 1435 1470 1505a 1540a 1575a 800 840 880 920 960 100 1040 1080 1120 1160 1200 1240 1280 1320 1360 1400 1440 1480 15201 15601 1600 1 match the VCO frequency range of 800 to 1600 MHz in order to achieve stable PLL operation: (3) MMIN = 4fVCO,MIN / fXTAL and MMAX = 4fVCO,MAX / fXTAL (4) For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M=200 and M = 400. Table 10 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation (2) reduces to: (5) FOUT = 2 M / N Output frequency for fXTAL=16 MHz and for N = 1 2 4 8 10 12 14 16 18 20 800 850 810 855 900 945 990 1035 1080 1125 1170 1215 1260 1305 1350 1395 1440 1485 1530 1575 1 1 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1 400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 700 720 740 7602 7802 800 2 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 3802 3902 400 2 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 1902 1952 200 2 50 52.5 55 57.5 60 62.5 65 67.5 70 72.5 75 77.5 80 82.5 85 87.5 90 92.5 952 97.52 1002 16001 1. This VCO frequency is only available at the 0C to +70C temperature range. 2. This output frequency is only available at the 0C to +70C temperature range. 396 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9230 Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 11. Output Frequency Range for fXTAL = 16 MHz N 1 0 Value 00 01 10 11 2 4 8 1 FOUT M M/2 M/4 2M Output Output Frequency Frequency Range for Range for TA = 0C to 70C TA = -40C to 85C 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz 400 - 800 MHz 200 - 375 MHz 100 - 187.5 MHz 50 - 93.75 MHz 400 - 750 MHz FOUT Step 1 MHz 500 kHz 250 kHz 2 MHz Example Frequency Calculation for an 16 MHz Input Frequency If an output frequency of 131 MHz was desired the following steps would be taken to identify the appropriate M and N values. According to Table 11, 131 MHz falls in the frequency set by a value of 4 so N[1:0] = 01. For N = 4 the output frequency is FOUT = M / 2 and M = FOUT x 2. Therefore M = 2 x 131 = 262, so M[8:0] = 010000011. Following this procedure a user can generate any whole frequency between 50 MHz and 800 MHz. Note than for N > 2 fractional values of can be realized. The size of the programmable frequency steps (and thus the indicator of the fractional output frequencies achievable) will be equal to: fSTEP = fXTAL / 8 / N APPLICATIONS INFORMATION Using the Parallel and Serial Interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[8:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[8:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 14 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 4 illustrates the timing diagram for both a parallel and a serial load of the MPC9230 synthesizer. M[8:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. Using the Test and Diagnosis Output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the LVPECL compatible TEST output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. The T2, T1 and T0 control bits are preset to `000' when P_LOAD is LOW so that the LVPECL compatible FOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC9230 itself. However the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC9230 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree. Table 12 shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 50 MHz as the divide ratio of the Post-PLL divider is 4 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle. Table 12. Test and Debug Configuration for TEST T[2:0] T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 TEST Output 14-bit shift register out1 Logic 1 fXTAL / 16 M-Counter out FOUT Logic 0 M-Counter out in PLL-bypass mode FOUT / 4 1. Clocked out at this rate of S_CLOCK Table 13. Debug Configuration for PLL Bypass1 Output FOUT TEST Configuration S_CLOCK / N M-Counter out2 1. T[2:0]=110. AC specifications do not apply in PLL bypass mode 2. Clocked out at the rate of S_CLOCK/(2N) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 397 MPC9230 S_CLOCK S_DATA S_LOAD M[8:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 Last Bit Figure 4. Serial Interface Timing Diagram Power Supply Filtering The MPC9230 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device characteristics. The MPC9230 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC9230. Figure 5 illustrates a typical power supply filter scheme. The MPC9230 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the MPC9230 pin of the MPC9230. From the data sheet, the VCC_PLL current (the current sourced through the VCC_PLL pin) is maximum 20 mA, assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. The resistor shown in Figure 5 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 H choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than 15 ). RF = 10-15 CF = 22 F C2 VCC VCC_PLL MPC9230 VCC C1, C2 = 0.01...0.1 F C1 Figure 5. VCC_PLL Power Supply Filter Layout Recommendations The MPC9230 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 6 shows a representative board layout for the MPC9230. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 6 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC9230 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. Although the MPC9230 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential 398 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9230 PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. C1 C1 1 CF C2 XTAL = VCC = GND = Via recommended, but not required. Because the series resonant design is affected by capacitive loading on the XTAL terminals loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance it may be required to place a resistance across the terminals to suppress the third harmonic. Although typically not required it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 and 1 K. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately most crystals are characterized in a parallel resonant mode. Fortunately there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result a parallel resonant crystal can be used with the MPC9230 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. Table 14 below specifies the performance requirements of the crystals to be used with the MPC9230. Table 14. Recommended Crystal Specifications Parameter Crystal Cut Resonance Value Fundamental AT Cut Series Resonance1 75ppm at 25C 150pm 0 to 70C 0 to 70C 5-7pF 50 to 80 100 5ppm/Yr (First 3 Years) Figure 6. PCB Board Layout Recommendation for the PLCC28 Package Using the On-Board Crystal Oscillator The MPC9230 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC9230 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging 1. See accompanying text for series versus parallel resonant discussion. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 399 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9239 Rev 2, 03/2003 900 MHz Low Voltage LVPECL Clock Synthesizer The MPC9239 is a 3.3 V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from 3.125 MHz to 900 MHz and the support of differential LVPECL output signals the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * * 3.125 MHz to 900 MHz synthesized clock output signal Differential LVPECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference input 3.3 V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 28 PLCC and 32 LQFP packaging SiGe Technology Ambient temperature range 0C to + 70C Pin and function compatible to the MC12439 MPC9239 900 MHz LOW VOLTAGE CLOCK SYNTHESIZER FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC - 2.0 V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. Refer to PROGRAMMING INTERFACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the fOUT by 16. The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the fOUT input will step back up to its programmed frequency in four discrete increments. 400 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9239 XTAL_IN XTAL_OUT fREF_EXT VCC XTAL_SEL VCC P_LOAD S_LOAD LE P/S 0 S_DATA S_CLOCK BITS 11-5 VCC 1 BITS 3-4 12-BIT SHIFT REGISTER 0 1 BITS 0-2 XTAL 10 - 20 MHz 1 /2 0 Ref VCO /2 PLL 800 - 1800 MHz FB /0 TO /127 7-BIT M-DIVIDER 9 M-LATCH /2 /1 /2 /4 /8 11 00 01 10 /16 1 OE 0 fOUT fOUT TEST 2 N-LATCH 3 T-LATCH TEST M[0:6] N[1:0] PWR_DOWN OE Figure 1. MPC9239 Logic Diagram XTAL_SEL M[6] M[5] 18 TEST GND S_CLOCK S_DATA S_LOAD VCC_PLL PWR_DOWN fREF_EXT XTAL_IN 2 6 2 7 2 8 1 2 3 4 25 24 23 22 21 20 GND fOUT VCC fOUT VCC 19 18 17 16 N[1] N[0] NC XTAL_SEL M[6] M[5] M[4] 24 GND TEST VCC VCC GND fOUT fOUT VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 M[4] 17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT 13 12 11 10 9 8 XTAL_IN N[1] N[0] 3 NC MPC9239 15 14 13 12 MPC9239 5 XTAL_OUT 6 OE 7 P_LOAD 8 M[0] 9 M[1] 10 M[2] 11 M[3] 2 NC 4 5 6 7 VCC_PLL VCC_PLL S_CLOCK S_DATA Figure 2. MPC9239 28-Lead PLCC Pinout (Top View) Figure 3. MPC9239 32-Lead LQFP Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA PWR_DOWN S_LOAD fREF_EXT 401 MPC9239 Table 1. Pin Configurations Pin XTAL_IN, XTAL_OUT fREF_EXT fOUT, fOUT TEST XTAL_SEL PWR_DOWN Input Output Output Input Input 1 0 0 I/O Default Type Analog Crystal oscillator interface. Function LVCMOS Alternative PLL reference input. LVPECL Differential clock output. LVCMOS Test and device diagnosis output. LVCMOS PLL reference select input. LVCMOS Configuration input for power down mode. Assertion (deassertion) of power down will decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps. PWR_DOWN assertion (deassertion) is synchronous to the input reference clock. LVCMOS Serial configuration control input. This inputs controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. LVCMOS Parallel configuration control input. this input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive. LVCMOS Serial configuration data input. LVCMOS Serial configuration clock input. LVCMOS Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. LVCMOS Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD. LVCMOS Output enable (active high). The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the fOUT output. OE = L low stops fOUT in the logic low stat (fOUT = L, fOUT = H). Ground VCC VCC Negative power supply (GND). Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. PLL positive power supply (analog power supply). Do not connect. S_LOAD Input 0 P_LOAD Input 1 S_DATA S_CLOCK M[0:6] N[1:0] OE Input Input Input Input Input 0 0 1 1 1 GND VCC VCC_PLL NC Supply Supply Supply Table 2. Output Frequency Range and PLL Post-Divider N PWR_DOWN 0 0 0 0 1 1 1 1 N 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 VCO Output Frequency Division 2 4 8 1 32 64 128 16 fOUT Frequency Range 200 - 450 MHz 100 - 225 MHz 50 - 112.5 MHz 400 - 900 MHz 12.5 - 28.125 MHz 6.25 - 14.0625 MHz 3.125 - 7.03125 MHz 25 - 56.25 MHz 402 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9239 Table 3. Function Table Input XTAL_SEL OE PWR_DOWN 0 fREF_EXT Outputs disabled. fOUT is stopped in the logic low state (fOUT = L, fOUT = H) Output divider / 1 1 XTAL interface Outputs enabled Output divider / 16 Table 4. General Specifications Symbol VTT MM HBM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Input Capacitance LQFP 32 Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 200 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2 Max Unit V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Condition JESD 51-6, 2S2P multilayer test board JC LQFP 32 Thermal Resistance Junction to Case C/W MIL-SPEC 883E Method 1012.1 Table 5. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 403 MPC9239 Table 6. DC Characteristics (VCC = 3.3V 5%, TA = 0C to +70C) Symbol VIH VIL IIN Input High Voltage Input Low Voltage Input Current1 2 Characteristics Min 2.0 Typ Max VCC + 0.3 0.8 200 Unit V V A Condition LVCMOS LVCMOS VIN = VCC or GND LVCMOS Control Inputs (fREF_EXT, PWR_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE) Differential Clock Output fOUT VOH VOL VOH VOL ICC_PLL ICC Output High Voltage3 Output Low Voltage 3 VCC-1.02 VCC-1.95 2.0 VCC-0.74 VCC-1.60 V V V LVPECL LVPECL IOH = -0.8 mA IOL = 0.8 mA VCC_PLL Pins All VCC Pins Test and Diagnosis Output TEST Output High Voltage3 Output Low Voltage3 Maximum PLL Supply Current Maximum Supply Current 62 0.55 20 100 V mA mA Supply Current 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 to VTT = VCC - 2 V. 3. The MPC9239 TEST output levels are compatible to the MC12429 output levels. The MPC9239 is capable of driving 25 loads. Table 7. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C)1 Symbol fXTAL fVCO fMAX Characteristics Crystal Interface Frequency Range VCO Frequency Range2 Output Frequency N = 11 (/ 1) N = 00 (/ 2) N = 01 (/ 4) N = 10 (/ 8) (S_LOAD, P_LOAD) Min 10 800 400 300 100 50 0 50 45 0.05 S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD N = 11 (/ 1) N = 00 (/ 2) N = 01 (/ 4) N = 10 (/ 8) N = 11 (/ 1) N = 00 (/ 2) N = 01 (/ 4) N = 10 (/ 8) 20 20 20 20 20 60 90 120 160 40 65 90 120 10 50 55 0.3 Typ Max 20 1800 900 450 225 112.5 10 Unit MHz MHz MHz MHz MHz MHz MHz ns % ns ns ns ns ns ns ps ps ps ps ps ps ps ps ms 20% to 80% PWR_DOWN = 0 Condition fS_CLOCK tP,MIN DC tr, tf tS Serial Interface Programming Clock Frequency3 Minimum Pulse Width Output Duty Cycle Output Rise/Fall Time Setup Time tS tJIT(CC) Hold Time Cycle-to-Cycle Jitter tJIT(PER) Period Jitter tLOCK Maximum PLL Lock Time 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL 2 M. 3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. Refer to APPLICATIONS INFORMATION for more details. 404 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9239 Table 8. MPC9239 Frequency Operating Range (in MHz) M 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 M[6:0] 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 800 820 840 860 880 900 920 940 960 980 1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1260 1260 1280 816 840 864 888 912 936 960 984 1008 1032 1056 1080 1104 1128 1152 1176 1200 1224 1248 1272 1296 1320 1344 1368 1392 1416 1440 1488 1512 1512 1536 812 840 875 868 896 924 952 980 1008 1036 1064 1092 1120 1148 1176 1204 1232 1260 1288 1316 1344 1372 1400 1428 1456 1484 1512 1540 1568 1596 1624 1652 1680 1736 1764 1764 1792 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 828 864 900 936 972 1008 1044 1080 1116 1152 1188 1224 1260 1296 1332 1368 1404 1440 1476 1512 1548 1584 1620 1656 1692 1728 1764 1800 VCO frequency for a crystal interface frequency of 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz 800 840 880 920 960 1000 1040 1080 1120 1160 1200 1240 1280 1320 1360 1400 1440 1480 1520 1560 1600 1640 1680 1720 1760 1800 400 416 432 448 464 480 496 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 784 800 816 832 848 864 880 896 200 208 216 224 232 240 248 256 264 272 280 288 296 304 312 320 328 336 344 352 360 368 376 384 392 400 408 416 424 432 440 448 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 220 224 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 Output frequency for fXTAL=16 MHz and for N = 1 2 4 8 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 405 MPC9239 PROGRAMMING INTERFACE Programming the MPC9239 Programming the MPC9239 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: (1) fOUT = (fXTAL / 2) (M 4) / (N 2) or (2) fOUT = fXTAL M / N where fXTAL is the crystal frequency, M is the PLL feedback-divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured to match the VCO frequency range of 800 to 1800 MHz in order to achieve stable PLL operation: (3) MMIN = fVCO,MIN / (2 fXTAL) and (4) MMAX = fVCO,MAX / (2 fXTAL) For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M = 25 and M = 56. Table 8 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation (2) reduces to: fOUT = 16 M / N Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 9. Output Frequency Range for fXTAL = 10 MHz N 1 0 0 1 1 0 0 1 0 1 Value 2 4 8 1 fOUT 8M 4M 2M 16M fOUT Range 200-450 MHz 100-225 MHz 50-112.5 MHz 400-900 MHz fOUT Step 8 MHz 4 MHz 2 MHz 16 MHz Example Calculation for an 16 MHz Input Frequency For example, if an output frequency of 384 MHz was desired, the following steps would be taken to identify the appropriate M and N values. 384 MHz falls within the frequency range set by an N value of 2, so N[1:0]=00. For N = 2, fOUT = 8M, and M = fOUT / 8. Therefore, M = 384 / 8 = 48, so M[6:0] = 0110000. Following this procedure a user can generate any whole frequency between 50 MHz and 900 MHz. The size of the programmable frequency steps will be equal to: fSTEP = fXTAL / N APPLICATIONS INFORMATION Using the Parallel and Serial Interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[6:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[6:0] and N[1:0] inputs will affect the fOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 12 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two, and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1, and M6). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 4 illustrates the timing diagram for both a parallel and a serial load of the MPC9239 synthesizer. M[6:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. Using the Test and Diagnosis Output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents fOUT, the LVCMOS output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. The T2, T1, and T0 control bits are preset to `000' when P_LOAD is LOW so that the PECL fOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC9239 itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC9239 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the fOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving fOUT directly gives the user more control on the test clocks sent through the clock tree shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the fOUT pin can be toggled via the S_CLOCK is 100 MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle. 406 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9239 Table 10. Test and Debug Configuration for TEST T[2:0] T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 TEST Output 12-bit shift register out1 Logic 1 fXTAL / 2 M-Counter out fOUT Logic 0 M-Counter out in PLL-bypass mode fOUT / 4 Table 11. Debug Configuration for PLL Bypass1 Output fOUT TEST S_CLOCK / N M-Counter out2 Configuration 1. T[2:0] = 110. AC specifications do not apply in PLL bypass mode. 2. Clocked out at the rate of S_CLOCK / (2 N) 1. Clocked out at the rate of S_CLOCK. S_CLOCK S_DATA S_LOAD M[6:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M6 M5 M4 M3 M2 M1 M0 Last Bit Figure 4. Serial Interface Timing Diagram Power Supply Filtering The MPC9239 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device characteristics. The MPC9239 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC9239. Figure 5 illustrates a typical power supply filter scheme. The MPC9239 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the MPC9239 pin of the MPC9239. From the data sheet, the VCC_PLLcurrent (the current sourced through the VCC_PLL pin) is maximum 20 mA, assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. The resistor shown in Figure 5 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 H choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than 15 ). VCC RF = 10-15 CF = 22 F C2 VCC_PLL MPC9239 VCC C1, C2 = 0.01...0.1 F C1 Figure 5. VCC_PLL Power Supply Filter FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 407 MPC9239 Layout Recommendations The MPC9239 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 6 shows a representative board layout for the MPC9239. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 6 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC9239 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on--board oscillator. Although the MPC9239 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. C1 C1 Using the On-Board Crystal Oscillator The MPC9239 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC9239 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are recommended, but not required. Because the series resonant design is affected by capacitive loading on the XTAL terminals loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance it may be required to place a resistance across the terminals to suppress the third harmonic. Although typically not required it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 and 1K. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately most crystals are characterized in a parallel resonant mode. Fortunately there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result a parallel resonant crystal can be used with the MPC9239 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. Table 12 below specifies the performance requirements of the crystals to be used with the MPC9239. Table 12. Recommended Crystal Specifications Parameter Crystal Cut Resonance Frequency Tolerance Value Fundamental AT Cut Series Resonance1 75ppm at 25C 150pm 0 to 70C 0 to 70C 5-7pF 50 to 80 100 W 5ppm/Yr (First 3 Years) 1 Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging = VCC = GND = Via CF C2 XTAL 1. See accompanying text for series versus parallel resonant discussion. Figure 6. PCB Board Layout Recommendation for the PLCC28 Package 408 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC92429 Rev 1, 08/2004 400 MHz Low Voltage PECL Clock Synthesizer The MPC9429 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 25 MHz to 400 MHz and the support of differential PECL output signals the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * * 25 MHz to 400 MHz synthesized clock output signal Differential PECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation 3.3V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 32-lead LQFP and 28-PLCC packaging 32-lead Pb-free package available SiGe Technology Ambient temperature range 0C to +70C Pin and function compatible to the MC12429 and MPC9229 MPC92429 400 MHz LOW VOLTAGE CLOCK SYNTHESIZER FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 FA SUFFIX 32-LEAD TQFP PACKAGE CASE 873A-03 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 4M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC - 2.0V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAMMING INTERFACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 409 MPC92429 XTAL_IN XTAL_OUT XTAL 10 - 20 MHz /16 Ref VCO /4 PLL 800 - 1800 MHz FB /0 TO /511 9-BIT M-DIVIDER 9 /1 /2 /4 /8 00 01 10 11 OE FOUT FOUT SYNC TEST 2 N-LATCH 3 T-LATCH TEST VCC P_LOAD S_LOAD LE P/S M-LATCH 0 BITS 5-13 S_DATA S_CLOCK VCC M[0:8] N[1:0] OE 1 BITS 3-4 0 14-BIT SHIFT REGISTER 1 BITS 0-2 Figure 1. MPC92429 Logic Diagram M[8] M[7] M[6] M[5] 18 FOUT FOUT TEST GND GND VCC VCC S_CLOCK S_DATA S_LOAD VCC_PLL NC NC XTAL_IN 26 27 28 1 2 3 4 25 24 23 22 21 20 19 24 18 17 16 N[1] N[0] M[8] M[7] M[6] M[5] M[4] GND TEST VCC VCC GND FOUT FOUT VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 M[4] 17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT 13 12 11 10 9 8 XTAL_IN N[1] 2 N[0] 3 NC MPC9249 15 14 13 12 MPC9249 5 XTAL_OUT 6 OE 7 P_LOAD 8 M[0] 9 M[1] 10 M[2] 11 M[3] 4 5 6 7 S_CLOCK S_DATA NC S_LOAD VCC_PLL Figure 2. MPC9249 28-Lead PLCC Pinout (Top View) Figure 3. MPC9249 32-Lead Package Pinout (Top View) 410 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA VCC_PLL NC MPC92429 Table 1. Pin Configurations Pin XTAL_IN, XTAL_OUT FOUT, FOUT TEST S_LOAD Output Output Input 0 I/O Default Type Analog LVPECL LVCMOS LVCMOS Crystal oscillator interface Differential clock output Test and device diagnosis output Serial configuration control input. This inputs controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. Parallel configuration control input. This input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive Serial configuration data input. Serial configuration clock input. Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD Output enable (active high) The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the FOUT output. OE = L low stops FOUT in the logic low state (FOUT = L, FOUT = H) Negative power supply (GND) Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation PLL positive power supply (analog power supply) Function P_LOAD Input 1 LVCMOS S_DATA S_CLOCK M[0:8] N[1:0] OE Input Input Input Input Input 0 0 1 1 1 LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS GND VCC VCC_PLL Supply Supply Supply Supply Supply Supply Ground VCC VCC Table 2. Output Frequency Range and PLL Post-Divider N N 1 0 0 1 1 0 0 1 0 1 Output Division 1 2 4 8 Output Frequency Range 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz 25 - 50 MHz FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 411 MPC92429 Table 3. General Specifications Symbol VTT MM HBM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Input Capacitance LQFP 32 Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 200 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2 Max Unit V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC LQFP 32 Thermal Resistance Junction to Case Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 3.3V 5%, TA = 0C to +70C) Symbol VIH VIL IIN Input High Voltage Input Low Voltage Input Current1 VCC-1.02 VCC-1.95 2.0 0.55 20 100 Characteristics Min 2.0 Typ Max VCC + 0.3 0.8 200 Unit V V A Condition LVCMOS LVCMOS VIN = VCC or GND LVCMOS Control Inputs (P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE) Differential Clock Output FOUT2 VOH VOL VOH VOL ICC_PLL ICC Output High Voltage3 Output Low Voltage 3 VCC-0.74 VCC-1.60 V V V V mA mA LVPECL LVPECL IOH = -0.8 mA IOH = 0.8 mA VCC_PLL Pins All VCC Pins Test and Diagnosis Output TEST Output High Voltage3 Output Low Voltage3 Maximum PLL Supply Current Maximum Supply Current Supply Current 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 to VTT = VCC - 2V. 3. The MPC92429 TEST output levels are compatible to the MC12429 output levels. 412 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92429 Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C)1 Symbol fXTAL fVCO fMAX Characteristics Crystal Interface Frequency Range VCO Frequency Range2 Output Frequency N = 00 (/1) N = 01 (/2) N = 10 (/4) N = 11 (/8) Min 10 200 200 100 50 25 45 0.05 0 50 20 20 20 20 20 90 130 160 190 70 120 140 170 10 50 Typ Max 20 1600 400 200 100 50 55 0.3 10 Unit MHz MHz MHz MHz MHz MHz % ns MHz ns ns ns ns ns ns ps ps ps ps ps ps ps ps ms 20% to 80% Condition DC tr, tf fS_CLOCK tP,MIN tS Output Duty Cycle Output Rise/Fall Time Serial Interface Programming Clock Frequency3 Minimum pulse width Setup Time (S_LOAD, P_LOAD) S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD N = 00 (/1) N = 01 (/2) N = 10 (/4) N = 11 (/8) N = 00 (/1) N = 01 (/2) N = 10 (/4) N = 11 (/8) tS tJIT(CC) Hold Time Cycle-to-Cycle jitter tJIT(PER) Period Jitter tLOCK Maximum PLL Lock Time 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL x M / 4. 3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. See APPLICATIONS INFORMATION for more details. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 413 MPC92429 PROGRAMMING INTERFACE Programming the MPC92429 Programming the MPC92429 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: (1) FOUT = (fXTAL / 16) x (M) / (N) where fXTAL is the crystal frequency, M is the PLL feedbackdivider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured to match the VCO frequency range of 200 to 400 MHz in order to achieve stable PLL operation: MMIN = fVCO,MIN / fXTAL and (2) MMAX = fVCO,MAX / fXTAL (3) For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M = 200 and M = 400. Table 7 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation 1 reduces to: (4) FOUT = M / N Table 7. MPC9230 Frequency Operating Range M 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 510 M[8:0] 010100000 010101010 010110100 010111110 011001000 011010010 011011100 011100110 011110000 011111010 100000100 100001110 100011000 100100010 100101100 100110110 101000000 101001010 101010100 101011110 101101000 101110010 101111100 110000110 110010000 110011010 110100100 110101110 110111000 111000010 111111110 800 825 850 875 900 925 950 975 1000 1025 1050 1075 1100 1125 1275 810 840 870 900 930 960 990 1020 1050 1080 1110 1140 1170 1200 1230 1260 1290 1320 1350 1530 805 840 875 910 945 980 1015 1050 1085 1120 1155 1190 1225 1260 1295 1330 1365 1400 1435 1470 1505 1540 1575 800 840 880 920 960 100 1040 1080 1120 1160 1200 1240 1280 1320 1360 1400 1440 1480 1520 1560 1600 810 855 900 945 990 1035 1080 1125 1170 1215 1260 1305 1350 1395 1440 1485 1530 1575 VCO frequency for an crystal interface frequency of 10 12 14 16 18 20 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1600 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 190 195 200 50 52.5 55 57.5 60 62.5 65 67.5 70 72.5 75 77.5 80 82.5 85 87.5 90 92.5 95 97.5 100 25 26.25 27.50 28.75 30 31.25 32.50 33.75 35 36.25 37.5 38.75 40 41.25 42.5 43.75 45 46.25 47.5 48.75 50 Output frequency for fXTAL = 16 MHz and for N = 1 2 4 16 414 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92429 Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 8. Output Frequency Range for fXTAL = 16 MHz N 1 0 0 1 1 0 0 1 0 1 Value 1 2 4 8 FOUT M M/2 M/4 M/8 FOUT Range 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz 25 - 50 MHz FOUT Step 1 MHz 500 kHz 250 kHz 125 kHz Example Frequency Calculation for an 16 MHz Input Frequency If an output frequency of 131 MHz was desired the following steps would be taken to identify the appropriate M and N values. According to Table 8, 131 MHz falls in the frequency set by an value of 2 so N[1:0] = 01. For N = 2 the output frequency is FOUT = M / 2 and M = FOUT x 2. Therefore M = 2 x 131 = 262, so M[8:0] = 100000110. Following this procedure a user can generate any whole frequency between 25 MHz and 400 MHz. Note than for N > 2 fractional values of can be realized. The size of the programmable frequency steps (and thus the indicator of the fractional output frequencies achievable) will be equal to: (5) fSTEP = fXTAL / 16 / N APPLICATIONS INFORMATION Using the Parallel and Serial Interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW-to-HIGH transition will latch the information present on the M[8:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[8:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 14 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH-to-LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 4 illustrates the timing diagram for both a parallel and a serial load of the MPC9229 synthesizer. M[8:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. Using the Test and Diagnosis Output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the CMOS output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. The T2, T1 and T0 control bits are preset to `000' when P_LOAD is LOW so that the PECL FOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC9229 itself. However the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC9229 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree. Figure 6 shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 100 MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle. Table 9. Test and Debug Configuration for TEST T[2:0] T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 Logic 1 fXTAL / 16 M-Counter out FOUT Logic 0 M-Counter out in PLL-bypass mode FOUT / 4 TEST Output 14-bit shift register out1 1. Clocked out at the rate of S_CLOCK. Table 10. Debug Configuration for PLL Bypass1 Output FOUT TEST Configuration S_CLOCK / N M-Counter out2 1. T[2:0] = 110. AC specifications do not apply in PLL bypass mode. 2. Clocked out at the rate of S_CLOCK/(4N) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 415 MPC92429 S_CLOCK S_DATA S_LOAD M[8:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 Last Bit Figure 4. Serial Interface Timing Diagram Power Supply Filtering The MPC9229 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device characteristics. The MPC9229 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC9229. Figure 5 illustrates a typical power supply filter scheme. The MPC9229 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the MPC9229 pin of the MPC9229. From the data sheet, the VCC_PLL current (the current sourced through the VCC_PLL pin) is maximum 20 mA, assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. The resistor shown in Figure 5 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 H choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than 15 ). RF = 10-15 CF = 22 F C2 VCC VCC_PLL MPC92429 VCC C1, C2 = 0.01...0.1 F C1 Figure 5. VCC_PLL Power Supply Filter Layout Recommendations The MPC9229 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 6 shows a representative board layout for the MPC9229. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 6 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC9229 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. Although the MPC9229 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential 416 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92429 PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. C1 C1 1 CF C2 XTAL = VCC = GND = Via recommended, but not required. Because the series resonant design is affected by capacitive loading on the XTAL terminals loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance it may be required to place a resistance across the terminals to suppress the third harmonic. Although typically not required it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 and 1K. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately most crystals are characterized in a parallel resonant mode. Fortunately there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result a parallel resonant crystal can be used with the MPC9229 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. Table 11 below specifies the performance requirements of the crystals to be used with the MPC9229. Table 11. Recommended Crystal Specifications Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance1 75ppm at 25C 150pm 0 to 70C 0 to 70C 5-7pF 50 to 80 100W 5ppm/Yr (First 3 Years) Figure 6. PCB Board Layout Recommendation for the PLCC28 Package Using the On-Board Crystal Oscillator The MPC9229 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC9229 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are 1. See accompanying test for series versus parallel resonant discussion. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 417 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC92430 Rev 1, 08/2004 800 MHz Low Voltage PECL Clock Synthesizer The MPC92430 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 50 MHz to 800 MHz and the support of differential PECL output signals the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * * * 50 MHz to 800 MHz synthesized clock output signal Differential PECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference clock input 3.3V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 32-lead LQFP and 28-PLCC packaging 32-lead Pb-free package available SiGe Technology Ambient temperature range 0C to +70C Pin and function compatible to the MC12430 and MPC9230 MPC92430 800 MHz LOW VOLTAGE CLOCK SYNTHESIZER FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 FA SUFFIX 32-LEAD TQFP PACKAGE CASE 873A-03 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 400 to 800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (400 to 800 MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC - 2.0V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAMMING INTERFACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. 418 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92430 XTAL_IN XTAL_OUT FREF_EXT XTAL 10 - 20 MHz /16 Ref VCO /2 PLL 400 - 800 MHz /1 /2 /4 /8 11 00 01 10 OE FOUT FOUT FB VCC XTAL_SEL /0 TO /511 9-BIT M-DIVIDER 9 VCC P_LOAD S_LOAD LE P/S 0 BITS 5-13 S_DATA S_CLOCK VCC 1 BITS 3-4 14-BIT SHIFT REGISTER 0 1 BITS 0-2 M-LATCH /2 TEST 2 N-LATCH 3 T-LATCH TEST M[0:8] N[1:0] OE Figure 1. MPC92429 Logic Diagram M[8] M[7] M[6] M[5] 18 FOUT FOUT TEST GND GND VCC VCC S_CLOCK S_DATA S_LOAD VCC_PLL FREF_EXT XTAL_SEL XTAL_IN 26 27 28 1 2 3 4 25 24 23 22 21 20 19 24 18 17 16 N[1] N[0] M[8] M[7] M[6] M[5] M[4] GND TEST VCC VCC GND FOUT FOUT VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 M[4] 17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT 13 12 11 10 9 8 XTAL_IN N[1] 2 MPC92430 15 14 13 12 N[0] 3 NC MPC92430 5 XTAL_OUT 6 OE 7 P_LOAD 8 M[0] 9 M[1] 10 M[2] 11 M[3] 4 5 6 7 S_CLOCK S_DATA S_LOAD FREF_EXT Figure 2. MPC92430 28-Lead PLCC Pinout (Top View) Figure 3. MPC92430 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA XTAL_SEL VCC_PLL VCC_PLL 419 MPC92430 Table 1. Pin Configurations Pin XTAL_IN, XTAL_OUT FREF_EXT FOUT, FOUT TEST XTAL_SEL S_LOAD Input Output Output Input Input 1 0 0 I/O Default Type Analog LVCMOS LVPECL LVCMOS LVCMOS LVCMOS Crystal oscillator interface Alternative PLL reference input Differential clock output Test and device diagnosis output PLL reference select input Serial configuration control input. This input controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. Parallel configuration control input. This input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive Serial configuration data input. Serial configuration clock input. Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD Output enable (active high) The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the FOUT output. Negative power supply (GND) Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation PLL positive power supply (analog power supply) Function P_LOAD Input 1 LVCMOS S_DATA S_CLOCK M[0:8] N[1:0] OE Input Input Input Input Input 0 0 1 1 1 LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS GND VCC VCC_PLL Supply Supply Supply Supply Supply Supply Ground VCC VCC Table 2. Output Frequency Range and PLL Post-Divider N N 1 0 0 1 1 0 0 1 0 1 Output Division 2 4 8 1 Output Frequency Range 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz 400 - 800 MHz Table 3. Function Table Input XTAL_SEL OE 0 FREF_EXT Outputs disabled, FOUT is stopped in the logic low state (FOUT = L, FOUT = H) 1 XTAL interface Outputs enabled 420 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92430 Table 4. General Specifications Symbol VTT MM HBM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Input Capacitance LQFP 32 Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 200 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2 Max Unit V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC LQFP 32 Thermal Resistance Junction to Case Table 5. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Characteristics Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 6. DC Characteristics (VCC = 3.3V 5%, TA = 0C to +70C) Symbol Characteristics Min Typ Max Unit V V A Condition LVCMOS LVCMOS VIN = VCC or GND LVCMOS Control Inputs (FREF_EXT, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE) VIH 2.0 VCC + 0.3 Input High Voltage VIL IIN Input Low Voltage Input Current 1 0.8 200 Differential Clock Output FOUT2 VOH VOL Output High Voltage Output Low Voltage VCC-1.02 VCC-1.95 VCC-1.02 VCC-1.95 VCC-0.74 VCC-1.60 VCC-0.74 VCC-1.60 20 100 V V LVPECL LVPECL Test and Diagnosis Output TEST VOH Output High Voltage VOL Output Low Voltage Supply Current ICC_PLL Maximum PLL Supply Current ICC Maximum Supply Current V V mA mA LVPECL LVPECL VCC_PLL Pins All VCC Pins 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 to VTT = VCC - 2V. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 421 MPC92430 Table 7. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C)1 Symbol fXTAL fREF fVCO fMAX Characteristics Crystal Interface Frequency Range FREF_EXT Reference Frequency Range VCO Frequency Range3 Output Frequency N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) Min 10 10 400 400 200 100 50 0 50 45 0.05 S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD 20 20 20 20 20 25 10 50 55 0.3 Typ Max 20 (fVCO,MAX/M)22 800 800 400 200 100 10 Unit MHz MHz MHz MHz MHz MHz MHz MHz ns % ns ns ns ns ns ns ps ms 20% to 80% Condition fS_CLOCK fP,MIN DC tr, tf tS Serial Interface Programming Clock Frequency4 Minimum Pulse Width Output Duty Cycle Output Rise/Fall Time Setup Time (S-LOAD, P_LOAD) tH tJIT(PER) tLOCK Hold Time Period Jitter Maximum PLL Lock Time 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The maximum frequency of FREF_EXT is a function of the max. VCO frequency and the M counter. M should be higher than 160 for stable PLL operation. 3. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL M / 4. 4. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. See APPLICATIONS INFORMATION for more details. 422 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92430 PROGRAMMING INTERFACE Programming the MPC92430 Programming the MPC92430 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: (1) fOUT = (fXTAL / 16) (2 M) / (N) or (2) fOUT = (fXTAL / 8) M / N where fXTAL is the crystal frequency, M is the PLL feedback-divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured Table 8. MPC92430 Frequency Operating Range VCO frequency for an crystal interface frequency of M 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 370 380 390 400 410 420 430 440 450 510 M[8:0] 010100000 010101010 010110100 010111110 011001000 011010010 011011100 011100110 011110000 011111010 100000100 100001110 100011000 100100010 100101100 100110110 101000000 101001010 101010100 101011110 101110010 101111100 110000110 110010000 110011010 110100100 110101110 110111000 111000010 111111110 800 825 850 875 925 950 975 1000 1025 1050 1075 1100 1125 1275 810 840 870 900 930 960 990 1020 1050 1110 1140 1170 1200 1230 1260 1290 1320 1350 1530 805 840 875 910 945 980 1015 1050 1085 1120 1155 1190 1225 1295 1330 1365 1400 1435 1470 1505 1540 1575 800 840 880 920 960 100 1040 1080 1120 1160 1200 1240 1280 1320 1360 1400 1480 1520 1560 1600 810 855 900 945 990 1035 1080 1125 1170 1215 1260 1305 1350 1395 1440 1485 1530 1575 10 12 14 16 18 20 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1600 400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 700 740 760 780 800 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 370 380 390 400 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 185 190 195 200 50 52.5 55 57.5 60 62.5 65 67.5 70 72.5 75 77.5 80 82.5 85 87.5 92.5 95 97.5 100 Output frequency for fXTAL = 16 MHz and for N = 1 2 4 8 to match the VCO frequency range of 400 to 800 MHz in order to achieve stable PLL operation: (3) MMIN = 2fVCO,MIN / fXTAL and MMAX = 2fVCO,MAX / fXTAL (4) For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M = 200 and M = 400. Table 8 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation "fOUT = (fXTAL / 8) M / N (2)" reduces to: (5) fOUT = 2 M / N FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 423 MPC92430 Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 9. Output Frequency Range for fXTAL = 16 MHz N 1 0 0 1 1 0 0 1 0 1 Value 2 4 8 1 FOUT M M/2 M/4 2M FOUT Range 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz 400 - 800 MHz FOUT Step 1 MHz 500 kHz 250 kHz 2 MHz Example Frequency Calculation for an 16 MHz Input Frequency If an output frequency of 131 MHz was desired the following steps would be taken to identify the appropriate M and N values. According to Table 9, 131 MHz falls in the frequency set by a value of 4 so N[1:0] = 01. For N = 4 the output frequency is FOUT = M / 2 and M = FOUT x 2. Therefore, M = 2 x 131 = 262, so M[8:0] = 010000011. Following this procedure a user can generate any whole frequency between 50 MHz and 800 MHz. Note than for N > 2 fractional values of can be realized. The size of the programmable frequency steps (and thus the indicator of the fractional output frequencies achievable) will be equal to: (6) fSTEP = fXTAL / 8 / N APPLICATIONS INFORMATION Using the Parallel and Serial Interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW-to-HIGH transition will latch the information present on the M[8:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[8:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 14 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 4 illustrates the timing diagram for both a parallel and a serial load of the MPC92430 synthesizer. M[8:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. Using the Test and Diagnosis Output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the LVPECL compatible TEST output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. The T2, T1 and T0 control bits are preset to `000' when P_LOAD is LOW so that the LVPECL compatible FOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC92430 itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC92430 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree. Table 10 shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 50 MHz as the divide ratio of the Post-PLL divider is 4 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle. Table 10. Test and Debug Configuration for TEST T[2:0] T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 Logic 1 fXTAL / 16 M-Counter out FOUT Logic 0 M-Counter out in PLL-bypass mode FOUT / 4 TEST Output 14-bit shift register out1 1. Clocked at the rate of S_CLOCK Table 11. Debug Configuration for PLL Bypass1 Output FOUT TEST S_CLOCK / N M-Counter out2 Configuration 1. T[2:0]=110. AC specifications do not apply in PLL bypass mode 2. Clocked out at the rate of S_CLOCK/(2N) 424 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92430 S_CLOCK S_DATA S_LOAD M[8:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 Last Bit Figure 4. Serial Interface Timing Diagram Power Supply Filtering The MPC92430 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device characteristics. The MPC92430 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC92430. Figure 5 illustrates a typical power supply filter scheme. The MPC92430 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the MPC92430 pin of the MPC92430. From the data sheet, the VCC_PLL current (the current sourced through the VCC_PLL pin) is maximum 20 mA, assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. The resistor shown in Figure 5 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 H choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than 15 ). RF = 10-15 CF = 22 F C2 VCC VCC_PLL MPC92430 VCC C1, C2 = 0.01...0.1 F C1 Figure 5. VCC_PLL Power Supply Filter Layout Recommendations The MPC92430 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 6 shows a representative board layout for the MPC92430. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 6 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC92430 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. Although the MPC92430 has several design features to minimize the susceptibility to power supply noise (isolated FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 425 MPC92430 power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. C1 C1 1 CF C2 XTAL = VCC = GND = Via parasitics. To facilitate co-location surface mount crystals are recommended, but not required. Because the series resonant design is affected by capacitive loading on the xtal terminals loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance it may be required to place a resistance across the terminals to suppress the third harmonic. Although typically not required it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 and 1K. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately most crystals are characterized in a parallel resonant mode. Fortunately there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result a parallel resonant crystal can be used with the MPC92430 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. Table 12 below specifies the performance requirements of the crystals to be used with the MPC92430. Table 12. Recommended Crystal Specifications Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance1 75ppm at 25C 150pm 0 to 70C 0 to 70C 5-7pF 50 to 80 100W 5ppm/Yr (First 3 Years) Figure 6. PCB Board Layout Recommendation for the PLCC28 Package Using the On-Board Crystal Oscillator The MPC92430 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC92430 as possible to avoid any board level 1. See accompanying text for series versus parallel resonant discussion. 426 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC92432 Rev 1, 08/2004 Product Preview 1360 MHz Dual Output LVPECL Clock Synthesizer The MPC92432 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from 21.25 MHz to 1360 MHz and the support of two differential PECL output signals, the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * 21.25 MHz to 1360 MHz synthesized clock output signal Two differential, LVPECL-compatible high-frequency outputs Output frequency programmable through 2-wire I2C bus or parallel interface On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference clock input Synchronous clock stop functionality for both outputs LOCK indicator output (LVCMOS) LVCMOS compatible control inputs Fully integrated PLL 3.3-V power supply 48-lead LQFP SiGe Technology Ambient temperature range: -40C to +85C MPC92432 1360 MHz LOW VOLTAGE CLOCK SYNTHESIZER SCALE 2:1 FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932-03 Applications * Programmable clock source for server, computing, and telecommunication systems * Frequency margining * Oscillator replacement Functional Description The MPC92432 is a programmable high-frequency clock source (clock synthesizer). The internal PLL generates a high-frequency output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can be changed on the fly for frequency margining purpose. The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS compatible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a selectable divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2720 MHz. Its output is scaled by a divider that is configured by either the I2C or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL pre-divider P, the feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL post-divider N is configured through either the I2C or the parallel interfaces, and can provide one of six division ratios (2, 4, 8, 16, 32, 64). This divider extends the performance of the part while providing a 50% duty cycle. The high-frequency outputs, QA and QB, are differential and are capable of driving a pair of transmission lines terminated 50 to VCC - 2.0 V. The second high-frequency output, QB, can be configured to run at either 1x or 1/2x of the clock frequency or the first output (QA). The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: I2C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB, and P parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I2C interface. The serial interface is I2C compatible and provides read and write access to the internal PLL configuration registers. The lock state of the PLL is indicated by the LVCMOS-compatible LOCK outputs. This document contains certain information on a new product. Specifications and information herein are subject to change without notice. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 427 MPC92432 REF_CLK XTAL1 XTAL2 REF_SEL TEST_EN SDA SCL ADR[1:0] PLOAD M[9:0] NA[2:0] NB P CLK_STOPx BYPASS MR XTAL fREF /P PLL fVCO /NA fQA QA fQB /NB QB /M PLL Configuration Registers I2C Control LOCK Figure 1. MPC92432 -- Generic Logic Diagram TEST_EN 25 24 23 22 21 20 36 35 34 33 32 31 30 29 28 27 GND NA2 NA1 NA0 PLOAD VCC MR SDA SCL ADR1 ADR0 P LOCK 26 GND GND VCC VCC VCC QA QA QB QB NB 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 M9 M8 M7 M6 M5 GND M4 M3 M2 M1 M0 VCC MPC92432 19 18 17 16 15 14 13 CLK_STOPA CLK_STOPB It is recommended to use an external RC filter for the analog VCC_PLL supply pin. Please see the application section for details. BYPASS REF_CLK GND REF_SEL GND XTAL1 428 VCC_PLL Figure 2. 48-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA XTAL2 VCC VCC MPC92432 Table 1. Signal Configuration Pin XTAL1, XTAL2 REF_CLK REF_SEL QA QB LOCK M[9:0] NA[2:0] NB P P_LOAD SDA SCL ADR[1:0] BYPASS TEST_EN CLK_STOPx MR GND VCC_PLL VCC I/O Input Input Input Output Output Output Input Input Input Input Input I/O Input Input Input Input Input Input Supply Supply Supply Analog LVCMOS LVCMOS Differential LVPECL Differential LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC Type Crystal oscillator interface PLL external reference input Selects the reference clock input High frequency clock output High frequency clock output PLL lock indicator PLL feedback divider configuration PLL post-divider configuration for output QA PLL post-divider configuration for output QB PLL pre-divider configuration Selects the programming interface I2C data I2C clock Selectable two bits of the I2C slave address Selects the static circuit bypass mode Factory test mode enable. This input must be set to logic low level in all applications of the device. Output Qx disable in logic low state Device master reset Negative power supply Positive power supply for the PLL (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Positive power supply for I/O and core Function FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 429 MPC92432 Table 2. Function Table Control Inputs REF_SEL M[9:0] NA[2:0] NB P PLOAD 1 01 1111 0100b2 010 0 1 0 Selects REF_CLK input as PLL reference clock Selects the XTAL interface as PLL reference clock Default1 0 1 PLL feedback divider (10-bit) parallel programming interface PLL post-divider parallel programming interface. See Table 9 PLL post-divider parallel programming interface. See Table 10 PLL pre-divider parallel programming interface. See Table 8 Selects the parallel programming interface. The internal PLL divider settings (M, NA, NB and P) are equal to the setting of the hardware pins. Leaving the M, NA, NB and P pins open (floating) results in a default PLL configuration with fOUT = 250 MHz. See application/programming section. Address bit = 0 See Programming the MPC92432 Selects the serial (I2C) programming interface. The internal PLL divider settings (M, NA, NB and P) are set and read through the serial interface. ADR[1:0] SDA, SCL BYPASS 00 Address bit = 1 1 PLL function bypassed fQA=fREF/ NA and fQB=fREF/ (NA* NB) Application mode. Test mode disabled. Output Qx is disabled in logic low state. Synchronous disable is only guaranteed if NB = 0. PLL function enabled fQA = (fREF/ P) * M / NA and fQB = (fREF / P) * M / (NA * NB) Factory test mode is enabled Output Qx is synchronously enabled TEST_EN CLK_STOPx MR 0 1 The device is reset. The output frequency is zero and The PLL attempts to lock to the reference signal. The tLOCK specification applies. the outputs are asynchronously forced to logic low state. After releasing reset (upon the rising edge of MR and independent on the state of PLOAD), the MPC92432 reads the parallel interface (M, NA, NB and P) to acquire a valid startup frequency configuration. See application/programming section. Outputs LOCK PLL is not locked PLL is frequency locked 1. Default states are set by internal input pull-up or pull-down resistors of 75 k 2. If fREF = 16 MHz, the default configuration will result in a output frequency of 250 MHz 430 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92432 Table 3. General Specifications Symbol VTT MM HBM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-Up Immunity Input Capacitance Thermal Resistance Junction to Ambient JESD 51-3, single layer test board Min -- 200 2000 200 -- -- Typ VCC - 2 -- -- -- 4.0 -- Max -- -- -- -- -- TBD Unit V V V mA pF C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min -- -- TBD C/W MIL-SPEC 883E Method 1012.1 Inputs Condition JESD 51-6, 2S2P multilayer test board JC LQFP 32 Thermal Resistance Junction to Case Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Characteristics Min -0.3 -0.3 -0.3 -- -- -65 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 431 MPC92432 Table 5. DC Characteristics (VCC = 3.3 V 5%, TJ = -40C to +85C) Symbol Characteristics Min Typ Max Unit Condition LVCMOS Control Inputs (M[9:0], N[2:0], ADDR[1:0], NB, P, CLK_STOPx, BYPASS, MR, REF_SEL, TEST_EN, PLOAD) VIH VIL IIN Input High Voltage Input Low Voltage Input Current1 2.0 -- -- -- -- -- VCC + 0.3 0.8 200 V V A LVCMOS LVCMOS VIN = VCC or GND I2C Inputs (SCL, SDA) VIH VIL IIN Input High Voltage Input Low Voltage Input Current 2.0 -- -- -- -- -- VCC + 0.3 0.8 10 V V A LVCMOS LVCMOS LVCMOS Output (LOCK) VOH VOL Output High Voltage Output Low Voltage 2.4 -- -- -- -- 0.4 V V IOH = -4 mA IOL = 4 mA I2C Open-Drain Output (SDA) VOL Input Low Voltage -- -- 0.4 V IOL = 4 mA Differential Clock Output QA, QB2 VOH VOL VO(P-P) Output High Voltage Output Low Voltage Output Peak-to-Peak Voltage VCC - 1.05 VCC - 1.95 0.5 -- -- 0.6 VCC - 0.74 VCC - 1.60 1.0 V V V LVPECL LVPECL Supply current ICC_PLL ICC Maximum PLL Supply Current Maximum Supply Current -- -- -- -- TBD TBD mA mA VCC_PLL Pins All VCC Pins 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 to VTT = VCC - 2 V 432 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92432 Table 6. AC Characteristics (VCC = 3.3 V 5%, TJ = -40C to +85C)1 2 Symbol fXTAL fREF fVCO fMAX Characteristics Crystal Interface Frequency Range FREF_EXT Reference Frequency Range VCO Frequency Range3 Output Frequency4 N= /2 N= /4 N= /8 N= /16 N= /32 N= /64 Min 15 15 1360 680 340 170 85 42.5 21.25 0 (P_LOAD) 50 45 Same frequency Different frequency -- -- 0.05 -- TFOUT 0.5 * TFOUT N= /2 N= /4 N= /8 N= /16 N= /32 N= /64 fOUT = 250 MHz Any other frequency -- -- -- -- -- -- -- -- -- Typ 16 -- -- -- -- -- -- -- -- -- -- 50 -- 50 -- -- -- -- -- -- -- -- -- -- -- -- -- 55 25 0.3 250 2 * TFOUT 1.5 * TFOUT TBD TBD 25 25 TBD TBD 10 TBD 10 ps ps ps ps ps ps ps ps ms Max 20 20 2720 1360 680 340 170 85 42.5 0.4 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns % ps ps ns ns 20% to 80% CL = 400 pF T = period of Qx T = period of Qx Condition fSCL tP,MIN DC tSK(O) tr, tf tr, tf tP_EN tP_DIS tJIT(CC) Serial Interface (I2C) Clock Frequency Minimum Pulse Width Output Duty Cycle Output-to-Output Skew Output Rise/Fall Time (QA, QB) Output Rise/Fall Time (SDA) Output Enable Time (CLKSTOPx to QA, QB) Output Enable Time (CLKSTOPx to QA, QB) Cycle-to-Cycle Jitter tJIT(CC) tLOCK Period Jitter (RMS) Maximum PLL Lock Time 1. AC specifications are subject to change 2. AC characteristics apply for parallel output termination of 50 to VTT 3. The input frequency fXTAL, the PLL divider M and P must match the VCO frequency range: fVCO = fXTAL * M / P. The feedback divider M is limited to 170 <= M <= 340 (for P = 2) and 340 <= M <= 680 (for P = 4) for stable PLL operation 4. Output frequency for QA, QB if NB=0. With NB=1 the QB output frequency is half of the QA output frequency FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 433 MPC92432 APPLICATION INFORMATION Output Frequency Configuration The MPC92432 is a programmable frequency source (synthesizer) and supports an output frequency range of 21.25 - 1360 MHz. The output frequency fOUT is a function of the reference frequency fREF and the three internal PLL dividers P, M, and N. fOUT can be represented by this formula: fOUT = (fREF / P) * M / (NA, B) (1) Table 7. Frequency Ranges (fREF = 16 MHz) fOUT (QA) [MHz] 680 - 1360 340 - 680 170 - 340 85 - 170 42.5 - 85 21.25 - 42.5 NA NA=2 NA=4 NA=8 NA=16 NA=32 NA=64 M 170 - 340 340 - 680 170 - 340 340 - 680 170 - 340 340 - 680 170 - 340 340 - 680 170 - 340 340 - 680 170 - 340 340 - 680 P 2 4 2 4 2 4 2 4 2 4 2 4 G [MHz] 4 2 2 1 1 0.5 0.5 0.25 0.25 0.125 0.125 0.0625 The M, N and P dividers require a configuration by the user to achieve the desired output frequency. The output divider, NA, determines the achievable output frequency range (see Table 7). The PLL feedback-divider M is the frequency multiplication factor and the main variable for frequency synthesis. For a given reference frequency fREF, the PLL feedback-divider M must be configured to match the specified VCO frequency range in order to achieve a valid PLL configuration: fVCO = (fREF / P) * M and 1360 fVCO 2720 (2) (3) The output frequency may be changed at any time by changing the value of the PLL feedback divider M. The smallest possible output frequency change is the synthesizer granularity G (difference in fOUT when incrementing or decrementing M). At a given reference frequency, G is a function of the PLL pre-divider P and post-divider N: G = fREF / (P * NA,B) (4) Example Output Frequency Configuration If a reference frequency of 16 MHz is available, an output frequency at QA of 250 MHz and a small frequency granularity is desired, the following steps would be taken to identify the appropriate P, M, and N configuration: 1. Use Table 7 to select the output divider, NA, that matches the desired output frequency or frequency range. According to Table 7, a target output frequency of 250 MHz falls in the fOUT range of 170 to 340 MHz and requires to set NA = 8 Calculate the VCO frequency fVCO = fOUT * NA, which is 2000 MHz in this example. Determine the PLL feedback divider: M = fVCO / P. The smallest possible output granularity in this example calculation is 500 kHz (set P = 4). M calculates to a value of 2000 / 4 = 500. Configure the MPC92432 with the obtained settings: M[9:0] = 0111110100b (binary number for M=500) NA[2:0] = 010 P=1 NB = 0 5. (/8 divider, see Table 9) (/4 divider, see Table 8) (fOUT, QB = fOUT, QA) The NB divider configuration determines if the output QB generates a 1:1 or 2:1 frequency copy of the QA output signal. The purpose of the PLL pre-divider P is to situated the PLL into the specified VCO frequency range fVCO (in combination with M). For a given output frequency, P = 4 results in a smaller output frequency granularity G, P = 2 results a larger output frequency granularity G and also increases the PLL bandwidth compared to the P = 2 setting. The following example illustrates the output frequency range of the MPC92432 using a 16-MHz reference frequency. 2. 3. 4. Use either parallel or serial interface to apply the setting. The I2C configuration byte for this examples are: PLL_H=01010010b and PLL_L=11110100b. See Table 14 and Table 15 for register maps. 434 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92432 PLL Divider Configuration Table 8. Pre-PLL Divider P P 0 1 Value fREF / 2 fREF / 4 Upon startup, when the device reset signal is released (rising edge of the MR signal), the device reads its startup configuration through the parallel interface and independent on the state of PLOAD. It is recommended to provide a valid PLL configuration for startup. If the parallel interface pins are left open, a default PLL configuration will be loaded. After the low-to-high transition of PLOAD, the configuration pins have no more effect and the configuration registers are made accessible through the serial interface. Table 11. PLL Feedback-Divider Configuration (M) Feedback Divider M Pin Default 9 M9 0 8 M8 1 7 M7 1 6 M6 1 5 M5 1 4 M4 1 3 M3 0 2 M2 1 1 M1 0 0 M0 0 Table 9. Post-PLL Divider NA NA0 0 0 0 0 1 1 NA1 0 0 1 1 0 0 NA2 0 1 0 1 0 1 fOUT (QA) fVCO / 2 fVCO / 4 fVCO / 8 fVCO / 16 fVCO / 32 fVCO / 64 Table 12. PLL Pre/Post-Divider Configuration (N, P) Post-D. NA Pin 2 NA2 0 1 NA1 1 0 NA0 1 Post-D. NB Pin Default NB NB 0 Pre-D. P Pin Default P P 1 Table 10. Post-PLL Divider NB NB 0 1 Value fOUT, QB = fOUT, QA fOUT, QB = fOUT, QA / 2 Default Programming the MPC92432 The MPC92432 has a parallel and a serial configuration interface. The purpose of the parallel interface is to directly configure the PLL dividers through hardware pins without the overhead of a serial protocol. At device startup, the device always obtains an initial PLL frequency configuration through the parallel interface. The parallel interface does not support reading the PLL configuration. The serial interface is I2C compatible. It allows reading and writing devices settings by accessing internal device registers. The serial interface is designed for host-controller access to the synthesizer frequency settings for instance in frequency-margining applications. Using the Parallel Interface The parallel interface supports write-access to the PLL frequency setting directly through 15 configuration pins (P, M[9:0], NA[2:0], and NB). The parallel interface must be enabled by setting PLOAD to logic low level. During PLOAD = 0, any change of the logical state of the P, M[9:0], NA[2:0], and NB pins will immediately affect the internal PLL divider settings, resulting in a change of the internal VCO-frequency and the output frequency. The parallel interface mode disables the I2C write-access to the internal registers; however, I2C read-access to the internal configuration registers is enabled. Using the I2C Interface PLOAD = 1 enables the programming and monitoring of the internal registers through the I2C interface. Device register access (write and read) is possible through the 2-wire interface using SDA (configuration data) and SCL (configuration clock) signals. The MPC92432 acts as a slave device at the I2C bus. For further information on I2C it is recommended to refer to the I2C bus specification (version 2.1). PLOAD = 0 disables the I2C-write-access to the configuration registers and any data written into the register is ignored. However, the MPC92432 is still visible at the I2C interface and I2C transfers are acknowledged by the device. Read-access to the internal registers during PLOAD = 0 (parallel programming mode) is supported. Note that the device automatically obtains a configuration using the parallel interface upon the release of the device reset (rising edge of MR) and independent on the state of PLOAD. Changing the state of the PLOAD input is not supported when the device performs any transactions on the I2C interface. Programming Model and Register Set The synthesizer contains two fully accessible configuration registers (PLL_L and PLL_H) and a write-only command register (CMD). Programming the synthesizer frequency through the I2C interface requires two steps: 1) writing a valid PLL configuration to the configuration registers and 2) loading the registers into the PLL by an I2C command. The PLL frequency is affected as a result of the second step. This two-step procedure can be performed by a single I2C FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 435 MPC92432 transaction or by multiple, independent I2C transactions. An alternative way to achieve small PLL frequency changes is to use the increment or decrement commands of the synthesizer, which have an immediate effect on the PLL frequency. Synthesizer - PLL P N M LOAD/GET PLL_L (R/W) PLL_H (R/W) 0x00 0x01 CMD (W) 0xF0 I2C Registers I2C Access Register Maps Table 13. Configuration Registers Address 0x00 Name PLL_L PLL_H Content Least significant 8 bits of M Most significant 2 bits of M, P, NA, NB, and lock state Command register (write only) Access R/W R/W Configuration Latches 0x01 0xF0 CMD W only Register 0x00 (PLL_L) contains the least significant bits of the PLL feedback divider M. Table 14. PLL_L (0x00, R/W) Register Bit Name 7 M7 6 M6 5 M5 4 M4 3 M3 2 M2 1 M1 0 M0 Figure 3. I2C Mode Register Set Figure 3 illustrates the synthesizer register set. PLL_L and PLL_H store a PLL configuration and are fully accessible (Read/Write) by the I2C bus. CMD (Write only) accepts commands (LOAD, GET, INC, DEC) to update registers and for direct PLL frequency changes. Set the synthesizer frequency: 1) Write the PLL_L and PLL_H registers with a new configuration (see Table 14 and Table 15 for register maps) 2) Write the LOAD command to update the PLL dividers by the current PLL_L, PLL_H content. Read the synthesizer frequency: 1) Write the GET commands to update the PLL_L, PLL_H registers by the PLL divider setting 2) Read the PLL_L, PLL_H registers through I2C Change the synthesizer frequency in small steps: 1) Write the INC or DEC command to change the PLL frequency immediately. Repeat at any time if desired. LOAD and GET are inverse command to each other. LOAD updates the PLL dividers and GET updates the configuration registers. A fast and convenient way to change the PLL frequency is to use the INC (increment M) and DEC (decrement M) commands of the synthesizer. INC (DEC) directly increments (decrements) the PLL-feedback divider M and immediately changes the PLL frequency by the smallest step G (see Table 7 for the frequency granularity G). The INC and DEC commands are designed for multiple and rapid PLL frequency changes as required in frequency margining applications. INC and DEC do not require the user to update the PLL dividers by the LOAD command, INC and DEC do not update the PLL_L and PLL_H registers either (use LOAD for an initial PLL divider setting and, if desired, use GET to read the PLL configuration). Note that the synthesizer does not check any boundary conditions such as the VCO frequency range. Applying the INC and DEC commands could result in invalid VCO frequencies (VCO frequency beyond lock range). Register content: M[7:0] PLL feedback-divider M, bits 7-0 Register 0x01 (PLL_H) contains the two most significant bits of the PLL feedback divider M, four bits to control the PLL post-dividers N and the PLL pre-divider P. The bit 0 in PLL_H register indicates the lock condition of the PLL and is set by the synthesizer automatically. The LOCK state is a copy of the PLL lock signal output (LOCK). A write-access to LOCK has no effect. Table 15. PLL_H (0x01, R/W) Register Bit Name 7 M9 6 M8 5 NA2 4 NA1 3 NA0 2 NB 1 P 0 LOCK Register content: M[9:8] NA[2:0] NB P LOCK PLL feedback-divider M, bits 9-8 PLL post-divider NA, see Table 9 PLL post-divider NB, see Table 10 PLL pre-divider P, see Table 8 Copy of LOCK output signal (read-only) Note that the LOAD command is required to update the PLL dividers by the content of both PLL_L and PLL_H registers. Register 0xF0 (CMD) is a write-only command register. The purpose of CMD is to provide a fast way to increase or decrease the PLL frequency and to update the registers. The register accepts four commands, INC (increment M), DEC (decrement M), LOAD and GET (update registers). It is recommended to write the INC, DEC commands only after a valid PLL configuration is achieved. INC and DEC only affect the M-divider of the PLL (PLL feedback). Applying INC and DEC commands can result in a PLL configuration beyond the specified lock range and the PLL may loose lock. The MPC92432 does not verify the validity of any commands such 436 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92432 as LOAD, INC, and DEC. The INC and DEC commands change the PLL feedback divider without updating PLL_L and PLL_H. Table 16. CMD (0xF0): PLL Command (Write-Only) Command INC DEC LOAD GET Op-Code xxxx0001b (0x01) xxxx0010b (0x02) xxxx0100b (0x04) xxxx1000b (0x08) Description Increase internal PLL frequency M:=M+1 Decrease internal PLL frequency M:=M-1 Update the PLL divider config. PLL divider M, N, P:=PLL_L, PLL_H Update the configuration registers PLL_L, PLL_H:=PLL divider M, N, P Table 17. PLL Configuration in Parallel and Serial Modes PLL Configuration NA[2:0] NB P LOCK status Parallel Set pins NA2...NA0 Set pin NB Set bit P in PLL_H LOCK pin 26 Serial (Registers PLL_L, PLL_H) NA[2:0] (R/W) NB (R/W) P (R/W) LOCK (Read only) Programming the I2C Interface Table 18. I2C Slave Address Bit Value 7 1 6 0 5 1 4 1 3 0 2 Pin ADR1 1 Pin ADR0 0 R/W I2C -- Register Access in Parallel Mode The MPC92432 supports the configuration of the synthesizer through the parallel interlace (PLOAD = 0) and serial interface (PLOAD = 1). Register contents and the divider configurations are not changed when the user switches from parallel mode to serial mode. However, when switching from serial mode to parallel mode, the PLL dividers immediately reflect the logical state of the hardware pins M[9:0], NA[2:0], NB, and P. Applications using the parallel interface to obtain a PLL configuration can use the serial interface to verify the divider settings. In parallel mode (PLOAD = 0), the MPC92432 allows read-access to PLL_L and PLL_H through I2C (if PLOAD = 0, the current PLL configuration is stored in PLL_L, PLL_H. The GET command is not necessary and also not supported in parallel mode). After changing from parallel to serial mode (PLOAD = 1), the last PLL configuration is still stored in PLL_L, PLL_H. The user now has full write and read access to both configuration registers through the I2C bus and can change the configuration at any time. Table 17. PLL Configuration in Parallel and Serial Modes PLL Configuration M[9:0] Parallel Set pins M9-M0 Serial (Registers PLL_L, PLL_H) M[9:0] (R/W) The 7-bit I2C slave address of the MPC92432 synthesizer is a combination of a 5-bit fixed addresses and two variable bits which are set by the hardware pins ADR[1:0]. Bit 0 of the MPC92432 slave address is used by the bus controller to select either the read or write mode.'0' indicates a transmission (I2C-WRITE) to the MPC92432.'1' indicates a request for data (I2C-READ) from the synthesizer. The hardware pins ADR1 and ADR0 and should be individually set by the user to avoid address conflicts of multiple MPC92432 devices on the same I2C bus. Write Mode (R/W = 0) The configuration registers are written by the bus controller by the initiation of a write transfer with the MPC92432 slave address (first byte), followed by the address of the configuration register (second byte: 0x00, 0x01 or 0xF0), and the configuration data byte (third byte). This transfer may be followed by writing more registers by sending the configuration register address followed by one data byte. Each byte sent by the bus controller is acknowledged by the MPC92432. The transfer ends by a stop bit sent by the bus controller. The number of configuration data bytes and the write sequence are not restricted. Table 19. Complete Configuration Register Write Transfer 1 bit Start 7 bits Slave address 10110xx Master Master 1 1 bit R/W 0 Mast 1 bit ACK 8 bits &PLL_H 0x01 1 bit ACK 8 bits Config-Byte 1 Data 1 bit ACK 8 bits &PLL_L 0x00 1 bit ACK 8 bits Config-Byte 2 Data 1 bit ACK 1 bit Stop Slave Master Slave Master Slave Master Slave Master Slave Mast 1. xx = state of ADR1, ADR0 pins FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 437 MPC92432 Read Mode (R/W = 1) The configuration registers are read by the bus controller by the initiation of a read transfer. The MPC92432 supports read transfers immediately after the first byte without a change in the transfer direction. Immediately after the bus controller sends the slave address, the MPC92432 acknowledges and then sends both configuration register PLL_L and PLL_H (back-to-back) to the bus controller. The CMD register cannot be read. In order to read the two synthesizer registers and the current PLL configuration setting, the user can 1) read PLL_L, PLL_H, write the GET command (loads the current configuration into PLL_L, PLL_H) and read PLL_L, PLL_H again. Note that the PLL_L, PLL_H registers and divider settings may not be equivalent after the following cases: a. b. c. Writing the INC command Writing the DEC command Writing PLL_L, PLL_H registers with a new configuration and not writing the LOAD command. Table 20. Configuration Register Read Transfer 1 bit Start 7 bits Slave address 10110xx1 Master Master 1 bit R/W 1 Mast Slave 1 bit ACK 8 bits PLL_L Data Slave Mast 1 bit ACK 8 bits PLL_H Data Slave Master Slave 1 bit ACK 1 bit Stop 1. xx = state of ADR1, ADR0 pins Device Startup General Device Configuration It is recommended to reset the MPC92432 during or immediately after the system powers up (MR = 0). The device acquires an initial PLL divider configuration through the parallel interface pins M[9:0], NA[2:0], N, and P(1) with the low-to-high transition of MR(2). PLL frequency lock is achieved within the specified lock time (tLOCK) and is indicated by an assertion of the LOCK signal which completes the startup procedure. It is recommended to disable the outputs (CLK_STOPx = 0) until PLL lock is achieved to suppress output frequency transitions. The output frequency can be reconfigured at any time through either the parallel or the serial interface. Note that a PLL configuration obtained by the parallel interface can be read through I2C independent on the current programming mode (parallel or serial). Refer to I2C -- Register Access in Parallel Mode for additional information on how to read a PLL startup configuration through the I2C interface. Starting-Up Using the Parallel Interface The simplest way to use the MPC92432 is through the parallel interface. The serial interface pins (SDA, SDL, and ADDR[1:0]) can be left open and PLOAD is set to logic low. After the release of MR and at any other time the PLL/output frequency configuration is directly set to through the M[9:0], NA[2:0], NB, and P pins. Start-Up Using the Serial (I2C) Interface VCC MR P, M, N PLOAD LOCK CLK_STOPx QA, QB Disabled (Low) tPLH Active Acquiring Lock Stable & Valid Selects I2C PLL Lock Figure 4. Start-Up Using I2C Interface Set PLOAD = 1, CLK_STOPx = L and leave the parallel interface pins (M[9:0], NA[2:0], N, and P) open. The PLL dividers are configured by the default configuration at the low-to-high transition of MR. This initial PLL configuration can be re-programmed to the final VCO frequency at any time through the serial interface. After the PLL achieved lock at the desired VCO frequency, enable the outputs by setting CLK_STOPx = H. PLL lock and re-lock (after any configuration change through M or P) is indicated by LOCK being asserted. 1. The parallel interface pins M[9:0], NA[2:0], N, and P may be left open (floating). In this case the initial PLL configuration will have the default setting of M = 500, P = 1, NA[2:0] = 010, NB = 0, resulting in an internal VCO frequency of 2000 MHz (fref = 16 MHz) and an output frequency of 250 MHz. 2. The initial PLL configuration is independent on the selected programming mode (PLOAD low or high) 438 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92432 LOCK Detect The LOCK detect circuitry indicates the frequency-lock status of the PLL by setting and resetting the pin LOCK and register bit LOCK simultaneously. The LOCK status is asserted after the PLL acquired frequency lock during the startup and is immediately deasserted when the PLL lost lock, for instance when the reference clock is removed. The PLL may also loose lock when the PLL feedback-divider M or pre-divider P is changed or the DEC/INC command is issued. The PLL may not loose lock as a result of slow reference frequency changes. In any case of loosing LOCK, the PLL attempts to re-lock to the reference frequency. LOCK and re-lock of the PLL is indicated by the LOCK signal after a delay of TBD cycles to prevent signaling temporary PLL locks during frequency transitions. Output Clock Stop Asserting CLK_STOPx will stop the respective output clock in logic low state. The CLK_STOPx control is internally synchronized to the output clock signal, therefore, enabling and disabling outputs does not produce runt pulses. See Figure 5.The clock stop controls of the QA and QB outputs are independent on each other. If the QB runs at half of the QA output frequency and both outputs are enabled at the same time, the first clock pulse of QA may not appear at the same time of the first QB output. (See Figure 6.) Concident rising edges of QA and QB stay synchronous after the assertion and de-assertion of the CLK_STOPx controls. Asserting MR always resets the output divider to a logic low output state, with the risk of producing an output runt pulse. CLK_STOPx (Enable) (Disable) (Enable) Qx tP_DIS tP_EN Figure 5. Clock Stop Timing for NB = 0 (fQA = fQB) CLK_STOPA,B (Enable) (Disable) (Enable) QA QB Figure 6. Clock Stop Timing for NB = 1 (fQA = 2 fQB) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 439 MPC92432 Frequency Operating Range Table 21. MPC92432 Frequency Operating Range for P = 2 fVCO [MHz] (Parameter: fREF in MHz) M 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 M[9:0] 0010101010 0010110100 0010111110 0011001000 0011010010 0011011100 0011100110 0011110000 0011111010 0100000100 0100001110 0100011000 0100100010 0100101100 0100110110 0101000000 0101001010 0101010100 1425 1500 1575 1650 1725 1800 1875 1950 2025 2100 2175 2250 2325 2400 2475 2550 15 16 1360 1440 1520 1600 1680 1760 1840 1920 2000 2080 2160 2240 2320 2400 2480 2560 2640 2720 18 1530 1620 1710 1800 1890 1980 2070 2160 2250 2340 2430 2520 2610 2700 20 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2 680 720 760 800 840 880 920 960 1000 1040 1080 1120 1160 1200 1240 1280 1320 1360 Output Frequency for fXTAL = 16 MHz (Parameter N) 4 340 360 380 400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 8 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 16 85 90 95 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 32 42.50 45.00 47.50 50.00 52.50 55.00 57.50 60.00 62.50 65.00 67.50 70.00 72.50 75.00 77.50 80.00 82.50 85.00 64 21.25 22.50 23.75 25.00 26.25 27.50 28.75 30.00 31.25 32.50 33.75 35.00 36.25 37.50 38.75 40.00 41.25 42.50 440 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92432 Table 22. MPC92432 Frequency Operating Range for P = 4 fVCO [MHz] (Parameter: fREF in MHz) M 340 350 360 370 380 390 400 410 420 430 440 450 460 470 480 490 500 510 520 530 540 550 560 570 580 590 600 610 620 630 640 650 660 670 680 M[9:0] 0101010100 0101011110 0101101000 0101110010 0101111100 0110000110 0110010000 0110110010 0110100100 0110101110 0110111000 0111000010 0111001100 0111010110 0111100000 0111101010 0111110100 0111111110 1000001000 1000010010 1000011100 1000100110 1000110000 1000111010 1001000100 1001001110 1001011000 1001100010 1001101100 1001110110 1010000000 1010001010 0010010100 1010011110 1010101000 1387.5 1425.0 1462.5 1500.0 1537.5 1575.0 1612.5 1650.0 1687.5 1725.0 1762.5 1800.0 1837.5 1875.0 1912.5 1950.0 1987.5 2025.0 2062.5 2100.0 2137.5 2175.0 2212.5 2250.0 2287.5 2325.0 2362.5 2400.0 2437.5 2475.0 2512.5 2550.0 15 16 1360 1400 1440 1480 1520 1560 1600 1640 1680 1720 1760 1800 1840 1880 1920 1960 2000 2040 2080 2120 2160 2200 2240 2280 2320 2360 2400 2440 2480 2520 2560 2600 2640 2680 2720 18 1530 1575 1620 1665 1710 1755 1800 1845 1890 1935 1980 2025 2070 2115 2160 2205 2250 2295 2340 2475 2520 2565 2610 2700 20 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 2650 2700 2 680 700 720 740 760 780 800 820 840 860 880 900 920 940 960 980 1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1240 1260 1280 1300 1320 1340 1360 Output Frequency for fXTAL = 16 MHz (Parameter N) 4 340 350 360 370 380 390 400 410 420 430 440 450 460 470 480 490 500 510 520 530 540 550 560 570 580 590 600 610 620 630 640 650 660 670 680 8 170 175 180 185 190 195 200 205 210 215 220 225 230 235 240 245 250 255 260 265 270 285 280 285 290 295 300 305 310 315 320 325 330 335 340 16 85.0 87.5 90.0 92.5 95.0 97.5 100.0 102.5 105.0 107.5 110.0 112.5 115.0 117.5 120.0 122.5 125.0 127.5 130.0 132.5 135.0 137.5 140.0 142.5 145.0 147.5 150.0 152.5 155.0 157.5 160.0 162.5 165 167.5 170 32 42.50 43.75 45.00 46.25 47.50 48.75 50.00 51.25 52.50 53.75 55.00 56.25 57.50 58.75 60.00 61.25 62.50 63.75 65.00 66.25 67.50 68.75 70.00 71.25 72.50 73.75 75.00 76.25 77.50 78.75^ 80.00 81.25 82.5 83.75 85.00 64 21.25 21.875 22.50 23.125 23.75 24.375 25.00 25.625 26.25 26.875 27.50 28.125 28.75 29.375 30.00 30.626 31.25 31.875 32.50 33.125 33.75 34.375 35.00 35.625 36.25 36.875 37.50 38.125 38.75 39.375 40.00 40.625 41.25 41.875 42.50 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 441 MPC92432 VCC_PLL Filter The MPC92432 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device AC characteristics. The MPC92432 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In digital system environments where it is more difficult to minimize noise on the power supplies a second level of isolation is recommended: a power supply filter on the VCC_PLL pin for the MPC92432. RF = TBD CF = 22 F 10 nF VCC VCC_PLL MPC92432. From the data sheet, the VCC_PLL current (the current sourced through the VCC_PLL pin) is maximum TBD mA, assuming that a minimum of TBD V must be maintained on the VCC_PLL pin. The resistor shown in Figure 8 must have a resistance of TBD to meet the voltage drop criteria. The minimum values for RF and the filter capacitor CF are defined by the filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above TBD kHz. In the recommended filter shown in Figure 7 the filter cut-off frequency is around 4.5 TBD and the noise attenuation at TBD KHz is better than TBD dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. MPC92432 VCC 7 33...100 nF Figure 7. VCC_PLL Power Supply Filter Figure 7 illustrates a recommended power supply filter scheme. The MPC9230 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCC_PLL pin of the . AC Test Reference and Output Termination The MPC92432 LVPECL outputs are designed to drive 50 transmission lines and require a DC termination to VTT = VCC - 2 V. Figure 8 illustrates the AC test reference for the MPC92432 as used in characterization and test of this circuit. If a separate termination voltage (VTT) is not available, applications may use alternative output termination methods such as shown in Figure 9 and Figure 10. The high-speed differential output signals of the MPC92432 are incompatible to single-ended LVCMOS signals. In order to use the synthesizer in LVCMOS clock signal environments, the dual-channel translator device MC100ES60T23 provides the necessary level conversion. The MC100ES60T23 has been specifically designed to interface with the MPC92432 and supports clock frequency up to 180 MHz QA Pulse Generator Z = 50 fREF = 16 MHz Z = 50 QB RT = 50 Synthesizer Z = 50 Z = 50 DUT MPC92432 VTT RT = 50 Figure 8. MPC92432 AC Test Reference 442 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92432 VCC 130 Qx Z = 50 MPC92432 MPC92432 82 Qx Z = 50 50 50 SMD Resistor Network 46.4 Figure 9. Thevenin Termination Figure 10. Resistor Network Termination VTT 50 QA Z = 50 QB Z = 50 MPC92432 VTT MC100ES60T23 Figure 11. Interfacing with LVCMOS Logic for Frequency < 180 MHz FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 443 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC92439 Rev 1, 08/2004 900 MHz Low Voltage LVPECL Clock Synthesizer The MPC92439 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 3.125 MHz to 900 MHz and the support of differential LVPECL output signals the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * * * 3.125 MHz to 900 MHz synthesized clock output signal Differential LVPECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference input 3.3V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 28-PLCC and 32-LQFP packaging 32-lead Pb-free package available SiGe Technology Ambient temperature range 0C to + 70C Pin and function compatible to the MC12439 MPC92439 900 MHz LOW VOLTAGE CLOCK SYNTHESIZER FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 FA SUFFIX 32-LEAD TQFP PACKAGE CASE 873A-03 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC - 2.0V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAMMING INTERFACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments. 444 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92439 XTAL_IN XTAL_OUT FREF_EXT VCC XTAL_SEL VCC P_LOAD S_LOAD LE P/S 0 S_DATA S_CLOCK BITS 11-5 VCC 1 BITS 3-4 12-BIT SHIFT REGISTER 0 1 BITS 0-2 XTAL 10 - 20 MHz 1 /2 0 Ref VCO /2 PLL 800 - 1800 MHz FB /0 TO /127 7-BIT M-DIVIDER 9 M-LATCH /2 /1 /2 /4 /8 11 00 01 10 /16 1 OE 0 FOUT FOUT TEST 2 N-LATCH 3 T-LATCH TEST M[0:6] N[1:0] PWR_DOWN OE Figure 1. MPC92439 Logic Diagram XTAL_SEL M[6] M[5] 18 FOUT FOUT TEST GND GND VCC VCC S_CLOCK S_DATA S_LOAD VCC_PLL PWR_DOWN FREF_EXT XTAL_IN 26 27 28 1 2 3 4 25 24 23 22 21 20 19 18 17 16 N[1] N[0] NC XTAL_SEL M[6] M[5] M[4] 24 GND TEST VCC VCC GND FOUT FOUT VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 M[4] 17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT 13 12 11 10 9 8 XTAL_IN NC NC 3 MPC92439 15 14 13 12 MPC92439 5 XTAL_OUT 6 OE 7 P_LOAD 8 M[0] 9 M[1] 10 M[2] 11 M[3] 2 NC 4 N1 5 6 7 S_CLOCK S_DATA POWER_DOWN S_LOAD Figure 2. MPC92439 28-Lead PLCC Pinout (Top View) Figure 3. MPC92439 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA FREF_EXT VCC_PLL VCC_PLL 445 MPC92439 Table 1. Pin Configurations Pin XTAL_IN, XTAL_OUT FREF_EXT FOUT, FOUT TEST XTAL_SEL PWR_DOWN Input Output Output Input Input 1 0 0 I/O Default Type Analog LVCMOS LVPECL LVCMOS LVCMOS LVCMOS Crystal oscillator interface Alternative PLL reference input Differential clock output Test and device diagnosis output PLL reference select input Configuration input for power down mode. Assertion (deassertion) of power down will decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps. PWR_DOWN assertion (deassertion) is synchronous to the input reference clock. Serial configuration control input. This inputs controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. Parallel configuration control input. this input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive. Serial configuration data input. Serial configuration clock input. Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD. Output enable (active high) The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the FOUT output. OE = L low stops FOUT in the logic low state (FOUT = L, FOUT = H). Negative power supply (GND). Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. PLL positive power supply (analog power supply). Do not connect Function S_LOAD Input 0 LVCMOS P_LOAD Input 1 LVCMOS S_DATA S_CLOCK M[0:6] N[1:0] OE Input Input Input Input Input 0 0 1 1 1 LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS GND VCC VCC_PLL NC Supply Supply Supply Ground VCC VCC Table 2. Output Frequency Range and PLL Post-Divider N PWR_DOWN 0 0 0 0 1 1 1 1 N 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 VCO Output Frequency Division 2 4 8 1 32 64 128 16 FOUT Frequency Range 200 - 450 MHz 100 - 225 MHz 50 - 112.5 MHz 400 - 900 MHz 12.5 - 28.125 MHz 6.25 - 14.0625 MHz 3.125 - 7.03125 MHz 25 - 56.25 MHz 446 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92439 Table 3. Function Table Input XTAL_SEL OE PWR_DOWN 0 FREF_EXT Outputs disabled, FOUT is stopped in the logic low state (FOUT = L, FOUT = H) Output divider / 1 1 XTAL interface Outputs enabled Output divider / 16 Table 4. General Specifications Symbol VTT MM HBM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Input Capacitance LQFP 32 Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 200 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2 Max Unit V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC LQFP 32 Thermal Resistance Junction to Case Table 5. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 4.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 447 MPC92439 Table 6. DC Characteristics (VCC = 3.3V 5%, TA = 0C to +70C) Symbol VIH VIL IIN Input High Voltage Input Low Voltage Input Current1 Characteristics Min 2.0 Typ Max VCC + 0.3 0.8 200 Unit V V A Condition LVCMOS LVCMOS VIN = VCC or GND LVCMOS Control Inputs (FREF_EXT, POWER_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE) Differential Clock Output FOUT2 VOH VOL VOH VOL ICC_PLL ICC Output High Voltage3 Output Low Voltage3 VCC-1.02 VCC-1.95 2.0 0.55 VCC-0.74 VCC-1.60 V V LVPECL LVPECL Test and Diagnosis Output TEST Output High Voltage Output Low Voltage V V IOH = -0.8 mA IOL = 0.8 mA VCC_PLL Pins All VCC Pins Supply Current Maximum PLL Supply Current Maximum Supply Current 62 20 110 mA mA 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 to VTT = VCC - 2V. 3. The MPC92439 FOUT output levels are compatible to the MC12439 output levels. The MPC92439 is capable of driving 25 loads. Table 7. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C)1 Symbol fXTAL fVCO fMAX Characteristics Crystal Interface Frequency Range VCO Frequency Range Output Frequency 2 Min 10 800 N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) (S-LOAD, P_LOAD) 400 200 100 50 0 50 45 0.05 Typ Max 20 1800 900 450 225 112.5 10 Unit MHz MHz MHz MHz MHz MHz MHz ns Condition PWWR_DOWN = 0 fS_CLOCK tP,MIN DC tr, tf tS Serial Interface Programming Clock Frequency3 Minimum Pulse Width Output Duty Cycle Output Rise/Fall Time Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD 50 55 0.3 % ns ns ns ns ns ns 20% to 80% 20 20 20 20 20 25 10 tH tJIT(PER) tLOCK Hold Time Period Jitter Maximum PLL Lock Time ps ms 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL 2 M. 3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. See APPLICATIONS INFORMATION for more details. 448 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92439 Table 8. MPC92439 Frequency Operating Range (In MHz) M 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ... M[6:0] 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 800 820 840 860 880 900 920 940 960 980 1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1260 1260 1280 ... 816 840 864 888 912 936 960 984 1008 1032 1056 1080 1104 1128 1152 1176 1200 1224 1248 1272 1296 1320 1344 1368 1392 1416 1440 1488 1512 1512 1536 ... 812 840 875 868 896 924 952 980 1008 1036 1064 1092 1120 1148 1176 1204 1232 1260 1288 1316 1344 1372 1400 1428 1456 1484 1512 1540 1568 1596 1624 1652 1680 1736 1764 1764 1792 ... 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 828 864 900 936 972 1008 1044 1080 1116 1152 1188 1224 1260 1296 1332 1368 1404 1440 1476 1512 1548 1584 1620 1656 1692 1728 1764 1800 VCO frequency for an crystal interface frequency of 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz 800 840 880 920 960 1000 1040 1080 1120 1160 1200 1240 1280 1320 1360 1400 1440 1480 1520 1560 1600 1640 1680 1720 1760 1800 400 416 432 448 464 480 496 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 784 800 816 832 848 864 880 896 200 208 216 224 232 240 248 256 264 272 280 288 296 304 312 320 328 336 344 352 360 368 376 384 392 400 408 416 424 432 440 448 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 220 224 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 Output frequency for fXTAL=16 MHz and for N = 1 2 4 8 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 449 MPC92439 PROGRAMMING INTERFACE Programming the MPC92439 Programming the MPC92439 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: (1) fOUT = (fXTAL / 2) (M 4) / (N 2) or (2) fOUT = fXTAL M / N where fXTAL is the crystal frequency, M is the PLL feedback-divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured to match the VCO frequency range of 800 to 1800 MHz in order to achieve stable PLL operation: (3) MMIN = fVCO,MIN / (2 fXTAL) and (4) MMAX = 2fVCO,MAX / (2 fXTAL) For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M = 25 and M = 56. Table 8 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation (2) reduces to: (5) fOUT = 16 M / N Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 9. Output Frequency Range for fXTAL = 16 MHz N 1 0 0 1 1 0 0 1 0 1 Value 2 4 8 1 FOUT 8M 4M 2M 16M FOUT Range 200-450 MHz 100-225 MHz 50-112.5 MHz 400-900 MHz FOUT Step 8 MHz 4 MHz 2 MHz 16 MHz Example Calculation for an 16 MHz Input Frequency For example, if an output frequency of 384 MHz was desired, the following steps would be taken to identify the appropriate M and N values. 384 MHz falls within the frequency range set by an N value of 2, so N[1:0]=00. For N = 2, FOUT = 8M and M = FOUT/8. Therefore, M = 384 / 8 = 48, so M[6:0] = 0110000. Following this procedure a user can generate any whole frequency between 50 MHz and 900 MHz. The size of the programmable frequency steps will be equal to: (6) fSTEP = fXTAL / N APPLICATIONS INFORMATION Using the Parallel and Serial Interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[6:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[6:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 12 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two, and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1 and M6). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 4 illustrates the timing diagram for both a parallel and a serial load of the MPC92439 synthesizer. M[6:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. Using the Test and Diagnosis Output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the LVCMOS output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. The T2, T1 and T0 control bits are preset to `000' when P_LOAD is LOW so that the PECL FOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC92439 itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC92439 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clocktree shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 100 MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle. 450 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92439 Table 10. Test and Debug Configuration for TEST T[2:0] T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 Logic 1 fXTAL / 2 M-Counter out FOUT Logic 0 M-Counter out in PLL-bypass mode FOUT / 4 TEST Output 12-bit shift register out1 Table 11. Debug Configuration for PLL Bypass1 Output FOUT TEST S_CLOCK / N M-Counter out2 Configuration 1. T[2:0] = 110. AC specifications do not apply in PLL bypass mode 2. Clocked out at the rate of S_CLOCK / (2N) 1. Clocked out at the rate of S_CLOCK S_CLOCK S_DATA S_LOAD M[6:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M6 M5 M4 M3 M2 M1 M0 Last Bit Figure 4. Serial Interface Timing Diagram Power Supply Filtering The MPC92439 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device characteristics. The MPC92439 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC92439. Figure 5 illustrates a typical power supply filter scheme. The MPC92439 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the MPC92439 pin of the MPC92439. From the data sheet, the VCC_PLL current (the current sourced through the VCC_PLL pin) is maximum 20 mA, assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. The resistor shown in Figure 5 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 H choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than 15 ). VCC RF = 10-15 CF = 22 F C2 VCC_PLL MPC92439 VCC C1, C2 = 0.01...0.1 F C1 Figure 5. VCC_PLL Power Supply Filter FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 451 MPC92439 Layout Recommendations The MPC92439 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 6 shows a representative board layout for the MPC92439. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 6 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC92439 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. Although the MPC92439 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. C1 C1 Using the On-Board Crystal Oscillator The MPC92439 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC92439 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are recommended, but not required. Because the series resonant design is affected by capacitive loading on the xtal terminals loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance it may be required to place a resistance across the terminals to suppress the third harmonic. Although typically not required it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 and 1K. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately most crystals are characterized in a parallel resonant mode. Fortunately there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result a parallel resonant crystal can be used with the MPC92439 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. Table 12 below specifies the performance requirements of the crystals to be used with the MPC92439. Table 12. Recommended Crystal Specifications Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance1 75ppm at 25C 150pm 0 to 70C 0 to 70C 5-7pF 50 to 80 100W 5ppm/Yr (First 3 Years) 1 CF C2 XTAL = VCC = GND = Via 1. See accompanying text for series versus parallel resonant discussion. Figure 6. PCB Board Layout Recommendation for the PLCC28 Package 452 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC92459 Rev 0, 08/2004 Preliminary Information 900 MHz Low Voltage LVDS Clock Synthesizer The MPC92459 is a 3.3 V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 50 MHz to 900 MHz and the support of differential LVDS output signals the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * 50 MHz to 900 MHz synthesized clock output signal Differential LVDS output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference input 3.3 V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 32 Pin LQFP Package SiGe Technology Ambient temperature range 0C to + 70C MPC92459 900 MHz LOW VOLTAGE CLOCK SYNTHESIZER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAMMING INTERFACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the fOUT by 16. The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the fOUT input will step back up to its programmed frequency in four discrete increments. This document contains certain information on a new product. Specifications and information herein are subject to change without notice. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 453 MPC92459 XTAL_IN XTAL_OUT fREF_EXT VCC XTAL_SEL VCC P_LOAD S_LOAD LE P/S 0 S_DATA S_CLOCK BITS 11-5 VCC 1 BITS 3-4 12-BIT SHIFT REGISTER 0 1 BITS 0-2 XTAL 10 - 20 MHz 1 /2 0 Ref VCO /2 PLL 800 - 1800 MHz FB / 0 TO / 127 7-BIT M-DIVIDER 9 M-LATCH /2 /1 /2 /4 /8 11 00 01 10 / 16 1 OE 0 fOUT fOUT TEST 2 N-LATCH 3 T-LATCH TEST M[0:6] N[1:0] PWR_DOWN OE Figure 1. MPC92459 Logic Diagram XTAL_SEL M[6] M[5] 18 24 GND TEST VCC VCC GND fOUT fOUT VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 M[4] 17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT 13 12 11 10 9 8 XTAL_IN N[1] N[0] 3 NC MPC92459 2 NC 4 5 6 7 S_CLOCK S_DATA S_LOAD Figure 2. MPC92459 32-Lead LQFP Pinout (Top View) 454 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA PWR_DOWN fREF_EXT VCC_PLL VCC_PLL MPC92459 Table 1. Pin Configurations Pin XTAL_IN, XTAL_OUT fREF_EXT fOUT, fOUT TEST XTAL_SEL PWR_DOWN Input Output Output Input Input 1 0 0 I/O Default Type Analog Crystal oscillator interface Function LVCMOS Alternative PLL reference input LVDS Differential clock output LVCMOS Test and device diagnosis output LVCMOS PLL reference select input LVCMOS Configuration input for power down mode. Assertion (deassertion) of power down will decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps. PWR_DOWN assertion (deassertion) is synchronous to the input reference clock. LVCMOS Serial configuration control input. This inputs controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. LVCMOS Parallel configuration control input. this input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive. LVCMOS Serial configuration data input. LVCMOS Serial configuration clock input. LVCMOS Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. LVCMOS Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD LVCMOS Output enable (active high) The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the fOUT output. OE = L low stops fOUT in the logic low state (fOUT = L, fOUT = H). Ground VCC VCC Negative power supply (GND). Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. PLL positive power supply (analog power supply). S_LOAD Input 0 P_LOAD Input 1 S_DATA S_CLOCK M[0:6] N[1:0] OE Input Input Input Input Input 0 0 1 1 1 GND VCC VCC_PLL Supply Supply Supply Table 2. Output Frequency Range and PLL Post-Divider N PWR_DOWN 0 0 0 0 1 1 1 N 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 VCO Output Frequency Division 2 4 8 1 32 64 128 fOUT Frequency Range 200 - 450 MHz 100 - 225 MHz 50 - 112.5 MHz 400 - 900 MHz 12.5 - 28.125 MHz 6.25 - 14.0625 MHz 3.125 - 7.03125 MHz FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 455 MPC92459 Table 3. Function Table Input XTAL_SEL OE PWR_DOWN 0 FREF_EXT Outputs disabled. fOUT is stopped in the logic low state (fOUT = L, fOUT = H) Output divider / 1 1 XTAL interface Outputs enabled Output divider / 16 Table 4. General Specifications Symbol MM HBM LU CIN Characteristics ESD Protection (Machine model) ESD Protection (Human body model) Latch-up Immunity Input Capacitance Min 200 2000 200 4.0 Typ Max Unit V V mA pF Inputs Condition Table 5. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 456 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92459 Table 6. DC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C)1 Symbol Characteristics Min Typ Max Unit Condition LVCMOS Control Inputs (fREF_EXT, PWR_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:6], N[0:1], OE) VIH VIL IIN Input High Voltage Input Low Voltage Input Current2 2.0 VCC + 0.3 0.8 200 V V A LVCMOS LVCMOS VIN = VCC or GND Differential Clock Output fOUT VPP VOS Output Differential Voltage (peak-to-peak) Output Offset Voltage 250 1125 1275 mV mV LVDS LVDS Test and Diagnosis Output TEST VOH VOL Output High Voltage Output Low Voltage 2.0 0.55 V V IOH =-0.8 mA IOL = 0.8 mA Supply Current ICC_PLL ICC Maximum PLL Supply Current Maximum Supply Current 20 110 mA mA VCC_PLL Pins All VCC Pins 1. All AC characteristics are design targets and subject to change upon device characterization. 2. Inputs have pull-down resistors affecting the input current. Table 7. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C)1 Symbol fXTAL fVCO fMAX Characteristics Crystal Interface Frequency Range VCO Frequency Range2 Output Frequency N = 11 (/ 1) N = 00 (/ 2) N = 01 (/ 4) N = 10 (/ 8) Min 10 800 400 200 100 50 0 50 45 0.05 S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD RMS (1 )4 RMS (1 ) 20 20 20 20 20 TBD TBD 25 10 50 55 TBD Typ Max 20 1800 900 450 225 112.5 10 Unit MHz MHz MHz MHz MHz MHz MHz ns % ns ns ns ns ns ns ps ps ms 20% to 80% PWR_DOWN = 0 Condition fS_CLOCK tP,MIN DC tr, tf tS Serial Interface Programming Clock Frequency3 Minimum Pulse Width Output Duty Cycle Output Rise/Fall Time Setup Time (S_LOAD, P_LOAD) tS tJIT(CC) tJIT(PER) tLOCK Hold Time Cycle-to-Cycle Jitter Period Jitter Maximum PLL Lock Time 1. All AC characteristics are design targets and subject to change upon device characterization. 2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL 2 M. 3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. See APPLICATIONS INFORMATION for more details. 4. Refer to the application section for a jitter calculation for other confidence factors than 1 . FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 457 MPC92459 Table 8. MPC92459 Frequency Operating Range (in MHz) M 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ... M[6:0] 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 800 820 840 860 880 900 920 940 960 980 1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1260 1260 1280 ... 816 840 864 888 912 936 960 984 1008 1032 1056 1080 1104 1128 1152 1176 1200 1224 1248 1272 1296 1320 1344 1368 1392 1416 1440 1488 1512 1512 1536 ... 812 840 875 868 896 924 952 980 1008 1036 1064 1092 1120 1148 1176 1204 1232 1260 1288 1316 1344 1372 1400 1428 1456 1484 1512 1540 1568 1596 1624 1652 1680 1736 1764 1764 1792 ... 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 828 864 900 936 972 1008 1044 1080 1116 1152 1188 1224 1260 1296 1332 1368 1404 1440 1476 1512 1548 1584 1620 1656 1692 1728 1764 1800 VCO frequency for a crystal interface frequency of 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz 800 840 880 920 960 1000 1040 1080 1120 1160 1200 1240 1280 1320 1360 1400 1440 1480 1520 1560 1600 1640 1680 1720 1760 1800 400 416 432 448 464 480 496 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 784 800 816 832 848 864 880 896 200 208 216 224 232 240 248 256 264 272 280 288 296 304 312 320 328 336 344 352 360 368 376 384 392 400 408 416 424 432 440 448 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 220 224 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 Output frequency for fXTAL = 16 MHz and for N = 1 2 4 8 458 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC92459 PROGRAMMING INTERFACE Programming the MPC92459 Programming the MPC92459 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: (1) fOUT = (fXTAL / 2) (M 4) / (N 2) or (2) fOUT = fXTAL M / N where fXTAL is the crystal frequency, M is the PLL feedback-divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured to match the VCO frequency range of 800 to 1800 MHz in order to achieve stable PLL operation: (3) MMIN = fVCO,MIN / (2 fXTAL) and (4) MMAX = fVCO,MAX / (2 fXTAL) For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M = 25 and M = 56. Table 8 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation (2) reduces to: fOUT = 16 M / N Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 9. Output Frequency Range for fXTAL = 16 MHz N 1 0 0 1 1 0 0 1 0 1 Value 2 4 8 1 fOUT 8M 4M 2M 16 M fOUT Range 200 - 450 MHz 100 - 225 MHz 50 - 112.5 MHz 400 - 900 MHz fOUT Step 8 MHz 4 MHz 2 MHz 16 MHz Example Calculation for an 16 MHz Input Frequency For example, if an output frequency of 384 MHz was desired, the following steps would be taken to identify the appropriate M and N values. 384 MHz falls within the frequency range set by an N value of 2, so N[1:0]=00. For N = 2, fOUT = 8 M and M = fOUT / 8. Therefore, M = 384 / 8 = 48, so M[6:0] = 0110000. Following this procedure a user can generate any whole frequency between 50 MHz and 900 MHz. The size of the programmable frequency steps will be equal to: fSTEP = fXTAL / N APPLICATIONS INFORMATION Using the Parallel and Serial Interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[6:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[6:0] and N[1:0] inputs will affect the fOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 12 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two, and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1, and M6). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 3 illustrates the timing diagram for both a parallel and a serial load of the MPC92459 synthesizer. M[6:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. Using the Test and Diagnosis Output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents fOUT, the LVCMOS output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. The T2, T1, and T0 control bits are preset to `000' when P_LOAD is LOW so that the PECL fOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC92459 itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC92459 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the fOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving fOUT directly gives the user more control on the test clocks sent through the clock tree shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the fOUT pin can be toggled via the S_CLOCK is 100 MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 459 MPC92459 Table 10. Test and Debug Confutation for TEST T2 0 0 0 0 1 1 1 1 T[2:0] T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 TEST Output 12-bit shift register out1 Logic 1 fXTAL / 2 M-Counter out fOUT Logic 0 M-Counter out in PLL-bypass mode fOUT / 4 Table 11. Debug Configuration for PLL Bypass1 Output fOUT TEST S_CLOCK / N M-Counter out2 Configuration 1. T[2:0] = 110. AC specifications do not apply in PLL bypass mode 2. Clocked out at the rate of S_CLOCK / (2 N) 1. Clocked out at the rate of S_CLOCK S_CLOCK S_DATA S_LOAD M[6:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M6 M5 M4 M3 M2 M1 M0 Last Bit Figure 3. Serial Interface Timing Diagram Power Supply Filtering The MPC92459 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC92459 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC92459. Figure 4 illustrates a typical power supply filter scheme. The MPC92459 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the MPC92459 pin of the MPC92459. From the data sheet, the VCC_PLL current (the current sourced through the VCC_PLL pin) is typically TBD mA (TBD maximum), assuming that a minimum of 3.135 V must be maintained on the VCC_PLL pin, very little DC voltage drop can be tolerated when a 3.3 V VCC supply is used. The resistor shown in Figure 4 must have a resistance of TBD to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 H choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than TBD ). R1 = TBD R1 C3 C3 = TBD F C2 = 10 nF VCC_PLL MPC92459 VCC C1 = 33...100 nF VCC Figure 4. VCC_PLL Power Supply Filter 460 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC926508 Rev 2, 02/2004 Networking Clock Source The MPC926508 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts an input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The MPC926508 outputs all have 0 ppm synthesis error. Features * * * * * * * * Packaged in 20 pin narrow (150 mil) SSOP (QSOP) 25 or 125 MHz fundamental clock input or 25 MHz crystal input Two output clocks SDRAM frequencies of 100 and 133 MHz Zero ppm synthesis error in all clocks Full CMOS output swing with 25 mA output drive capability at TTL levels Advanced, low power, sub-micron CMOS process 3.3 V operating voltage MPC926508 NETWORKING CLOCK SOURCE SCALE 2:1 SD SUFFIX 20 LEAD SSOP CASE 1461-01 VDD 2 GND 2 SEL_25 SEL_CLK CLOCK SYNTHESIS AND CONTROL CIRCUITRY OUTPUT BUFFER OUT1 (100 MHz) 25 MHz OR 125 MHz CLOCK OR 25 MHz CRYSTAL X1 CLOCK BUFFER / CRYSTAL OSCILLATOR OUTPUT BUFFER OUT2 (133.3 MHz) X2 *Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board). FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 461 MPC926508 Table 1. Function Table Control SEL_25 SEL_CLK Default 1 1 0 125 XTAL 1 25 REF_CLK X2 NC X1/ICLK VDD NC GND NC NC NC OUT2 (133.33 MHz) 1 2 3 4 5 6 7 8 9 10 NC = Not Connected 20 19 18 17 NC SEL_CLK NC OUT1 (100 MHz) VDD NC GND NC NC SEL_25 MPC926508 16 15 14 13 12 11 Figure 1. MPC926508 Pin Assignment Table 2. Pin Description Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name X2 NC X1/ICLK VDD NC GND NC NC NC OUT1 (133.33 MHz) SEL_25 NC NC GND NC VDD OUT2 (100 MHz) NC SEL_CLK NC Type XO -- XI P -- P -- -- -- O I -- -- P -- P O -- I -- Not Connected Crystal connection. Connect to a fundamental crystal or clock input. Connect to +3.3 V. Must be same as other VDD. Not Connected Connect to ground. Not Connected Not Connected Not Connected 133.33 MHz Output REF_CLK or XTAL Input Selection. Not Connected Not Connected Connect to ground. Not Connected Connect to +3.3 V. Must be same as other VDD. 100 MHz Output Not Connected 25 or 125 MHz REF_CLK Selection. Not Connected Description Crystal connection. Connect to a crystal or leave unconnected for a clock input. Key: XI, XO = crystal connections; I = Input with internal pull-up resistor; O = Output; P = power supply connection. 462 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC926508 Table 3. Absolute Maximum Ratings1 Symbol VDD Supply Voltage Inputs and Clock Outputs TA TA TSOL TS Ambient Operating Temperature Ambient Operating Temperature, I version Soldering Temperature Storage Temperature -65 -0.5 0 -40 Characteristics Min Typ Max 3.9 VDD + 0.5 70 85 260 150 Unit V V C C C C Industrial temp Max of 20 seconds Condition Referenced to GND Referenced to GND 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. DC Characteristics (VDD = 3.3 V 10%, TA = -40C to 85C) Symbol VIH VIL VOH VOL VOH IDD Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage, CMOS level Operating Supply Current Short Circuit Current Internal Pull-Up Resistor VDD - 0.4 35 90 200 X1 pin only all I type inputs X1 pin only all I type inputs 2.4 0.4 Min VDD/2 + 1 2 Typ VDD/2 VDD/2 VDD/2-1 0.8 Max Unit V V V V V V V mA mA k IOH = -25 mA IOL = 25 mA IOH = -8 mA No Load Each Output SEL_25, SEL_CLK Condition Table 5. AC Characteristics (VDD = 3.3 V 10%, TA = -40C to 85C) Symbol fREF fREF tr tf DCO tJIT(CC) Input Frequency Input Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Frequency Error Jitter (Cycle-to-Cycle) 300 40 Characteristics Min 12 Typ 25 125 1 1 50 60 0 Max 27 Unit MHz MHz ns ns % ppm ps Condition Crystal Oscillator External Input 0.8 to 2.0 V 2.0 to 0.8 V At VDD/2 All clocks Variation from mean FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 463 MPC926508 APPLICATIONS INFORMATION External Components The MPC926508 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01 F should be connected between each VDD and GND (pins 4 and 6, pins 16, and 14), as close to the MPC926508 as possible. A series termination resistor of 33 may be used for each clock output. The crystal must be connected as close to the chip as possible. The crystal should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-6) x 2. So for a crystal with 16 pF load capacitance, two 20 pF caps should be used. 464 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9994 Rev 1, 03/2001 HSTL Low Voltage Differential Clock The MPC9994 is a low voltage 3.3 V, HSTL differential clock synthesizer. The clock is designed to support single and multiple processor systems requiring HSTL differential inputs. The MPC9994 supports two differential HSTL output pairs that may be operated from 340 MHz to 640 MHz. Features * * * * * * 2 clock outputs: (PCLK0 and PCLK1), each fully selectable Fully integrated PLL Output frequencies from 340 MHz to 640 MHz HSTL outputs HSTL and LVPECL reference clocks 32-lead LQFP packaging MPC9994 HSTL LOW VOLTAGE DIFFERENTIAL CLOCK SYNTHESIZER FOR 340 - 360 MHz Functional Description The fully integrated Phase Locked Loop multiplies the HSTL_CLK input or the PECL_CLK input frequency to the desired processor clock frequency. The PLL may be bypassed for test purposes such that the PCLK outputs are fed directly from the HSTL_CLK or PECL_CLK input. All outputs are HSTL. The PCLK outputs are capable of driving 25 to ground with at least 600 mV p-p signals. The EXTFB_OUT is capable of driving 50 ground with at least a 600 mV p-p signal. For on-chip power reduction, the outputs are powered from 1.8 V external supply. For zero delay applications the buffer can operate with either external or internal feedback. FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 465 MPC9994 PCLK0_EN (pullup) PCLK1_EN (pullup) TESTM (pullup) PLLREF_EN (pullup) REF_SEL (pullup) 1 HSTL_CLK (pullup) 0 1 0 0 /M PCLK0 PLL 1 PECL_CLK (pullup) 0 PCLK1 (pullup) EXTFB_IN (HSTL) (pulldown) EXTFB_EN (pullup) 1 /N EXTFB_OUT (HSTL) SEL[4:0] (pullup) RESET (pullup) PLL_BYPASS (pullup) Decode Figure 1. MPC9994 Logic Diagram PLL_BYPASS PLLREF_EN PCLK0 PCLK0 PCLK1 PCLK1 18 VCCO 24 VEEA RESET SEL4 SEL3 SEL2 SEL1 SEL0 VCCA 25 26 27 28 29 30 31 32 1 23 22 21 20 19 VCC0 17 16 15 14 EXTFB_OUT EXTFB_OUT VCCO EXTFB_IN EXTFB_IN EXTFB_EN PECL_CLK PECL_CLK 13 12 11 10 9 8 HSTL_CLK MPC9994 2 3 4 5 6 7 PCLK0_EN PCLK1_EN Figure 2. 32-Lead Package Pinout (Top View) 466 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA HSTL_CLK REF_SEL VCCI TESTM VEE MPC9994 Table 1. Pin Configuration Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VCCI TESTM VEE PCLK0_EN PCLK1_EN REF_SEL HSTL_CLK HSTL_CLK PECL_CLK PECL_CLK EXTFB_EN EXTFB_IN EXTFB_IN VCCO EXTFB_OUT EXTFB_OUT VCCO PCLK1 PCLK1 PCLK0 PCLK0 VCCO PLLREF_EN PLL_BYPASS VEEA RESET SEL[4] SEL[3] SEL[2] SEL[1] SEL[0] VCCA Pin I/O Type Power Input Power (GND) Input Input Input Input Input Input Input Input Input Input Power Output Output Power Output Output Output Output Power Input Input Power (GND) Input Input Input Input Input Input Power Type Power Supply LVCMOS Ground LVCMOS LVCMOS LVCMOS Differential HSTL Differential HSTL Differential LVPECL Differential LVPECL LVCMOS Differential HSTL Differential HSTL Power Supply Differential HSTL Differential HSTL Power Supply Differential HSTL Differential HSTL Differential HSTL Differential HSTL Power Supply LVCMOS LVCMOS Ground LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Power Supply 3.3 V M divider test pins Digital GND PCLK0 enable PCLK1 enable Selects the PLL input reference clock PLL reference clock input PLL reference clock input PLL reference clock input PLL reference clock input External feedback enable External feedback input External feedback input Output buffers power supply External feedback output clock External feedback output clock Ouput buffers power supply Output clock 1 Output clock 1 Output clock 0 Output clock 0 Ouput buffers power supply PLL reference enable Input signal PLL bypass Analog GND for PLL PLL bypass reset (for test use) Selection of input and feedback frequency Selection of input and feedback frequency Selection of input and feedback frequency Selection of input and feedback frequency Selection of input and feedback frequency 3.3 V filtered for PLL (PLL power supply) Description FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 467 MPC9994 Table 2. Frequency Selection Table SEL 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input Divide M 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Feedback Divide N 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 468 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9994 Table 3. Function Table (Controls) Control Pin REF_SEL TESTM PLLREF_EN PLL_BYPASS EXTFB_EN PCLK0_EN PCLK1_EN RESET SEL[4:0] 0 HSTL_CLK M divider test mode enabled Disable the input to the PLL and reset the M divider Outputs fed by input reference or M divider External feedback enabled PCLK0 = low, PCLK0 = high PCLK1 = low, PCLK1 = high Resets feedback N divider See Table 2.Frequency Selection Table 1 PECL_CLK Reference fed to Bypass mux Enable the input to the PLL Outputs fed by VCO Internal feedback enabled PCLK0 = high, PCLK0 = low PCLK1 = high, PCLK1 = low Feedback enabled Table 4. Absolute Maximum Ratings1 Symbol VCC VCCO VIN IIN TS Supply Voltage Output Supply Voltage Input Voltage Input Current Storage Temperature Characteristics Min -0.5 -0.5 -0.5 -1 -50 Max 4.4 4.4 VCC + 0.3 1 150 Unit V V V mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCCA = VCCI = 3.3 V 5%, VCCO = 1.7 to 2.1 V, TA = 0 to 70C) Symbol VIH VIL VCMR VPP VIN(dc) VDIF(dc) VCM(dc) VOH VOL ICCI ICCA ICCO ThetaJA 1. 2. 3. 4. 5. 6. 7. 8. Characteristics Input High Voltage Input Low Voltage Input High Voltage1 Input Low Voltage1 DC Input Signal Voltage DC Differential Input Voltage DC Common Mode Input Voltage Output High Voltage Output Low Voltage Core Supply Current PLL Supply Current Output Supply Current Junction to Ambient Thermal Resistance 15 150 53 Min 2.0 0.0 1 0.5 -0.3 0.4 0.4 VX + 0.3 0.0 VX + 0.5 VX - 0.5 Typ Max VCCI 0.8 VCCI - 0.3 1 1.45 1.75 1.0 1.4 VX - 0.3 140 20 Unit V V V V V V V V V mA mA mA Note 7 C/W Note 8 Condition LVCMOS LVCMOS LVPECL LVPECL2 HSTL3 HSTL4 HSTL5 HSTL6,1 HSTL6 DC levels will vary 1:1 with VCC. VPP minimum and maximum required to maintain AC specifications. Actual device function will tolerate minimum VPP of 200 mV. VIN (dc) specifies the maximum allowable dc excursion of each differential input. VDIF (dc) specifies the minimum input differential voltage (VTR - VCP) required for switching, where VTR is the "true" input signal and VCP is the "complement" input signal. VCM(dc) specifies the maximum allowable range of input signal crosspoint voltage. VX is the differential output crosspoint voltage defined in the "AC CHARACTERISTICS" section. 2 PCLK into 25 and 1 EXTFB into 50 . Measured with 1.3 M/s (250 fpm) airflow FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 469 MPC9994 Table 6. AC Characteristics (VCCA = VCCI = 3.3 V 5%, VCCO = 1.7 to 2.1 V, TA = 0 to 70C) Symbol fref fMAX tsk(o) tjit(0) tjit(cc) tjit(1/2per) VDIFout Vx tlock 1. 2. 3. 4. 5. Characteristics1 Input Frequency Maximum Output Frequency Skew Error (PCLK) Phase jitter (IO jitter) Cycle-to-cycle jitter (full period) Cycle-to-cycle jitter (half period) Differential Output pk-pk swing Differential output crosspoint voltage Maximum PLL lock time 0.6 0.68 0.9 10 340 Min Typ 100 - 125 640 35 output period / 2 5% 6% Note4 V V ms Max Unit MHz MHz ps Note2 Note3 Note3 Note3, 4 Note3, 5 For all HSTL output pairs For all HSTL output pairs Condition All PCLK outputs are terminated in 25 to ground, EXTFB_OUT is terminated in 50 to ground (applies to all measurements). With PLL active but in bypass mode, fref Max is limited by input buffer; best performance is expected with PECL input. Measured at differential pair crossover. Reference to full PCLK period. Reference to half PCLK period. VCCO VTR VDIF VCMR VX VCP VEE Figure 3. HSTL Differential Input Levels Z = 50 MPC9994 Output RT = 25 VTT = GND For external feedback output RT = 50 Figure 4. Output Termination and AC Test Reference 470 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9994 APPLICATIONS INFORMATION Power Supply Filtering The MPC9994 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC9994 provides separate power supplies for the output buffers (VCCO) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC9994. Figure 5 illustrates a typical power supply filter scheme. The MPC9994 is most susceptible to noise with spectral content in the 10kHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC9994. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15 mA (20 mA maximum), assuming that a minimum of 3.3 V-5% must be maintained on the VCCA pin. Very little DC voltage drop can be tolerated when a 3.3 V VCC supply is used. The resistor shown in Figure 5 must have a resistance of 5-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. It is recommended that the user start with an 8-10 resistor to avoid potential VCC drop problems and only move to the higher value resistors when a higher level of attenuation is shown to be needed. 2.5 V or 3.3 V RS = 5-15 VCCA MPC9994 VCC 0.01 F 0.01 F 22 F Figure 5. Power Supply Filter Although the MPC9994 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 471 MPC9994 END 472 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Chapter Six Zero-Delay Buffer Data Sheets Zero-Delay Buffer Device Index Device Number Page Device Number Page MPC962308 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 MPC9653 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 MPC9653A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 MPC9658 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 MPC96877 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 MPC9608 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 MPC961C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 MPC961P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 MPC962304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 MPC962305 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 473 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9608 Rev 3, 08/2004 1:10 LVCMOS Zero Delay Clock Buffer The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a very wide frequency range and low output skews the MPC9608 is targeted for high performance and mid-range clock tree designs. Features * 1:10 outputs LVCMOS zero-delay buffer * Single 3.3 V supply * Supports a clock I/O frequency range of 12.5 to 200 MHz * Selectable divide-by-two for one output bank * Synchronous output enable control (CLK_STOP) * Output tristate control (output high impedance) * PLL bypass mode for low frequency system test purpose * Supports networking, telecommunications and computer applications * Supports a variety of microprocessors and controllers * Compatible to PowerQuicc I and II * Ambient Temperature Range -40C to +85C * 32-lead Pb-free Package Available MPC9608 LOW VOLTAGE 3.3 V LVCMOS 1:10 ZERO-DELAY CLOCK BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 AC SUFFIX 32-LEAD LQFP PACKAGE Functional Description CASE 873A-03 The MPC9608 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. This enables nested clock designs with near-zero insertion delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed from traditional fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input frequency and phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs to generate either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain synchronized to the input reference for both bank B configurations. Outputs are only disabled or enabled when the outputs are already in logic low state (CLK_STOP). For system test and diagnosis, the MPC9608 outputs can also be set to high-impedance state by connecting OE to logic high level. Additionally, the device provides a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static phase offset specification do not apply. CLK_STOP and OE do not affect the PLL feedback output (QFB) and down stream clocks can be disabled without the internal PLL losing lock. The MPC9608 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines on the incident edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package. 474 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9608 CCLK CCLK 25k FB 25k F_RANGE[0:1] 25k PLL_EN 25k CLK_STOP 25k BSEL 25k OE 25k 2 /2 Ref PLL 00: 100-200 MHz 01: 50-100 MHz 10: 25- 50 MHz 11:12.5- 25 MHz Bank A QA0 STOP QA1 QA2 QA3 QA4 Bank B QB0 QB1 QB2 QB3 QB4 PLL feedback VCO FB_IN QFB Figure 1. MPC9608 Logic Diagram F_RANGE0 F_RANGE1 CLK_STOP BSEL GND 24 VCC QA4 QA3 QA2 GND QA1 QA0 VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 17 16 15 14 VCC QB4 QB3 QB2 GND QB1 QB0 VCC GND 13 12 11 10 9 8 VCC MPC9608 2 3 4 5 6 FB_IN OE 7 GND PLL_EN CCLK VCCA Figure 2. MPC9608 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GND QFB VCC 475 MPC9608 Table 1. Pin Configuration Pin CCLK FB_IN F_RANGE[0:1] BSEL PLL_EN OE CLK_STOP QA0-4, QB0-4 QFB GND VCCA VCC I/O Input Input Input Input Input Input Input Output Output Supply Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock signal PLL feedback signal input, connect to a QFB output PLL frequency range select Frequency divider select for bank B outputs PLL enable/disable Output enable/disable (high-impedance tristate) Synchronous clock enable/stop Clock outputs PLL feedback signal output. Connect to FB_IN Negative power supply PLL positive power supply (analog power supply). The MPC9608 requires an external RC filter for the analog power supply pin VCCA. Refer to the Applications Information section for details. Positive power supply for I/O and core Function Table 2. Function Table Control F_RANGE[0:1] BSEL CLK_STOP OE Default 00 0 0 0 0 1 PLL frequency range. Refer to Table 3.Clock Frequency Configuration for QFB Connected to FB_INT fQB0-4 = fQA0-4 Outputs enabled Outputs enabled (active) fQB0-4 = fQA0-4 / 2 Outputs synchronously stopped in logic low state Outputs disabled (high-impedance state), independent on CLK_STOP. Applying OE = 1 and PLL_EN = 1 resets the device. The PLL feedback output QFB is not affected by OE. Test mode with PLL disabled. CCLK is substituted for the internal VCO output. MPC9608 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Applying OE = 1 and PLL_EN = 1 resets the device. PLL_EN 0 Normal operation mode with PLL enabled. Table 3. Clock Frequency Configuration for QFB Connected to FB_IN F_RANGE[0] F_RANGE[1] BSEL fREF (CCLK) range [MHz] 100.0 - 200.0 QA0-QA4 Ratio fREF fREF fREF fREF fQA0-4 [MHz] 100.0 - 200.0 Ratio fREF fREF / 2 50.0 - 100.0 50.0 - 100.0 fREF fREF / 2 25.0 - 50.0 25.0 - 50.0 fREF fREF / 2 12.5 - 25.0 12.5 - 25 fREF fREF / 2 QB0-B4 fQB0-4 [MHz] 100.0 - 200.0 50.0 - 25.0 50.0 - 100.0 25.0 - 50.0 25.0 - 50.0 12.5 - 25.0 12.5 - 25.0 6.25 - 12.5 fREF fREF fREF fREF fREF fREF fREF fREF QFB 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 476 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9608 Table 4. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output termination voltage ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Power dissipation capacitance Input capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 5. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 6. DC Characteristics (VCC = 3.3 V 5%, TA = -40 to 85C) Symbol VIH VIL VOH VOL ZOUT IIN ICCA ICCQ Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current2 Maximum PLL Supply Current Maximum Quiescent Supply Current 4.0 1.0 14 - 17 200 8.0 4.0 2.4 0.55 0.30 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V V V A mA mA VIN = VCC or GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS IOH = -24 mA1 IOL = 24 mA IOL = 12 mA 1. The MPC9608 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. Inputs have pull-down resistors affecting the input current. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 477 MPC9608 Table 7. AC Characteristics (VCC = 3.3 V 5%, TA = -40 to 85C)1 Symbol fREF Characteristics Input reference frequency in PLL mode 2 Min 100 50 25 12.5 0 100 50 25 12.5 2.0 Typ Max 200 100 50 25 200 200 100 50 25 1.0 +175 +1.75% of tPER 80 100 150 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz ns ns ps ps ps Condition F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 Input reference frequency in PLL bypass mode3 Output Frequency4 F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 fmax BSEL = 0 BSEL = 0 BSEL = 0 BSEL = 0 0.8 V to 2.0 V PLL Locked tPW, MIN tr, tf t() Reference Input Pulse Width5 CCLK Input Rise/Fall Time Propagation Delay (SPO) CCLK to FB_IN fREF = 100 MHz and above -175 fREF = 12.5 MHz to 100 MHz -1.75% of tPER Output-to-Output Skew Within a bank Bank-to-bank All outputs, including QFB Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle Jitter Period Jitter I/O Phase Jitter PLL closed loop bandwidth6 RMS (1 ) F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 7 - 15 2-7 1-3 0.5 - 1.3 10 45 0.1 50 tSK(o) DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW 55 1.0 10 10 150 150 125 % ns ns ns ps ps ps MHz MHz MHz MHz ms BSEL = 0 BSEL = 0 BSEL = 0 0.55 V to 2.4 V tLOCK 1. 2. 3. 4. 5. Maximum PLL Lock Time AC characteristics apply for parallel output termination of 50 to VTT. PLL mode requires PLL_EN = 0 to enable the PLL and zero-delay operation. In bypass mode, the MPC9608 divides the input reference clock. Applies for bank A and for bank B if BSEL = 0. If BSEL = 1, the minimum and maximum output frequency of bank B is divided by two. Calculation of reference duty cycle limits: DCREF, MIN = tPW,MIN * fREF *100% and DCREF,MAX = 100% - DCREF,MIN. For example, at fREF = 100 MHz the input duty cycle range is 20% < DC < 80%. 6. -3 dB point of PLL transfer characteristics. 478 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9608 APPLICATIONS INFORMATION Power Supply Filtering The MPC9608 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9608 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9608. Figure 3 illustrates a typical power supply filter scheme. The MPC9608 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 4 mA (8 mA maximum), assuming that a minimum of 3.125 V must be maintained on the VCCA pin. The resistor RF shown in Figure 3 must have a resistance of 9 - 10 (VCC = 3.3 V) to meet the voltage drop criteria. RF = 9-10 for VCC = 3.3 V CF = 1 F for VCC = 3.3 V being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9608 in Zero-delay Applications Nested clock trees are typical applications for the MPC9608. Designs using the MPC9608, as LVCMOS PLL fanout buffer with zero insertion delay, will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9608 clock driver allows for its use as a zero delay buffer. By using the QFB output as a feedback to the PLL the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting in a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC9608 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9608 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() . CF VCC RF CF 10 nF VCCA MPC9608 VCC 33...100 nF This maximum timing uncertainty consists of 4 components: static phase offset, output skew, feedback board trace delay, and I/O (phase) jitter: CCLKCommon -t() QFBDevice 1 tPD,LINE(FB) Figure 3. VCCA Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9608 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is Any QDevice 1 tJIT() +tSK(O) +t() QFBDevice2 tJIT() Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 4. MPC9608 maximum device-to-device skew FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 479 MPC9608 Due to the statistical nature of I/O jitter, an RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. Table 8. Confidence Factor CF CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 IN MPC9608 OUTPUT BUFFER 14 MPC9608 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA RS = 36 ZO = 50 OutB0 RS = 36 ZO = 50 OutB1 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -295 ps to 295 ps(1) relative to CCLK: tSK(PP) = tSK(PP) = [-100 ps...100 ps] + [-150 ps...150 ps] + [(15 ps . -3)...(15 ps . 3)] + tPD, LINE(FB) [-295 ps...295 ps] + tPD, LINE(FB) Figure 5. Single versus Dual Transmission Lines The waveform plots in Figure 6. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9608 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. From the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9608. The output waveform in Figure 6. Single versus Dual Waveforms shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18 + 17 + 25)) = 1.31 V At the load end the voltage will double to 2.6 V due to the near unity reflection coefficient. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). Driving Transmission Lines The MPC9608 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC / 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9608 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 5 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9608 clock driver is effectively doubled due to its capability to drive multiple lines. 1. Skew data are designed targets and pending device specifications. 480 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9608 3.0 2.5 VOLTAGE (V) 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (nS) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 MPC9608 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 7. Optimized Dual Line Termination Figure 6. Single versus Dual Waveforms Since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 7. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9608 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 8. CCLK MPC9608 AC Test Reference for VCC = 3.3 V FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 481 MPC9608 VCC VCC / 2 GND VCC VCC / 2 GND FB_IN CCLK VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device. t() Figure 9. Output-to-Output Skew tSK(O) Figure 10. Propagation Delay (tPD, static phase offset) Test Reference VCC VCC /2 CCLK GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. FB_IN TJIT() = |T0 - T1 mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles. Figure 11. Output Duty Cycle (DC) Figure 12. I/O Jitter TN TN + 1 TJIT(CC) = |TN -TN + 1| T0 TJIT(PER) = |TN - 1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles. Figure 13. Cycle-to-Cycle Jitter Figure 14. Period Jitter VCC = 3.3 V 2.4 0.55 tF tR CLK_STOP CCLK VCC VCC / 2 GND VCC VCC / 2 GND ts tH Figure 15. Output Transition Time Test Reference Figure 16. Setup and Hold Time (ts, tH) Test Reference 482 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC961C Rev 2, 08/2004 Low Voltage Zero Delay Buffer The MPC961 is a 2.5 V or 3.3 V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200 MHz, output skews of 150 ps the device meets the needs of the most demanding clock tree applications. Features * * * * * * * * * Fully Integrated PLL Up to 200 MHz I/O Frequency LVCMOS Outputs Outputs Disable in High Impedance LVCMOS Reference Clock Options LQFP Packaging 32-lead Pb-free Package Available 50 ps Cycle-Cycle Jitter 150 ps Output Skews MPC961C LOW VOLTAGE ZERO DELAY BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC961 is offered with two different input configurations. The MPC961C offers an LVCMOS reference clock while the MPC961P offers an LVPECL reference clock. When pulled high the OE pin will force all of the outputs (except QFB) into a high impedance state. Because the OE pin does not affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock. The MPC961 is fully 2.5 V or 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50 transmission lines. For series terminated lines the MPC961 can drive two lines per output giving the device an effective fanout of 1:36. The device is packaged in a 32 lead LQFP. Q0 PLL 100 - 200 MHz 50- 100 MHz O 1 Q1 Q2 Q3 CCLK 50 k FB_IN 50 k Ref FB Q14 F_RANGE 50 k Q15 Q16 OE 50 k QFB The MPC961C requires an external RC filter for the analog power supply pin VCCA. Refer to APPLICATIONS INFORMATION for details. Figure 1. MPC961C Logic Diagram FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 483 MPC961C GND Q10 18 24 Q5 Q4 Q3 GND Q2 Q1 Q0 VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 Q11 17 16 15 14 VCC Q12 Q13 Q14 GND Q15 Q16 QFB 13 12 11 10 9 8 VCC Description VCC Q6 Q7 Q8 MPC961C 2 3 4 5 Q9 6 OE 7 F_RANGE CCLK GND MC Figure 2. 32-Lead Pinout (Top View) Table 1. Pin Configurations Number CCLK FB_IN F_RANGE OE Q0 - Q16 QFB GND VCCA Input Input Input Input Output Output Supply Supply Name Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC PLL reference clock signal PLL feedback signal input, connect to a QFB output PLL frequency range select Output enable/disable Clock outputs PLL feedback signal output, connect to a FB_IN Negative power supply PLL positive power supply (analog power supply). The MPC961C requires an external RC filter for the analog power supply pin VCCA. Refer to APPLICATIONS INFORMATION for details. Positive power supply for I/O and core Not connected VCC NC Supply VCC Table 2. Function Table Control F_RANGE OE Default 0 0 0 PLL high frequency range. MPC961C input reference and output clock frequency range is 100 - 200 MHz Outputs enabled 1 PLL low frequency range. MPC961C input reference and output clock frequency range is 50 - 100 MHz Outputs disabled (high-impedance state) 484 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA FB_IN VCCA MPC961C Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Characteristics Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -40 Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 4. DC Characteristics (VCC = 3.3 V 5%, TA = -40 to 85C) Symbol VIH VIL VOH VOL ZOUT IIN CIN CPD ICCA ICC VTT Characteristics Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Impedance Input Current Input Capacitance Power Dissipation Capacitance Maximum PLL Supply Current Maximum Quiescent Supply Current Output Termination Voltage VCC / 2 4.0 8.0 2.0 10 5.0 14 Min 2.0 -0.3 2.4 0.55 20 120 Typ Max VCC + 0.3 0.8 Unit V V V V A pF pF mA mA V Per Output VCCA Pin All VCC Pins Condition LVCMOS LVCMOS IOH = -20 mA1 IOL = 20 mA1 1. The MPC961C is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50 series terminated transmission lines. Table 5. AC Characteristics (VCC = 3.3 V 5%, TA = -40 to 85C)1 Symbol fREF fMAX fREFDC tr, tf t() tsk(O) DCO tr, tf tPLZ,HZ tPZL,LZ tJIT(CC) tJIT(PER) tJIT() tlock Characteristics Input Frequency F_RANGE = 0 F_RANGE = 1 Maximum Output Frequency F_RANGE = 0 F_RANGE = 1 Reference Input Duty Cycle TCLK Input Rise/Fall Time Propagation Delay (static phase offset) Output-to-Output Skew2 Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time RMS RMS (1) RMS (1) (1)3 7.0 CCLK to FB_IN -80 90 F_RANGE = 0 F_RANGE = 1 40 45 0.1 50 50 Min 100 50 100 50 25 Typ Max 200 100 200 100 75 3.0 120 150 60 55 1.0 10 10 15 10 15 10 Unit MHz MHz % ns ps ps % ns ns ns ps ps ns ms 0.6 to 1.8 V 0.7 to 1.7 V PLL locked Condition 1. AC characteristics apply for parallel output termination of 50 to VTT 2. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation. 3. Refer to APPLICATIONS INFORMATION for calculation for other confidence factors than 1 . FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 485 MPC961C Table 6. DC Characteristics (VCC = 2.5 V 5%, TA = -40 to 85C) Symbol VIH VIL VOH VOL ZOUT IIN CIN CPD ICCA ICC VTT Characteristics Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Impedance Input Current Input Capacitance Power Dissipation Capacitance Maximum PLL Supply Current Maximum Quiescent Supply Current Output Termination Voltage VCC / 2 4.0 8.0 2.0 10 5.0 18 Min 1.7 -0.3 1.8 0.6 26 120 Typ Max VCC + 0.3 0.7 Unit V V V V W A pF pF mA mA V Per Output VCCA Pin All VCC Pins Condition LVCMOS LVCMOS IOH = -15 mA1 IOL = 15 mA1 1. The MPC961C is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50 series terminated transmission lines. Table 7. AC Characteristics (VCC = 2.5 V 5%, TA = -40 to 85C)1 Symbol fREF fMAX fREFDC tr, tf t() tsk(O) DCO tr, tf tPLZ,HZ tPZL,LZ tJIT(CC) tJIT(PER) tJIT() tlock fREF fMAX Input Frequency Maximum Output Frequency Reference Input Duty Cycle TCLK Input Rise/Fall Time Propagation Delay (static phase offset) Output-to-Output Skew2 Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time Input Frequency Maximum Output Frequency F_RANGE = 0 F_RANGE = 1 F_RANGE = 0 F_RANGE = 1 100 50 100 50 RMS (1)3 7.0 F_RANGE = 0 F_RANGE = 1 40 45 0.1 CCLK to FB_IN -80 90 50 50 Characteristics F_RANGE = 0 F_RANGE = 1 F_RANGE = 0 F_RANGE = 1 Min 100 50 100 50 25 Typ Max 200 100 200 100 75 3.0 120 150 60 55 1.0 10 10 15 10 15 10 200 100 200 100 Unit MHz MHz % ns ps ps % ns ns ns ps ps ns ms MHz MHz 0.6 to 1.8 V 0.7 to 1.7 V PLL locked Condition RMS (1) RMS (1) 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. See APPLICATIONS INFORMATION for part-to-part skew calculation. 3. See APPLICATIONS INFORMATION for calculation for other confidence factors than 1 . 486 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC961C APPLICATIONS INFORMATION Power Supply Filtering The MPC961C is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC961C provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC961C. Figure 3 illustrates a typical power supply filter scheme. The MPC961C is most susceptible to noise with spectral content in the 10 kHz to 10 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC961C. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 2 mA (5 mA maximum), assuming that a minimum of 2.375 V (VCC = 3.3 V or VCC = 2.5 V) must be maintained on the VCCA pin. The resistor RF shown in Figure 3 must have a resistance of 270 (VCC = 3.3 V) or 5 to 15 (VCC = 2.5 V) to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. RF = 270 for VCC = 3.3 V RF = 5-15 for VCC = 2.5 V VCC RF CF 10 nF VCCA MPC961C schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC961C clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 15 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to the Application Note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC961C clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC961C clock driver is effectively doubled due to its capability to drive multiple lines. MPC961 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA MPC961 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 4. Single versus Dual Transmission Lines VCC 33...100 nF Figure 3. Power Supply Filter Although the MPC961C has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter The waveform plots of Figure 5 show the simulation results of an output driving a single line verses two lines. In both cases the drive capability of the MPC961C output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC961C. The output waveform in Figure 5 shows a step in the waveform, this step is caused by the impedance mismatch FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 487 MPC961C seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (ZO / (RS + RO +ZO)) ZO = 50 || 50 RS = 36 || 36 RO = 14 VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.62 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 TCLKCommon --t() tPD,LINE(FB) OutA tD = 3.8956 OutB tD = 3.9386 SPICE level and IBIS output buffer models are available for engineers who want to simulate their specific interconnect schemes. Using the MPC961C in Zero-Delay Applications Nested clock trees are typical applications for the MPC961C. Designs using the MPC961C as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC961C clock driver allows for its use as a zero delay buffer. By using the QFB output as a feedback to the PLL the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC961C zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC961C are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() * CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: VOLTAGE (V) Figure 5. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC961 OUTPUT BUFFER 14 QFBDevice 1 tJIT() +tSK(O) +t() Any QDevice 1 QFBDevice2 RS = 22 ZO = 50 tJIT() Any QDevice 2 Max. skew +tSK(O) tSK(PP) RS = 22 ZO = 50 Figure 7. MPC961C Max. Device-to-Device Skew 14 + 22 || 22 = 50 || 50 25 = 25 Figure 6. Optimized Dual Line Termination Due to the statistical nature of I/O jitter a rms value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8.Confidence Factor CF. 488 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC961C Table 8. Confidence Factor CF CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC961C die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability refer to the Application Note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature: Table 9. Die Junction Temperature and MTBF Junction Temperature (C) MTBF (Years) 20.4 9.1 4.2 2.0 100 110 120 130 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -275 ps to 315 ps relative to CCLK: tSK(PP) = [-80ps...120ps] + [-150ps...150ps] + [(15ps @ -3)...(15ps @ 3)] + tPD, LINE(FB) tSK(PP) = [-275ps...315ps] + tPD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 8 can be used for a more precise timing performance analysis. 18 16 14 12 10 8 6 4 2 0 50 F_RANGE = 1 F_RANGE = 0 70 90 110 130 150 170 190 Clock frequency [MHz] Figure 8. Max. I/O Jitter versus Frequency Power Consumption of the MPC961C and Thermal Management The MPC961C AC specification is guaranteed for the entire operating frequency range up to 200 MHz. The MPC961C power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section PTOT = [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] * VCC M Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC961C needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC961C is represented in equation 1. Where ICCQ is the static current consumption of the MPC961C, CPD is the power dissipation capacitance per output, ()CL represents the external capacitive output load, N is the number of active outputs (N is always 27 in case of the MPC961C). The MPC961C supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH, and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Equation 1 Equation 2 Equation 3 PTOT = VCC * [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] + [ DCQ * IOH * (VCC - VOH) + (1 - DCQ) * IOL * VOL ] M P TJ = TA + PTOT * Rthja fCLOCK,MAX = 1 * CPD * N * V2CC tjit() [ps] RMS [ Tj,MAX - TA Rthja - (ICCQ * VCC) ] Equation 4 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 489 MPC961C Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 9.Die Junction Temperature and MTBF, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC961C in a series terminated transmission line system. Table 10. Thermal Package Impedance of the 32ld LQFP Convection, LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm Rthja (1P2S board), K/W 80 70 61 57 56 55 TJ,MAX should be selected according to the MTBF system requirements and Table 9.Die Junction Temperature and MTBF. Rthja can be derived from Table 10.Thermal Package Impedance of the 32ld LQFP. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. If the calculated maximum frequency is below 200 MHz, it becomes the upper clock speed limit for the given application conditions. The following two derating charts describe the safe frequency operation range for the MPC961C. The charts were calculated for a maximum tolerable die junction temperature of 110C, corresponding to an estimated MTBF of 9.1 years, a supply voltage of 3.3 V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. There are no operating frequency limitations if a 2.5 V power supply or the system specifications allow for a MTBF of 4 years (corresponding to a max. junction temperature of 120C. 200 OPERATING FREQUENCY (MHz) 180 160 140 120 100 80 60 40 20 0 500 400 fMAX (AC) OPERATING FREQUENCY (MHz) TA = 85C 200 180 160 140 120 100 80 60 40 20 0 500 fMAX (AC) TA = 75C TA = 85C Safe operation 300 200 IFPM, CONVECTION 100 0 Safe operation 400 300 200 IFPM, CONVECTION 100 0 Figure 9. Maximum MPC961C Frequency, VCC = 3.3 V, MTBF 9.1 Years, Driving Series Terminated Transmission Lines Figure 10. Maximum MPC961C Frequency, VCC = 3.3 V, MTBF 9.1 Years, 4 pF Load per Line MPC961C DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 11. TCLK MPC961C AC Test Reference for VCC = 3.3 V and VCC = 2.5 V 490 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC961C VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device FB_IN t() CCLK VCC VCC / 2 GND VCC VCC / 2 GND Figure 12. Output-to-Output Skew tSK(O) Figure 13. Propagation Delay (tPD, static phase offset) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage FB_IN TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles CCLK Figure 14. Output Duty Cycle (DC) Figure 15. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 16. Cycle-to-Cycle Jitter Figure 17. Period Jitter VCC=3.3V 2.4 0.55 tF tR VCC=2.5V 1.8V 0.6V Figure 18. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 491 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC961P Rev 3, 08/2004 Low Voltage Zero Delay Buffer The MPC961 is a 2.5 V or 3.3 V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200 MHz, output skews of 150 ps the device meets the needs of the most demanding clock tree applications. Features * * * * * * * * * Fully Integrated PLL Up to 200 MHz I/O Frequency LVCMOS Outputs Outputs Disable in High Impedance LVPECL Reference Clock Options LQFP Packaging 32-lead Pb-free Package Available 50 ps Cycle-Cycle Jitter 150 ps Output Skews MPC961P LOW VOLTAGE ZERO DELAY BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC961 is offered with two different input configurations. The MPC961P offers an LVCMOS reference clock while the MPC961P offers an LVPECL reference clock. When pulled high the OE pin will force all of the outputs (except QFB) into a high impedance state. Because the OE pin does not affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock. The MPC961 is fully 2.5 V or 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50 transmission lines. For series terminated lines the MPC961 can drive two lines per output giving the device an effective fanout of 1:36. The device is packaged in a 32 lead LQFP package to provide the optimum combination of board density and performance. VCC 50 k PCLK PCLK 50 k FB_IN 50 k Q14 F_RANGE 50 k Q15 Q16 OE 50 k QFB 50 k PLL Ref 100 - 200 MHz 50 - 100 MHz Q0 Q1 0 1 Q2 Q3 FB The MPC961P requires an external RC filter for the analog power supply pin VCCA. Refer to APPLICATIONS INFORMATION for details. Figure 1. MPC961P Logic Diagram 492 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC961P GND Q10 18 Q11 17 16 15 14 VCC Q12 Q13 Q14 GND Q15 Q16 QFB 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC Description PLL reference clock signal PLL feedback signal input, connect to a QFB output PLL frequency range select Output enable/disable Clock outputs PLL feedback signal output, connect to a FB_IN Negative power supply PLL positive power supply (analog power supply). The MPC961P requires an external RC filter for the analog power supply pin VCCA. Please see applications section for details. Positive power supply for I/O and core VCC Q6 Q7 Q8 24 Q5 Q4 Q3 GND Q2 Q1 Q0 VCC 25 26 27 28 29 30 31 32 23 22 21 20 MPC961P PCLK PCLK F_RANGE Q9 19 OE Figure 2. 32-Lead Pinout (Top View) Table 1. Pin Configurations Number PCLK, PCLK FB_IN F_RANGE OE Q0 - Q16 QFB GND VCCA Input Input Input Input Output Output Supply Supply Name Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC Supply VCC Table 2. Function Table Control F_RANGE OE Default 0 0 0 PLL high frequency range. MPC961P input reference and output clock frequency range is 100 - 200 MHz Outputs enabled 1 PLL low frequency range. MPC961P input reference and output clock frequency range is 50 - 100 MHz Outputs disabled (high-impedance state) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA FB_IN GND VCCA 493 MPC961P Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Characteristics Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition -40 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 4. DC Characteristics (VCC = 3.3 V 5%, TA = -40 to 85C) Symbol VIH VIL VPP VCMR VOH VOL ZOUT IIN CIN CPD ICCA ICC VTT Characteristics Input HIGH Voltage Input LOW Voltage Peak-to-peak input voltage1 Common Mode Range2 Output HIGH Voltage Output LOW Voltage Output Impedance Input Current Input Capacitance Power Dissipation Capacitance Maximum PLL Supply Current Maximum Quiescent Supply Current Output Termination Voltage 14 4.0 8.0 2.0 VCC / 2 PECL_CLK, PECL_CLK PECL_CLK, PECL_CLK Min 2.0 -0.3 500 1.2 2.4 0.55 20 120 10 5.0 Typ Max VCC + 0.3 0.8 1000 VCC - 0.8 Unit V V mV V V V A pF pF mA mA V Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -20 mA2 IOL = 20 mA2 Per Output VCCA Pin All VCC Pins 1. Exceeding the specified VCMR/VPP window results in a tPD changes of approximately 250 ps. 2. The MPC961P is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50 series terminated transmission lines. Table 5. AC Characteristics (VCC = 3.3 V 5%, TA = -40 to 85C)1 Symbol fREF fMAX fREFDC t() tsk(O) DCO tr, tf tPLZ,HZ tPZL,LZ tJIT(CC) tJIT(PER) tJIT() tlock 1. 2. 3. 4. Characteristics Input Frequency F_RANGE = 0 F_RANGE = 1 Maximum Output Frequency F_RANGE = 0 F_RANGE = 1 Reference Input Duty Cycle Propagation Delay2 (static phase offset) Output-to-Output Skew3 Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle Jitter RMS (1)4 Period Jitter RMS (1) I/O Phase Jitter RMS (1) F_RANGE = 0 F_RANGE = 1 Maximum PLL Lock Time PECL_CLK to FB_IN Min 100 50 100 50 25 -80 Typ Max 200 100 200 100 75 120 150 60 55 1.0 10 10 15 10 0.0015 * T 0.0010 * T 10 Unit MHz MHz % ps ps % ns ns ns ps ps ns ms 0.6 to 1.8V Condition PLL locked 90 F_RANGE = 0 F_RANGE = 1 40 45 0.1 50 50 7.0 T = Clock Signal Period AC characteristics apply for parallel output termination of 50 to VTT. tPD applies for VCMR = VCC -1.3 V and VPP = 800 mV. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation. Refer to APPLICATIONS INFORMATION for calculation for other confidence factors than 1. 494 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC961P Table 6. DC Characteristics (VCC = 2.5 V 5%, TA = -40 to 85C) Symbol VIH VIL VPP VCMR VOH VOL ZOUT IIN CIN CPD ICCA ICC VTT Input HIGH Voltage Input LOW Voltage Peak-to-peak input voltage1 Common Mode Rangea Output HIGH Voltage Output LOW Voltage Output Impedance Input Current Input Capacitance Power Dissipation Capacitance Maximum PLL Supply Current Maximum Quiescent Supply Current Output Termination Voltage VCC / 2 4.0 8.0 2.0 10 5.0 18 PECL_CLK, PECL_CLK PECL_CLK, PECL_CLK Characteristics Min 1.7 -0.3 500 1.2 1.8 0.6 26 120 Typ Max VCC + 0.3 0.7 1000 VCC - 0.7 Unit V V mV V V V A pF pF mA mA V Per Output VCCA Pin All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -15 mA2 IOL = 15 mAb 1. Exceeding the specified VCMR/VPP window results in a tPD changes < 250 ps. 2. The MPC961P is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50 series terminated transmission lines. Table 7. AC Characteristics (VCC = 2.5 V 5%, TA = -40 to 85C)1 Symbol fREF fMAX fREFDC t() tsk(O) DCO tr, tf tPLZ,HZ tPZL,LZ tJIT(CC) tJIT(PER) tJIT() tlock 1. 2. 3. 4. Input Frequency Maximum Output Frequency Reference Input Duty Cycle Propagation Delay2 (static phase offset) Output-to-Output Skew3 Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time RMS (1)4 7.0 F_RANGE = 0 F_RANGE = 1 40 45 0.1 CCLK to FB_IN Characteristics F_RANGE = 0 F_RANGE = 1 F_RANGE = 0 F_RANGE = 1 Min 100 50 100 50 25 -50 90 50 50 Typ Max 200 100 200 100 75 175 150 60 55 1.0 10 10 15 10 0.0015 * T 0.0010 * T 10 Unit MHz MHz % ps ps % ns ns ns ps ps ns ms T = Clock Signal Period 0.6 to 1.8 V PLL locked Condition RMS (1) RMS (1) F_RANGE = 0 F_RANGE = 1 AC characteristics apply for parallel output termination of 50 to VTT. tPD applies for VCMR = VCC -1.3 V and VPP = 800 mV. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation. Refer to APPLICATIONS INFORMATION for calculation for other confidence factors than 1. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 495 MPC961P APPLICATIONS INFORMATION Power Supply Filtering The MPC961P is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC961P provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC961P. Figure 3 illustrates a typical power supply filter scheme. The MPC961P is most susceptible to noise with spectral content in the 10 kHz to 5 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC961P. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 2 mA (5 mA maximum), assuming that a minimum of 2.375 V (VCC = 3.3 V or VCC = 2.5 V) must be maintained on the VCCA pin. The resistor RF shown in Figure 3 must have a resistance of 270 (VCC = 3.3 V) or 5 to 15 (VCC = 2.5 V) to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. RF = 270 for VCC = 3.3 V RF = 5-15 for VCC = 2.5 V VCC RF CF 10 nF VCCA MPC961P VCC 33...100 nF IN schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC961P clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 15 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC961P clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC961P clock driver is effectively doubled due to its capability to drive multiple lines. MPC961 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA MPC961 OUTPUT BUFFER 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 4. Single versus Dual Transmission Lines The waveform plots of Figure 5 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC961P output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC961P. The output waveform in Figure 5 shows a step in the waveform, this step is caused by the impedance mismatch seen Figure 3. Power Supply Filter Although the MPC961P has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter 496 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC961P looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (ZO / (RS + RO +ZO)) ZO = 50 || 50 RS = 36 || 36 RO = 14 VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.62 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0ns). 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 TCLKCommon --t(y) QFBDevice 1 tPD,LINE(FB) OutA tD = 3.8956 OutB tD = 3.9386 SPICE level and IBIS output buffer models are available for engineers who want to simulate their specific interconnect schemes. Using the MPC961P in Zero-Delay Applications Nested clock trees are typical applications for the MPC961P. Designs using the MPC961P as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC961P clock driver allows for its use as a zero delay buffer. By using the QFB output as a feedback to the PLL the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC961P zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC961P are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() * CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: VOLTAGE (V) Figure 5. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC961 OUTPUT BUFFER 14 tJIT() +tSK(O) +t() Any QDevice 1 QFBDevice2 RS = 22 ZO = 50 Any QDevice 2 RS = 22 ZO = 50 Max. skew +tSK(O) tJIT() tSK(PP) Figure 7. MPC961P Max. Device-to-Device Skew 14 + 22 || 22 = 50 || 50 25 = 25 Figure 6. Optimized Dual Line Termination Due statistical nature of I/O jitter a rms value (1) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8.Confidence Factor CF. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 497 MPC961P describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC961P die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability refer to the Application Note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature: Table 9. Die Junction Temperature and MTBF Junction temperature (C) 100 110 120 130 MTBF (Years) 20.4 9.1 4.2 2.0 Table 8. Confidence Factor CF CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -236 ps to 361 ps relative to PCLK (f=125 MHz, VCC=2.5 V): tSK(PP) = [-50 ps...175ps] + [-150 ps...150 ps] + [(12ps @ -3)...(12ps @ 3)] + tPD, LINE(FB) tSK(PP) = [-236ps...361ps] + tPD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 8 "Max. I/O Jitter versus frequency" can be used for a more precise timing performance analysis. F_RANGE = 1 18 16 14 VCC = 2.5 V 12 10 8 V = 3.3 V 6 CC 4 2 0 50 70 90 F_RANGE = 0 VCC = 3.3 V VCC = 2.5 V 110 130 150 170 190 Clock frequency [MHz] Figure 8. Max. I/O Jitter versus Frequency Power Consumption of the MPC961P and Thermal Management The MPC961P AC specification is guaranteed for the entire operating frequency range up to 200 MHz. The MPC961P power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section PTOT = [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] * VCC M Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC961P needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC961P is represented in equation 1. Where ICCQ is the static current consumption of the MPC961P, CPD is the power dissipation capacitance per output, ()CL represents the external capacitive output load, N is the number of active outputs (N is always 27 in case of the MPC961P). The MPC961P supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH, and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. tjit() [ps] RMS Equation 1 Equation 2 Equation 3 PTOT = VCC * [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] + [ DCQ * IOH * (VCC - VOH) + (1 - DCQ) * IOL * VOL ] M P TJ = TA + PTOT * Rthja fCLOCK,MAX = 1 * CPD * N * V2CC [ Tj,MAX - TA Rthja - (ICCQ * VCC) ] Equation 4 498 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC961P Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 9.Die Junction Temperature and MTBF, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC961P in a series terminated transmission line system. Table 10. Thermal Package Impedance of the 32ld LQFP Convection, LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm Rthja (1P2S board), K/W 80 70 61 57 56 55 TJ,MAX should be selected according to the MTBF system requirements and Table 9.Die Junction Temperature and MTBF. Rthja can be derived from Table 10.Thermal Package Impedance of the 32ld LQFP. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. If the calculated maximum frequency is below 200 MHz, it becomes the upper clock speed limit for the given application conditions. The following two derating charts describe the safe frequency operation range for the MPC961P. The charts were calculated for a maximum tolerable die junction temperature of 110C, corresponding to an estimated MTBF of 9.1 years, a supply voltage of 3.3 V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. There are no operating frequency limitations if a 2.5 V power supply or the system specifications allow for a MTBF of 4 years (corresponding to a max. junction temperature of 120C. 200 OPERATING FREQUENCY (MHz) 180 160 140 120 100 80 60 40 20 0 500 400 fMAX (AC) OPERATING FREQUENCY (MHz) TA = 85C 200 180 160 140 120 100 80 60 40 20 0 500 fMAX (AC) TA = 75C TA = 85C Safe operation 300 200 IFPM, CONVECTION 100 0 Safe operation 400 300 200 IFPM, CONVECTION 100 0 Figure 9. Maximum MPC961P Frequency, VCC = 3.3 V, MTBF 9.1 Years, Driving Series Terminated Transmission Lines Figure 10. Maximum MPC961P Frequency, VCC = 3.3 V, MTBF 9.1 Years, 4 pF Load per Line MPC961P DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 11. TCLK MPC961P AC Test Reference for VCC = 3.3 V and VCC = 2.5 V FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 499 MPC961P PCLK PCLK VPP VCMR VCC VCC / 2 GND VCC = 3.3 V 2.4 0.55 tF tR VCC = 2.5 V 1.8 V 0.6 V Ext_FB t() Figure 12. Propagation Delay (t, static phase offset) Test Reference Figure 13. Output Transition Time Test Reference VCC VCC / 2 GND VCC VCC / 2 VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage tSK(O) GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 14. Output Duty Cycle (DC) Figure 15. Output-to-Output Skew tSK(O) TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 16. Cycle-to-Cycle Jitter Figure 17. Period Jitter PCLK PCLK Ext_FB TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a T0 mean in a random sample of cycles Figure 18. I/O Jitter 500 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC962304 Rev 0, 07/2004 3.3 V Zero Delay Buffer The MPC962304 is a 3.3 V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other highperformance applications. The MPC962304 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. The input-to-output skew is guaranteed to be less than 250 ps and output-to-output skew is guaranteed to be less than 200 ps. Features * * * * 1:4 outputs LVCMOS zero-delay buffer Zero input-output propagation delay, adjustable by the capacitive load on FBK input Multiple Configurations, See Table 1. Available MPC962304 Configurations Multiple low-skew outputs - 200 ps max output-output skew - 500 ps max device-device skew Supports a clock I/O frequency range of 10 MHz to 133 MHz Low jitter, 200 ps max cycle-cycle 8-pin SOIC package Single 3.3 V supply Ambient temperature range: -40C to +85C Compatible with the CY2304 MPC962304 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-06 * * * * * * Functional Description The MPC962304 has two banks of two outputs each. The MPC962304 PLL enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate. When the PLL is turned off, there is less than 25 A of current draw. Multiple MPC962304 devices can accept and distribute the same input clock throughout the system. In this situation, the difference between the output skews of two devices will be less than 500 ps. The MPC962304 is offered in two configurations. In the -1 version, the reference frequency is reproduced by the PLL and provided to the outputs. The MPC962304-2 provides 1/2X and 2X the reference frequency at the output banks. Block Diagram Pin Configuration 8-pin SOIC Top View REF CLKA1 CLKA2 GND 1 2 3 4 8 7 6 5 FBK VDD CLKB2 CLKB1 FBK REF PLL Extra Divider (-2) CLKB1 CLKB2 CLKA1 CLKA2 /2 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 501 MPC962304 Table 1. Available MPC962304 Configurations Device MPC962304-1 MPC962304-2 MPC962304-2 Feedback From Bank A or Bank B Bank A Bank B Bank A Frequency Reference Reference 2 X Reference Bank B Frequency Reference Reference/2 Reference Table 2. Pin Description Pin 1 2 3 4 5 6 7 8 REF 1 2 2 Signal Description Input reference frequency, 5 V tolerant input Clock output, Bank A Clock output, Bank A Ground CLKA1 CLKA2 GND CLKB1 2 Clock output, Bank B Clock output, Bank B 3.3 V supply PLL feedback input CLKB22 VDD FBK 1. Weak pull-down. 2. Weak pull-down on all outputs. Table 3. Maximum Ratings Characteristics Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage REF Storage Temperature Junction Static Discharge Voltage (per MIL-STD-883, Method 3015) Value -0.5 to +3.9 -0.5 to VDD+0.5 -0.5 to 5.5 -65 to +150 150 >2000 Unit V V V C C V 502 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC962304 Table 4. Operating Conditions for MPC962304-X Industrial Temperature Devices Parameter VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance1 Description Min 3.0 -40 Max 3.6 85 30 15 7 Unit V C pF pF pF 1. Applies to both REF clock and FBK. Table 5. Electrical Characteristics for MPC962304-X Industrial Temperature Devices1 Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage2 Output HIGH Voltage2 Power Down Supply Current Supply Current VIN = 0 V VIN = VDD IOL = 8 mA (-1, -2) IOH = -8 mA (-1, -2) REF = 0 MHz Unloaded outputs, 100 MHz, Select inputs at VDD or GND Unloaded outputs, 66-MHz REF (-1, -2) Unloaded outputs, 35-MHz REF (-1, -2) 1. All parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. 2.4 25.0 45.0 35.0 20.0 2.0 50.0 100.0 0.4 Test Conditions Min Max. 0.8 Unit V V A A V V A mA mA mA FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 503 MPC962304 Table 6. Switching Characteristics for MPC962304-X Industrial Temperature Devices1 Parameter t1 Name Output Frequency Output Frequency Duty Cycle2 = t2 / t1 (-1, -2) Duty Cycle2 = t2 / t1 (-1, -2) t3 Rise Time2 (-1, -2) Rise Time2 (-1, -2) t4 Fall Time2 (-1, -2) Fall Time2 (-1, -2) t5 Output to Output Skew on same Bank (-1, -2)2 Output Bank A to Output Bank B Skew (-1) Output Bank A to Output Bank B Skew (-2) t6 t7 tJ Delay, REF Rising Edge to FBK Rising Edge2 Device to Device Skew2 Cycle to Cycle Jitter2 (-1) Test Conditions 30-pF load, all devices 15-pF load, all devices Measured at 1.4 V, FOUT = 66.66 MHz 30-pF load Measured at 1.4 V, FOUT < 50.0 MHz 15-pF load Measured between 0.8 V and 2.0 V, 30-pF load Measured between 0.8 V and 2.0 V, 15-pF load Measured between 0.8 V and 2.0 V, 30-pF load Measured between 0.8 V and 2.0 V, 15-pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured at 66.67 MHz, loaded outputs, 15-pF load Measured at 66.67 MHz, loaded outputs, 30-pF load Measured at 133.3 MHz, loaded outputs, 15 pF load tJ Cycle to Cycle Jitter2 (-2) Measured at 66.67 MHz, loaded outputs 30-pF load Measured at 66.67 MHz, loaded outputs 15-pF load tLOCK PLL Lock Time2 Stable power supply, valid clocks presented on REF and FBK pins 1. All parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. 1.0 ms 380 ps 400 ps 100 ps 200 ps 180 ps 0 0 200 200 400 250 500 ps ps ps ps ps 1.50 ns 2.50 ns 1.50 ns 2.50 ns 45.0 55.0 % Min 10 10 40.0 Typ Max 100 133.3 60.0 Unit MHz MHz % 504 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC962304 APPLICATIONS INFORMATION VCC 1.4 V GND VCC 1.4 V GND t5 The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t6 FB_IN CCLK VCC VCC / 2 GND VCC VCC / 2 GND Figure 1. Output-to-Output Skew tSK(O) Figure 2. Static Phase Offset Test Reference VCC 1.4 V GND t2 t1 DC = t2/t1 x 100% t7 The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage DEVICE 2 DEVICE 1 VCC VCC / 2 GND VCC VCC / 2 GND Figure 4. Device-to-Device Skew Figure 3. Output Duty Cycle (DC) VCC = 3.3 V 2.0 tJ = |tN-tN+1| t4 t3 0.8 tN tN+1 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 5. Cycle-to-Cycle Jitter Figure 6. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 505 MPC962304 Test Circuit #1 VDD 0.1 F OUTPUTS CLKOUT CLOAD 0.1 F VDD GND GND Test Circuit for all parameters Ordering Information (Available) Ordering Code MPC962304D-1 MPC962304D-1R2 MPC962304D-2 MPC962304D-2R2 Package Name D8 D8 D8 D8 8-pin 150-mil SOIC 8-pin 150-mil SOIC -- Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC -- Tape and Reel Package Type 506 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC962305 Rev 5, 08/2004 Low-Cost 3.3 V Zero Delay Buffer The MPC962309 is a zero delay buffer designed to distribute high-speed clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin version of the MPC962309 which drives five outputs with one reference input. The -1H versions of these devices have higher drive than the -1 devices and can operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which lock to an input clock presented on the REF pin. The PLL feedback is on-chip and is obtained from the CLOCKOUT pad. Features * * * * * * * * * * * * * * 1:5 LVCMOS zero-delay buffer (MPC962305) 1:9 LVCMOS zero-delay buffer (MPC962309) Zero input-output propagation delay Multiple low-skew outputs 250 ps max output-output skew 700 ps max device-device skew Supports a clock I/O frequency range of 10 MHz to 133 MHz, compatible with CPU and PCI bus frequencies Low jitter, 200 ps max cycle-cycle, and compatible with Pentium(R) based systems Test Mode to bypass PLL (MPC962309 only. See Table 3.Select Input Decoding for MPC962309) 8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin TSSOP package (MPC962309) Single 3.3 V supply Ambient temperature range: -40C to +85C Compatible with the CY2305, CY23S05, CY2309, CY23S09 Spread spectrum compatible MPC962305 MPC962309 D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 DT SUFFIX 8-LEAD TSSOP PACKAGE CASE 948J-01 D SUFFIX 16-LEAD SOIC PACKAGE CASE 751B-05 DT SUFFIX 16-LEAD TSSOP PACKAGE CASE 948F-01 Functional Description The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3.Select Input Decoding for MPC962309. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 A of current draw for the device. The PLL shuts down in one additional case as shown in Table 3.Select Input Decoding for MPC962309. Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this situation, the difference between the output skews of two devices will be less than 700 ps. All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps. The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H, are available to provide faster rise and fall times of the base device. Pentium II is a trademark of Intel Corporation. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 507 MPC962305 Block Diagram PLL MUX REF CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 Select Input Decoding CLKB2 CLKB3 CLKB4 Pin Configuration REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 SOIC/TSSOP Top View 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 SOIC/TSSOP Top View 1 8 2 7 3 6 4 5 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 S2 S1 REF CLK2 CLK1 GND CLKOUT CLK4 VDD CLK3 Table 1. Pin Description for MPC962309 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF 1 Signal CLKA12 CLKA2 VDD GND CLKB1 3 2 2 Description Input reference frequency, 5 V-tolerant input Buffered clock output, Bank A Buffered clock output, Bank A 3.3 V supply Ground Buffered clock output, Bank B Buffered clock output, Bank B Select input, bit 2 Select input, bit 1 CLKB22 S2 S13 CLKB3 CLKB4 GND VDD CLKA3 CLKA4 2 2 2 2 Buffered clock output, Bank B Buffered clock output, Bank B Ground 3.3 V supply Buffered clock output, Bank A Buffered clock output, Bank A Buffered output, internal feedback on this pin CLKOUT2 Table 2. Pin Description for MPC962305 Pin 1 2 3 4 5 6 7 8 REF1 CLK22 CLK1 GND CLK3 VDD CLK42 CLKOUT2 2 2 Signal Buffered clock output Buffered clock output Ground Buffered clock output 3.3 V supply Buffered clock output Description Input reference frequency, 5 V-tolerant input Buffered clock output, internal feedback on this pin3 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 508 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC962305 Table 3. Select Input Decoding for MPC962309 S2 0 0 1 1 S1 0 1 0 1 CLOCK A1-A4 Three-State Driven Driven Driven CLOCK B1-B4 Three-State Three-State Driven Driven CLKOUT1 Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown N N Y N 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Table 4. Maximum Ratings Characteristics Supply Voltage to Ground Potential DC Input Voltage (Except Ref) DC Input Voltage REF Storage Temperature Junction Temperature Static Discharge Voltage (per MIL-STD-883, Method 3015) Value -0.5 to +3.9 -0.5 to VDD+0.5 -0.5 to 5.5 -65 to +150 150 >2000 Unit V V V C C V Table 5. Operating Conditions for MPC962305-X and MPC962309-X Industrial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance Description Min 3.0 -40 Max 3.6 85 30 10 7 Unit V C pF pF pF Table 6. Electrical Characteristics for MPC962305-X and MPC962309-X Industrial Temperature Devices1 Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage2 Input HIGH Voltage2 Input LOW Current Input HIGH Current Output LOW Voltage3 Output HIGH Voltage3 Power Down Supply Current Supply Current VIN = 0 V VIN = VDD IOL = 8 mA (-1) IOH = 12 mA (-1H) IOH = -8 mA (-1) IOL = -12 mA (-1H) REF = 0 MHz Unloaded outputs at 66.67 MHz, SEL inputs at VDD 2.4 25.0 35.0 2.0 50.0 100.0 0.4 Test Conditions Min Max 0.8 Unit V V A A V V A mA 1. All parameters are specified with loaded outputs. 2. REF input has a threshold voltage of VPP/2. 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 509 MPC962305 Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices1 Parameter t1 Name Output Frequency Duty Cycle2 = t2 / t1 t3 t4 t5 t6A t6B t7 tJ tLOCK Rise Time2 Fall Time2 Output to Output Skew2 Delay, REF Rising Edge to CLKOUT Rising Edge2 Delay, REF Rising Edge to CLKOUT Rising Edge2 Device to Device Skew Cycle to Cycle Jitter2 PLL Lock Time2 2 Test Conditions 30-pF load 10-pF load Measured at 1.4 V, FOUT = 66.67 MHz Measured between 0.8 V and 2.0 V Measured between 0.8 V and 2.0 V All outputs equally loaded Measured at VDD/2 Measured at VDD/2. Measured in PLL Bypass Mode, MPC962309 device only Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin Min 10 10 40.0 Typ Max 100 133.33 Unit MHz MHz % ns ns ps ps ns 50.0 60.0 2.50 2.50 250 0 1 5 350 8.7 0 700 200 1.0 ps ps ms 1. All parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices1 Parameter t1 Name Output Frequency Duty Cycle2 = t2 / t1 Duty Cycle2 = t2 / t1 t3 t4 t5 t6A t6B t7 t8 tJ tLOCK Rise Time2 Fall Time2 Output to Output Skew2 30-pF load 10-pF load Measured at 1.4 V, FOUT = 66.67 MHz Measured at 1.4 V, FOUT < 50 MHz Measured between 0.8 V and 2.0 V Measured between 0.8 V and 2.0 V All outputs equally loaded 0 1 5 Test Conditions Min 10 10 40.0 45.0 50.0 55.0 Typ Max 100 133.33 60.0 55.0 1.50 1.50 250 350 8.7 Unit MHz MHz % % ns ns ps ps ns Delay, REF Rising Edge to Measured at V /2 DD CLKOUT Rising Edge2 Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL Bypass Mode, CLKOUT Rising Edge2 MPC962309 device only Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8 V and 2.0 V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin 1 Device to Device Skew2 Output Slew Rate2 Cycle to Cycle Jitter2 PLL Lock Time2 0 700 ps V/ns 200 1.0 ps ms 1. All parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. 510 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC962305 APPLICATIONS INFORMATION VCC 1.4 V GND VCC 1.4 V GND t5 The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t6 FB_IN CCLK VCC VCC / 2 GND VCC VCC / 2 GND Figure 1. Output-to-Output Skew tSK(O) Figure 2. Static Phase Offset Test Reference VCC 1.4 V GND t2 t1 DC = t2/t1 x 100% t7 The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage DEVICE 2 DEVICE 1 VCC VCC / 2 GND VCC VCC / 2 GND Figure 4. Device-to-Device Skew Figure 3. Output Duty Cycle (DC) VCC = 3.3 V 2.0 tJ = |tN-tN+1| t4 t3 0.8 tN tN+1 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 5. Cycle-to-Cycle Jitter Figure 6. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 511 MPC962305 Test Circuit #1 VDD 0.1 F OUTPUTS CLKOUT CLOAD VDD 0.1 F GND GND 0.1 F VDD GND GND 0.1 F Test Circuit #2 VDD OUTPUTS 1K 1K CLKOUT 10 pF Test Circuit for all parameters except t8 Test Circuit for t8, Output slew rate on -1H, -5 device Table 9. Ordering Information Ordering Code MPC962305D-1 MPC962305D-1R2 MPC962305D-1H MPC962305D-1HR2 MPC962305DT-1H MPC962305DT-1HR2 MPC962309D-1 MPC962309D-1R2 MPC962309D-1H MPC962309D-1HR2 MPC962309DT-1H MPC962309DT-1HR2 8-pin 150-mil SOIC 8-pin 150-mil SOIC-Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC-Tape and Reel 8-pin 150-mil TSSOP 8-pin 150-mil TSSOP-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP-Tape and Reel Package Type 512 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC962308 Rev 3, 08/2004 3.3 V Zero Delay Buffer The MPC962308 is a 3.3 V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. The MPC962308 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. The input-to-output skew is guaranteed to be less than 250 ps and output-to-output skew is guaranteed to be less than 200 ps. Features * * * * * * * * * * * * * * * 1:8 outputs LVCMOS zero-delay buffer Zero input-output propagation delay, adjustable by the capacitive load on FBK input Multiple Configurations, see Table 11. Available MPC962308 Configurations Multiple low-skew outputs 200 ps max output-output skew 700 ps max device-device skew Two banks of four outputs, output tristate control by two select inputs Supports a clock I/O frequency range of 10 MHz to 133 MHz Low jitter, 200 ps max cycle-cycle (-1, -1H, -4, -5H) 250 ps static phase offset (SPO) 16-pin SOIC package or 16-pin TSSOP package Single 3.3 V supply Ambient temperature range: -40C to +85C Compatible with the CY2308 and CY23S08 Spread spectrum compatible MPC962308 D SUFFIX 16-LEAD SOIC PACKAGE CASE 751B-05 DT SUFFIX 16-LEAD TSSOP PACKAGE CASE 948F-01 Functional Description The MPC962308 has two banks of four outputs each which can be controlled by the select inputs as shown in Table 10. Select Input Decoding. Bank B can be tristated if all of the outputs are not required. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The MPC962308 PLL enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate and there is less than 50 A of current draw. The PLL shuts down in two additional cases explained in Table 10. Select Input Decoding. Multiple MPC962308 devices can accept and distribute the same input clock throughout the system. In this situation, the difference between the output skews of two devices will be less than 700 ps. The MPC962308 is available in five different configurations as shown in Table 11. Available MPC962308 Configurations. In the MPC962308-1, the reference frequency is reproduced by the PLL and provided at the outputs. A high drive version of this configuration, the MPC962308-1H, is available to provide faster rise and fall times of the device. The MPC962308-2 provides 2X and 1X the reference frequency at the output banks. In addition, the MPC962308-3 provides 4X and 2X the reference frequency at the output banks. The output banks driving the feedback will determine the different configurations of the above devices. The MPC962308-4 provides outputs 2X the reference frequency.The MPC962308-5H is a high drive version with outputs of REF/2. The MPC962308 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines on the incident edge. Depending on the configuration, the device is offered in a 16-lead SOIC or 16-lead TSSOP package. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 513 MPC962308 Block Diagram /2 REF /2 Extra Divider (-3, -4) Extra Divider (-5H) S2 S1 Select Input Decoding Pin Configuration SOIC/TSSOP Top View REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 PLL MUX FBK CLKA1 CLKA2 CLKA3 CLKA4 /2 CLKB1 CLKB2 CLKB3 Extra Divider (-2, -3) CLKB4 Table 10. Select Input Decoding S2 0 0 1 1 S1 0 1 0 1 CLOCK A1--A4 Three-State Driven Driven1 Driven CLOCK B1--B4 Three-State Three-State Driven1 Driven Output Source PLL PLL Reference PLL PLL Shutdown Y N Y N 1. Outputs inverted on MPC962308-2 in bypass mode, S2=1 and S1=0. Table 11. Available MPC962308 Configurations Device MPC962308-1 MPC962308-1H MPC962308-2 MPC962308-2 MPC962308-3 MPC962308-3 MPC962308-4 MPC962308-5H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Reference /2 Bank B Frequency Reference Reference Reference/2 Reference Reference or Reference[1] 2 X Reference 2 X Reference Reference /2 1. Output phase is indeterminate (0 or 180 from input clock). If phase integrity is required, use the MPC962308-2. 514 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC962308 Table 12. Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF 1 Signal Description Input reference frequency, 5 V tolerant input Clock output, Bank A Clock output, Bank A 3.3 V supply Ground CLKA12 CLKA22 VDD GND CLKB1 2 Clock output, Bank B Clock output, Bank B Select input, bit 2 Select input, bit 1 Clock output, Bank B Clock output, Bank B Ground 3.3 V supply Clock output, Bank A Clock output, Bank A PLL feedback input CLKB22 S23 S13 CLKB32 CLKB42 GND VDD CLKA32 CLKA42 FBK 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. Table 13. Maximum Ratings Characteristics Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage REF Storage Temperature Junction Static Discharge Voltage (per MIL-STD-883, Method 3015) Value -0.5 to +3.9 -0.5 to VDD+0.5 -0.5 to 5.5 -65 to +150 150 >2000 Unit V V V C C V FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 515 MPC962308 Table 14. Operating Conditions for MPC962308-X Industrial Temperature Devices Parameter VDD TA CL Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz CIN Input Capacitance1 Description Min 3.0 -40 Max 3.6 85 30 15 7 Unit V C pF pF pF 1. Applies to both REF clock and FBK. Table 15. Electrical Characteristics for MPC962308-X Industrial Temperature Devices1 Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage2 Output HIGH Voltage2 Power Down Supply Current Supply Current VIN = 0V VIN = VDD IOL = 8 mA (-1, -2, -3, -4) IOL = 12 mA (-1H, -5H) IOH = -8 mA (-1, -2, -3, -4) IOH = -12 mA (-1H, -5H) REF = 0 MHz Unloaded outputs, 100 MHz, Select inputs at VDD or GND Unloaded outputs, 66-MHz REF (-1, -2, -3, -4) Unloaded outputs, 35-MHz REF (-1, -2, -3, -4) 1. All parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. 2.4 25.0 45.0 70(-1H, -5H) 35.0 20.0 2.0 50.0 100.0 0.4 Test Conditions Min Max 0.8 Unit V V A A V V A mA mA mA mA 516 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC962308 Table 16. Switching Characteristics for MPC962308-X Industrial Temperature Devices1 Parameter t1 t1 t1 Name Output Frequency Output Frequency2 Output Frequency2 Duty Cycle2 = t2 / t1 (-1, -2, -3, -4, -1H, -5H) Duty Cycle2 = t2 / t1 (-1, -2, -3, -4, -1H, -5H) t3 Rise Time2 (-1, -2, -3, -4) Rise Time2 (-1, -2, -3, -4) Rise Time2 (-1H, -5H) t4 Fall Time2 (-1, -2, -3, -4) Fall Time2 (-1, -2, -3, -4) Fall Time2 (-1H, -5H) Output-to-Output Skew on same Bank (-1, -2, -3, -4)2 t5 Output-to-Output Skew (-1H, -5H) Output Bank A to Output Bank B Skew (-1, -4, -5H) Output Bank A to Output Bank B Skew (-2, -3) t6 t7 t8 tJ Delay, REF Rising Edge to FBK Rising Edge2 Device-to-Device Skew2 Output Slew Rate 2 Test Conditions 30-pF load, All devices 20-pF load, -1H, -5H devices 15-pF load, -1, -2, -3, -4 devices Measured at 1.4 V, FOUT =66.66 MHz 30-pF load Measured at 1.4 V, FOUT <50.0 MHz 15-pF load Measured between 0.8 V and 2.0 V, 30-pF load Measured between 0.8 V and 2.0 V, 15-pF load Measured between 0.8 V and 2.0 V, 30-pF load Measured between 0.8 V and 2.0 V, 30-pF load Measured between 0.8 V and 2.0 V, 15-pF load Measured between 0.8 V and 2.0 V, 30-pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured between 0.8 V and 2.0 V on -1H, -5H device using Test Circuit # 2 Measured at 66.67 MHz, loaded outputs, 15-pF load Measured at 66.67 MHz, loaded outputs, 30-pF load Measured at 133.3 MHz, loaded outputs, 15 pF load Min 10 10 10 40.0 45.0 Typ Max 100 133.3 133.3 60.0 55.0 2.50 1.50 1.50 2.50 1.50 1.25 200 200 200 400 Unit MHz MHz MHz % % ns ns ns ns ns ns ps ps ps ps ps ps V/ns 0 0 1 250 700 Cycle-to-Cycle Jitter (-1, -1H, -4, -5H)2 200 200 100 400 400 1.0 ps ps ps ps ps ms tJ Cycle-to-Cycle Jitter (-2, -3)2 Measured at 66.67 MHz, loaded outputs 30-pF load Measured at 66.67 MHz, loaded outputs 15-pF load tLOCK PLL Lock Time2 Stable power supply, valid clocks presented on REF and FBK pins 1. All parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 517 MPC962308 APPLICATIONS INFORMATION VCC 1.4 V GND VCC 1.4 V GND t5 The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t6 FB_IN CCLK VCC VCC / 2 GND VCC VCC / 2 GND Figure 1. Output-to-Output Skew tSK(O) Figure 2. Static Phase Offset Test Reference VCC 1.4 V GND t2 t1 DC = t2/t1 x 100% VCC DEVICE 1 VCC / 2 GND DEVICE 2 VCC VCC / 2 GND t7 The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 4. Device-to-Device Skew Figure 3. Output Duty Cycle (DC) VCC = 3.3 V 2.0 tJ = |tN-tN+1| t4 t3 0.8 tN tN+1 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 5. Cycle-to-Cycle Jitter Figure 6. Output Transition Time Test Reference 518 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC962308 Test Circuit #1 VDD 0.1 F OUTPUTS CLKOUT CLOAD 0.1 F VDD GND GND 0.1 F VDD GND GND 0.1 F Test Circuit #2 VDD OUTPUTS 1 K 1 K CLKOUT 10 pF Test Circuit for all parameters except t8 Test Circuit for t8, Output slew rate on -1H, -5 device Ordering Information (Available) Ordering Code MPC962308D-1 MPC962308D-1R2 MPC962308D-1H MPC962308D-1HR2 MPC962308DT-1H MPC962308DT-1HR2 MPC962308D-2 MPC962308D-2R2 Package Name D16 D16 D16 D16 DT16 DT16 D16 D16 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP -- Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel Package Type Ordering Information (Planned) Ordering Code MPC962308D-3 MPC962308D-3R2 MPC962308D-4 MPC962308D-4R2 MPC962308D-5H MPC962308D-5HR2 MPC962308DT-5H MPC962308DT-5HR2 Package Name D16 D16 D16 D16 D16 D16 DT16 DT16 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP -- Tape and Reel Package Type FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 519 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9653 Rev 2, 02/2002 3.3 V 1:8 LVCMOS PLL Clock Generator The MPC9653 is a 3.3 V compatible, 1:8 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 125 MHz and output skews less than 150 ps the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * 1:8 PLL based low-voltage clock generator Supports zero-delay operation 3.3 V power supply Generates clock signals up to 125 MHz Maximum output skew of 150 ps Differential LVPECL reference clock input External PLL feedback Drives up to 16 clock lines 32 lead LQFP packaging Ambient temperature range 0C to +70C Pin and function compatible to the MPC953 MPC9653 LOW VOLTAGE 3.3 V LVCMOS 1:8 PLL CLOCK GENERATOR FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC9653 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9653 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to 62.5 MHz or 50 to 125 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653 is running at either 4x or 8x of the reference clock frequency. The MPC9653 has a differential LVPECL reference input along with an external feedback input. The device is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9653 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9653 outputs can drive one or two traces giving the devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package. 520 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9653 VCC 225 k PCLK PCLK 0 & Ref VCO 1 /1 /2 0 1 0 /4 1 Q0 Q1 Q2 Q3 Q4 Q5 PLL * 200-500 MHz VCC 25 k FB_IN VCC 325 k PLL_EN VCO_SEL BYPASS MR/OE 25 k FB Q6 Q7 QFB * PLL will lock @ 145 MHz. Figure 1. MPC9653 Logic Diagram GND 24 GND Q0 VCC QFB GND PLL_EN BYPASS VCO_SEL 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 GND 17 16 15 14 Q5 VCC Q6 GND Q7 VCC MR/OE PCLK 13 12 11 10 9 8 PCLK VCC VCC 6 NC Q1 Q2 Q3 MPC9653 2 3 4 5 VCC_PLL NC NC FB_IN NC Figure 2. MPC9653 32-Lead Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GND Q4 7 521 MPC9653 Table 1. Pin Configurations Number PCLK, PCLK FB_IN VCO_SEL BYPASS PLL_EN MR/OE Q0-7 QFB GND VCC_PLL Name Input Input Input Input Input Input Output Output Supply Supply Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC PECL reference clock signal PLL feedback signal input, connect to QFB Operating frequency range select PLL and output divider bypass select PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Clock output for PLL feedback, connect to FB_IN Negative power supply (GND) PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see APPLICATIONS INFORMATION for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Description VCC Supply VCC Table 2. Function Table Control PLL_EN Default 1 0 Test mode with PLL bypassed. The reference clock (PCLK) Selects the VCO output1 is substituted for the internal VCO output. MPC9653 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs. MPC9653 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. VCO / 1 (High frequency range). fREF = fQ0-7 = 4 fVCO Outputs enabled (active) Selects the output dividers. 1 BYPASS 1 VCO_SEL MR/OE 1 0 VCO / 2 (Low output range). fREF = fQ0-7 = 8 fVCO Outputs disabled (high-impedance state) and reset of the device. During reset the PLL feedback loop is open. The VCO is tied to its lowest frequency. The length of the reset pulse should be greater than one reference clock cycle (PCLK). 1. PLL operation requires BYPASS = 1 and PLL_EN = 1. 522 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9653 Table 3. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance Min Typ VCC / 2 Max Unit V V V mA Condition 200 2000 200 10 4.0 pF pF Per output Inputs Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 3.3 V 5%, TA = 0C to 70C) Symbol VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICC_PLL ICCQ 4 Characteristics Input high voltage Input low voltage Peak-to-peak input voltage Common Mode Range Output High Voltage Output Low Voltage Output impedance Input Current3 Maximum PLL Supply Current Maximum Quiescent Supply Current (PCLK) (PCLK) Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V mV Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -24 mA2 IOL = 24 mA IOL = 12 mA 300 1.0 2.4 0.55 0.30 14 - 17 200 5.0 10 10 VCC-0.6 V V V V A mA mA VIN = VCC or GND VCC_PLL Pin All VCC Pins 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9653 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. The MPC9653 meets the VOH and VOL specification of the MPC953 (VOH > VCC -0.6 V at IOH= -20 mA and VOL > 0.6 V at IOL= 20 mA). 3. Inputs have pull-down or pull-up resistors affecting the input current. 4. OE/MR = 1 (outputs in high-impedance state). FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 523 MPC9653 Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to 70C)1 Symbol fREF Characteristics Input Reference Frequency PLL Mode, External Feedback / 4 feedback2 / 8 feedback 3 Min 50 25 0 200 / 4 feedback2 / 8 feedback3 PCLK PCLK 50 25 450 1.2 2 PCLK to FB_IN -75 1.2 3.0 Typ Max 125 62.5 200 500 125 62.5 1000 VCC -0.75 Unit MHz MHz MHz MHz MHz MHz mV V ns Condition PLL locked PLL locked Input reference frequency in PLL bypass mode4 fVCO fMAX VPP VCMR6 tPW,MIN t() tPD VCO Lock Frequency Range Output Frequency Peak-to-Peak Input Voltage Common Mode Range Input Reference Pulse Width7 Propagation Delay (static phase offset)8 5 PLL locked PLL locked LVPECL LVPECL 125 3.3 7.0 150 1.5 ps ns ns ps ns % ns ns ns ps ps ps MHz MHz ms PLL locked Propagation Delay PLL and divider bypass (BYPASS = 0), PCLK to Q0-7 PLL disable (BYPASS = 1 and PLL_EN = 0), PCLK to Q0-7 Output-to-Output Skew9 Device-to-Device Skew in PLL and Divider Bypass10 Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter11 PLL Closed Loop Bandwidth12 PLL Mode, External Feedback Maximum PLL Lock Time /8 RMS (1) / 4 feedback2 feedback3 tsk(O) tsk(PP) DC tR, tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW BYPASS = 0 PLL locked 0.55 to 2.4 V 45 0.1 50 55 1.0 7.0 6.0 100 100 25 0.8 - 4 0.5 - 1.3 10 tLOCK 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. AC characteristics apply for parallel output termination of 50 to VTT. /4 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE = 0. /8 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE = 0. In bypass mode, the MPC9653 divides the input reference clock. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO / FB. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF,MIN. For example, at fREF = 100 MHz the input duty cycle range is 20% < DC < 80%. Valid for fREF = 50 MHz and FB = / 8 (VCO_SEL = 1). For other reference frequencies: t() [ps] = 50 ps (1 / (120 fREF)). Refer to APPLICATIONS INFORMATION for part-to-part skew calculation in PLL zero-delay mode. For a specified temperature and voltage, includes output skew. I/O phase jitter is reference frequency dependent. Refer to APPLICATIONS INFORMATION for details. -3 dB point of PLL transfer characteristics. 524 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9653 APPLICATIONS INFORMATION Programming the MPC9653 The MPC9653 supports output clock frequencies from 25 to 125 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500 MHz for stable and optimal operation. Two operating frequency ranges Table 7. MPC9653 Configurations (QFB connected to FB_IN) BYPASS 0 1 1 1 1 PLL_EN X 0 0 1 1 VCO_SEL X 0 1 0 1 Operation Test mode: PLL and divider bypass Test mode: PLL bypass Test mode: PLL bypass PLL mode (high frequency range) PLL mode (low frequency range) Frequency Ratio fQ0-7 = fREF fQ0-7 = fREF / 4 fQ0-7 = fREF / 8 fQ0-7 = fREF fQ0-7 = fREF Output range (fQ0-7) 0-200 MHz 0-50 MHz 0-25 MHz 50 to 125 MHz 25 to 62.5 MHz VCO n/a n/a n/a fVCO = fREF 4 fVCO = fREF 8 are supported: 25 to 62.5 MHz and 50 to 125 MHz. Table 7.MPC9653 Configurations (QFB connected to FB_IN) illustrates the configurations supported by the MPC9653. PLL zero-delay is supported if BYPASS = 1, PLL_EN = 1 and the input frequency is within the specified PLL reference frequency range. Power Supply Filtering The MPC9653 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9653 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9653. Figure 3 illustrates a typical power supply filter scheme. The MPC9653 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCC_PLL pin) is typically 5 mA (10 mA maximum), assuming that a minimum of 2.985 V must be maintained on the VCC_PLL pin. RF = 5-15 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9653 VCC 33...100 nF The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 4 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9653 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9653 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9653. Designs using the MPC9653 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9653 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Figure 3. VCC_PLL Power Supply Filter FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 525 MPC9653 Calculation of Part-to-Part Skew The MPC9653 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9653 are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consist of four components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of - 197 ps to 297 ps (at 125 MHz reference frequency) relative to PCLK: tSK(PP) = [-17ps...117ps] + [-150ps...150ps] + [(10ps -3)...(10ps 3)] + tPD, LINE(FB) tSK(PP) = [-197ps...297ps] + tPD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 5 can be used for a more precise timing performance analysis. 30 --t(y) QFBDevice 1 I/O Jitter [ps] RMS tPD,LINE(FB) 20 10 0 TCLKCommon tJIT() +tSK(O) +t() FB = / 8 25 35 45 55 65 75 FB = / 4 85 95 105 115 125 Reference frequency [MHz] Any QDevice 1 Figure 5. Max. I/O Jitter versus Frequency tJIT() QFBDevice2 Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 4. MPC9653 Max. Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8.Confidence Factor CF. Table 8. Confidence Factor CF CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 Driving Transmission Lines The MPC9653 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola Application Note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC / 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9653 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 6. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9653 clock driver is effectively doubled due to its capability to drive multiple lines. 526 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9653 MPC953 OUTPUT BUFFER IN 14 3.0 2.5 OutA VOLTAGE (V) 2.0 In 1.5 1.0 0.5 0 OutA tD = 3.8956 OutB tD = 3.9386 RS = 36 ZO = 50 MPC953 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9653 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9653. The output waveform in Figure 7 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18 + 14 + 25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0ns). 2 4 6 8 TIME (ns) 10 12 14 Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 8 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC961 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 8. Optimized Dual Line Termination Pulse Generator Z = 50 ZO = 50 MPC0653 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 9. PCLK MPC9653 AC Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 527 MPC9653 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device FB_IN t(PD) PCLK PCLK VPP = 0.8 V VCMR = VCC -1.3 V VCC VCC / 2 GND Figure 10. Output-to-Output Skew tSK(O) Figure 11. Propagation delay (t(PD), static phase offset) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage PCLK PCLK Ext_FB TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a T0 mean in a random sample of cycles Figure 12. Output Duty Cycle (DC) Figure 13. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 14. Cycle-to-Cycle Jitter Figure 15. Period Jitter VCC=3.3 V 2.4 0.55 tF tR Figure 16. Output Transition Time Test Reference 528 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9653A Rev 3, 08/2004 3.3 V 1:8 LVCMOS PLL Clock Generator The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 125 MHz and output skews less than 150 ps the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * 1:8 PLL based low-voltage clock generator Supports zero-delay operation 3.3 V power supply Generates clock signals up to 125 MHz PLL guaranteed to lock down to 145 MHz, output frequency = 36.25 MHz Maximum output skew of 150 ps Differential LVPECL reference clock input External PLL feedback Drives up to 16 clock lines 32-lead LQFP packaging 32-lead Pb-free Package Available Ambient temperature range 0C to +70C Pin and function compatible to the MPC953 and MPC9653 MPC9653A LOW VOLTAGE 3.3 V LVCMOS 1:8 PLL CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 AC SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC9653A utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9653A requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to 62.5 MHz or 50 to 125 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653A is running at either 4x or 8x of the reference clock frequency. The MPC9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or Fref = 36.25 MHz. The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 529 MPC9653A VCC 225 k PCLK PCLK 0 & Q0 /1 /2 0 0 1 /4 1 Q1 Q2 Q3 Q4 Q5 Ref VCO 1 VCC 25 k FB_IN VCC 325 k PLL_EN VCO_SEL BYPASS MR/OE 25 k PLL1 200-500 MHz FB Q6 Q7 QFB Note 1. PLL will lock @ 145 MHz Figure 1. MPC9653A Logic Diagram GND 24 GND Q0 VCC QFB GND PLL_EN BYPASS VCO_SEL 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 GND 17 16 15 14 13 Q5 VCC Q6 GND Q7 VCC MR/OE PCLK 12 11 10 9 8 PCLK VCC VCC 6 NC Q1 Q2 Q3 MPC9653A 2 3 4 5 NC NC FB_IN NC Figure 2. MPC9653A 32-Lead Package Pinout (Top View) 530 VCC_PLL FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GND Q4 7 MPC9653A Table 1. Pin Configuration Pin PCLK, PCLK FB_IN VCO_SEL BYPASS PLL_EN MR/OE Q0-7 QFB GND VCC_PLL VCC I/O Input Input Input Input Input Input Output Output Supply Supply Supply Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PECL reference clock signal PLL feedback signal input, connect to QFB Operating frequency range select PLL and output divider bypass select PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Clock output for PLL feedback, connect to FB_IN Negative power supply (GND) PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Refer to APPLICATIONS INFORMATION for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function Table 2. Function Table Control PLL_EN Default 1 0 Test mode with PLL bypassed. The reference clock (PCLK) is substituted for the internal VCO output. MPC9653A is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs. MPC9653A is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. VCO / 1 (High frequency range). fREF = fQ0-7 = 4 fVCO Outputs enabled (active) Selects the VCO output1 1 BYPASS 1 Selects the output dividers. VCO_SEL MR/OE 1 0 VCO / 2 (Low output range). fREF = fQ0-7 = 8 fVCO Outputs disabled (high-impedance state) and reset of the device. During reset the PLL feedback loop is open. The VCO is tied to its lowest frequency. The length of the reset pulse should be greater than one reference clock cycle (PCLK). 1. PLL operation requires BYPASS = 1 and PLL_EN = 1. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 531 MPC9653A Table 3. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 3.3 V 5%, TA = 0C to 70C) Symbol VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICC_PLL ICCQ4 Characteristics Input high voltage Input low voltage Peak-to-peak input voltage Common Mode Range Output High Voltage Output Low Voltage Output impedance Input Current3 Maximum PLL Supply Current Maximum Quiescent Supply Current 5.0 14 - 17 200 10 10 (PCLK) (PCLK) 300 1.0 2.4 0.55 0.30 VCC - 0.6 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V mV V V V V A mA mA VIN = VCC or GND VCC_PLL Pin All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -24 mA2 IOL = 24 mA IOL = 12 mA 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9653A is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. The MPC9653A meets the VOH and VOL specification of the MPC953 (VOH > VCC -0.6 V at IOH = -20 mA and VOL > 0.6 V at IOL = 20 mA). 3. Inputs have pull-down or pull-up resistors affecting the input current. 4. OE/MR = 1 (outputs in high-impedance state). 532 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9653A Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to 70C)1 Symbol fREF Characteristics Input Reference Frequency PLL Mode, External Feedback / 4 feedback 2 Min / 8 feedback3 50 25 0 200 145 / 4 feedback2 /8 feedback3 PCLK PCLK 50 25 450 1.2 2 PCLK to FB_IN -75 1.2 3.0 Typ Max 125 62.5 200 500 500 125 62.5 1000 VCC - 0.75 Unit MHz MHz MHz MHz MHz MHz MHz mV V ns Condition PLL locked PLL locked Input reference frequency in PLL bypass mode4 fVCO fVCOlock fMAX VPP VCMR 8 VCO Operating Frequency Range5, 6 VCO Lock Frequency Range7 Output Frequency Peak-to-Peak Input Voltage Common Mode Range Input Reference Pulse Width9 Propagation Delay (static phase offset)10 PLL locked PLL locked LVPECL LVPECL tPW, MIN t() tPD 125 3.3 7.0 150 1.5 ps ns ns ps ns % ns ns ns ps ps ps MHz MHz ms PLL locked Propagation Delay PLL and divider bypass (BYPASS = 0), PCLK to Q0-7 PLL disable (BYPASS = 1 and PLL_EN = 0), PCLK to Q0-7 Output-to-Output Skew11 Device-to-Device Skew in PLL and Divider Bypass12 Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle jitter Period Jitter I/O Phase Jitter13 PLL closed loop bandwidth14 PLL mode, external feedback Maximum PLL Lock Time RMS (1) / 4 feedback2 / 8 feedback 3 tsk(O) tsk(PP) DC tR, tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW tLOCK 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. BYPASS = 0 PLL locked 0.55 to 2.4 V 45 0.1 50 55 1.0 7.0 6.0 100 100 25 0.8 - 4 0.5 - 1.3 10 AC characteristics apply for parallel output termination of 50 to VTT. / 4 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE = 0. / 8 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE = 0. In bypass mode, the MPC9653A divides the input reference clock. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO / FB. fVCO is frequency range where AC parameters are guaranteed. fVCOlock is frequency range that the PLL guaranteed to lock, AC parameters only guaranteed over fVCO. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF,MIN. For example, at fREF = 100 MHz the input duty cycle range is 20% < DC < 80%. Valid for fREF = 50 MHz and FB = / 8 (VCO_SEL = 1). For other reference frequencies: t() [ps] = 50 ps (1 / (120 fREF)). Refer to the Application Information section for part-to-part skew calculation in PLL zero-delay mode. For a specified temperature and voltage, includes output skew. I/O phase jitter is reference frequency dependent. Refer to APPLICATIONS INFORMATION section for details. -3 dB point of PLL transfer characteristics. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 533 MPC9653A APPLICATIONS INFORMATION Programming the MPC9653A The MPC9653A supports output clock frequencies from 25 to 125 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500 MHz for stable and optimal operation. Two operating frequency ranges Table 7. MPC9653A Configurations (QFB connected to FB_IN) BYPASS 0 1 1 1 1 PLL_EN X 0 0 1 1 VCO_SEL X 0 1 0 1 Operation Test mode: PLL and divider bypass Test mode: PLL bypass Test mode: PLL bypass PLL mode (high frequency range) PLL mode (low frequency range) Frequency Ratio fQ0-7 = fREF fQ0-7 = fREF / 4 fQ0-7 = fREF / 8 fQ0-7 = fREF fQ0-7 = fREF Output Range (fQ0-7) 0 - 200 MHz 0 - 50 MHz 0 - 25 MHz 50 to 125 MHz 25 to 62.5 MHz VCO n/a n/a n/a fVCO = fREF 4 fVCO = fREF 8 are supported: 25 to 62.5 MHz and 50 to 125 MHz. Table 7 illustrates the configurations supported by the MPC9653A. PLL zero-delay is supported if BYPASS = 1, PLL_EN = 1 and the input frequency is within the specified PLL reference frequency range. Power Supply Filtering The MPC9653A is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9653A provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9653A. Figure 3 illustrates a typical power supply filter scheme. The MPC9653A frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCC_PLL pin) is typically 5 mA (10 mA maximum), assuming that a minimum of 2.985 V must be maintained on the VCC_PLL pin. RF = 5-15 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9653A VCC 33...100 nF The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 4 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9653A has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9653A in Zero-Delay Applications Nested clock trees are typical applications for the MPC9653A. Designs using the MPC9653A as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9653A clock driver allows for its use as a zero-delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Figure 3. VCC_PLL Power Supply Filter 534 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9653A Calculation of Part-to-Part Skew The MPC9653A zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9653As are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -197 ps to 297 ps (at 125 MHz reference frequency) relative to PCLK: tSK(PP) = [-17ps...117ps] + [-150ps...150ps] + [(10ps @ -3)...(10ps @ 3)] + tPD, LINE(FB) tSK(PP) = [-197ps...297ps] + tPD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 5, can be used for a more precise timing performance analysis. 30 3I/O Jitter [ps] RMS PCLKCommon --t(y) QFBDevice 1 tPD,LINE(FB) 20 tJIT() +tSK(O) +t() Any QDevice 1 10 0 25 FB = / 8 FB = / 4 35 45 55 65 75 85 95 105 115 125 Reference Frequency [MHz] QFBDevice2 tJIT() Figure 5. Maximum I/O Jitter versus Frequency Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 4. MPC9653A Maximum Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. Table 8. Confidence Factor CF CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 Driving Transmission Lines The MPC9653A clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC / 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9653A clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 5, illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9653A clock driver is effectively doubled due to its capability to drive multiple lines. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 535 MPC9653A MPC9653A OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA VOLTAGE (V) 2.0 In 1.5 1.0 0.5 0 3.0 2.5 OutA tD = 3.8956 OutB tD = 3.9386 MPC9653A OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9653A output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9653A. The output waveform in Figure 7 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18 + 14 + 25) = 1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 2 4 6 8 TIME (ns) 10 12 14 Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 8, should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9653A OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 8. Optimized Dual Line Termination Differential Pulse Generator Z = 50 ZO = 50 MPC9653A DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 9. MPC9653A AC Test Reference 536 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9653A VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device FB_IN t(PD) PCLK PCLK VPP = 0.8 V VCMR = VCC -1.3 V VCC VCC / 2 GND Figure 10. Output-to-Output Skew tSK(O) Figure 11. Propagation delay (t(PD), static phase offset) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage PCLK PCLK Ext_FB TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a T0 mean in a random sample of cycles Figure 12. Output Duty Cycle (DC) Figure 13. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 14. Cycle-to-Cycle Jitter Figure 15. Period Jitter VCC = 3.3 V 2.4 0.55 tF tR Figure 16. Output Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 537 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9658 Rev 4, 08/2004 3.3 V 1:10 LVCMOS PLL Clock Generator The MPC9658 is a 3.3 V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 250 MHz and output skews less than 120 ps the device meets the needs of the most demanding clock applications. The MPC9658 is specified for the temperature range of 0C to +70C. Features * * * * * * * * * * * 1:10 PLL based low-voltage clock generator Supports zero-delay operation 3.3 V power supply Generates clock signals up to 250 MHz Maximum output skew of 120 ps Differential LVPECL reference clock input External PLL feedback Drives up to 20 clock lines 32-lead LQFP packaging 32-lead Pb-free Package Available Pin and function compatible to the MPC958 MPC9658 LOW VOLTAGE 3.3 V LVCMOS 1:10 PLL CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC9658 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9658 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 50 to 125 MHz or 100 to 250 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-2 or divide-by-4) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9658 is running at either 2x or 4x of the reference clock frequency. The MPC9658 has a differential LVPECL reference input along with an external feedback input. The MPC9658 is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9658 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9658 outputs can drive one or two traces giving the devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package. 538 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9658 Q0 VCC 225 k PCLK PCLK 0 & Q1 /1 /2 0 0 1 /2 1 Q2 Q3 Q4 Q5 Q6 Ref VCO 1 PLL 200 - 480 MHz VCC 25 k FB_IN VCC 325 k PLL_EN VCO_SEL BYPASS MR/OE 25 k FB Q7 Q8 Q9 QFB Figure 1. MPC9658 Logic Diagram GND 24 GND Q1 VCC Q0 GND QFB VCC VCO_SEL 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 GND 17 16 15 14 Q6 VCC Q7 GND Q8 VCC Q9 GND 13 12 11 10 9 8 GND VCC VCC 6 PCLK Q2 Q3 Q4 MPC9658 2 3 4 5 VCC_PLL BYPASS FB_IN PLL_EN Figure 2. MPC9658 32-Lead Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MR/OE PCLK Q5 7 539 MPC9658 Table 1. Pin Configurations Number PCLK, PCLK FB_IN VCO_SEL BYPASS PLL_EN MR/OE Q0-9 QFB GND VCC_PLL Name Input Input Input Input Input Input Output Output Supply Supply Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC PECL reference clock signal PLL feedback signal input, connect to QFB Operating frequency range select PLL and output divider bypass select PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Clock output for PLL feedback, connect to FB_IN Negative power supply (GND) PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Refer to APPLICATIONS INFORMATION for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. Description VCC Supply VCC Table 2. Function Table Control PLL_EN Default 1 0 Test mode with PLL bypassed. The reference clock (PCLK) Selects the VCO output.1 is substituted for the internal VCO output. MPC9658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs. MPC9658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. VCO / 1 (High frequency range). fREF = fQ0-9 = 2 fVCO Outputs enabled (active) Selects the output dividers. 1 BYPASS 1 VCO_SEL MR/OE 1 0 VCO / 2 (Low output range). fREF = fQ0-9 = 4 fVCO Outputs disabled (high-impedance state) and reset of the device. During reset the PLL feedback loop is open. The VCO is tied to its lowest frequency. The length of the reset pulse should be greater than one reference clock cycle (PCLK). 1. PLL operation requires BYPASS = 1 and PLL_EN = 1. Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC +0.3 VCC +0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 540 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9658 Table 4. General Specifications Symbol VTT MM HBM LU CPD CIN JA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance LQFP 32 Thermal resistance junction to ambient JESD 51-3, single layer test board 200 2000 200 10 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC / 2 Max Unit V V V mA pF pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Per output Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC LQFP 32 Thermal resistance junction to case Table 5. DC Characteristics (VCC = 3.3 V 5%, TA = 0C to 70C) Symbol VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICC_PLL ICCQ Characteristics Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage3 Output Impedance Input Current4 12 13 14 - 17 200 20 20 (PCLK) (PCLK) 250 1.0 2.4 0.55 0.30 VCC -0.6 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V mV V V V V A mA mA VIN = VCC or GND VCC_PLL Pin All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -24 mA2 IOL = 24 mA IOL = 12 mA Maximum PLL Supply Current Maximum Quiescent Supply Current 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9658 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 3. The MPC9658 output levels are compatible to the MPC958 output levels. 4. Inputs have pull-down resistors affecting the input current. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 541 MPC9658 Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to 70C)1 Symbol fREF Characteristics Input reference frequency PLL mode, external feedback / 2 feedback 2 Min / 4 feedback3 100 50 0 200 / 2 feedback3 / 4 feedback 4 Typ Max 250 125 250 500 250 125 1000 VCC -0.9 Unit MHz MHz MHz MHz MHz MHz mV V ns Condition PLL locked PLL locked Input reference frequency in PLL bypass mode4 fVCO fMAX VPP VCMR6 tPW,MIN t() VCO lock frequency range5 Output Frequency Peak-to-peak input voltage (PCLK) Common Mode Range (PCLK) Input Reference Pulse Width7 Propagation Delay (static phase offset) PCLK to FB_IN fREF = 100 MHz any frequency PCLK to Q0-9 100 50 500 1.2 2.0 -70 -125 1.0 PLL locked PLL locked LVPECL LVPECL PLL locked +80 +125 4.0 120 (T / 2)-400 0.1 T/2 (T / 2)+400 1.0 7.0 6.0 80 80 5.5 6.5 6 - 20 2-8 10 ps ps ns ps ps ns ns ns ps ps ps ps MHz MHz ms 0.55 to 2.4 V tPD tsk(O) DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW Propagation Delay (PLL and divider bypass) Output-to-output Skew8 Output Duty Cycle9 Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter I/O Phase Jitter fVCO = 500 MHz and / 2 feedback, RMS (1)10 fVCO = 500 MHz and / 4 feedback, RMS (1) PLL closed loop bandwidth11 Maximum PLL Lock Time / 2 feedback3 /4 feedback5 tLOCK 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. AC characteristics apply for parallel output termination of 50 to VTT. / 2 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE = 0. / 4 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE = 0. In bypass mode, the MPC9658 divides the input reference clock. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO / FB. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF,MIN. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation in PLL zero-delay mode. Output duty cycle is DC = (0.5 400 ps fOUT) 100%. For example, the DC range at fOUT = 100MHz is 46% < DC < 54%. T = output period. Refer to APPLICATIONS INFORMATION for a jitter calculation for other confidence factors than 1 and a characteristic for other VCO frequencies. -3 dB point of PLL transfer characteristics. 542 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9658 APPLICATIONS INFORMATION Programming the MPC9658 The MPC9658 supports output clock frequencies from 50 to 250 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500 MHz for stable and optimal operation. Two operating frequency ranges Table 7. MPC9658 Configurations (QFB connected to FB_IN) BYPASS 0 1 1 1 1 PLL_EN X 0 0 1 1 VCO_SEL X 0 1 0 1 Operation Test mode: PLL and divider bypass Test mode: PLL bypass Test mode: PLL bypass PLL mode (high frequency range) PLL mode (low frequency range) Frequency Ratio fQ0-9 = fREF fQ0-9 = fREF / 2 fQ0-9 = fREF / 4 fQ0-9 = fREF fQ0-9 = fREF Output range (fQ0-9) 0 - 250 MHz 0 - 125 MHz 0 - 62.5 MHz 100 - 250 MHz 50 - 125 MHz VCO n/a n/a n/a fVCO = fREF 2 fVCO = fREF 4 are supported: 50 to 125 MHz and 100 to 250 MHz. Table 7.MPC9658 Configurations (QFB connected to FB_IN) illustrates the configurations supported by the MPC9658. PLL zero-delay is supported if BYPASS = 1, PLL_EN = 1, and the input frequency is within the specified PLL reference frequency range. Power Supply Filtering The MPC9658 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9658 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9658. Figure 3 illustrates a typical power supply filter scheme. The MPC9658 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 12 mA (20 mA maximum), assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. RF = 5-15 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9658 VCC 33...100 nF The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 3 - 5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9658 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9658 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9658. Designs using the MPC9658 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9658 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Figure 3. VCC_PLL Power Supply Filter FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 543 MPC9658 Calculation of Part-to-Part Skew The MPC9658 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9658 are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consist of four components: static phase offset, output skew, feedback board trace delay, and I/O (phase) jitter: The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -214 ps to 224 ps relative to PCKL (fREF = 100 MHz, FB = 4, tjit() = 8 ps RMS at fVCO = 400 MHz): tSK(PP) = [-70ps...80ps] + [-120ps...120ps] + [(8ps -3)...(8ps 3)] + tPD, LINE(FB) tSK(PP) = [-214ps...224ps] + tPD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 5 can be used for a more precise timing performance analysis. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 20 tjit() [ps] RMS 15 FB = / 4 10 5 0 200 tJIT() FB = / 2 TCLKCommon --t(y) QFBDevice 1 tPD,LINE(FB) tJIT() +tSK(O) +t() Any QDevice 1 250 QFBDevice2 300 350 400 FCO Frequency [MHz] 450 500 Figure 5. Max. I/O Jitter versus Frequency Driving Transmission Lines The MPC9658 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Motorola Application Note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC / 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9658 clock driver. However, for the series terminated case there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 6. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9658 clock driver is effectively doubled due to its capability to drive multiple lines. Any QDevice 2 Max. skew +tSK(O) tSK(PP) Figure 4. MPC9658 Max. Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8.Confidence Factor CF. Table 8. Confidence Factor CF CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 544 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9658 MPC958 OUTPUT BUFFER IN 14 3.0 2.5 OutA VOLTAGE (V) 2.0 In 1.5 1.0 0.5 0 OutA tD = 3.8956 OutB tD = 3.9386 RS = 36 ZO = 50 MPC958 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 RS = 36 Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9658 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9658. The output waveform in Figure 7 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18+14+25) = 1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0ns). 2 4 6 8 TIME (ns) 10 12 14 Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering. However, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 8 should be used. In this case, the series terminating resistors are reduced such that, when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. MPC958 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 8. Optimized Dual Line Termination Pulse Generator Z = 50 ZO = 50 MPC9658 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 9. PCLK MPC9658 AC Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 545 MPC9658 VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device FB_IN t(PD) PCLK PCLK VPP = 0.8V VCMR = VCC-1.3V VCC VCC / 2 GND Figure 10. Output-to-Output Skew tSK(O) Figure 11. Propagation Delay (t(PD), static phase offset) Test Reference VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage PCLK FB_IN TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a T0 mean in a random sample of cycles Figure 12. Output Duty Cycle (DC) Figure 13. I/O Jitter TN TN+1 TJIT(CC) = |TN-TN+1| T0 TJIT(PER) = |TN-1/f0| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 14. Cycle-to-Cycle Jitter Figure 15. Period Jitter VCC=3.3 V 2.4 0.55 tF tR Figure 16. Output Transition Time Test Reference 546 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC96877 Rev 1, 08/2004 Product Preview 1.8 V PLL 1:10 Differential SDRAM Clock Driver Recommended Applications * DDR II Memory Modules * Zero Delay Board fan-out Features * * * * * * * * * * 1.8 V Phase Lock Loop Clock Driver for (DDR II) Applications Spread Spectrum Clock Compatible Operating Frequency: 100 MHz to 340 MHz 1 to 10 differential clock distribution (SSTL_18) 52-Ball VF-BGA (FP-MAPBGA 0.65-mm pitch) and 40-Pin MLF (QFN) 52-lead Pb-free Package Available External Feedback Pins (FBIN, FBIN) are used to synchronize the Outputs to the Input Clocks Single-Ended Input and Single-Ended Output Modes Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300 Auto Power Down detect logic MPC96877 DDR II MEMORY CLOCK / ZERO DELAY BUFFER VK SUFFIX 52-BALL FP-MAPBGA PACKAGE CASE 1544-01 Switching Characteristics * Cycle-to-Cycle Jitter (>165 Mhz): 40 ps max. * Output-to-Output Skew: 40 ps max. Functional Description EP SUFFIX 40-PIN MLF/QFN PACKAGE CASE 1545-01 AVAILABLE ORDERING OPTIONS The MPC96877 is a high-performance, low-jitter, low-skew, zero-delay buffer TA 52-Ball BGA 40-Pin QFN that distributes a differential clock input pair (CK, CK) to ten differential pairs of MPC96877VK MPC96877EP 0C to 70C clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (Pb-Free) (Pb-Free) (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time. The MPC96877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0C to 70C. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 547 MPC96877 Y0 Y0 OE OS AVDD Powerdown Control and Test Logic LD* LD* OR OE LD*, OS or OE PLL bypass Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 CK CK PLL Y6 Y6 Y7 10 K-100 K GND FBIN FBIN Y7 Y8 Y8 Y9 Y9 FBOUT * The Logic Detect (LD) powers down the device when a logic low is applied to both CK and CK. FBOUT Figure 1. MPC96877 Logic Diagram 548 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC96877 VF-MAPBGA (VK) PACKAGE GND Y0 GND Y5 Y1 Y0 Y5 Y6 5 6 1 A B 2 3 4 Y1 GND Y2 GND Y2 VDDQ VDDQ CK VDDQ CK VDDQ AGND VDDQ VDDQ AVDD GND Y3 GND Y6 GND NB NB Y7 GND Y7 OS VDDQ FBIN VDDQ FBIN OE FBOUT VDDQ VDDQ FBOUT GND Y8 GND C D E F G NB NB NB NB H NB NB J K EP PACKAGE (TOP VIEW) VDDQ GND Y4 GND Y9 VDDQ Y7 Y7 VDDQ FBIN FBIN FBOUT FBOUT VDDQ OE OS 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 20 Y3 Y3 Y4 Y4 Y9 Y9 Y8 VDDQ Y8 VDDQ Y3 Y4 Y9 Y8 Y1 Y1 Y0 Y0 Y5 Y5 Y6 Y6 VDDQ Y2 Y2 CK CK VDDQ AGND AVDD VDDQ GND 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 30 GND 40-Pin TE-QFN(6.0 x 6.0 mm Body Size, 0.5 mm Pitch, M0#220, Variation VJJD-2, E2 = D2 = 2.9 mm 0.15 mm) Package Pinouts FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 549 MPC96877 Table 1. Pin Configuration Pin AGND AVDD CK CK FBIN FBIN FBOUT FBOUT OE OS GND H6 G6 F5 D5 B2, B3, B4, B5, C2,C5,H2,H5, J2, J3, J4, J5 D2, D3, D4, E2, E5, F2, G2, G3, G4, G5 A2, A1, D1, J1, K3, A5, A6, D6, J6, K4 A3, B1, C1, K1, K2, A4, B6, C6, K6, K5 BGA G1 H1 E1 E6 F6 MLF 7 8 4 5 27 26 24 25 22 21 10 Input Input Input Input Output Output Input Input I/O Analog ground Analog power Clock input with a (10k to 100k) pulldown resistor Complimentary clock input with a (10k to 100k) pulldown resistor Feedback clock input Complimentary Feedback clock input Feedback clock output Complimentary feeback clock output Output Enable (asynchronous) Output Select (tied to GND or VDD) Ground Function VDDQ Y[0:9] Y[0:9] 1, 6, 9, 15, 20, 23, 28, 31, 36 38, 39, 3, 11, 14, 34, 33, 29,19, 16 37, 40, 2, 12, 13, 35, 32, 30, 18, 17 Output Output Logic and output power Clock outputs Complimentary clock outputs Table 2. Function Table Inputs AVDD GND GND GND GND 1.8 V Nominal 1.8 V Nominal 1.8 V Nominal 1.8 V Nominal 1.8 V Nominal X OE H H L L L L H H X X OS X X H L H L X X X X CK L H L H L H L H L H CK H L H L H L H L L H Y L H LZ LZ 1 Y7 Active LZ 1 LZ 1 Y7 Active L H LZ 1 Y H L LZ LZ 1 Y7 Active LZ 1 LZ 1 Y7 Active H L LZ 1 Outputs FBOUT L H L H L H L H LZ 1 RESERVED FBOUT H L H L H L H L LZ 1 PLL Bypassed / OFF Bypassed / OFF Bypassed / OFF Bypassed / OFF ON ON ON ON OFF 1. L(Z) means the outputs are disabled to a low state meeting the IODL limit in Table 5. 550 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC96877 Table 3. Absolute Maximum Ratings Over Free-Air Operating Range1 Parameter Supply voltage range, VDDQ or AVDD Input voltage range, VI2, 3 Output voltage range, VO1, 2 Input clamp current, IIK (VI < 0 or VI > VDDQ) Output clamp voltage, IOK (VO < 0 or VO > VDDQ) Continuous output current, IO (VO = 0 to VDDQ) Continuous current through each VDDQ or GND Storage temperature range, TSTG Value -0.5 V to 2.5 V -0.5 V to VDDQ + 0.5 V -0.5 V to VDDQ + 0.5 V 50 mA 50 mA 50 mA 100 mA -65C to 150C 1. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 2.5 V maximum. Table 4. Recommended Operating Conditions Rating Output supply voltage Supply voltage1 Low-level input voltage2 High-level input voltage2 High-level output current Low-level output current Input differential-pair cross voltage Input voltage level Input differential-pair voltage (see Figure 9. Half-Period Jitter) Operating free-air temperature 2 Parameter VDDQ AVDD VIL VIH IOH IOL VIX VIN VID Affected Pins Min 1.7 Nom 1.8 VDDQ Max 1.9 Unit V OE, OS, CK, CK OE, OS, CK, CK 0.65 x VDDQ 0.35 x VDDQ V -9 9 (VDDQ/2) -0.15 -0.3 DC AC 0.3 0.6 0 (VDDQ/2) +0.15 VDDQ +0.3 VDDQ +0.4 VDDQ +0.4 70 mA mA V C 1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and not timing parameters are guaranteed. 2. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 12. Time Delay between OE and Clock Output for definition. For CK and CK the VIH and VIL limits are used to define the DC low and high levels for the logic detect state. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 551 MPC96877 Table 5. Electrical Characteristics Over Recommended Free-Air Operating Temperature Range Description All inputs High output voltage Parameter VIK VOH Affected Pins Test Conditions II = -18mA IOH = -100 A IOH = -9 mA Low output voltage VOL IOL = 100 A IOL = 9 mA Output disable current Output differential voltage Input leakage current IODL VOD II CK, CK OE, OS, FBIN, FBIN Static supply current IDDQ + IADD Dynamic Supply current IDDQ + IADD, see Note 1 for CPD calculation IDDLD IDD VI = VDDQ or GND VI = VDDQ or GND CK and CK = L CK and CK = 270 MHz all outputs open OE = L, VODL = 100 mV AVDD, VDDQ 1.7 V 1.7 to 1.9 V 1.7 V 1.7 to 1.9 V 1.7 V 1.7 V 1.7 V 1.9 V 1.9 V 1.9 V 1.9 V 100 0.5 250 10 500 300 A mA VDDQ -0.2 1.1 0.1 0.6 A V A V Min Max -1.2 Unit V V 1. Total IDD = IDDQ + IADD = FCK* CPD * VDDQ, solving for CPD = (IDDQ + IADD)/(FCK * VDDQ) where FCK is the input Frequency, VDDQ is the power supply and CPD is the Power Dissipation Capacitance. Table 6. Timing Requirements Over Recommended Free-Air Operating Temperature Range Timing Requirements Operating clock frequency1, 2 Application clock frequency1, 3 Input clock duty cycle Stabilization time 4 AVDD, VDDQ = 1.8 V 0.1 V Min 125 160 40 Max 340 340 60 15 Unit MHz MHz % s 1. The PLL must be able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) 3. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. 552 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC96877 Table 7. Switching Characteristics over Recommended Free-Air Operating Temperature Range Unless Otherwise Noted (see Notes) Description OE to any Y/Y OE to any Y/Y Cycle-to-Cycle period jitter Parameter ten tdis tjit(cc+) tjit(cc-) Static phase offset Dynamic phase offset Output clock skew Period Jitter Half -period jitter Output Enable Input clock slew rate, measured single ended Output clock slew rate, measured single ended Output differential-pair cross voltage SSC modulation frequency SSC clock input frequency deviation PLL Loop bandwidth (-3dB from unity gain) slr(o) VOX see Figure 3 and Figure 9 see Figure 2 t() t()dyn tsk(o) tjit(per) tjit(hper) slr(i) see Figure 5 see Figure 10 see Figure 6 see Figure 7 see Figure 8 see Figure 3 and Figure 9 -40 -75 0.5 1 1.5 (VDDQ/2) - 0.1 30 0.0 2.0 2.5 2.5 4 3 (VDDQ/2) + 0.1 33 -0.5 MHz V/ns V kHz Diagram see Figure 11 see Figure 11 see Figure 4 0 0 -50 -50 AVDD, VDDQ = 1.8 V 0.1 V Min Nom Max 8 8 40 -40 50 50 40 40 75 Unit ns ns ps ps ps ps ps ps ps V/ns NOTES: 1. There are two different terminations that are used with the following tests. The loadboard in Figure 2. IBIS Model Output Load is used to measure the input and output differential-pair cross voltage only. The loadboard in Figure 3. Output Load Test Circuit 1 is used to measure all other tests. For consistency, equal length cables must be used. 2. Static Phase offset does not include Jitter. 3. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other. 4. The Output Slew Rate is determined form the IBIS model into the load shown in Figure 4. Output Load Test Circuit 2. It is measured single ended. 5. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock Input FBIN, FBIN are recommended to be nearly equal. The 2.5 V/ns slew rates are shown as a recommended target. Compliance with these Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2 DIMM application. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 553 MPC96877 TEST CIRCUIT AND SWITCHING WAVEFORMS VDD CU877 VCK 60 60 VCK GND Figure 2. IBIS Model Output Load VDD/2 VDDQ CU877 Z=60 L=2.97" Z=60 L=2.97" GND R=1M C=1pF R=1M C=1pF SCOPE GND GND Figure 3. Output Load Test Circuit 1 VDDQ/2 CU877 C=10pF Z=60 L=2.97" Z=60 L=2.97" C=10pF -VDDQ/2 -VDDQ/2 Note: VTT = GND Figure 4. Output Load Test Circuit 2 -VDDQ/2 R=10 SCOPE Z=50 Z=50 R=1M VTT R=1M VTT R=10 554 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC96877 TEST CIRCUIT AND SWITCHING WAVEFORMS (Continued) Yx, FBOUT Yx, FBOUT t cycle n t cycle n+1 tjit(cc) = t cycle n - t cycle n+1 Figure 5. Cycle-to-Cycle Period Jitter CK CK FBIN FBIN t(o) n t(o) = t(o) n+1 n=N t 1 (o) n N (N is a large number of samples) Figure 6. Static Phase Offset Yx Yx Yx, FBOUT Yx, FBOUT t sk(0) Figure 7. Output Skew FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 555 MPC96877 TEST CIRCUIT AND SWITCHING WAVEFORMS (Continued) Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT 1 f0 tjit(per) = t cycle n Figure 8. Period Jitter t cycle n 1 f0 Yx, FBOUT Yx, FBOUT t half period n t half period n+1 1 f0 tjit(hper) = t cycle n 1 2 * f0 n = any half cycle Figure 9. Half-Period Jitter 80% 80% Clock Inputs and Outputs, OE 20% 20% tr(i),tr(0) V -V slrr(i/o) = 80% 20% tr(i/o) tf(i),tf(0) V -V slrf(i/o) = 80% 20% tf(i/o) Figure 10. Input and Output Slew Rates 556 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC96877 TEST CIRCUIT AND SWITCHING WAVEFORMS (Continued) CK CK FBIN FBIN t(o) SSC OFF SSC ON t(o) dyn t(o) dyn t(o) dyn t(o) SSC OFF SSC ON t(o) dyn Figure 11. Dynamic Phase Offset OE 50% VDDQ ten 50% VDDQ Y/Y OE 50% VDDQ tdis Y Y 50% VDDQ Figure 12. Time Delay between OE and Clock Output FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 557 MPC96877 RECOMMENDED FILTERING FOR THE ANALOG POWER SUPPLY (AVDD) VDDQ R1 1 ohm Bead 0603 R1 4.7 uF 1206 4.7 uF 1206 AVDD 4.7 uF 1206 AGND PLL GND CARD VIA NOTES: 1. Place the 2200pF capacitor close to the PLL 2. Use a wide trace for the PLL analog power and ground. Connect PLL and caps to AGND to AGND trace & connect trace to one GND via (farthest from PLL). 3. Recommended bead: Fair Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz) Figure 13. AVDD Filtering 558 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Chapter Seven LVCMOS Fanout Buffer Data Sheets LVCMOS Fanout Buffer Device Index Device Number Page Device Number Page MPC905 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 MPC9109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 MPC940L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 MPC941 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 MPC942C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 MPC942P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 MPC9443 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 MPC9446 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 MPC9447 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 MPC9448 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 MPC9449 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 MPC94551 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 MPC9456 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 559 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC905 Rev 2, 05/2003 1:6 PCI Clock Generator/ Fanout Buffer MPC905 The MPC905 is a six output clock generation device targeted to provide the 1:6 PCI clocks required in a 3.3V or 5.0V PCI environment. The device operates from CLOCK GENERATOR/ a 3.3V supply and can interface to either a TTL input or an external crystal. The FANOUT BUFFER inputs to the device can be driven with 5.0V when the VCC is at 3.3V. The outputs of the MPC905 meet all of the specifications of the PCI standard. * Six Low Skew Outputs * Synchronous Output Enables for Power Management * Low Voltage Operation * XTAL Oscillator Interface * 16-Lead SOIC Package * 5.0V Tolerant Enable Inputs D SUFFIX PLASTIC SOIC PACKAGE The MPC905 device is targeted for PCI bus or processor bus environments CASE 751B-05 with up to 12 clock loads. Each of the six outputs on the MPC905 can drive two series terminated 50 transmission lines. This capability effectively makes the MPC905 a 1:12 fanout buffer. The MPC905 offers two synchronous enable inputs to allow users flexibility in developing power management features for their designs. Both enable signals are active HIGH inputs. A logic `0' on the ENABLE1 will pull outputs 0 to 4 into the logic `0' state. A logic `1' on the ENABLE1 input will result in outputs 0 to 4 to be toggling. A logic `0' on ENABLE2 will cause output BLK5 to a logic `0' state, whereas a logic `1' on ENABLE2 will cause output BLK5 to toggle. The oscillator remains on. The ENABLE2 input can be used to disable any high power device for system power savings during periods of inactivity. Both enable inputs are synchronized internal to the chip so that the output disabling will happen only when the outputs are already LOW. This feature guarantees no runt pulses will be generated during enabling and disabling. SCALE 2:1 VDD (3) GND (3) Pinout: 16-Lead Plastic Package (Top View) BCLK0 XTAL_IN BCLK1 BCLK2 XTAL_OUT ENABLE1 BCLK3 BCLK4 SYNCHRONIZE BCLK5 ENABLE2 SYNCHRONIZE XTAL_OUT 1 ENABLE2 2 GND1 3 BCLKO 4 VDD1 5 BCLK1 6 GND2 7 BCLK2 8 16 XTAL_IN 15 ENABLE1 14 BCLK5 13 VDD3 12 BCLK4 11 GND3 10 BCLK3 9 VDD2 560 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC905 Table 1. Pin Configurations Pin XTAL_IN, XTAL_OUT ENABLE1, ENABLE2 BCLK0-BCLK5 VDD GND I/O Input Input Output Type Analog LVCMOS LVCMOS Supply Supply Function Crystal Oscillator Terminals Output Enable Clock Outputs Positive Power Supply Negative Power Supply Table 2. Function Table ENABLE1 0 0 1 1 ENABLE2 0 1 0 1 Outputs 0 to 4 Low Low Toggling Toggling Output 5 Low Toggling Low Toggling OSC (On/Off) ON ON ON ON Table 3. Absolute Maximum Ratings1 Symbol VDD VIN Toper Tstg Tsol Tj ESD ILatch Parameter Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Soldering Temperature Range (10 Sec) Junction Temperature Range Static Discharge Voltage Latch Up Current 1500 50 Min -0.5 -0.5 0 -65 Max 4.6 VCC + 0.5 +70 +150 +260 +125 Unit V V C C C C V mA 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Table 4. Recommended Operating Conditions Symbol TA VCC tDCin Ambient Temperature Range Positive Supply Voltage (Functional Range) Thigh (at XTAL_IN Input) Tlow (at XTAL_IN Input) Parameter Min 0 3.0 0.44T1 0.44T1 Max 70 3.6 0.56T1 0.56T1 Unit C V T = Period 1. When using External Source for reference, requirement to meet PCI clock duty cycle requirement on the output. Table 5. DC Characteristics (TA = 0-70C; VDD = 3.3 V 0.3 V) Symbol VIH VIL VOH VOL IIH IIL ICC Characteristic High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input High Current Input Low Current Power Supply Current DC 33MHz 66MHz XTAL_IN Others 20 37 78 2.4 0.4 2.52 2.5 45 95 9.0 4.5 Min 2.0 Typ Max 5.52 0.8 Unit V V V V A A A mA mA pF IOH = -36mA1 IOL = 36mA1 Condition CIN Input Capacitance 1. The MPC905 can drive 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to VTT = VCC/2. Alternately, the device drives up to two 50 series terminated transmission lines per output. 2. XTAL_IN input will sink up to 10mA when driven to 5.5V. There are no reliability concerns associated with the condition. Note that the ENABLE1 input must be a logic HIGH. Do not take the ENABLE1 input to a logic LOW with >VCC volts on the XTAL_IN input. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 561 MPC905 Table 6. AC CHARACTERISTICS (TA = 0-70C; VDD = 3.3V 0.3 V) Symbol Fmax tpw Maximum Operating Frequency Output Pulse Width Characteristic Using External Crystal Using External Clock Source HIGH (Above 2.0V) LOW (Below 0.8V) HIGH (Above 2.0V) LOW (Below 0.8V) tper tos tr, tf Output Period Output-to-Output Skew Rise/Fall Times (Slew Rate) Rising Edges Falling Edges 1 Min -- DC 0.40T1 0.40T1 0.45T2 0.45T2 T - 400ps 400 500 4 ps V/ns Series Terminated Transmission Lines Typ Max 50 100 0.60T1 0.60T1 0.55T2 0.55T2 T = Desired Period Unit MHz T = Periods Condition tEN tDIS Aosc Enable Time Disable Time XTAL_IN to XTAL_OUT Oscillator Gain ENABLE1 ENABLE2 ENABLE1 ENABLE2 6 30 5 4 4 4 ms Cycles Cycles db Degrees Phase Loop Phase Shift Modulo 360 + 1. Assuming input duty cycle specs from Recommended Operating Conditions table are met. 2. Assuming external crystal or 50% duty cycle external reference is used. PIN 16 PIN 1 100 PIN 16 PIN 1 fFUND = 1 2 LTRAP CTRAP Y1 33.3333MHz C1 10pF C3 Y1 11.1111MHz CTRAP LTRAP 16pF 16pF C1 10pF C3 Figure 1. Crystal Oscillator Interface (Fundamental) Figure 2. Crystal Oscillator Interface (3rd Overtone) Table 7. Crystal Specifications Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Parallel Resonance 75ppm at 25C 150pm 0 to 70C 0 to 70C 5-7pF 50 to 80 100W 5ppm/Yr (First 3 Years) 562 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC905 BCLK5 BCLK0-4 ENABLE2 ENABLE1 Figure 3. Enable Timing Diagram APPLICATIONS INFORMATION DRIVING TRANSMISSION LINES The MPC905 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of approximately 10 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions data book (DL207/D). In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC905 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC905 clock driver is effectively doubled due to its capability to drive multiple lines. MPC905 OUTPUT BUFFER IN 10 RS = 40 ZO = 50 OutA MPC905 OUTPUT BUFFER IN 10 RS = 40 ZO = 50 OutB0 RS = 40 ZO = 50 OutB1 Figure 4. Single versus Dual Transmission Lines The waveform plots of Figure 5 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC905 output buffers is more than sufficient to drive 50 transmission lines on the incident edge. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 563 MPC905 Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. The output waveform in Figure 5 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 40 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Zo / Rs + Ro + Zo) = 3.0 (25/55) = 1.36V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.73V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 3.0 2.5 2.0 VOLTAGE (V) IN 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 MPC905 OUTPUT BUFFER 10 RS = 30 ZO = 50 RS = 30 ZO = 50 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. OutB tD = 3.9386 10 + 30 || 30 = 50 ||50 25 = 25 Figure 6. Optimized Dual Line Termination Figure 5. Single versus Dual Waveforms 564 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9109 Rev 1, 03/1999 Low Voltage 1:18 Clock Distribution Chip The MPC9109 is a 1:18 low voltage clock distribution chip with 2.5 V or 3.3 V LVCMOS output capabilities. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 18 outputs are 2.5 V or 3.3 V LVCMOS compatible and feature the drive strength to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 200 ps, the MPC9109 is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5 V outputs also make the device ideal for supplying clocks for a high performance Pentium II microprocessor based design. For a higher performance version of the 9109 refer to the MPC940L data sheet. Features * * * * * * LVPECL or LVCMOS clock input 2.5 V LVCMOS outputs for Pentium II microprocessor support 200 ps maximum output-to-output skew @ 3.3 V output Maximum output frequency of 250 MHz @ 3.3 V core 32-lead QFP packaging Dual or single supply device: * Dual VCC supply voltage, 3.3 V core and 2.5 V output * Single 3.3 V VCC supply voltage for 3.3 V outputs * Single 2.5 V VCC supply voltage for 2.5 V I/O MPC9109 LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP FA SUFFIX 32-LEAD QFP PACKAGE CASE 873A-03 Functional Description With a low output impedance (20 ), in both the HIGH and LOW logic states, the output buffers of the MPC9109 are ideal for driving series terminated transmission lines. With a 20 output impedance the 9109 has the capability of driving two series terminated lines from each output. This gives the device an effective fanout of 1:36. If a lower output impedance is desired please see the MPC942 data sheet. If better performance is desired please see the MPC940L data sheet. The differential LVPECL inputs of the MPC9109 allow the device to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. All inputs of the MPC9109 have internal pullup/pulldown resistor so they can be left open if unused. The MPC9109 is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a 3.3 V core and 3.3 V output, a 3.3 V core and 2.5 V outputs as well as a 2.5 V core and 2.5 V outputs. The 32-lead QFP package was chosen to optimize performance, board space and cost of the device. The 32-lead TQFP has a 7x7mm body size with a conservative 0.8 mm pin spacing. Pentium II is a trademark of Intel Corporation. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 565 MPC9109 PECL_CLK PECL_CLK LVCMOS_CLK LVCMOS_CLK_Sel (INTERNAL PULLDOWN) 0 1 16 Q0 Q1-Q16 Q17 Figure 1. Logic Diagram 24 GNDO Q5 Q4 Q3 VCCO Q2 Q1 Q0 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 GND 17 16 15 14 VCCO Q12 Q13 Q14 GNDO Q15 Q16 Q17 VCCI Q10 Q11 Q6 Q7 Q8 Q9 Table 1. Function Table LVCMOS CLK_Sel 0 1 Input PECL_CLK LVCMOS_CLK MPC9109 13 12 11 10 9 Table 2. Power Supply Voltages Supply Pin VCCI VCCO Voltage Level 2.5 V or 3.3 V 5% 2.5 V or 3.3 V 5% 2 3 4 5 6 7 8 GNDO LVCMOS_CLK PECL_CLK PECL_CLK LVCMOS_CLK_Sel GNDI Figure 2. Pinout: 32-Lead TQFP (Top View) 566 VCCO FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA VCCI MPC9109 Table 3. Absolute Maximum Ratings1 Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 3.6 VCC + 0.3 20 125 Unit V V mA C 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 4. DC Characteristics (TA = 0 to 70C, VCCI = 3.3 V 5%; VCCO = 3.3 V 5%) Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 18 4.0 10 23 0.5 28 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCC-1.4 2.4 0.5 200 Min 2.4 Typ Max VCCI 0.8 1000 VCC-0.6 Unit V V mV V V V A pF pF mA Per output IOH = -20 mA IOH = 20 mA Condition Table 5. AC Characteristics (TA = 0 to 70C, VCCI = 3.3 V 5%; VCCO = 3.3 V 5%) Symbol Fmax tPLH tsk(o) tsk(pr) dt tr, tf Characteristic Maximum Input Frequency Propagation Delay Output-to-Output Skew Part-to-Part Skew Duty Cycle Output Rise/Fall Time PECL_CLK CMOS_CLK PECL_CLK CMOS_CLK PECL_CLK CMOS_CLK 45 0.1 1.8 1.6 2.8 2.5 Min Typ Max 250 3.8 3.3 200 200 2.0 1.7 55 1.3 Unit MHz ns ps ns % ns Note1 Note1 Note1 Note1 Note1 Condition 1. Guaranteed by statistical analysis, not 100% tested in production. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 567 MPC9109 Table 6. Absolute Maximum Ratings1 Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 3.6 VCC + 0.3 20 125 Unit V V mA C 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 7. DC Characteristics (TA = 0 to 70C, VCCI = 3.3 V 5%; VCCO = 2.5 V 5%) Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 4.0 10 23 0.5 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCC-1.4 1.8 0.5 200 Min 2.4 Typ Max VCCI 0.8 1000 VCC-0.6 Unit V V mV V V V A pF pF mA Per output IOH = -20 mA IOH = 20 mA Condition Table 8. AC Characteristics (TA = 0 to 70C, VCCI = 3.3 V 5%; VCCO = 2.5 V 5%) Symbol Fmax tPLH tsk(o) tsk(pr) dt tr, tf Characteristic Maximum Input Frequency Propagation Delay Output-to-Output Skew Part-to-Part Skew Duty Cycle Output Rise/Fall Time PECL_CLK CMOS_CLK PECL_CLK CMOS_CLK PECL_CLK CMOS_CLK 45 0.1 1.8 1.6 2.8 2.5 Min Typ Max 250 3.9 3.4 250 250 2.1 1.8 55 1.3 Unit MHz ns ps ns % ns Note1 Note1 Note1 Note1 Note1 Condition 1. Guaranteed by statistical analysis, not 100% tested in production. 568 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9109 Table 9. Absolute Maximum Ratings1 Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 3.6 VCC + 0.3 20 125 Unit V V mA C 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 10. DC Characteristics (TA = 0 to 70C, VCCI = 2.5 V 5%; VCCO = 2.5 V 5%) Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 18 4.0 10 23 0.5 28 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCC-1.0 1.8 0.5 200 Min 2.0 Typ Max VCCI 0.8 1000 VCC-0.6 Unit V V mV V V V A pF pF mA Per output IOH = -12 mA IOH = 12 mA Condition Table 11. AC Characteristics (TA = 0 to 70C, VCCI = 2.5 V 5%; VCCO = 2.5 V 5%) Symbol Fmax tPLH tsk(o) tsk(pr) dt tr, tf Characteristic Maximum Input Frequency Propagation Delay Output-to-Output Skew Part-to-Part Skew Duty Cycle Output Rise/Fall Time PECL_CLK CMOS_CLK PECL_CLK CMOS_CLK PECL_CLK CMOS_CLK 45 0.1 2.2 2.0 2.8 2.5 Min Typ Max 200 4.9 4.2 250 250 2.7 2.2 55 1.3 Unit MHz ns ps ns % ns Note1 Note1 Note1 Note1 Note1 Condition 1. Guaranteed by statistical analysis, not 100% tested in production. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 569 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC940L Rev 4, 08/2004 Low Voltage 1:18 Clock Distribution Chip MPC940L The MPC940L is a 1:18 low voltage clock distribution chip with 2.5V or 3.3V LOW VOLTAGE LVCMOS output capabilities. The device features the capability to select either 1:18 CLOCK a differential LVPECL or an LVCMOS compatible input. The 18 outputs are 2.5V DISTRIBUTION CHIP or 3.3V LVCMOS compatible and feature the drive strength to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 150ps, the MPC940L is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5V outputs also make the device ideal for supplying clocks for a high performance microprocessor based design. For a similar device at a lower price/performance point the reader is referred to the MPC9109. * LVPECL or LVCMOS Clock Input FA SUFFIX * 2.5V LVCMOS Outputs for Pentium II Microprocessor Support 32-LEAD LQFP PACKAGE * 150ps Maximum Output-to-Output Skew CASE 873A-03 * Maximum Output Frequency of 250MHz * 32-Lead LQFP Packaging * 32-Lead Pb-free Package Available * Dual or Single Supply Device: * Dual VCC Supply Voltage, 3.3V Core and 2.5V Output * Single 3.3V VCC Supply Voltage for 3.3V Outputs * Single 2.5V VCC Supply Voltage for 2.5V I/O With a low output impedance (20), in both the HIGH and LOW logic states, the output buffers of the MPC940L are ideal for driving series terminated transmission lines. With a 20 output impedance the 940L has the capability of driving two series terminated lines from each output. This gives the device an effective fanout of 1:36. If a lower output impedance is desired please see the MPC942 data sheet. The differential LVPECL inputs of the MPC940L allow the device to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_SEL pin will select the LVCMOS level clock input. All inputs of the MPC940L have internal pullup/pulldown resistor so they can be left open if unused. The MPC940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a 3.3V core and 3.3V output, a 3.3V core and 2.5V outputs as well as a 2.5V core and 2.5V outputs. The 32-lead LQFP package was chosen to optimize performance, board space and cost of the device. The 32-lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing. Pentium II is a trademark of Intel Corporation. 570 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC940L LOGIC DIAGRAM PECL_CLK PECL_CLK LVCMOS_CLK LVCMOS_CLK_SEL (Internal Pulldown) 0 1 16 Q1-Q16 Q17 Q0 Pinout: 32-Lead TQFP (Top View) GND 17 16 15 14 VCCO Q12 Q13 Q14 GNDO Q15 Q16 Q17 VCCI Q10 19 Q11 18 Q6 Q7 Q8 Q9 20 24 GNDO Q5 Q4 Q3 VCCO Q2 Q1 Q0 25 26 27 28 29 30 31 32 1 23 22 21 FUNCTION TABLE LVCMOS_CLK_SEL 0 1 Input PECL_CLK LVCMOS_CLK MPC940L 13 12 11 10 9 POWER SUPPLY VOLTAGES Supply Pin VCCI VCCO Voltage Level 2.5V or 3.3V 5% 2.5V or 3.3V 5% 2 3 4 5 6 7 8 GNDO LVCMOS_CLK_SEL LVCMOS_CLK PECL_CLK PECL_CLK GNDI Table 1. Pin Configurations Pin PECL_CLK PECL_CLK LVCMOS_CLK LVCMOS_CLK_SEL Q0-Q17 VCCO VCCI GNDO GNDI I/O Input Input Input Output Type LVPECL LVCMOS LVCMOS LVCMOS Supply Supply Supply Supply Function Reference Clock Input Alternative Reference Clock Input Selects Clock Source Clock Outputs Output Positive Power Supply Core Positive Power Supply Output Negative Power Supply Core Negative Power Supply FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA VCCO VCCI 571 MPC940L Table 2. Absolute Maximum Ratings1 Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 3.6 VDD + 0.3 20 125 Unit V V mA C 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 3. DC Characteristics (TA = 0 to 70C, VCCI = 3.3V 5%; VCCO = 3.3V 5%) Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 18 4.0 10 23 0.5 28 1.0 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCC -1.4 2.4 0.5 200 Min 2.4 Typ Max VCCI 0.8 1000 VCC -0.6 Unit V V mV V V V A pF pF mA per output IOH = -20mA IOH = 20mA Condition Table 4. AC Characteristics (TA = 0 to 70C, VCCI = 3.3V 5%; VCCO = 3.3V 5%) Symbol Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC tr, tf Characteristic Maximum Input Frequency Propagation Delay Propagation Delay Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle Output Rise/Fall Time PECL_CLK 150MHz CMOS_CLK 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134MHz fCLK 250MHz 45 40 0.3 50 50 2.0 1.8 2.0 1.8 2.7 2.5 2.9 2.4 Min Typ Max 250 3.4 3.0 3.7 3.2 150 150 1.4 1.2 1.7 1.4 850 750 55 60 1.1 Unit MHz ns ns ps ns ns ps % % ns Note 1 Notes 1, 2 Notes 1, 2 Notes 1, 3 Input DC = 50% Input DC = 50% 0.5 - 2.4 V Note 1 Condition 1. Tested using standard input levels. Production tested @ 150MHz. 2. Across temperature and voltage ranges. Includes output skew. 3. For specific temperature and voltage. Includes output skew. 572 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC940L Table 5. DC Characteristics (TA = 0 to 70C, VCCI = 3.3V 5%; VCCO = 2.5V 5%) Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 4.0 10 23 0.5 1.0 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCC -1.4 1.8 0.5 200 Min 2.4 Typ Max VCCI 0.8 1000 VCC -0.6 Unit V V mV V V V A pF pF mA per output IOH = -20mA IOH = 20mA Condition Table 6. AC Characteristics (TA = 0 to 70C, VCCI = 3.3V 5%; VCCO = 2.5V 5%) Symbol Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC tr, tf Characteristic Maximum Input Frequency Propagation Delay Propagation Delay Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle Output Rise/Fall Time PECL_CLK 150MHz CMOS_CLK 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK 250 MHz 45 40 0.3 50 50 2.0 1.7 2.0 1.8 2.8 2.5 2.9 2.5 Min Typ Max 250 3.5 3.0 3.8 3.3 150 150 1.5 1.3 1.8 1.5 850 750 55 60 1.2 Unit MHz ns ns ps ns ns ps % % ns Note 1 Notes 1, 2 Notes 1, 2 Notes 1, 3 Input DC = 50% Input DC = 50% 0.5 - 1.8 V Note 1 Condition 1. Tested using standard input levels. Production tested @ 150MHz. 2. Across temperature and voltage ranges. Includes output skew. 3. For specific temperature and voltage. Includes output skew. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 573 MPC940L Table 7. DC Characteristics (TA = 0 to 70C, VCCI = 2.5V 5%; VCCO = 2.5V 5%) Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 18 4.0 10 23 0.5 28 1.0 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCC -1.0 1.8 0.5 200 Min 2.0 Typ Max VCCI 0.8 1000 VCC -0.6 Unit V V mV V V V A pF pF W mA per output IOH = -12mA IOH = 12mA Condition Table 8. AC Characteristics (TA = 0 to 70C, VCCI = 2.5V 5%; VCCO = 2.5V 5%) Symbol Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC tr, tf Characteristic Maximum Input Frequency Propagation Delay Propagation Delay Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle Output Rise/Fall Time PECL_CLK 150MHz CMOS_CLK 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134MHz fCLK 250MHz 45 40 0.3 50 50 2.6 2.3 2.8 2.3 4.0 3.1 3.8 3.1 Min Typ Max 200 5.2 4.0 5.0 4.0 200 200 2.6 1.7 2.2 1.7 1.2 1.0 55 60 1.2 Unit MHz ns ns ps ns ns ns % % ns Note 1 Notes 1, 2 Notes 1, 2 Notes 1, 3 Input DC = 50% Input DC = 50% 0.5 - 1.8 V Note 1 Condition 1. Tested using standard input levels. Production tested @ 150MHz. 2. Across temperature and voltage ranges. Includes output skew. 3. For specific temperature and voltage. Includes output skew. 574 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC940L MPC940L DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 1. LVCMOS_CLK MPC940L AC Test Reference for VCC = 3.3V and VCC = 2.5V ZO = 50 MPC940L DUT ZO = 50 Differential Pulse Generator Z = 50 RT = 50 VTT RT = 50 VTT Figure 2. PECL_CLK MPC940L AC Test Reference for VCC = 3.3V and VCC = 2.5V PCLK_CLK PCLK_CLK VPP VCC VCMR VCC VCC /2 GND tPD LVCMOS_CLK VCC / 2 GND Q tPD VCC VCC / 2 GND Q Figure 3. Propagation Delay (tPD) Test Reference VCC VCC / 2 tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage GND Figure 4. LVCMOS Propagation Delay (tPD) Test Reference VOH VCC / 2 GND VOH VCC / 2 tSK(O) GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay path within a single device Figure 5. Output Duty Cycle (DC) VCC = 3.3V VCC = 2.5V 2.4 0.55 tF tR 1.8V 0.6V tF Figure 6. Output-to-Output Skew TSK(O) VCC = 3.3V VCC = 2.5V 2.0 0.8 tR 1.7V 0.7V Figure 7. Output Transition Time Test Reference Figure 8. Input Transition Time Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 575 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC941 Rev 5, 08/2004 Low Voltage 1:27 Clock Distribution Chip MPC941 The MPC941 is a 1:27 low voltage clock distribution chip. The device features the capability to select either a differential LVPECL or an LVCMOS LOW VOLTAGE 3.3V/2.5V compatible input. The 27 outputs are LVCMOS compatible and feature the drive 1:27 CLOCK strength to drive 50 series or parallel terminated transmission lines. With DISTRIBUTION CHIP output-to-output skews of 250ps, the MPC941 is ideal as a clock distribution chip for the most demanding of synchronous systems. For a similar product with a smaller number of outputs, please consult the MPC940 data sheet. * LVPECL or LVCMOS Clock Input * 250ps Maximum Output-to-Output Skew * Drives Up to 54 Independent Clock Lines * Maximum Output Frequency of 250MHz * High Impedance Output Enable * Extended Temperature Range: -40C to +85C FA SUFFIX * 48-Lead LQFP Packaging 48-LEAD LQFP PACKAGE * 32-Lead Pb-free Package Available CASE 932-03 * 3.3V or 2.5V VCC Supply Voltage With a low output impedance, in both the HIGH and LOW logic states, the output buffers of the MPC941 are ideal for driving series terminated transmission lines. More specifically, each of the 27 MPC941 outputs can drive two series terminated 50 transmission lines. With this capability, the MPC941 has an effective fanout of 1:54. With this level of fanout, the MPC941 provides enough copies of low skew clocks for most high performance synchronous systems. The differential LVPECL inputs of the MPC941 allow the device to interface directly with an LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used as a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. The MPC941 is fully 3.3V and 2.5V compatible. The 48-lead LQFP package was chosen to optimize performance, board space and cost of the device. The 48-lead LQFP has a 7x7mm body size. SCALE 2:1 576 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC941 LOGIC DIAGRAM PECL_CLK PECL_CLK LVCMOS_CLK LVCMOS_CLK_SEL PULLDOWN PULLDOWN PULLDOWN Q26 OE PULLDOWN 0 1 25 Q1-Q25 Q0 Pinout: 48-Lead TQFP (Top View) GND GND Q10 Q11 Q12 Q13 Q14 27 Q15 26 VCC VCC Q7 Q6 Q5 GND Q4 Q3 VCC Q2 Q1 Q0 GND 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 VCC 25 24 23 22 21 20 Q8 Q9 GND Q16 Q17 Q18 VCC Q19 Q20 GND Q21 Q22 Q23 VCC FUNCTION TABLE LVCMOS_CLK_SEL 0 1 Input PECL_CLK LVCMOS_CLK MPC941 19 18 17 16 15 14 1 2 3 4 5 6 7 8 9 10 11 13 12 LVCMOS_CLK PECL_CLK PECL_CLK VCC GND VCC LVCMOS_CLKSEL Table 1. Pin Configuration Pin PECL_CLK, PECL_CLK LVCMOS_CLK LVCMOS_CLK_SEL OE GND VCC Q0-Q26 Output I/O Input Input Input Input Type LVPECL LVCMOS LVCMOS LVCMOS Supply Supply LVCMOS Function LVPECL differential reference clock inputs Alternative reference clock input Input reference clock select Output tristate control Negative voltage supply output bank (GND) Positive voltage supply Clock outputs FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GND OE Q26 Q25 Q24 577 MPC941 Table 2. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C -40 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 3. DC Characteristics (VCC = 3.3V 5%, TA = -40 to +85C) Symbol VIH VIL IIN VPP VCMR VOH VOL IOZ ZOUT CPD CIN ICCQ VTT Characteristics Input High Voltage Input Low Voltage Input Current Peak-to-Peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage Output Tristate Leakage Current Output Impedance Power Dissipation Capacitance Input Capacitance Maximum Quiescent Supply Current Output Termination Voltage 14 - 17 7-8 4.0 5 VCC / 2 LVCMOS_CLK LVCMOS_CLK PECL_CLK, PECL_CLK PECL_CLK, PECL_CLK Min 2.0 -0.3 500 1.2 2.4 0.55 0.40 100 10 VCC -0.8 Typ Max VCC + 0.3 0.8 120 1 Unit V V A mV V V V V A pF pF mA V Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -24 mA2 IOL = 24mA2 IOL = 12mA Per Output All VCC Pins 1. Input pull-up / pull-down resistors influence input current. 2. The MPC941 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. Table 4. AC Characteristics (VCC = 3.3V 5%, TA = -40 to +85C)1 Symbol fMAX tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) tsk(PP) tsk(PP) DCQ tr, tf Characteristics Maximum Output Frequency LVCMOS_CLK Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Output-to-Output Skew Device-to-Device Skew Device-to-Device Skew Output Duty Cycle Output Rise/Fall Time PECL_CLK to any Q LVCMOS_CLK to any Q PECL_CLK to any Q LVCMOS_CLK to any Q PECL_CLK to any Q LVCMOS_CLK to any Q PECL_CLK to any Q LVCMOS_CLK to any Q 45 45 0.2 50 50 125 125 250 250 1000 1000 1400 1400 60 55 1.0 PECL_CLK to any Q LVCMOS_CLK to any Q 1.2 0.9 1.8 1.5 Min 0 Typ Max 2502 1.03 2.6 2.3 Unit MHz ns ns ns ns ns ps ps ps ps ps % % ns For a given TA and VCC, any Q For any TA, VCC and Q DCREF = 50% DCREF = 50% 0.55 to 2.4V Condition 0.8 to 2.0V 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. AC characteristics are guaranteed up to fmax. Please refer to applications section for information on power consumption versus operating frequency and thermal management. 3. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application, signal transition times smaller than 3 ns can be applied to the MPC941. 578 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC941 Table 5. DC Characteristics (VCC = 2.5V 5%, TA = -40 to +85C) Symbol VIH VIL IIN VPP VCMR VOH VOL IOZ ZOUT CPD CIN ICCQ VTT Input High Voltage Input Low Voltage Input Current Peak-to-Peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage Output Tristate Leakage Current Output Impedance Power Dissipation Capacitance Input Capacitance Maximum Quiescent Supply Current Output Termination Voltage VCC / 2 18 - 20 7-8 4.0 5 10 PECL_CLK, PECL_CLK PECL_CLK, PECL_CLK 500 1.1 1.8 0.6 100 VCC - 0.7 Characteristics LVCMOS_CLK LVCMOS_CLK Min 1.7 -0.3 Typ Max VCC + 0.3 0.7 1201 Unit V V A mV V V V A pF pF mA V All VCC Pins Per Output LVPECL LVPECL IOH = -15 mA2 IOL = 15 mA2 Condition LVCMOS LVCMOS 1. Input pull-up / pull-down resistors influence input current. 2. The MPC941 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. Table 6. AC Characteristics (VCC = 2.5V 5%, TA = -40 to +85C)1 Symbol fMAX tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) tsk(PP) tsk(PP) DCQ tr, tf Characteristics Maximum Output Frequency LVCMOS_CLK Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Output-to-Output Skew Device-to-Device Skew Device-to-Device Skew Output Duty Cycle Output Rise/Fall Time PECL_CLK to any Q LVCMOS_CLK to any Q PECL_CLK to any Q LVCMOS_CLK to any Q PECL_CLK to any Q LVCMOS_CLK to any Q PECL_CLK to any Q LVCMOS_CLK to any Q 45 45 0.2 50 50 125 125 250 250 1200 1200 1600 1600 60 55 1.0 PECL_CLK to any Q LVCMOS_CLK to any Q 1.3 1.0 2.1 1.8 Min 0 Typ Max 250 2 Unit MHz ns ns ns ns ns ps ps ps ps ps % % ns Condition 0.7 to 1.7V 1.03 2.9 2.6 For a given TA and VCC, any Q For any TA, VCC and Q DCREF = 50% DCREF = 50% 0.6 to 1.6V 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. AC characteristics are guaranteed up to fMAX. Please refer to the applications section for information on power consumption versus operating frequency and thermal management. 3. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application, signal transition times smaller than 3 ns can be applied to the MPC941. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 579 MPC941 APPLICATIONS INFORMATION Driving Transmission Lines The MPC941 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions data book (DL207/D). In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC941 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 1 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC941 clock driver is effectively doubled due to its capability to drive multiple lines. MPC941 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Zo / (Rs + Ro + Zo)) Zo = 50 || 50 Rs = 36 || 36 Ro = 14 VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 3.0 2.5 2.0 VOLTAGE (V) IN 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 Figure 2. Single versus Dual Waveforms MPC941 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB1 RS = 36 ZO = 50 OutB0 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 3 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. Figure 1. Single versus Dual Transmission Lines The waveform plots of Figure 2 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC941 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC941. The output waveform in Figure 2 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the MPC941 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 ||50 25 = 25 Figure 3. Optimized Dual Line Termination 580 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC941 Power Consumption of the MPC941 and Thermal Management The MPC941 AC specification is guaranteed for the entire operating frequency range up to 250 MHz. The MPC941 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperture, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC941 die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability please refer to the application note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature: Table 7. Die Junction Temperature and MTBF Junction Temperature (C) 100 110 120 130 MTBF (Years) 20.4 9.1 4.2 2.0 In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cyle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 7, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC941 in a series terminated transmission line system. TJ,MAX should be selected according to the MTBF system requirements and Table 7. Rthja can be derived from Table 8 The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. Table 8. Thermal Package Impedance of the 48ld LQFP Convection, LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm Rthja (1P2S board), K/W 78 68 59 56 54 53 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC941 needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC941 is represented in equation 1. Where ICCQ is the static current consumption of the MPC941, CPD is the power dissipation capacitance per output, ()CL represents the external capacitive output load, N is the number of active outputs (N is always 27 in case of the MPC941). The MPC941 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. PTOT = [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] * VCC M If the calculated maximum frequency is below 250 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the MPC941. The charts were calculated for a maximum tolerable die junction temperature of 110C (120C), corresponding to a estimated MTBF of 9.1 years (4 years), a supply voltage of either 3.3V or 2.5V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. Equation 1 Equation 2 Equation 3 PTOT = VCC * [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] + [ DCQ * IOH * (VCC - VOH) + (1 - DCQ) * IOL * VOL ] M P TJ = TA + PTOT * Rthja fCLOCK,MAX = 1 * CPD * N * V2CC [ Tj,MAX - TA Rthja - (ICCQ * VCC) ] Equation 4 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 581 MPC941 300 TA = 65C OPERATING FREQUENCY (MHz) 250 200 150 100 50 0 500 fMAX (AC) TA = 75C 300 OPERATING FREQUENCY (MHz) 250 200 TA = 65C 150 100 50 0 500 TA = 75C TA = 85C TA = 45C TA = 55C fMAX (AC) TA = 55C TA = 35C TA = 85C Safe operation 400 300 200 IFPM, CONVECTION 100 0 Safe operation 400 300 200 IFPM, CONVECTION 100 0 Figure 4. Maximum MPC941 frequency, VCC = 3.3V, MTBF 9.1 years, driving series terminated transmission lines Figure 5. Maximum MPC941 frequency, VCC = 3.3V, MTBF 9.1 years, 4 pF load per line 300 OPERATING FREQUENCY (MHz) 250 200 150 100 50 0 500 fMAX (AC) TA = 75C TA = 85C TA = 65C OPERATING FREQUENCY (MHz) 300 250 200 150 100 50 0 500 TA = 55C TA = 65C TA = 75C TA = 85C fMAX (AC) TA = 45C Safe operation 400 300 200 IFPM, CONVECTION 100 0 Safe operation 400 300 200 IFPM, CONVECTION 100 0 Figure 6. Maximum MPC941 frequency, VCC = 3.3V, MTBF 4 years, driving series terminated transmission lines Figure 7. Maximum MPC941 frequency, VCC = 3.3V, MTBF 4 years, 4 pF load per line 582 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC941 300 TA = 75C OPERATING FREQUENCY (MHz) OPERATING FREQUENCY (MHz) 250 200 150 100 50 0 500 fMAX (AC) TA = 85C 250 200 150 100 50 0 500 fMAX (AC) TA = 75C TA = 85C 300 TA = 65C Safe operation 400 300 200 IFPM, CONVECTION 100 0 Safe operation 400 300 200 IFPM, CONVECTION 100 0 Figure 8. Maximum MPC941 frequency, VCC = 2.5V, MTBF 9.1 years, driving series terminated transmission lines Figure 9. Maximum MPC941 frequency, VCC = 2.5V, MTBF 9.1 years, 4 pF load per line 300 OPERATING FREQUENCY (MHz) 250 200 150 100 50 0 500 OPERATING FREQUENCY (MHz) fMAX (AC) TA = 85C 300 250 200 150 100 50 0 500 fMAX (AC) TA = 75C TA = 85C Safe operation 400 300 200 IFPM, CONVECTION 100 0 Safe operation 400 300 200 IFPM, CONVECTION 100 0 Figure 10. Maximum MPC941 frequency, VCC = 2.5V, MTBF 4 years, driving series terminated transmission lines Figure 11. Maximum MPC941 frequency, VCC = 2.5V, MTBF 4 years, 4 pF load per line FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 583 MPC941 DUT MPC941 Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 12. LVCMOS_CLK MPC941 AC Test Reference for VCC = 3.3V and VCC = 2.5V ZO = 50 DUT MPC941 ZO = 50 Differential Pulse Generator Z = 50 RT = 50 VTT RT = 50 VTT Figure 13. PECL_CLK MPC941 AC Test Reference for VCC = 3.3V and VCC = 2.5V PCLK_CLK PCLK_CLK VPP VCC VCMR VCC VCC /2 GND tPD tPD LVCMOS_CLK VCC / 2 GND Q VCC VCC / 2 GND Q Figure 14. LVPECL Propagation Delay (tPD) Test Reference Figure 15. LVCMOS Propagation Delay (tPD) Test Reference VCC VCC / 2 tP t0 DC = tP/t0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage tSK(O) GND VCC VCC / 2 GND VOH VCC / 2 GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay path within a single device Figure 16. Output Duty Cycle (DC) Figure 17. Output-to-Output Skew tSK(O) VCC = 3.3V VCC = 2.5V 2.4 0.55 tF tR 1.8V 0.6V tF tR VCC = 3.3V VCC = 2.5V 2.0 0.8 1.7V 0.7V Figure 18. Output Transition Time Test Reference Figure 19. Input Transition Time Test Reference 584 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC942C Rev 0, 02/2001 Low Voltage 1:18 Clock Distribution Chip MPC942C The MPC942 is a 1:18 low voltage clock distribution chip with 2.5V or 3.3V LVCMOS output capabilities. The device is offered in two versions; the LOW VOLTAGE MPC942C has an LVCMOS input clock while the MPC942P has a LVPECL 1:18 CLOCK input clock. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature DISTRIBUTION CHIP the drive strength to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 200ps, the MPC942 is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5V outputs also make the device ideal for supplying clocks for a high performance Pentium II microprocessor based design. * LVCMOS/LVTTL Clock Input * 2.5V LVCMOS Outputs for Pentium II Microprocessor Support * 150ps Maximum Targeted Output-to-Output Skew * Maximum Output Frequency of 250MHz @ 3.3 VCC * 32-Lead TQFP Packaging FA SUFFIX 32-LEAD TQFP PACKAGE * Single 3.3V or 2.5V Supply CASE 873A-03 With a low output impedance (12), in both the HIGH and LOW logic states, the output buffers of the MPC942 are ideal for driving series terminated transmission lines. With an output impedance of 12 the MPC942 can drive two series terminated transmission lines from each output. This capability gives the MPC942 an effective fanout of 1:36. The MPC942 provides enough copies of low skew clocks for most high performance synchronous systems. The LVCMOS/LVTTL input of the MPC942C provides a more standard LVCMOS interface. The OE pins will place the outputs into a high impedance state. The OE pin has an internal pullup resistor. The MPC942 is a single supply device. The VCC power pins require either 2.5V or 3.3V. The 32-lead TQFP package was chosen to optimize performance, board space and cost of the device. The 32-lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing. Pentium II is a trademark of Intel Corporation. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 585 MPC942C Pentium II is a trademark of Intel Corporation. LOGIC DIAGRAM MPC942C Block Diagram LVCMOS_CLK Q0 Q1:Q16 Q17 OE (Int. Pullup) FUNCTION TABLE OE 0 1 Output HIGH IMPEDANCE OUTPUTS ENABLED Pinout: 32-Lead (Top View) GND 17 16 15 14 VCC Q12 Q13 Q14 GND Q15 Q16 Q17 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC Q10 19 NC Q11 18 VCC VCC 21 NC Q9 20 OE Q6 Q7 23 Q8 22 LVCMOS_CLK 24 GND Q5 Q4 Q3 VCC Q2 Q1 Q0 25 26 27 28 29 30 31 32 MPC942C GND Table 1. Absolute Maximum Ratings Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 3.6 VCC + 0.3 20 125 Unit V V mA C 586 GND FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC942C Table 2. DC Characteristics (TA = 0 to 70C, VCCI = 2.5V 5%, VCCO = 2.5V 5%) Symbol VIH VIL VOH VOL IIN CIN CPD ZOUT ICC Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 4.0 14 12 0.5 2.0 0.5 200 Characteristic Min 2.0 Typ Max VCCI 0.8 Unit V V V V A pF pF mA Per Output IOH = -16 mA IOL = 16 mA Condition Table 3. AC Characteristics (TA = 0 to 70C, VCCI = 2.5V 5%, VCCO = 2.5V 5%) Symbol Fmax tPLH tsk(o) tsk(pr) tsk(pr) dt tr, tf Maximum Frequency Propagation Delay Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Duty Cycle Output Rise/Fall Time 45 0.2 1.5 Characteristic Min Typ Max 200 2.8 200 1.3 600 55 1.0 Unit MHz ns ps ns ps % ns Notes 1, 2 Notes 1, 3 Condition Table 4. DC Characteristics (TA = 0 to 70C, VCCI = 3.3V 5%, VCCO = 3.3V 5%) Symbol VIH VIL VOH VOL IIN CIN CPD ZOUT ICC Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 4.0 14 12 0.5 2.4 0.5 200 Characteristic Min 2.4 Typ Max VCCI 0.8 Unit V V V V A pF pF mA Per Output IOH = -20 mA IOL = 20 mA Condition Table 5. AC Characteristics (TA = 0 to 70C, VCCI = 3.3V 5%, VCCO = 3.3V 5%) Symbol Fmax tPLH tsk(o) tsk(pr) tsk(pr) dt tr, tf Maximum Frequency Propagation Delay Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Duty Cycle Output Rise/Fall Time 45 0.2 1.3 Characteristic Min Typ Max 250 2.3 200 1.0 500 55 1.0 Unit MHz ns ps ns ps % ns Notes 1, 2 Notes 1, 3 Note 1 Condition 1. Tested using standard input levels, production tested @ 133 MHz. 2. Across temperature and voltage ranges, includes output skew. 3. For a specific temperature and voltage, includes output skew. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 587 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC942P Rev 1, 02/2001 Low Voltage 1:18 Clock Distribution Chip MPC942P The MPC942 is a 1:18 low voltage clock distribution chip with 2.5V or 3.3V LVCMOS output capabilities. The device is offered in two versions; the LOW VOLTAGE MPC942C has an LVCMOS input clock while the MPC942P has a LVPECL 1:18 CLOCK input clock. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature DISTRIBUTION CHIP the drive strength to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 200ps, the MPC942 is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5V outputs also make the device ideal for supplying clocks for a high performance Pentium II microprocessor based design. * LVPECL Clock Input * 2.5V LVCMOS Outputs for Pentium II Microprocessor Support * 200ps Maximum Targeted Output-to-Output Skew * Maximum Output Frequency of 250MHz @ 3.3 VCC * 32-Lead LQFP Packaging FA SUFFIX 32-LEAD TQFP PACKAGE * Single 3.3V or 2.5V Supply CASE 873A-03 With a low output impedance (12), in both the HIGH and LOW logic states, the output buffers of the MPC942 are ideal for driving series terminated transmission lines. With an output impedance of 12 the MPC942 can drive two series terminated transmission lines from each output. This capability gives the MPC942 an effective fanout of 1:36. The MPC942 provides enough copies of low skew clocks for most high performance synchronous systems. The differential LVPECL inputs of the MPC942P allow the device to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The OE pins will place the outputs into a high impedance state. The OE pin has an internal pullup resistor. The MPC942 is a single supply device. The VCC power pins require either 2.5V or 3.3V. The 32-lead LQFP package was chosen to optimize performance, board space and cost of the device. The 32-lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing. Pentium II is a trademark of Intel Corporation. 588 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC942P LOGIC DIAGRAM MPC942P Block Diagram PECL_CLK PECL_CLK Q0 Q1:Q16 Q17 OE (Int. Pullup) FUNCTION TABLE OE 0 1 Output HIGH IMPEDANCE OUTPUTS ENABLED Pinout: 32-Lead (Top View) GND 17 16 15 14 VCC Q12 Q13 Q14 GND Q15 Q16 Q17 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC Q10 19 PECL_CLK Q11 18 VCC VCC 21 NC Q9 20 PECL_CLK Q6 Q7 23 Q8 22 OE 24 GND Q5 Q4 Q3 VCC Q2 Q1 Q0 25 26 27 28 29 30 31 32 MPC942P GND Table 1. Absolute Maximum Ratings1 Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 3.6 VCC + 0.3 20 125 Unit V V mA C 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GND 589 MPC942P Table 2. DC Characteristics (TA = 0 to 70C, VCC = 2.5V 5%) Symbol VIH VIL VPP VX VOH VOL IIN CIN CPD ZOUT ICC Input HIGH Voltage Input LOW Voltage Input Swing PECL_CLK Input Crosspoint PECL_CLK Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 4.0 14 12 0.5 5.0 0.6 VCC-1.0 2.0 0.5 200 Characteristic Min 2.0 Typ Max VCC 0.8 1.0 VCC-0.6 Unit V V V V V V A pF pF mA Per Output IOH = -16 mA IOL = 16 mA Condition Table 3. AC Characteristics (TA = 0 to 70C, VCC = 2.5V 5%) Symbol Fmax tPLH tPHL tsk(o) tsk(pr) tsk(pr) tr, tf Maximum Frequency Propagation Delay Propagation Delay Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Output Rise/Fall Time 0.1 1.8 2.0 Characteristic Min Typ Max 200 4.0 4.3 200 2.2 1.3 1.0 Unit MHz ns ns ps ns ps ns Note 2 Note 1 Condition 1. For a specific temperature and voltage, includes output skew. 2. Across temperature and voltage ranges, includes output skew. 590 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC942P Table 4. DC Characteristics (TA = 0 to 70C, VCC = 3.3V 5%) Symbol VIH VIL VPP VX VOH VOL IIN CIN CPD ZOUT ICC Input HIGH Voltage Input LOW Voltage Input Swing PECL.CLK Input Crosspoint PECL_CLK Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 4.0 14 12 0.5 5.0 0.6 VCC-1.0 2.4 0.6 200 Characteristic Min 2.4 Typ Max VCC 0.8 1.0 VCC-0.6 Unit V V V V V V A pF pF mA Per Output IOH = -20 mA IOL = 20 mA Condition Table 5. AC Characteristics (TA = 0 to 70C, VCC = 3.3V 5%) Symbol Fmax tPLH tPHL tsk(o) tsk(pr) tsk(pr) tr, tf Maximum Frequency Propagation Delay Propagation Delay Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Output Rise/Fall Time 0.1 1.5 1.5 Characteristic Min Typ Max 250 3.2 3.6 200 1.7 1.0 1.0 Unit MHz ns ns ps ns ps ns Note 2 Note 1 Condition 1. For a specific temperature and voltage, includes output skew. 2. Across temperature and voltage ranges, includes output skew. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 591 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9443 Rev 4, 07/2004 2.5 V and 3.3 V LVCMOS Clock Fanout Buffer The MPC9443 is a 2.5 V and 3.3 V compatible 1:16 clock distribution buffer designed for low-voltage high-performance telecom, networking and computing applications. The device supports 3.3 V, 2.5 V and dual supply voltage (mixed-voltage) applications. The MPC9443 offers 16 low-skew outputs which are divided into 4 individually configurable banks. Each output bank can be individually supplied by 2.5 V or 3.3 V, individually set to run at 1X or 1/2X of the input clock frequency or be disabled (logic low output state). Two selectable LVPECL compatible inputs support differential clock distribution systems. In addition, one selectable LVCMOS input is provided for LVCMOS clock distribution systems. The MPC9443 is specified for the extended temperature range of -40 to +85C. Features * * * * * * * * * * * * Configurable 16 outputs LVCMOS clock distribution buffer Compatible to single, dual and mixed 3.3 V / 2.5 V voltage supply Output clock frequency up to 350 MHz Designed for high-performance telecom, networking and computer applications Supports applications requiring clock redundancy Maximum output skew of 250 ps (125 ps within one bank) Selectable output configurations per output bank Individually per-bank high-impedance tristate Output disable (stop in logic low state) control 48-lead LQFP package 48-lead Pb-free Package Available Ambient operating temperature range of -40 to 85C MPC9443 LOW VOLTAGE SUPPLY 2.5 V AND 3.3 V LVCMOS CLOCK FANOUT BUFFER SCALE 2:1 FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932-03 Functional Description The MPC9443 is a full static design supporting clock frequencies up to 350 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the four output banks. Two independent LVPECL compatible clock inputs are available. This feature supports redundant differential clock sources. In addition, the MPC9443 supports single-ended LVCMOS clock distribution systems. Each of the four output banks can be individually supplied by 2.5 V or 3.3 V, supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each output bank. The MPC9443 output banks are in high-impedance state by deasserting the OEN pins. Asserting OEN will the enable output banks. Please see Table 4. Output High-Impedance Control (OEN) for details. The outputs can be synchronously stopped (logic low state). The outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9443 outputs can drive one or two traces giving the devices an effective fanout of 1:32 at VCC = 3.3 V. The device is packaged in a 7x7 mm2 48-lead LQFP package. 592 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9443 PCLK0 PCLK0 PCLK1 PCLK1 TCLK (PULLDOWN) (PULLUP) (PULLDOWN) (PULLUP) (PULLDOWN) 0 0 1 1 CLK / 2 1 CLK 0 BANK A QA0 QA1 QA2 QA3 QA4 PCLK_SEL TCLK_SEL (PULLDOWN) (PULLDOWN) 0 1 BANK B QB0 QB1 FSELA FSELB FSELC FSELD QB2 (PULLDOWN) (PULLDOWN) (PULLDOWN) (PULLDOWN) 0 1 BANK C QC0 QC1 QC2 QD0 BANK D 0 QD1 QD2 QD3 QD4 5 CLK_STOP OE0 OE1 (PULLDOWN) (PULLDOWN) (PULLDOWN) 1 Figure 1. MPC9443 Logic Diagram VCCC VCCB GND GND GND QC0 QC1 QC2 QB0 QB1 QB2 VCC QA4 QA3 QA2 GND QA1 QA0 VCCA FSELA FSELB FSELC GND 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 39 40 41 42 43 44 45 46 47 48 23 22 21 20 VCC VCCD QD0 QD1 QD2 GND QD3 QD4 VCCD CLK_STOP OE0 OE1 GND MPC9443 19 18 17 16 15 14 13 9 10 11 12 PCLK1 PCLK1 PCLK_SEL GND 1 2 FSELD 3 CCLK 4 CCLK_SEL 5 GND 6 PCLK0 7 PCLK0 8 VCC Figure 2. 48-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA VCC 593 MPC9443 Table 1. Pin Configuration Pin CCLK PCLK0, PCLK0 PCLK1, PCLK1 FSELA, FSELB, FSELC, FSELD CCLK_SEL PCLK_SEL OE0, OE1 CLK_STOP GND VCCA, VCCB, VCCC, VCCD VCC QA0 to QA4 QB0 to QB2 QC0 to QC2 QD0 to QD4 Output Output Output Output Input Input Input Input Input Input Input Input I/O Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Supply Supply Supply LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS clock inputs LVPECL differential clock input LVPECL differential clock input Output bank divide select input LVCMOS/LVPECL clock input select PCLK0/PCLK1 clock input select Output tristate control Synchronous output enable/disable (clock stop) control Negative voltage supply Positive voltage supply output bank (VCC) Positive voltage supply core (VCC) Bank A outputs Bank B outputs Bank C outputs Bank D outputs Function Table 2. Supported Single and Dual Supply Configurations Supply Voltage Configuration 3.3 V Supply Mixed Mode Supply 2.5 V Supply 1. 2. 3. 4. 5. VCC1 3.3 V 3.3 V 2.5 V VCCA2 3.3 V 3.3 V or 2.5 V 2.5 V VCCB3 3.3 V 3.3 V or 2.5 V 2.5 V VCCC4 3.3 V 3.3 V or 2.5 V 2.5 V VCCD5 3.3 V 3.3 V or 2.5 V 2.5 V GND 0V 0V 0V VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels. VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels. VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels. VCCD is the positive power supply of the bank D outputs. VCCD voltage defines bank D output levels. Table 3. Function Table (Controls) Control CCLK_SEL PCLK_SEL FSELA FSELB FSELC FSELD CLK_STOP OE0, OE1 Default 0 0 0 0 0 0 0 00 0 PCLK or PCLK1 active (LVPECL clock mode) PCLK0 active, PCLK1 inactive fQA0:4 = fREF fQB0:2 = fREF fQC0:2 = fREF fQD0:4 = fREF Normal operation 1 CCLK active (LVCMOS clock mode) PCLK1 active, PCLK0 inactive fQA0:4 = fREF / 2 fQB0:2 = fREF / 2 fQC0:2 = fREF / 2 fQD0:4 = fREF / 2 Outputs are synchronously disabled (stopped) in logic low state Asynchronous output enable control. See Table 4. Output High-Impedance Control (OEN) 594 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9443 Table 4. Output High-Impedance Control (OEN)1 OE0 0 0 1 1 OE1 0 1 0 1 QA0 to QA4 Enabled Enabled Enabled Disabled (tristate) QB0 to QB2 Enabled Disabled (tristate) Enabled Disabled (tristate) QC0 to QC2 Enabled Disabled (tristate) Disabled (tristate) Disabled (tristate) QD0 to QD4 Enabled Enabled Disabled (tristate) Disabled (tristate) Total Number of Enabled Outputs 16 10 8 0 1. OEN will tristate (high impedance) output banks independent on the logic state of the output and the status of CLK_STOP. Table 5. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 6. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Condition FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 595 MPC9443 Table 7. DC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 3.3 V 5%, TA = -40 to +85C) Symbol VIH VIL VPP VCMR1 IIN VOH VOL ZOUT ICCQ4 Characteristics Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range Input Current Output High Voltage Output Low Voltage Output Impedance Maximum Quiescent Supply Current 19 3.0 2 Min 2.0 PCLK0, 1 PCLK0, 1 -0.3 250 1.1 2.4 Typ Max VCC + 0.3 0.8 VCC - 0.6 200 0.55 0.30 Unit V V mV V A V V V mA Condition LVCMOS LVCMOS LVPECL LVPECL VIN = GND or VIN = VCC IOH = -24 mA3 IOL = 24 mA3 IOL = 12 mA All VCC Pins 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. Input pull-up / pull-down resistors influence input current. 3. The MPC9443 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC =3.3 V) or one 50 series terminated transmission line (for VCC = 2.5 V). 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 8. AC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 3.3 V 5%, TA = -40 to +85C)1 Symbol fref fMAX VPP VCMR 2 Characteristics Input Frequency Maximum Output Frequency Peak-to-Peak Input Voltage Common Mode Range Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation Delay PCLK0,1 to any Q PCLK0,1 to any Q CCLK to any Q CCLK to any Q /1 output /2 output PCLK0,1 PCLK0,1 Min 0 0 0 500 1.3 1.4 2.5 2.4 2.1 1.9 Typ Max 350 350 175 1000 VCC - 0.8 1.0 5.0 5.2 4.2 4.6 10 10 3 Unit MHz MHz MHz mV V ns ns ns ns ns ns ns ns ps ps ps ps ns ns ns ns ps ps % % ns Condition FSELx = 0 FSELx = 1 LVPECL LVPECL 0.8 to 2.0 V tP, REF tr, tf tPLH tPHL tPLH tPHL tPLZ, HZ tPZL, LZ Output Disable Time Output Enable Time 500 tS, tH Setup, Hold Time (reference clock to CLK_STOP) tsk(LH, HL) Output-to-Output Skew4 Within one bank Any output, same output divider Any output, any output divider tsk(PP) Device-to-Device Skew (LH)5 Using PCLK0,1 Using CCLK Device-to-Device Skew (LH, HL)6 Using PCLK0,1 Using CCLK tSK(P) DCQ tr, tf Using PCLK0,1 Using CCLK Output Duty Cycle fQ<140 MHz and using CCLK fQ<250 MHz and using PCLK0,1 Output Rise/Fall Time Output Pulse Skew7 125 225 250 2.5 2.1 2.8 2.7 300 400 55 55 1.0 DCREF = 50% 45 45 0.1 50 50 0.55 to 2.4 V 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge. 5. Device-to-device skew referenced to the rising output edge. 6. Device-to-device skew referenced to the rising output edge or referenced to the falling output edge. 7. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL | 596 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9443 Table 9. DC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 2.5 V 5%, TA = -40 to +85C) Symbol VIH VIL VPP VCMR1 IIN VOH VOL ZOUT ICCQ4 Characteristics Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range Input Current Output High Voltage Output Low Voltage Output Impedance Maximum Quiescent Supply Current 22 3.0 2 Min 1.7 PCLK0, 1 PCLK0, 1 -0.3 250 1.1 1.8 Typ Max VCC + 0.3 0.7 VCC - 0.7 200 0.6 Unit V V mV V A V V mA Condition LVCMOS LVCMOS LVPECL LVPECL VIN = GND or VIN = VCC IOH = -15 mA3 IOL = 15 mA3 All VCC Pins 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. Input pull-up / pull-down resistors influence input current. 3. The MPC9443 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to one 50 series terminated transmission line at VCC =2.5 V. 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 10. AC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 2.5 V 5%, TA = -40 to +85C)1 Symbol fref fMAX VPP VCMR2 tP, REF tr, tf tPLH tPHL tPLH tPHL tPLZ, HZ tPZL, LZ tS, tH tsk(LH, HL) Input Frequency Maximum Output Frequency Peak-to-Peak Input Voltage Common Mode Range Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation Delay PCLK0,1 to any Q PCLK0,1 to any Q CCLK to any Q CCLK to any Q 2.5 2.4 2.1 1.9 /1 output /2 output PCLK0,1 PCLK0,1 Characteristics Min 0 0 0 500 1.3 1.4 1.03 6.0 6.2 5.3 5.5 10 10 500 125 225 250 3.2 3.1 3.5 3.4 300 400 55 55 1.0 Typ Max 350 350 175 1000 VCC - 0.7 Unit MHz MHz MHz mV V ns ns ns ns ns ns ns ns ps ps ps ps ns ns ns ns ps ps % % ns DCREF = 50% 0.8 to 2.0 V Condition FSELx = 0 FSELx = 1 LVPECL LVPECL Output Disable Time Output Enable Time Setup, Hold Time (reference clock to CLK_STOP) Output-to-Output Skew4 Within one bank Any output, same output divider Any output, any output divider Device-to-Device Skew (LH)5 Using PCLK0,1 Using CCLK tsk(PP) Device-to-Device Skew (LH, HL)6 Using PCLK0,1 Using CCLK tSK(P) DCQ tr, tf Using PCLK0,1 Using CCLK Output Duty Cycle fQ<140 MHz and using CCLK fQ<140 MHz and using PCLK0,1 Output Rise/Fall Time Output Pulse Skew7 45 45 0.1 50 50 0.55 to 2.4 V 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge. 5. Device-to-device skew referenced to the rising output edge. 6. Device-to-device skew referenced to the rising output edge or referenced to the falling output edge. 7. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL | FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 597 MPC9443 Table 11. DC Characteristics (VCC = 3.3 V 5%, any VCCA,B,C,D = 2.5 V 5% or 3.3 V 5% (mixed), TA = -40 to +85C) Symbol VIH VIL IIN VOH VOL VPP VCMR3 ZOUT CPD ICCQ4 Characteristics Input High Voltage Input Low Voltage Input Current1 Output High Voltage Output Low Voltage 2.5 V output 3.3 V output 2.5 V output 3.3 V output PCLK0,1 PCLK0, 1 2.5 V output 3.3 V output 250 1.1 22 19 10 3.0 VCC - 0.6 1.7 2.0 0.6 0.55 Min 2.0 -0.3 Typ Max VCC + 0.3 0.8 200 Unit V V A V V IOH = -15 mA2 IOH = 24 mA2 IOL = 15 mA2 IOL = 24 mA2 LVPECL LVPECL Condition LVCMOS LVCMOS Peak-to-Peak Input Voltage Common Mode Range Output Impedance Power Dissipation Capacitance Maximum Quiescent Supply Current mV V pF mA Per Output All VCC Pins 1. Input pull-up / pull-down resistors influence input current. 2. The MPC9443 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC = 3.3 V) or one 50 series terminated transmission line (for VCC =2.5 V). 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 12. AC Characteristics (VCC = 3.3 V 5%, any VCCA,B,C,D = 2.5 V 5% or 3.3 V 5% (mixed), TA = -40 to +85C)1 2 Symbol tsk(LH, HL) Characteristics Output-to-Output Skew Any output, same output divider Any output, any output divider Device-to-Device Skew Propagation Delay Output Pulse Skew4 Using PCLK0,1 Using CCLK 45 45 50 50 3 Min Typ Max 275 350 Unit ps ps Condition tsk(PP) tPLH, HL tSK(P) See Table 8 (3.3 V AC Characteristics) See Table 8 (3.3 V AC Characteristics) 400 500 55 55 ps ps % % DCREF = 50% DCQ Output Duty Cycle fQ<140 MHz and using CCLK fQ<250 MHz and using PCLK0,1 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. This table only specifies AC parameter in mixed voltage supply conditions that vary from the corresponding AC tables. For all other parameters, see Table 8 (for 3.3 V outputs) or Table 10 (for 2.5 V outputs) 3. tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge. 4. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL | 598 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9443 APPLICATIONS INFORMATION Driving Transmission Lines The MPC9443 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines at VCC = 3.3 V. For more information on transmission lines the reader is referred to application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9443 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9443 clock driver is effectively doubled due to its capability to drive multiple lines (at VCC = 3.3 V). MPC9443 OUTPUT BUFFER IN 19 match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 31 || 31 R0 = 19 VL = 3.0 (25 / (15.5 + 19 + 25) = 1.26V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.52 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 3.0 2.5 2.0 In 1.5 1.0 0.5 OutA tD = 3.8956 OutB tD = 3.9386 RS = 31 ZO = 50 OutA VOLTAGE (V) 0 2 4 6 8 TIME (ns) 10 12 14 MPC9443 OUTPUT BUFFER IN 19 RS = 31 ZO = 50 OutB0 ZO = 50 OutB1 Figure 4. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9443 OUTPUT BUFFER 19 RS = 31 Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9443 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9443. The output waveform in Figure 4. Single versus Dual Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 31 series resistor plus the output impedance does not RS = 12 ZO = 50 RS = 12 ZO = 50 19 + 12 || 12 = 50 || 50 25 = 25 Figure 5. Optimized Dual Line Termination FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 599 MPC9443 Power Consumption of the MPC9443 and Thermal Management The MPC9443 AC specification is guaranteed for the entire operating frequency range up to 350 MHz. The MPC9443 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC9443 die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability please refer to the application note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature. Table 13. Die Junction Temperature and MTFBF Junction Temperature (C) 100 110 120 130 MTBF (Years) 20.4 9.1 4.2 2.0 In Equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used CL is zero in Equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature (TJ) as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 13, the junction temperature can be used to estimate the long-term device reliability. Further, combining Equation 1 and Equation 2 results in a maximum operating frequency for the MPC9443 in a series terminated transmission line system. TJ,MAX should be selected according to the MTBF system requirements and Table 13. Rthja can be derived from Table 14. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. Table 14. Thermal Package Impedance of the 48 ld LQFP Convection, LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm 64 50 Rthja (1P2S board), K/W 69 Rthja (2P2S board), K/W 53 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC9443 needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC9443 is represented in Equation 1. Where ICCQ is the static current consumption of the MPC9443, CPD is the power dissipation capacitance per output, ()CL represents the external capacitive output load, N is the number of active outputs (N is always 16 in case of the MPC9443). The MPC9443 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from Equation 1. Using parallel termination output termination results in Equation 2 for power dissipation. If the calculated maximum frequency is below 250 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the MPC9443. The charts were calculated for a maximum tolerable die junction temperature of 110C (120C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3 V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. Equation 1 Equation 2 Equation 3 PTOT = [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] * VCC M PTOT = VCC * [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] + [ DCQ * IOH * (VCC - VOH) + (1 - DCQ) * IOL * VOL ] M P TJ = TA + PTOT * Rthja fCLOCK,MAX = 1 * CPD * N * V2CC [ Tj,MAX - TA Rthja - (ICCQ * VCC) ] Equation 4 600 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9443 Figure 6. Maximum MPC9443 frequency, VCC = 3.3 V, MTBF 9.1 Years, Driving Series Terminated Transmission Lines Figure 7. Maximum MPC9443 Frequency, VCC = 3.3 V, MTBF 9.1 Years, 4 pF Load per Line Figure 8. Maximum MPC9443 Frequency, VCC = 3.3 V, MTBF 4 Years, Driving Series Terminated Transmission Lines Figure 9. Maximum MPC9443 Frequency, VCC = 3.3 V, MTBF 4 Years, 4 pF Load per Line FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 601 MPC9443 MPC9443 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 10. CCLK MPC9443 AC Test Reference for Vcc = 3.3 V and Vcc = 2.5 V Differential Pulse Generator Z = 50 ZO = 50 MPC9443 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 11. PCLK MPC9443 AC Test Reference PCLK PCLK VPP VCMR VCC QX tP(LH) tP(HL) VCC / 2 GND CCLK VCC VCC/2 GND VCC VCC/2 GND tP(LH) tP(HL) QX Figure 12. Propagation Delay (tPD) Test Reference Figure 13. Propagation Delay (tPD) Test Reference VCC VCC/2 GND VCC VCC/2 GND tSK(LH) tSK(HL) CCLK VCC VCC/2 GND VCC VCC/2 GND tP(LH) tP(HL) QX The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device tSK(P) = | tPLH - tPHL | Figure 14. Output-to-Output Skew tSK(LH, HL) Figure 15. Output Pulse Skew (tSK(P)) Test Reference 602 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9443 VCC VCC/2 GND tP T0 DC = (tP ? T0 x 100%) The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage tF tR VCC = 3.3 V VCC = 2.5 V 2.4 0.55 1.8 V 0.6 V Figure 16. Output Duty Cycle (DC) Figure 17. Output Transition Time Test Reference VCC CCLK PCLK TN TN+1 TJIT(CC) = |TN-TN+1| CLK_STOP tS tH VCC/2 GND VCC VCC/2 GND The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 18. Cycle-to-Cycle Jitter Figure 19. Setup and Hold Time (tS, tH) Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 603 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9446 Rev 2, 08/2004 2.5V and 3.3V LVCMOS Clock Fanout Buffer The MPC9446 is a 2.5V and 3.3V compatible 1:10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both 3.3V, 2.5V and dual supply voltages are supported for mixed-voltage applications. The MPC9446 offers 10 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1 and 1:2 output to input frequency ratios. The MPC9446 is specified for the extended temperature range of -40C to 85C. Features * * * * * * * * * * * Configurable 10 outputs LVCMOS clock distribution buffer Compatible to single, dual and mixed 3.3V/2.5V voltage supply Wide range output clock frequency up to 250 MHz Designed for mid-range to high-performance telecom, networking and computer applications Supports applications requiring clock redundancy Maximum output skew of 200 ps (150 ps within one bank) Selectable output configurations per output bank Tristable outputs 32-lead LQFP package 32-lead Pb-free Package Available Ambient operating temperature range of -40 to 85C MPC9446 LOW VOLTAGE SINGLE OR DUAL SUPPLY 2.5V AND 3.3V LVCMOS CLOCK DISTRIBUTION BUFFER FA SUFFIX LQFP PACKAGE CASE 873A-03 Functional Description The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS compatible clock inputs are available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be individually supplied by 2.5V or 3.3V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9446 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting MR/OE will enable the outputs. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible inputs. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package. 604 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9446 CCLK0 CCLK1 CCLK_SEL VCC 25k VCC 25k BANK A 0 1 CLK CLK / 2 0 1 QA0 QA1 QA2 25k 0 1 BANK B QB0 QB1 QB2 QC0 QC1 QC2 QC3 FSELA FSELB FSELC MR/OE BANK C 25k 25k 25k 25k 0 1 Figure 1. MPC9446 Logic Diagram VCCC VCCB VCCB GND GND QB0 QB1 QB2 VCCB is internally connected to VCC 24 VCCA QA2 GND QA1 VCCA QA0 GND MR/OE 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 QC3 GND QC2 VCCC QC1 GND QC0 VCCC MPC9446 13 12 11 10 9 CCLK_SEL CCLK0 CCLK1 VCC FSELA FSELB FSELC Figure 2. Pinout: 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GND 605 MPC9446 Table 1. Pin Configuration Pin CCLK0,1 FSELA, FSELB, FSELC MR/OE GND VCCA, VCCB , VCCC VCC QA0 - QA2 QB0 - QB2 QC0 - QC3 Output Output Output 1 I/O Input Input Input Type LVCMOS LVCMOS LVCMOS Supply Supply Supply LVCMOS LVCMOS LVCMOS LVCMOS clock inputs Output bank divide select input Function Internal reset and output (high impedance) control Negative voltage supply (GND) Positive voltage supply for output banks Positive voltage supply for core (VCC) Bank A outputs Bank B outputs Bank C outputs 1. VCCB is internally connected to VCC. Table 2. Supported Single and Dual Supply Configurations Supply Voltage Configuration 3.3V Mixed Voltage Supply 2.5V 1. 2. 3. 4. VCC1 3.3V 3.3V 2.5V VCCA2 3.3V 3.3V or 2.5V 2.5V VCCB3 3.3V 3.3V 2.5V VCCC4 3.3V 3.3V or 2.5V 2.5V GND 0V 0V 0V VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels. VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels. VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC. VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels. Table 3. Function Table (Controls) Control CCLK_SEL FSELA FSELB FSELC MR/OE Default 0 0 0 0 0 CCLK0 fQA0:2 = fREF fQB0:2 = fREF fQC0:3 = fREF Outputs enabled 0 CCLK1 fQA0:2 = fREF / 2 fQB0:2 = fREF / 2 fQC0:3 = fREF / 2 Internal reset outputs disabled (tristate) 1 Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. 606 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9446 Table 5. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Condition Table 6. DC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V 5%, TA = -40C to +85C) Symbol VIH VIL IIN VOH VOL ZOUT ICCQ 3 Characteristics Input High Voltage Input Low Voltage Input Current1 Output High Voltage Output Low Voltage Output Impedance Maximum Quiescent Supply Current Min 2.0 -0.3 Typ Max VCC + 0.3 0.8 200 Unit V V A V Condition LVCMOS LVCMOS VIN = GND or VIN = VCC IOH = -24 mA2 IOL = 24mA2 IOL = 12mA All VCC Pins 2.4 0.55 0.30 14 - 17 2.0 V V mA 1. Input pull-up / pull-down resistors influence input current. 2. The MPC9446 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 7. AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V 5%, TA = -40C to +85C)1 Symbol fref fMAX tP, REF tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) Input Frequency Maximum Output Frequency Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-Device Skew Output Pulse Skew Output Duty Cycle Output Rise/Fall Time 4 Characteristics /1 output /2 output Min 0 0 0 1.4 Typ Max 2502 2502 125 3 Unit MHz MHz MHz ns Condition FSELx = 0 FSELx = 1 1.0 CCLK0,1 to any Q CCLK0,1 to any Q 2.2 2.2 2.8 2.8 ns ns ns ns ns ps ps ps ns ps % % ns 0.8 to 2.0V 4.45 4.2 10 10 150 200 350 2.25 200 tsk(PP) tSK(P) DCQ tr, tf /1 output /2 output 47 45 0.1 50 50 53 55 1.0 DCREF = 50% DCREF = 25%-75% 0.55 to 2.4V 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 607 MPC9446 Table 8. DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V 5%, TA = -40C to +85C) Symbol VIH VIL VOH VOL ZOUT IIN ICCQ3 Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current2 Maximum Quiescent Supply Current 17 - 20 2 Min 1.7 -0.3 1.8 Typ Max VCC + 0.3 0.7 0.6 200 2.0 Unit V V V V A mA Condition LVCMOS LVCMOS IOH = -15 mA1 IOL = 15 mA VIN = GND or VIN = VCC All VCC Pins 1. The MPC9446 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output. 2. Input pull-up / pull-down resistors influence input current. 3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V 5%, TA = -40C to +85C)1 2 Symbol fref fMAX tP, REF tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) Input Frequency Maximum Output Frequency Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-Device Skew Output Pulse Skew5 Output Duty Cycle Output Rise/Fall Time /1 or /2 output 0.1 45 50 55 1.0 % ns CCLK0,1 to any Q CCLK0,1 to any Q 2.6 2.6 /1 output /2 output Characteristics Min 0 0 0 1.4 1.0 5.6 5.5 10 10 150 200 350 3.0 200 4 Typ Max 2503 2503 125 Unit MHz MHz MHz ns ns ns ns ns ns ps ps ps ns ps Condition FSELx = 0 FSELx = 1 0.7 to 1.7V tsk(PP) tSK(P) DCQ tr, tf 1. 2. 3. 4. DCREF = 50% 0.6 to 1.8V AC characteristics apply for parallel output termination of 50 to VTT. AC specifications are design targets, final specification is pending device characterization. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 5. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. Table 10. AC Characteristics (VCC = 3.3V + 5%, VCCA, VCCB, VCCC = 2.5 V + 5% or 3.3 V + 5%, TA = -40C to +85C)1 2 Symbol tsk(O) Characteristics Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-Device Skew Propagation Delay Output Pulse Skew3 /1 or /2 output CCLK0,1 to any Q 45 Min Typ Max 150 250 350 2.5 250 50 55 % Unit ps ps ps ns ps DCREF = 50% Condition tsk(PP) tPLH,HL tSK(P) DCQ See 3.3V Table Output Duty Cycle 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank. 3. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. 608 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9446 APPLICATIONS INFORMATION Driving Transmission Lines The MPC9446 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9446 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9446 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9446 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA = VS (Z0 / (RS + R0 + Z0)) = 50 || 50 = 36 || 36 = 14 = 3.0 (25 / (18 + 14 + 25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). VL Z0 RS R0 VL 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 VOLTAGE (V) Figure 4. Single versus Dual Waveforms MPC9446 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB1 RS = 36 ZO = 50 OutB0 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9446 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9446. The output waveform in Figure 4 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: MPC9446 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 5. Optimized Dual Line Termination FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 609 MPC9446 MPC9446 DUT PULSE GENERATOR Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 6. CCLK0, 1 MPC9446 AC Test Reference for VCC = 3.3V and VCC = 2.5V VCC CCLK VCC/2 GND Qx tF tR t(LH) t(HL) VCC VCC/2 GND VCC = 3.3V 2.4 0.55 VCC = 2.5V 1.8V 0.6V Figure 7. Output Transition Time Test Reference Figure 8. Propagation Delay (tPD) Test Reference VCC VCC/2 GND VCC VCC/2 GND tSK(LH) tSK(HL) CCLK VCC VCC/2 GND VCC VCC/2 GND t(LH) t(HL) QX The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device tSK(P) = | tPLH - tPHL | Figure 9. Output-to-Output Skew tSK(LH, HL) VCC VCC/2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 10. Output Pulse Skew (tSK(P)) Test Reference TN TN+1 TJIT(CC) = |TN-TN+1| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 11. Output Duty Cycle (DC) Figure 12. Cycle-to-Cycle Jitter 610 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9447 Rev 3, 08/2004 3.3 V/2.5 V 1:9 LVCMOS Clock Fanout Buffer The MPC9447 is a 3.3V or 2.5V compatible, 1:9 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 ps, the device meets the needs of most demanding clock applications. Features * * * * * * * * * * * * * MPC9447 LOW VOLTAGE 3.3 V/2.5 V LVCMOS 1:9 CLOCK FANOUT BUFFER 9 LVCMOS Compatible Clock Outputs 2 Selectable, LVCMOS Compatible Inputs Maximum Clock Frequency of 350 MHz Maximum Clock Skew of 150 ps Synchronous Output Stop in Logic Low State Eliminates Output Runt FA SUFFIX Pulses 32-LEAD LQFP PACKAGE CASE 873A-03 High-Impedance Output Control 3.3V or 2.5V Power Supply Drives up to 18 Series Terminated Clock Lines Ambient Temperature Range -40C to +85C 32-Lead LQFP Packaging 32-lead Pb-free Package Available Supports Clock Distribution in Networking, Telecommunications, and Computer Applications Pin and Function Compatible to MPC947 Functional Description MPC9447 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50 terminated transmission lines on the incident edge: each is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable independent LVCMOS compatible clock inputs are available, providing support of redundant clock source systems. The MPC9447 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of -40C to +85C. The MPC9447 is pin and function compatible but performance-enhanced to the MPC947. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 611 MPC9447 GND GND GND 17 16 15 14 GND Q6 VCC Q7 GND Q8 VCC GND 13 12 11 10 9 1 2 3 4 5 6 7 8 1 CLK1 input selected Outputs enabled Outputs active GND Condition Per output Inputs VCC VCC Q0 CCLK0 CCLK1 VCC 25k CLK_SEL VCC 25k CLK_STOP SYNC Q6 Q7 VCC OE (All input resistors have a value of 25 k) Q8 Q4 Q5 0 1 CLK STOP Q1 Q2 Q3 24 GND Q2 VCC Q1 GND Q0 VCC GND 25 26 27 28 29 30 31 32 23 22 21 20 19 MPC9447 GND CLK_STOP CCLK0 CLK_SEL CCLK1 OE Figure 1. Logic Diagram Table 1. Function Table Control CLK_SEL OE CLK_STOP Default 1 1 1 CLK0 input selected 0 Figure 2. 32-Lead Pinout (Top View) Outputs disabled (high-impedance state)1 Outputs synchronously stopped in logic low state 1. OE = 0 will high-impedance tristate all outputs independent on CLK_STOP Table 2. Pin Configurations Pin CCLK0 CCLK1 CLK_SEL CLK_STOP OE Q0-8 GND VCC I/O Input Input Input Input Input Output Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC Clock Signal Input Alternative Clock Signal Input Clock Input Select Clock Output Enable/Disable Output Enable/Disable (high-impedance tristate) Clock Outputs Negative Power Supply (GND) Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function Table 3. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-up Immunity Power Dissipation Capacitance Input Capacitance Min 200 2000 200 10 4.0 Typ VCC / 2 Max Unit V V V mA pF pF 612 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA VCC VCC 18 Q3 Q4 Q5 MPC9447 Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 3.3V 5%, TA = -40C to +85C) Symbol VIH VIL VOH VOL ZOUT IIN ICCQ Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current2 Current3 17 300 2.0 Min 2.0 -0.3 2.4 0.55 0.30 Typ Max VCC + 0.3 0.8 Unit V V V V V A mA VIN = VCC or GND All VCC Pins Condition LVCMOS LVCMOS IOH = -24 mA1 IOL = 24 mA IOL = 12 mA Maximum Quiescent Supply 1. The MPC9447 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC = 3.3V). 2. Inputs have pull-down or pull-up resistors affecting the input current. 3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 6. AC Characteristics (VCC = 3.3V 5%, TA = -40C to +85C)1 Symbol fref fmax fP,REF tr, tf tPLH/HL tPLZ, HZ tPZL, ZH tS tH tsk(O) tsk(PP) tSK(P) DCQ tr, tf tJIT(CC) Input Frequency Output Frequency Reference Input Pulse Width CCLK0, CCLK1 Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Setup Time Hold Time Output-to-Output Skew Device-to-Device Skew Output Pulse Skew Output Duty Cycle Cycle-to-cycle jitter 4 Characteristics Min 0 0 1.4 Typ Max 350 350 2 Unit MHz MHz ns ns ns ns ns ns ns Condition 1.0 1.3 0.8 to 2.0 V CCLK0 or CCLK1 to any Q 3.3 11 11 CCLK0 or CCLK1 to CLK_STOP CCLK0 or CCLK1 to CLK_STOP 3 3 0.0 1.0 150 2.0 300 55 1.0 TBD ps ns ps % ns ps DCREF = 50% 0.55 to 2.4 V fQ<170 MHz RMS (1 ) 45 0.1 50 Output Rise/Fall Time 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 3. Setup and hold times are referenced to the falling edge of the selected clock signal input. 4. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 613 MPC9447 Table 7. DC Characteristics (VCC = 2.5V 5%, TA = -40C to +85C) Symbol VIH VIL VOH VOL ZOUT IIN ICCQ Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current2 19 300 2.0 Min 1.7 -0.3 1.8 0.6 Typ Max VCC + 0.3 0.7 Unit V V V V A mA VIN = VCC or GND All VCC Pins Condition LVCMOS LVCMOS IOH = -15 mA1 IOL = 15 mA Maximum Quiescent Supply Current3 1. The MPC9447 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50 series terminated transmission lines per output (VCC = 2.5V). 2. Inputs have pull-down or pull-up resistors affecting the input current. 3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 8. AC Characteristics (VCC = 2.5V 5%, TA = -40C to +85C)1 Symbol fref fmax fP,REF tr, tf tPLH/HL tPLZ, HZ tPZL, ZH tS tH tsk(O) tsk(PP) tSK(P) DCQ tr, tf tJIT(CC) Input Frequency Output Frequency Reference Input Pulse Width CCLK0, CCLK1 Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Setup Time Hold Time Output-to-Output Skew Device-to-Device Skew Ouput Pulse Skew4 Output Duty Cycle Output Rise/Fall Time Cycle-to-Cycle jitter RMS (1 ) 50 fQ<350 MHz 45 0.1 TBD CCLK0 or CCLK1 to CLK_STOP3 0.0 1.0 150 2.7 200 55 1.0 CCLK0 or CCLK1 to any Q 1.7 Characteristics Min 0 0 1.4 1.02 4.4 11 11 Typ Max 350 350 Unit MHz MHz ns ns ns ns ns ns ns ps ns ps % ns ps DCREF = 50% 0.6 to 1.8V 0.7 to 1.7V Condition CCLK0 or CCLK1 to CLK_STOP3 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 3. Setup and hold times are referenced to the falling edge of the selected clock signal input. 4. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL | Figure 1. Figure 2. 614 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9447 APPLICATION INFORMATION CCLK0 or CCLK1 CLK_STOP Q0 to Q8 clock driver is effectively doubled due to its capability to drive multiple lines at VCC = 3.3V. 3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386 Driving Transmission Lines The MPC9447 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of 17 (VCC=3.3V), the outputs can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Motorola application note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. MPC9447 OUTPUT BUFFER IN 17 RS = 33 ZO = 50 OutA VOLTAGE (V) Figure 3. Output Clock Stop (CLK_STOP) Timing Diagram Figure 5. Single versus Dual Line Termination Waveforms The waveform plots in Figure 5. Single versus Dual Line Termination Waveforms show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the MPC9447 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9447. The output waveform in Figure 5. Single versus Dual Line Termination Waveforms shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 33 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 33 || 33 R0 = 17 VL = 3.0 (25 / (16.5+17+25) = 1.28V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). MPC9447 OUTPUT BUFFER IN 17 RS = 33 ZO = 50 OutB0 ZO = 50 OutB1 RS = 33 Figure 4. Single versus Dual Transmission Lines This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9447 clock driver. For the series terminated case, however, there is no DC current draw; thus, the outputs can drive multiple series terminated lines. Figure 4. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9447 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 615 MPC9447 Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 6. Optimized Dual Line Termination should be used. In this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9447 OUTPUT BUFFER 17 RS = 16 ZO = 50 RS = 16 ZO = 50 17 + 16 || 16 = 50 || 50 25 = 25 Figure 6. Optimized Dual Line Termination The Following Figures Illustrate the Measurement Reference for the MPC9447 Clock Driver Circuit MPC9447 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 7. CCLK MPC9447 AC Test Reference for VCC = 3.3V and VCC = 2.5V 616 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9447 CCLK VCC VCC/2 GND QX tP(LH) tP(HL) VCC VCC/2 GND Figure 8. Propagation Delay (tPD) Test Reference VCC VCC/2 GND VCC VCC/2 GND tSK(LH) tSK(HL) CCLK VCC VCC/2 GND VCC VCC/2 GND tP(LH) tP(HL) QX The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device tSK(P) = | tPLH - tPHL | Figure 9. Output-to-Output Skew tSK(LH, HL) Figure 10. Output Pulse Skew (tSK(P)) Test Reference VCC VCC2 GND tP T0 DC = (tP ? T0 x 100%) The time from the output controlled edge to the non-controlled edge, divided by the time between output controlled edges, expressed as a percentage tF tR VCC=3.3V 2.4 0.55 VCC=2.5V 1.8V 0.6V Figure 11. Output Duty Cycle (DC) Figure 12. Output Transition Time Test Reference VCC CCLK PCLK TN TN+1 TJIT(CC) = |TN-TN+1| CLK_STOP tS tH VCC/2 GND VCC VCC/2 GND The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 13. Cycle-to-Cycle Jitter Figure 14. Setup and Hold Time (tS, tH) Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 617 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9448 Rev 4, 08/2004 3.3 V/2.5 V LVCMOS 1:12 Clock Fanout Buffer he MPC9448 is a 3.3V or 2.5V compatible, 1:12 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 ps, the device meets the needs of most demanding clock applications. Features * * * * * * * * * * * * * MPC9448 LOW VOLTAGE 3.3 V/2.5 V LVCMOS 1:12 CLOCK FANOUT BUFFER 12 LVCMOS compatible clock outputs Selectable LVCMOS and differential LVPECL compatible clock inputs Maximum clock frequency of 350 MHz Maximum clock skew of 150 ps FA SUFFIX Synchronous output stop in logic low state eliminates output runt pulses 32-LEAD LQFP PACKAGE High-impedance output control CASE 873A-03 3.3V or 2.5V power supply Drives up to 24 series terminated clock lines Ambient temperature range -40C to +85C 32-Lead LQFP packaging 32-lead Pb-free package available Supports clock distribution in networking, telecommunication and computing applications Pin and function compatible to MPC948 Functional Description The MPC9448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50 terminated transmission lines on the incident edge: each output is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock distribution systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of -40C to +85C. The MPC9448 is pin and function compatible but performance-enhanced to the MPC948. 618 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9448 GND GND VCC VCC VCC PCLK PCLK CCLK Q0 Q4 Q5 Q6 Q1 0 1 CLK STOP Q2 Q3 VCC Q4 Q5 VCC Q6 SYNC Q7 Q8 Q9 Q3 VCC Q2 GND Q1 VCC Q0 GND 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 Q7 17 16 15 14 GND Q8 VCC Q9 GND Q10 VCC GND CLK_SEL MPC9448 13 12 11 10 9 CLK_STOP 1 2 3 4 5 6 7 8 CCLK PCLK PCLK CLK_STOP CLK_SEL VCC OE (All input resistors have a value of 25 k) Q11 Figure 1. Logic Diagram Table 1. Function Table Control CLK_SEL OE CLK_STOP Default 1 1 1 0 PECL differential input selected Outputs disabled (high-impedance Figure 2. 32-Lead Pinout (Top View) 1 CCLK input selected state)1 Outputs enabled Outputs active Outputs synchronously stopped in logic low state 1. OE = 0 will high-impedance tristate all outputs independent on CLK_STOP Table 2. Pin Configurations Pin PCLK, PCLK CCLK CLK_SEL CLK_STOP OE Q0-11 GND VCC Input Input Input Input Input Output Supply Supply I/O Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC Clock signal input Alternative clock signal input Clock input select Clock output enable/disable Output enable/disable (high-impedance tristate) Clock outputs Negative power supply (GND) Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GND OE VCC Q10 619 MPC9448 Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TStor Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 5. DC Characteristics (VCC = 3.3V 5%, TA = -40C to +85C) Symbol VIH VIL VPP VCMR1 IIN VOH VOL ZOUT ICCQ4 Characteristics Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Input Current2 Output HIGH Voltage Output LOW Voltage 2.4 0.55 0.30 17 2.0 PCLK PCLK Min 2.0 -0.3 250 1.1 VCC - 0.6 300 Typ Max VCC + 0.3 0.8 Unit V V mV V A V V V mA All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL VIN = VCC or GND IOH = -24mA3 IOL = 24mA3 IOL = 12mA Output Impedance Maximum Quiescent Supply Current 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. Input pull-up / pull-down resistors influence input current. 3. The MPC9448 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC = 3.3V) or one 50 series terminated transmission line (for VCC=2.5V). 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. 620 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9448 Table 6. AC Characteristics (VCC = 3.3V 5%, TA = -40C to +85C)1 Symbol fref fMAX VPP VCMR tr, tf tPLH/HL tPLH/HL tPLZ, HZ tPZL, LZ tS tH tsk(O) tsk(PP) tSK(P) Output Disable Time Output Enable Time Setup Time Hold Time Output-to-Output Skew Device-to-Device Skew Output Pulse skew4 PCLK or CCLK to any Q Using CCLK Using PCLK fQ<170 MHz 45 0.1 50 CCLK to CLK_STOP PCLK to CLK_STOP CCLK to CLK_STOP PCLK to CLK_STOP 0.0 0.0 1.0 1.5 150 2.0 300 400 55 1.0 2 Characteristics Input Frequency Maximum Output Frequency Peak-to-Peak Input Voltage Common Mode Range Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation Delay PCLK to any Q CCLK to any Q PCLK PCLK Min 0 0 400 1.3 1.4 Typ Max 350 350 1000 VCC - 0.8 Unit MHz MHz mV V ns Condition LVPECL LVPECL tP, REF 1.03 1.6 1.3 3.6 3.3 11 11 ns ns ns ns ns ns ns ns ns ps ns ps ps % ns 0.8 to 2.0V DCQ tr, tf Output Duty Cycle Output Rise/Fall Time DCREF = 50% 0.55 to 2.4V 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP). 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. Table 7. DC Characteristics (VCC = 2.5V 5%, TA = -40C to +85C) Symbol VIH VIL VPP VCMR IIN VOH VOL ZOUT ICCQ4 1 Characteristics Input high voltage Input low voltage Peak-to-peak input voltage Common Mode Range Input current2 Output High Voltage Output Low Voltage Output impedance Maximum Quiescent Supply Current PCLK PCLK Min 1.7 -0.3 250 1.0 Typ Max VCC + 0.3 0.7 Unit V V mV Condition LVCMOS LVCMOS LVPECL LVPECL VIN = GND or VIN = VCC IOH = -15 mA3 IOL= 15 mA3 All VCC Pins VCC - 0.7 300 V A V 1.8 0.6 19 2.0 V mA 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. Input pull-up / pull-down resistors influence input current. 3. The MPC9448 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50 series terminated transmission lines at VCC = 2.5V. 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 621 MPC9448 Table 8. AC Characteristics (VCC = 2.5V 5%, TA = -40C to +85C)1 Symbol fref fMAX VPP VCMR2 tP, REF tr, tf tPLH/HL tPLH/HL tPLZ, HZ tPZL, LZ tS tH tsk(O) tsk(PP) tSK(p) DCQ Output Disable Time Output Enable Time Setup time Hold time Output-to-output Skew Device-to-device Skew Output pulse skew4 PCLK or CCLK to any Q Using CCLK Using PCLK fQ< 350 MHz and using CCLK fQ<200 MHz and using PCLK 45 45 0.1 50 50 CCLK to CLK_STOP PCLK to CLK_STOP CCLK to CLK_STOP PCLK to CLK_STOP 0.0 0.0 1.0 1.5 150 2.7 200 300 55 55 1.0 Input Frequency Maximum Output Frequency Peak-to-peak input voltage Common Mode Range Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation delay PCLK to any Q CCLK to any Q 1.5 1.7 PCLK PCLK Characteristics Min 0 0 400 1.2 1.4 1.03 4.2 4.4 11 11 Typ Max 350 350 1000 VCC - 0.8 Unit MHz MHz mV V ns ns ns ns ns ns ns ns ns ns ps ns ps ps DCREF = 50% % % ns 0.6 to 1.8V 0.8 to 2.0V LVPECL LVPECL Condition Output Duty Cycle Output Rise/Fall Time tr, tf 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP). 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. 622 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9448 APPLICATION INFORMATION CCLK or PCLK CLK_STOP Q0 to Q11 clock driver is effectively doubled due to its capability to drive multiple lines at VCC = 3.3V. 3.0 2.5 OutA tD = 3.8956 OutB tD = 3.9386 Figure 3. 32-Lead Pinout (Top View) Driving Transmission Lines The MPC9448 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of 17 (VCC=3.3V), the outputs can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Motorola application note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. MPC9448 OUTPUT BUFFER IN 17 RS = 33 ZO = 50 OutA VOLTAGE (V) 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (ns) 10 12 14 Figure 5. Single versus Dual Line Termination Waveforms The waveform plots in Figure 5. Single versus Dual Line Termination Waveforms show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the MPC9448 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9448. The output waveform in Figure 5. Single versus Dual Line Termination Waveforms shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 33 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 33 || 33 R0 = 17 VL = 3.0 (25 / (16.5+17+25) = 1.28V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). MPC9448 OUTPUT BUFFER IN 17 RS = 33 ZO = 50 OutB0 ZO = 50 OutB1 RS = 33 Figure 4. Single versus Dual Transmission Lines This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9448 clock driver. For the series terminated case, however, there is no DC current draw; thus, the outputs can drive multiple series terminated lines. Figure 4. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9448 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 623 MPC9448 Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 6. Optimized Dual Line Termination should be used. In this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9448 OUTPUT BUFFER 17 RS = 16 ZO = 50 Table 9. Die Junction Temperature and MTFB Junction Temperature (C) 100 110 120 130 MTBF (Years) 20.4 9.1 4.2 2.0 RS = 16 ZO = 50 17 + 16 || 16 = 50 || 50 25 = 25 Figure 6. Optimized Dual Line Termination Power Consumption of the MPC9448 and Thermal Management The MPC9448 AC specification is guaranteed for the entire operating frequency range up to 350 MHz. The MPC9448 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC9448 die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability please refer to the application note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature: Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC9448 needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC9448 is represented in equation 1. Where ICCQ is the static current consumption of the MPC9448, CPD is the power dissipation capacitance per output, ()CL represents the external capacitive output load, N is the number of active outputs (N is always 12 in case of the MPC9448). The MPC9448 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 9. Die Junction Temperature and MTFB, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC9448 in a series terminated transmission line system, equation 4. Equation 1 Equation 2 Equation 3 PTOT = [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] * VCC M PTOT = VCC * [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] + [ DCQ * IOH * (VCC - VOH) + (1 - DCQ) * IOL * VOL ] M P TJ = TA + PTOT * Rthja fCLOCK,MAX = 1 * CPD * N * V2CC [T j,MAX - TA Rthja - (ICCQ * VCC) ] Equation 4 624 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9448 TJ,MAX should be selected according to the MTBF system requirements and Table 9. Die Junction Temperature and MTFB. Rthja can be derived from Table 10. Thermal Package Impedance of the 32ld LQFP. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. Table 10. Thermal Package Impedance of the 32ld LQFP Convection, LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm Rthja (1P2S board), C/W 86 76 71 68 66 60 Rthja (2P2S board), C/W 61 56 54 53 52 49 If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the MPC9448. The charts were calculated for a maximum tolerable die junction temperature of 110C (120C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. Figure 7. Maximum MPC9448 Frequency, VCC = 3.3V, MTBF 9.1 Years, Driving Series Terminated transmission lines, 2s2p board Figure 8. Maximum MPC9448 frequency, VCC = 3.3V, MTBF 9.1 Years, 4 pF Load per Line, 2s2p Board Figure 9. No maximum Frequency Limitation for VCC = 3.3V, MTBF 4 Years, Driving Series Terminated Transmission Lines, 2s2p Board Figure 10. Maximum MPC9448 Frequency, VCC = 3.3V, MTBF 4 Years, 4 pF Load per Line, 2s2p Board FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 625 MPC9448 The Following Figures Illustrate the Measurement Reference for the MPC9448 Clock Driver Circuit MPC9448 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT RT = 50 VTT Figure 11. CCLK MPC9448 AC Test Reference for Vcc = 3.3V and Vcc = 2.5V Differential Pulse Generator Z = 50 ZO = 50 MPC9448 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 12. PCLK MPC9448 AC Test Reference 626 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9448 PCLK PCLK VPP VCMR VCC QX GND tP(LH) tP(HL) tP(LH) tP(HL) QX VCC VCC/2 GND VCC VCC/2 GND CCLK Figure 13. Propagation Delay (tPD) Test Reference Figure 14. Propagation Delay (tPD) Test Reference VCC VCC/2 GND VCC VCC/2 GND tSK(LH) tSK(HL) CCLK VCC VCC/2 GND VCC VCC/2 GND tP(LH) tP(HL) QX The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device tSK(P) = | tPLH - tPHL | Figure 15. Output-to-Output Skew tSK(LH, HL) Figure 16. Output Pulse Skew (tSK(P)) Test Reference VCC VCC/2 GND tP T0 DC = (tP ? T0 x 100%) The time from the output controlled edge to the non-controlled edge, divided by the time between output controlled edges, expressed as a percentage tF tR VCC=3.3V 2.4 0.55 VCC=2.5V 1.8V 0.6V Figure 17. Output Duty Cycle (DC) Figure 18. Output Transition Time Test Reference VCC CCLK PCLK TN TN+1 TJIT(CC) = |TN-TN+1| CLK_STOP tS tH VCC/2 GND VCC VCC/2 GND The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 19. Cycle-to-Cycle Jitter Figure 20. Setup and Hold Time (tS, tH) Test Reference FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 627 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9449 Rev 2, 08/2004 3.3 V/2.5 V 1:15 PECL/LVCMOS Clock Fanout Buffer The MPC9449 is a 3.3 V or 2.5 V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * MPC9449 3.5 V/2.5 V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER 15 LVCMOS compatible clock outputs Two selectable LVCMOS and one differential LVPECL compatible clock inputs Selectable output frequency divider (divide-by-one and divide-by-two) Maximum clock frequency of 200 MHz FA SUFFIX Maximum clock skew of 200 ps 52-LEAD LQFP PACKAGE CASE 848D-03 High-impedance output control 3.3 V or 2.5 V power supply Drives up to 30 series terminated clock lines Ambient temperature range -40C to +85C 52-lead LQFP packaging 52-lead Pb-free package available Supports clock distribution in networking, telecommunication and computing applications Pin and function compatible to MPC949 Functional Description The MPC9449 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 200 MHz. The device has 15 identical outputs, organized in four output banks. Each output bank provides a retimed or frequency divided copy of the input signal with a near zero skew. The output buffer supports driving of 50 terminated transmission lines on the incident edge: each output is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5 V or 3.3 V power supply and an ambient temperature range of -40C to +85C. The MPC9449 is pin and function compatible but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package. 628 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9449 DSELA VCC CCLK0 CCLK1 CCLK_SEL VCC PCLK PCLK 0 1 0 1 /1 /2 0 1 0 1 QA0 QA1 QB0 QB1 QB2 QC0 0 1 QC1 QC2 QC3 DSELB DSELC 0 1 DSELD QD2 QD3 QD4 QD5 MR/OE QD0 QD1 PCLK_SEL Figure 1. MPC9449 Logic Diagram NC GND QC0 VCC QC1 GND QC2 VCC QC3 GND GND QD5 NC NC VCC QB2 GND QB1 VCC QB0 GND GND QA1 VCC QA0 GND 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 20 46 MPC9449 19 47 18 48 17 49 16 50 15 51 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 MR/OE CCLK_SEL VCC CCLK0 CCLK1 PCLK PCLK PCLK_SEL DSELA DSELB DSELC DSELD GND NC VCC QD4 GND QD3 VCC QD2 GND QD1 VCC QD0 GND NC Figure 2. PC9449 52-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 629 MPC9449 Table 1. Function Table Control PCLK_SEL CCLK_SEL DSELA, DSELB, DSELC, DSELD MR/OE Default 0 0 00 00 1 0 LVCMOS clock input selected (CCLK0 or CCLK1) CCLK0 selected /1 Outputs enabled 1 PCLK differential input selected CCLK1 selected /2 Outputs disabled (high impedance) Table 2. Pin Configuration Pin PCLK, PCLK CCLK0, CCLK1 PCLK_SEL CCLK_SEL DSELA, DSELB, DSELC, DSELD MR/OE QA0-1, QB0-2, QC0-3, QD0-5 GND VCC I/O Input Input Input Input Input Input Output Supply Supply Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC Differential LVPECL clock input LVCMOS clock inputs LVPECL clock input select LVCMOS clock input select Clock divider selection Output enable/disable (high-impedance tristate) Clock outputs Negative power supply (GND) Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function Table 3. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 12 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.8 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 630 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9449 Table 5. DC Characteristics (VCC = 3.3 V 5%, TA = -40C to 85C) Symbol VIH VIL VOH VPP VCMR2 VOL ZOUT IIN ICCQ Characteristics Input High Voltage Input Low Voltage Output High Voltage Peak-to-Peak Input Voltage Common Mode Range Output Low Voltage Output Impedance Input Current Maximum Quiescent Supply Current PCLK, PCLK PCLK, PCLK 2.4 250 1.0 VCC -0.6 0.55 0.30 14 - 17 200 10 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V mV V V V A mA VIN = VCC or GND All VCC Pins Condition LVCMOS LVCMOS IOH = -24 mA1 LVPECL LVPECL IOL = 24 mA IOL = 12 mA 1. The MPC9449 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = -40C to 85C)1 Symbol VPP VCMR2 fmax fref tP, REF tr, tf tsk(O) Characteristics Peak-to-Peak Input Voltage Common Mode Range Output Frequency Input Frequency Reference Input Pulse Width CCLK0, CCLK1 Input Rise/Fall Time Output-to-Output Skew Qa outputs Qb outputs Qc outputs Qd outputs All outputs All outputs 2.5 250 CCLK0 or CCLK1 to any Q PCLK to any Q OE to any Q OE to any Q 0.1 RMS (1 ) TBD 1.0 1.0 3.0 3.0 5.0 5.0 11 11 1.0 PCLK, PCLK PCLK, PCLK Min 400 1.0 0 0 1.5 1.0 50 50 50 100 200 300 Typ Max 1000 VCC -0.6 200 200 Unit mV V MHz MHz ns ns ps ps ps ps ps ps ns ps ns ns ns ns ns ps 0.55 to 2.4 V DCREF = 50% 0.8 to 2.0 V Condition LVPECL LVPECL Same Frequency Different Frequencies tsk(PP) tsk(P) tPLH, HL tPLZ, HZ tPZL, LZ tr, tf tJIT(CC) Device-to-Device Skew Output Pulse Skew Propagation Delay Output Disable Time Output Enable Time Output Rise/Fall Time3 Cycle-to-Cycle Jitter 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts propagation delay. 3. An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 631 MPC9449 Table 7. DC Characteristics (VCC = 2.5 V 5%, TA = -40C to 85C) Symbol VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICC Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage Output Impedance Input Current3 Maximum Quiescent Supply Current 17-20 200 10 PCLK, PCLK PCLK, PCLK Characteristics Min 1.7 -0.3 250 1.0 1.8 0.6 VCC -0.6 Typ Max VCC + 0.3 0.7 Unit V V mV V V V A mA VIN = VCC or GND All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -15 mA2 IOL = 15 mA 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9449 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. 3. Inputs have pull-down or pull-up resistors affecting the input current. Table 8. AC Characteristics (VCC = 2.5 V 5%, TA = -40C to 85C)1 Symbol VPP VCMR2 fmax fref tP, REF tr, tf tsk(O) Characteristics Peak-to-Peak Input Voltage Common Mode Range Output Frequency Input Frequency Reference Input Pulse Width CCLK Input Rise/Fall Time Output-to-Output Skew Qa outputs Qb outputs Qc outputs Qd outputs All outputs All outputs 5.0 350 CCLK0 or CCLK1 to any Q PCLK to any Q OE to any Q OE to any Q 0.1 RMS (1 ) TBD 1.0 1.0 3.5 3.5 7.0 7.0 11 11 1.0 PCLK, PCLK PCLK, PCLK Min 400 1.2 0 0 1.5 1.0 50 50 50 100 200 300 Typ Max 1000 VCC-0.6 200 200 Unit mV V MHz MHz ns ns ps ps ps ps ps ps ns ps ns ns ns ns ns ps 0.6 to 1.8 V DCREF = 50% 0.7 to 1.7 V Condition LVPECL LVPECL Same Frequency Different Frequencies tsk(PP) tSK(P) tPLH, HL tPLZ, HZ tPZL, LZ tr, tf tJIT(CC) Device-to-Device Skew Output Pulse Skew Propagation Delay Output Disable Time Output Enable Time Output Rise/Fall Time3 Cycle-to-Cycle Jitter 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts propagation delay. 3. An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition. 632 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9449 APPLICATIONS INFORMATION Driving Transmission Lines The MPC9449 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9449 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9449 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9449 OUTPUT BUFFER IN 14 VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18 + 17 + 25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 1. Final skew data pending specification. 3.0 2.5 2.0 In 1.5 1.0 0.5 OutA tD = 3.8956 OutB tD = 3.9386 RS = 36 ZO = 50 OutA VOLTAGE (V) 0 2 4 6 8 TIME (nS) 10 12 14 MPC9449 OUTPUT BUFFER IN 14 Figure 4. Single versus Dual Waveforms RS = 36 ZO = 50 OutB0 RS = 36 ZO = 50 OutB1 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9449 OUTPUT BUFFER 14 Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9449 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9449. The output waveform in Figure 4 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 5. Optimized Dual Line Termination FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 633 MPC9449 ZO = 50 Pulse Generator Z = 50 MPC9449 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 6. CCLK MPC9449 AC Test Reference for Vcc = 3.3V and Vcc = 2.5V Differential Pulse Generator Z = 50 ZO = 50 MPC9449 DUT ZO = 50 RT = 50 VTT RT = 50 VTT Figure 7. PCLK MPC9449 AC Test Reference 634 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9449 VCC VCC /2 GND VCC VCC /2 GND tSK(O) VCC CCLK VPP VCC /2 GND VCC VCC /2 GND t(LH) t(HL) QX The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 8. Output-to-Output Skew tSK(O) Figure 9. Propagation Delay (tPD) Test Reference VCC PCLK PCLK VPP CCLK VCMR VCC VCC /2 GND t(LH) t(HL) VCC /2 GND VCC VCC /2 GND t(LH) t(HL) t(HL) QX QX tSK(P) = tPLH-tPLH Figure 10. Propagation Delay (tPD) Test Reference Figure 11. Propagation Delay tSK(P) Test Reference VCC=3.3 V VCC=2.5 V 2.4 0.55 tF tR 1.8 V 0.6 V TN TN+1 TJIT(CC) = |TN -TN+1| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 12. Output Transition Time Test Reference Figure 13. Cycle-to-Cycle Jitter FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 635 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC94551 Rev 2, 06/2004 Product Preview Low Voltage 1:4 CMOS Clock Buffer The MPC94551 is a CMOS 1:4 fanout buffer. The MPC94551 is ideal for applications requiring lower voltage. Features * * * * * * * * 1:4 CMOS fanout buffer 250 ps output to output skew I/O frequency up to 160 MHz operation Non-inverting output clock 3.3 V supply voltage Output Enable mode tri-states outputs -40C to 85C industrial temperature range Standard 8-lead SOIC package MPC94551 1:4 LVCMOS CLOCK BUFFER D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 Q1 ORDERING INFORMATION Device Package SO-8 SO-8 MPC94551D MPC94551DR2 Q2 ICLK Q3 Q4 OE ICLK 1 2 3 4 8 7 6 5 OE VDD GND Q4 Q1 Q2 Q3 Figure 1. Logic Diagram Figure 2. Pin Assignment This document contains certain information on a new product. Specifications and information herein are subject to change without notice. 636 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC94551 Table 1. Pin Description Pin Number 1 2 3 4 5 6 7 8 Pin Name ICLK Q1 Q2 Q3 Q4 GND VDD OE Pin Type Input Output Output Output Output Power Power Input Clock input, internal pull-up resistor Clock output 1 Clock output 1 Clock output 1 Clock output 1 Connect to ground 2 Connect to 3.3 V 2 Output enable, tri-states outputs when low, internal pull-up resistor Pin Description 1. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. 2. A decoupling capacitor of 0.01 F should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. Table 2. Absolute Maximum Ratings1 Parameter Power Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature Rating 3.9 -0.5 to VDD +0.5 -40 to +85 -65 to +150 175 260 Unit V V C C C C 1. Stresses above the ratings listed below can cause permanent damage to the device. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Table 3. Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min -40 +3.135 Typ Max +85 +3.465 Unit C V FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 637 MPC94551 Table 4. DC Characteristics (VDD = 3.3 V 5%; Ambient Temperature = -40C to 85C) Parameter Operating Voltage Input High Voltage1, ICLK Input Low Voltage1, ICLK Input High Voltage, OE Input Low Voltage, OE Output High Voltage Ouput Low Voltage Output High Voltage (CMOS Level) Operating Supply Current Nominal Output Impedance Internal Pull-up Resistor Input Capacitance Symbol VDD VIH VIL VIH VIL VOH VOL VOH IDD ZO RPU CIN CIN Short Circuit Current 1. Nominal switching threshold is VDD/2. IOS ICLK OE pin ICLK IOH = -25 mA IOL = 25 mA IOH = -12 mA No load, 135 MHz VDD - 0.4 18 20 30 5 TBD 50 2.4 0.4 2 Conditions Min 3.15 VDD/2 + 0.7 Typ Max 3.45 3.8 VDD/2 - 0.7 VDD 0.8 Unit V V V V V V V V mA W k pF pF mA Table 5. AC Characteristics (VDD = 3.3 V 5%; Ambient Temperature = -40C to 85C) Parameter Input Frequency Output Frequency1 Output Clock Rise Time Output Clock Fall Time Propagation Delay 2 Symbol Condition Min 0 Typ Max 160 160 1.5 1.5 Unit MHz MHz ns ns ns ps 15 pF load tOR tOF 0.8 V to 2.0 V 2.0 V to 0.8 V 135 MHz Rising edges at VDD/2 2 4 8 250 Output to Output Skew3 1. Measured with an external series resistor of 33 positioned close to each output pin 2. Measured with rail to rail input clock 3. Measured between any 2 outputs with equal loading 638 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MPC9456 Rev 2, 08/2004 2.5 V and 3.3 V LVCMOS Clock Fanout Buffer The MPC9456 is a 2.5 V and 3.3 V compatible 1:10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for mixed-voltage applications. The MPC9456 offers 10 low-skew outputs and a differential LVPECL clock input. The outputs are configurable and support 1:1 and 1:2 output to input frequency ratios. The MPC9456 is specified for the extended temperature range of -40 to 85C. Features * * * * * * * * * * * Configurable 10 outputs LVCMOS clock distribution buffer Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply Wide range output clock frequency up to 250 MHz Designed for mid-range to high-performance telecom, networking and computer applications Supports high-performance differential clocking applications Maximum output skew of 200 ps (150 ps within one bank) Selectable output configurations per output bank Tristable outputs 32-lead LQFP package Ambient operating temperature range of -40 to 85C 32-lead Pb-free package available MPC9456 LOW VOLTAGE SINGLE OR DUAL SUPPLY 2.5 V AND 3.3 V LVCMOS CLOCK DISTRIBUTION BUFFER FA SUFFIX LQFP PACKAGE CASE 873A-03 Functional Description The MPC9456 is a full static design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Each of the three output banks can be individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9456 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting MR/OE will enable the outputs. All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. The clock input is low voltage PECL compatible for differential clock distribution support. Please consult the MPC9446 specification for a full CMOS compatible device. For series terminated transmission lines, each of the MPC9456 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 639 MPC9456 Bank A PCLK PCLK 25k VCC/2 Bank B 0 1 CLK 0 1 QA0 QA1 QA2 25k CLK / 2 QB0 QB1 QB2 QC0 FSELA 25k FSELB FSELC MR/OE 25k 25k 25k Bank C 0 1 QC1 QC2 QC3 Figure 1. MPC9456 Logic Diagram VCCC VCCB VCCB GND GND QB0 QB1 QB2 VCCB is internally connected to VCC 24 VCCA QA2 GND QA1 VCCA QA0 GND MR/OE 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 MPC9456 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 QC3 GND QC2 VCCC QC1 GND QC0 VCCC FSELC PECL_CLK PECL_CLK FSELA Figure 2. Pinout: 32-Lead Package Pinout (Top View) 640 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA FSELB GND NC VCC MPC9456 Table 1. Pin Configuration Pin PECL_CLK, PECL_CLK FSELA, FSELB, FSELC MR/OE GND VCCA, VCCB , VCCC VCC QA0 - QA2 QB0 - QB2 QC0 - QC3 Output Output Output 1 I/O Input Input Input Type LVPECL LVCMOS LVCMOS Supply Supply Supply LVCMOS LVCMOS LVCMOS Differential clock reference Low voltage positive ECL input Output bank divide select input Function Internal reset and output tristate control Negative voltage supply output bank (GND) Positive voltage supply for output banks Positive voltage supply core (VCC) Bank A outputs Bank B outputs Bank C outputs 1. VCCB is internally connected to VCC. Table 2. Supported Single and Dual Supply Configurations Supply Voltage Configuration 3.3V Mixed Voltage Supply 2.5V 1. 2. 3. 4. VCC1 3.3V 3.3V 2.5V VCCA2 3.3V 3.3V or 2.5V 2.5V VCCB3 3.3V 3.3V 2.5V VCCC4 3.3V 3.3V or 2.5V 2.5V GND 0V 0V 0V VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels. VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels. VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC. VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels. Table 3. Function Table (Controls) Control FSELA FSELB FSELC MR/OE Default 0 0 0 0 fQA0:2 = fREF fQB0:2 = fREF fQC0:3 = fREF Outputs enabled 0 fQA0:2 = fREF / 2 fQB0:2 = fREF / 2 fQC0:3 = fREF / 2 Internal reset Outputs disabled (tristate) 1 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 641 MPC9456 Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -40 Characteristics Min -0.3 -0.3 -0.3 Max 4.6 VCC +0.3 VCC +0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 5. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Condition Table 6. DC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V 5%, TA = -40 to + 85C) Symbol VIH VIL VPP VCMR1 IIN VOH VOL ZOUT ICCQ4 Characteristics Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range Input Current2 Output High Voltage Output Low Voltage 2.4 0.55 0.30 14-17 2.0 PCLK PCLK Min 2.0 -0.3 250 1.1 VCC -0.6 200 Typ Max VCC +0.3 0.8 Unit V V mV V A V V V mA All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL VIN = GND or VIN = VCC IOH = -24 mA3 IOL= 24mA2 IOL= 12mA Output Impedance Maximum Quiescent Supply Current 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. Input pull-up / pull-down resistors influence input current. 3. The MPC9456 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. 642 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9456 Table 7. AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V 5%, TA = -40 to + 85C)1 Symbol fref fMAX VPP VCMR tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) 3 Characteristics Input Frequency Maximum Output Frequency Peak-to-Peak Input Voltage Common Mode Range Reference Input Pulse Width PCLK Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-Device Skew Output Pulse Skew Output Duty Cycle Output Rise/Fall Time 5 Min 0 /1 output /2 output PCLK PCLK 0 0 500 1.3 1.4 Typ Max 250 2 2 Unit MHz MHz MHz mV V ns Condition FSELx = 0 FSELx = 1 LVPECL LVPECL 250 125 1000 VCC -0.8 tP, REF 1.0 CCLK to any Q CCLK to any Q 2.2 2.2 2.8 2.8 4 ns ns ns ns ns ps ps ps ns ps % % ns 0.8 to 2.0V 4.45 4.2 10 10 150 200 350 2.25 200 tsk(PP) tSK(P) DCQ tr, tf /1 output /2 output 47 45 0.1 50 50 53 55 1.0 DCREF = 50% DCREF = 25%-75% 0.55 to 2.4V 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. he MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. 4. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 5. Output pulse skew is the absolute difference of the propagation delay times: | tpLH -tpHL |. Table 8. DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V 5%, TA = -40 to +85C) Symbol VIH VIL VPP VCMR1 VOH VOL ZOUT IIN ICCQ4 Characteristics Input high voltage Input low voltage Peak-to-peak input voltage Common Mode Range Output High Voltage Output Low Voltage Output impedance Input current3 Maximum Quiescent Supply Current 17-202 200 2.0 PCLK PCLK Min 1.7 -0.3 250 1.1 1.8 0.6 VCC -0.7 Typ Max VCC +0.3 0.7 Unit V V mV V V V A mA VIN = GND or VIN = VCC All VCC Pins Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -15 mA2 IOL = 15 mA 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9456 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output. 3. Input pull-up / pull-down resistors influence input current. 4. CCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 643 MPC9456 Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V 5%, TA = -40 to +85C)1 Symbol fref fMAX VPP VCMR3 tP, REF tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) Input Frequency Maximum Output Frequency Peak-to-Peak Input Voltage Common Mode Range Reference Input Pulse Width PCLK Input Rise/Fall Time Propagation Delay PCLK to any Q PCLK to any Q 2.6 2.6 /1 output /2 output PCLK PCLK Characteristics Min 0 0 0 500 1.1 1.4 1.04 5.6 5.5 10 10 150 200 350 3.0 200 /1 or /2 output 45 0.1 50 55 1.0 Typ Max 2502 2502 125 1000 VCC -0.7 Unit MHz MHz MHz mV V ns ns ns ns ns ns ps ps ps ns ps % ns DCREF = 50% 0.6 to 1.8V 0.7 to 1.7V FSELx = 0 FSELx = 1 LVPECL LVPECL Condition Output Disable Time Output Enable Time Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-Device Skew Output Pulse Skew5 Output Duty Cycle Output Rise/Fall Time tsk(PP) tSK(P) DCQ tr, tf 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. 4. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 5. Output pulse skew is the absolute difference of the propagation delay times: | tpLH -tpHL |. Table 10. AC Characteristics (VCC = 3.3V 5%, VCCA = VCCB = VCCC = 2.5V 5% or 3.3V 5%, TA = -40 to +85C)1, 2 Symbol tsk(O) Characteristics Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-Device Skew Propagation Delay Output Pulse Skew3 Output Duty Cycle /1 or /2 output PCLK to any Q Min Typ Max 150 250 350 2.5 Unit ps ps ps ns Condition tsk(PP) tPLH,HL tSK(P) DCQ See 3.3V Table 250 45 50 55 ps % DCREF = 50% 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank. 3. Output pulse skew is the absolute difference of the propagation delay times: | tpLH -tpHL |. 644 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MPC9456 APPLICATIONS INFORMATION Driving Transmission Lines The MPC9456 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC /2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9456 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9456 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9456 OUTPUT BUFFER IN 14 parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 / (RS + R0 + Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 (25 / (18 + 14 + 25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 3.0 2.5 VOLTAGE (V) 2.0 In 1.5 1.0 0.5 OutA tD = 3.8956 OutB tD = 3.9386 RS = 36 ZO = 50 OutA 0 2 4 6 8 TIME (ns) 10 12 14 MPC9456 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 Figure 4. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. RS = 36 Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9456 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9456. The output waveform in Figure 4 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the MPC9456 OUTPUT BUFFER 14 RS = 22 ZO = 50 RS = 22 ZO = 50 14 + 22 || 22 = 50 || 50 25 = 25 Figure 5. Optimized Dual Line Termination FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 645 MPC9456 Differential Pulse Generator Z = 50 ZO = 50 MPC9456 DUT ZO = 50 RT = 50 VCC -2V RT = 50 VTT Figure 6. PCLK MPC9456 AC Test Reference for Vcc = 3.3V and Vcc = 2.5V PCLK VCC=3.3V VCC=2.5V 2.4 0.55 tF tR 1.8V 0.6V PCLK VPP VCMR VCC VCC /2 GND t(LH) t(HL) QX Figure 7. Output Transition Time Test Reference Figure 8. Propagation Delay (tPD) Test Reference VCC VCC /2 GND VOH VCC /2 GND tSK(LH) tSK(HL) VCC VCC /2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 9. Output Duty Cycle (DC) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 10. Output-to-Output Skew tSK(O) VCC=3.3V VCC=2.5V 2.4 0.55 tF tR 1.8V 0.6V Figure 11. Output Transition Time Test Reference 646 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Chapter Eight Differential Fanout Buffer Data Sheets Differential Fanout Buffer Device Index Device Number Page Device Number Page MC100ES6011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 MC100ES6014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 MC100ES60T22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 MC100ES60T23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 MC100ES6030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 MC100ES6039 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 MC100ES6056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 MC100ES6111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 MC100ES6130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 MC100ES6139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 MC100ES6210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 MC100ES6220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 MC100ES6221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 MC100ES6222 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 MC100ES6226 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 MC100ES6254 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 MC100ES6535 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 MC100ES7011H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 MC100ES7011P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 MC100ES7014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 MC100ES7111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 MC100ES8011H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 MC100ES8011P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 MC100ES8014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 MC100ES8111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 647 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6011 Rev 4, 08/2004 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer The MC100ES6011 is a differential 1:2 fanout buffer. The ES6011 is ideal for applications requiring lower voltage. The 100ES Series contains temperature compensation. Features * * * * * * * * 270 ps Typical Propagation Delay Maximum Frequency > 3 GHz Typical PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V Open Input Default State Q Output Will Default LOW with Inputs Open or at VEE LVDS Input Compatible 32-lead Pb-free Package Available MC100ES6011 D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 ORDERING INFORMATION Device MC100ES6011D MC100ES6011DR2 Package SO-8 SO-8 Q0 1 8 VCC Pin D1, D2 PIN DESCRIPTION Function ECL Data Inputs ECL Data Outputs Positive Supply Negative Supply Q0 2 7 D Q0, Q0 Q1, Q1 VCC VEE Q1 3 6 D 1. Pins will default LOW when left open. 2. Pins will default to 0.572 VCC/2 when left open. Q1 4 5 VEE Figure 1. 8-Lead Pinout (Top View) and Logic Diagram 648 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6011 Table 1. Attributes Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC Value 75 k 56 k > 4000 V > 200 V > 1500 V 190C/W 130C/W JA Thermal Resistance (Junction to Ambient) Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 2. Maximum Ratings1 Symbol VSUPPLY VIN IOUT TA Tstg Parameter Power Supply Voltage Input Voltage Conditions Difference between VCC & VEE VCC-VEE < 3.6 V Continuous Surge Rating 3.9 VCC +0.3 VEE -0.3 50 100 -40 to +85 -65 to +150 Units V V V mA mA C C Output Current Operating Temperature Range Storage Temperature Range 1. Absolute maxim continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. DC Characteristics (VCC = 0 V; VEE = -2.5 V 5% or VCC = 2.5 V 5%; VEE = 0 V)1 Symbol IEE VOH VOL VOUTPP VIH VIL VPP VCMR IIN Characteristic Power Supply Current Output HIGH Output LOW Voltage2 Voltage2 VCC-1160 VCC-1830 200 VCC-1165 VCC-1810 0.12 VEE +1.0 VCC-880 VCC-1475 1.3 VCC -0.8 150 -40C Min Typ 12 VCC-1005 VCC-1605 Max 25 VCC-880 VCC-1305 VCC-1100 VCC-1810 200 VCC-1165 VCC-1810 0.12 VEE +1.0 VCC-880 VCC-1475 1.3 VCC-0.8 150 Min 0C to 85C Typ 12 VCC-955 VCC-1705 Max 25 VCC-740 VCC-1405 Unit mA mV mV mV mV mV V V A Output Peak-to-Peak Voltage Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Differential Input Voltage3 Differential Cross Point Voltage4 Input Current 1. ES6011 circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow > 500 LFPM is maintained. 2. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 3. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 649 MC100ES6011 Table 4. DC Characteristics (VCC = 0 V; VEE = -3.8 to -3.135 or VCC = 3.8 to 3.135 V; VEE = 0 V)1 Symbol IEE VOH VOL VOUTPP VIH VIL VPP VCMR IIN Characteristic Power Supply Current Output HIGH Voltage2 Output LOW Voltage2 Output Peak-to-Peak Voltage Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Differential Input Input Current Voltage3 4 -40C Min Typ 12 VCC -1160 VCC -1830 200 VCC -1165 VCC -1810 0.12 VEE +1.0 VCC -880 VCC -1475 1.3 VCC -0.8 150 VCC -1005 VCC -1705 Max 25 VCC -880 VCC -1405 VCC -1100 VCC -1830 200 VCC -1165 VCC -1810 0.12 VEE +1.0 Min 0C to 85C Typ 12 VCC-955 VCC -1705 Max 25 VCC -740 VCC -1405 Unit mA mV mV mV VCC -880 VCC -1475 1.3 VCC -0.8 150 mV mV V V A Differential Cross Point Voltage 1. ES6011 circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow > 500 LFPM is maintained. 2. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 3. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Table 5. AC Characteristics (VCC = 0 V; VEE = -3.8 to -2.375 or VCC = 2.375 to 3.8 V; VEE = 0 V)1 Symbol fMAX tPLH, tPHL tSKEW tJITTER VPP VCMR tr tf Characteristic Maximum Frequency Propagation Delay (Differential) CLK to Q, Q Within Device Skew Q, Q Device-to-Device Skew2 Cycle-to-Cycle Jitter RMS (1) 150 VEE +1.2 70 170 -40C Min Typ >3 260 9 300 20 130 1 1200 VCC-1.1 220 150 VEE +1.2 70 180 Max Min 25C Typ >3 270 9 310 20 130 1 1200 VCC -1.1 220 150 VEE +1.2 70 210 Max Min 0C to 85C Typ >3 285 9 360 20 150 1 1200 VCC -1.1 220 Max Unit GHz ps ps ps mV V ps Input Voltage Swing (Differential) Differential Cross Point Voltage Output Rise/Fall Times (20% - 80%) 1. Measured using a 750 mV source 50% Duty Cycle clock source. All loading with 50 to VCC-2.0 V. 2. Skew is measured between outputs under identical transitions. Q Driver Device Qb 50 50 D Receiver Device Db VTT VTT = VCC - 2.0 V Figure 2. VOUTPP versus Frequency Figure 3. Typical Termination for Output Driver and Device Evaluation 650 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6011 Marking Notes: Device Nomenclature MC100ES6011D 8-Lead SOIC Marking M6011 Trace Code Identification: "A" -- The First character indicates the Assembly location. "L" -- The Second character indicates the Source Wafer Lot Tracking Code. "Y" -- The Third character indicates the "ALPHA CODE" of the year device was assembled. "W" -- The Fourth character indicates the "ALPHA CODE" of the Work Week device was assembled. The "Y" Year ALPHA CODES Month Work Week Code FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 The "W" Work Week ALPHA CODES 1st 6 Months (WW01 - WW26) 2nd 6 Months (WW27 - WW52) A = WW01 B = WW02 C = WW03 D = WW04 E = WW05 F = WW06 G = WW07 H = WW08 I = WW09 J = WW10 K = WW11 L = WW12 M = WW13 N = WW14 O = WW15 P = WW16 Q = WW17 R = WW18 S = WW19 T = WW20 U = WW21 V = WW22 W = WW23 X = WW24 Y = WW25 Z = WW26 A = WW27 B = WW28 C = WW29 D = WW30 E = WW31 F = WW32 G = WW33 H = WW34 I = WW35 J = WW36 K = WW37 L = WW38 M = WW39 N = WW40 O = WW41 P = WW42 Q = WW43 R = WW44 S = WW45 T = WW46 U = WW47 V = WW48 W = WW49 X = WW50 Y = WW51 Z = WW52 Year A = 2003 B = 2003 C = 2004 D = 2004 E = 2005 F = 2005 G = 2006 H = 2006 I = 2007 J = 2007 K = 2008 L = 2008 M = 2009 N = 2009 O = 2010 P = 2010 Q = 2011 R = 2011 S = 2012 T = 2012 U = 2013 V = 2013 W = 2014 X = 2014 Y = 2015 Z = 2015 Marking Example: XABR X A B = Assembly Location = First Lot Assembled of this device in the designated Work Week = 2003 Second 6 Months, WW27 - WW52 R = WW44 of 2003 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 651 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6014 Rev 2, 5/2004 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL and LVDS inputs can be used when the ES6014 is operating under PECL conditions. The ES6014 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The common enable (EN) is synchronous, outputs are enabled/disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. The MC100ES6014, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the ES6014 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single ended CLK input pin operation is limited to a VCC 3.0 V in PECL mode, or VEE -3.0 V in ECL mode. Designers can take advantage of the ES6014's performance to distribute low skew clocks across the backplane or the board. Features * * * * * * * * 25 ps Within Device Skew 400 ps Typical Propagation Delay Maximum Frequency > 2 GHz Typical The 100 Series Contains Temperature Compensation PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V ECL Mode: VCC = 0 V with VEE = -2.375 V to -3.8 V LVDS and HSTL Input Compatible Open Input Default State MC100ES6014 SCALE 2:1 DT SUFFIX 20 LEAD TSSOP PACKAGE CASE 948E-02 ORDERING INFORMATION Device MC100ES6014DT MC100ES6014DTR2 Package TSSOP-20 TSSOP-20 652 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6014 VCC 20 EN 19 VCC 18 CLK1 17 CLK1 16 VBB 15 CLK0 14 CLK0 CLK_SEL 13 12 VEE 11 1 0 D Q 1 Q0 2 Q0 3 Q1 4 Q1 5 Q2 6 Q2 7 Q3 8 Q3 9 Q4 10 Q4 Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 20-Lead Pinout (Top View) and Logic Diagram Table 1. Pin Description Pin CLK0*, CLK0** CLK1*, CLK1** Q0:4, Q0:4 CLK_SEL* EN* VBB VCC VEE Function ECL/PECL/HSTL CLK Input ECL/PECL/HSTL CLK Input ECL/PECL Outputs ECL/PECL Active Clock Select Input ECL Sync Enable Reference Voltage Output Positive Supply Negative Supply Table 2. Function Table CLK0 L H X X X CLK1 X X L H X CLK_SEL L L H H X EN L L L L H Q L H L H L* * On next negative transition of CLK0 or CLK1 * Pins will default LOW when left open. ** Pins will default to VCC/2 when left open. Table 3. General specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model 0 LFPM, 20 TSSOP 500 LFPM, 20 TSSOP Value 75 k 75 k > 2000 V > 200 V > 1500 V 140C/W 100C/W Thermal Resistance (Junction-to-Ambient) Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 653 MC100ES6014 Table 4. Absolute Maximum Ratings1 Symbol VSUPPLY VIN IOUT IBB TA TSTG Characteristic Power Supply Voltage Input Voltage Output Current VBB Sink/Source Current Operating Temperature Range Storage Temperature Range Conditions Difference between VCC & VEE VCC - VEE 3.6 V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 0.5 -40 to +85 -65 to +150 Units V V mA mA C C C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 0 V, VEE = -2.5 V5% or VCC = 2.5 V5%, VEE = 0 V) -40C Symbol IEE VOH VOL VoutPP VIH VIL VBB VPP VCMR IIN Characteristics Power Supply Current Output HIGH Voltage1 Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Reference Voltage IBB = 200 A Differential Input Voltage2 Differential Cross Point Input Current Voltage3 1 0C to 85C Max 60 VCC-800 VCC-1150 VCC-880 VCC-1475 VCC-1200 1.3 VCC-1.0 150 VCC-1200 VCC-1925 200 VCC-1165 VCC-1810 VCC-1400 0.12 VEE+0.2 VCC-880 VCC-1475 VCC-1200 1.3 VCC-1.0 150 Min Typ 30 VCC-960 VCC-1630 Max 60 VCC-750 VCC-1200 Unit mA mV mV mV mV mV mV mV mV A Min VCC-1250 VCC-2000 200 VCC-1165 VCC-1810 VCC-1400 0.12 VEE+0.2 Typ 30 VCC-990 VCC-1550 Output Peak-to-Peak Voltage 1. Output termination voltage VTT = 0V for VCC = 2.5V operation is supported but the power consumption of the device will increase. 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Table 6. DC Characteristics (VCC = 0 V, VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V) -40C Symbol IEE VOH VOL VoutPP VIH VIL VBB VPP VCMR IIN Characteristics Power Supply Current Output HIGH Voltage1 Output LOW Voltage1 Output Peak-to-Peak Voltage Input HIGH Voltage Input LOW Voltage Output Reference Voltage IBB = 200 A Differential Input Voltage2 Differential Cross Point Input Current Voltage3 VCC-1150 VCC-1950 200 VCC-1165 VCC-1810 VCC-1400 0.12 VEE+0.2 VCC-880 VCC-1475 VCC-1200 1.3 VCC-1.1 150 Min Typ 30 VCC-1020 VCC-1620 Max 60 VCC-800 VCC-1250 VCC-1200 VCC-2000 200 VCC-1165 VCC-1810 VCC-1400 0.12 VEE+0.2 VCC-880 VCC-1475 VCC-1200 1.3 VCC-1.1 150 Min 0C to 85C Typ 30 VCC-970 VCC-1680 Max 60 VCC-750 VCC-1300 Unit mA mV mV mV mV mV mV V V A 1. Output termination voltage VTT = 0V for VCC = 2.5V operation is supported but the power consumption of the device will increase. 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 654 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6014 Table 7. AC Characteristics (VCC = 0 V, VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)1 -40C Symbol fmax tPLH tPHL tSKEW Characteristics Maximum Output Frequency Propagation Delay (Differential) CLK to Q, Q Within Device Skew2 Device-to-Device Skew2 RMS (1) 200 VEE+0.2 70 Q, Q Min 2 300 355 23 425 45 125 1 1200 VCC-1.2 225 200 VEE+0.2 70 Typ Max Min 2 300 375 23 475 45 175 1 1200 VCC-1.2 250 200 VEE+0.2 70 25C Typ Max Min 2 300 400 23 525 45 225 1 1200 VCC-1.2 275 85C Typ Max Unit GHz ps ps ps ps mV V ps tJITTER Cycle-to-Cycle Jitter VPP VCMR tr/tf Input Peak-to-Peak Voltage Swing (Differential) Differential Cross Point Voltage Output Rise/Fall Time (20%-80%) 1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to VCC-2.0 V. 2. Skew is measured between outputs under identical transitions. Q Driver Device Q 50 50 D Receiver Device D VTT VTT = VCC - 2.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 655 MC100ES6014 Marking Notes: Device Nomenclature MC100ES6014DT 20-Lead TSSOP Marking 6014 Trace Code Identification for 20 TSSOP: ALYW "A" - The First character indicates the Assembly location. "L" - The Second character indicates the Source Wafer Lot Tracking Code. "Y" - The Third character indicates the "ALPHA CODE" of the year device was assembled. "W" - The Fourth character indicates the "ALPHA CODE" of the Work Week device was assembled. The "Y" Year ALPHA CODES Year A = 2003 B = 2003 C = 2004 D = 2004 E = 2005 F = 2005 G = 2006 H = 2006 I = 2007 J = 2007 K = 2008 L = 2008 M = 2009 N = 2009 O = 2010 P = 2010 Q = 2011 R = 2011 S = 2012 T = 2012 U = 2013 V = 2013 W = 2014 X = 2014 Y = 2015 Z = 2015 Month FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS Work Week Code WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 The "W" Work Week ALPHA CODES 1st 6 Months (WW01 - WW26) A = WW01 B = WW02 C = WW03 D = WW04 E = WW05 F = WW06 G = WW07 H = WW08 I = WW09 J = WW10 K = WW11 L = WW12 M = WW13 N = WW14 O = WW15 P = WW16 Q = WW17 R = WW18 S = WW19 T = WW20 U = WW21 V = WW22 W = WW23 X = WW24 Y = WW25 Z = WW26 2nd 6 Months (WW27 - WW52) A = WW27 B = WW28 C = WW29 D = WW30 E = WW31 F = WW32 G = WW33 H = WW34 I = WW35 J = WW36 K = WW37 L = WW38 M = WW39 N = WW40 O = WW41 P = WW42 Q = WW43 R = WW44 S = WW45 T = WW46 U = WW47 V = WW48 W = WW49 X = WW50 Y = WW51 Z = WW52 20 TSSOP Tracecode Marking Example: 5ABR 5 A = Assembly Location = First Lot Assembled of this device in the designated Work Week B = 2003 Second 6 Months, WW27 - WW52 R = WW44 of 2003 656 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES60T22 Rev 1, 5/2004 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator The MC100ES60T22 is a low skew dual LVTTL/LVCMOS to differential LVPECL translator. The low voltage PECL levels, small package, and dual gate design are ideal for clock translation applications. Features * * * * 280 ps typical propagation delay 100 ps max output-to-output skew LVPECL operating range: VCC = 3.135 V to 3.8 V 8-lead SOIC package Ambient temperature range -40C to +85C MC100ES60T22 D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 ORDERING INFORMATION Device MC100ES60T22D Q0 1 8 VCC MC100ES60T22DR2 Package SO-8 SO-8 PIN DESCRIPTION Q0 2 LVPECL LVTTL/LVCMOS 7 D0 Pin D0, D1 Qn, Qn Q1 3 6 D1 VCC GND Function LVTTL/LVCMOS Inputs LVPECL Differential Outputs Positive Supply Negative Supply Q1 4 5 GND Figure 1. 8-Lead Pinout (Top View) and Logic Diagram FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 657 MC100ES60T22 Table 1. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection JA Thermal Resistance (Junction-to-Ambient) Human Body Model Machine Model 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC Value 75 k 75 k > 2000 V > 200 V 190C/W 130C/W Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 2. Absolute Maximum Ratings1 Symbol VSUPPLY VIN Iout TA TSTG Power Supply Voltage Input Voltage Rating Conditions Difference between VCC & VEE VCC - VEE 3.6 V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 -40 to +85 -65 to +150 Units V V V mA mA C C Output Current Operating Temperature Range Storage Temperature Range 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. DC Characteristics (VCC = 3.135 V to 3.8 V; VEE = 0 V) Symbol IGND VOH 1 Characteristic Power Supply Current Output HIGH Voltage Output LOW Voltage -40C Min Typ Max 17 VCC - 1150 VCC - 1020 VCC - 800 VCC - 1200 Min 0C to 85C Typ VCC - 970 Max 22 VCC - 750 Unit mA mV mV VOL1 VCC - 1950 VCC - 1620 VCC - 1250 VCC - 2000 VCC - 1680 VCC - 1300 1. Outputs are terminated through a 50 resistor to VCC - 2 volts Table 4. LVTTL / LVCMOS Input DC Characteristics (VCC = 3.135 V to 3.8 V) Symbol IIN VIK VIH VIL Characteristic Input Current Input Clamp Voltage Input HIGH Voltage Input LOW Voltage Condition VIN = VCC IIN = -18 mA 2.0 -40C Min Typ Max 150 -1.2 VCC+0.3 0.8 2.0 Min 0C to 85C Typ Max 150 -1.2 VCC+0.3 0.8 Unit A V V V 658 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES60T22 Table 5. AC Characteristics (VCC = 3.134 V to 3.8 V; VEE = 0 V) Symbol fmax tPLH, tPHL tSKEW tJITTER VoutPP tr / tf Characteristic Maximum Toggle Frequency Propagation Delay Skew Cycle-to-Cycle Jitter part-to-part RMS (1) 350 50 750 400 100 260 -40C Min Typ Max 1 400 300 1 350 50 750 400 100 280 Min 25C Typ Max 1 400 300 1 350 50 750 400 100 280 Min 85C Typ Max 1 450 350 1 Unit GHz ps ps ps mV ps Output Peak-to-Peak Voltage Output Rise/Fall Times (20% - 80%) Q Driver Device Qb 50 50 D Receiver Device Db V TT Figure 2. Typical Termination for Output Driver and Device Evaluation FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 659 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES60T23 Rev 0, 05/2004 Product Preview 3.3 V Dual Differential LVPECL-to-LVTTL Translator The MC100ES60T23 is a dual differential LVPECL-to-LVTTL translator. The low voltage PECL levels, small package, and dual gate design is ideal for clock translation applications. Features * * * * * * Maximum Frequency > 180 MHz Differential LVPECL Inputs LVPECL Operating Range: VCC = 3.0 V to 3.6 V 24 mA LVTTL Compatible Outputs 8-Lead SOIC and 8-Lead TSSOP Packages Ambient Temperature Range: -40C to +85C MC100ES60T23 DUAL LVPECL TO LVTTL TRANSLATOR D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 D0 1 8 VCC DT SUFFIX 8-LEAD TSSOP PACKAGE CASE TBD D0 2 LVPECL LVTTL 7 Q0 ORDERING INFORMATION 6 Q1 Device MC100ES60T23D MC100ES60T23DR2 Package SO-8 SO-8 TSSOP-8 TSSOP-8 D1 3 D1 4 5 GND MC100ES60T23DT MC100ES60T23DTR2 Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Pin Qn Dn, Dn VCC GND PIN DESCRIPTION Function LVTTL Outputs LVPECL Differential Inputs Positive Supply Negative Supply This document contains certain information on a new product. Specifications and information herein are subject to change without notice. 660 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES60T23 Table 1. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistors ESD Protection Human Body Model Machine Model 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC 0 LFPM, 8 TSSOP 500 LFPM, 8 TSSOP Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test D D Value 75 k 112.5 k 75 k > 2000 V > 200 V 190 C/W 130 C/W TBD TBD JA Thermal Resistance (Junction to Ambient) Table 2. Absolute Maximum Ratings1 Symbol VSUPPLY VIN IOUT TA TSTG Power Supply Voltage Input Voltage Parameter Conditions Difference between VCC and VEE VCC-VEE 3.6 V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 -40 to +85 -65 to +150 Unit V V V mA mA C C Output Current Operating Temperature Range Storage Temperature Range 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. LVPECL Input DC Characteristics (VCC = 3.0 to 3.6 V; VEE = 0 V) Symbol ICCH ICCL VIH VIL VPP VCMR IIH IIL Characteristic Power Supply Current (Outputs set to HIGH) Power Supply Current (Outputs set to LOW) Input HIGH Voltage Input LOW Voltage Differential Input Voltage1 Differential Cross Point Voltage2 Input HIGH Current Input LOW Current D D -150 VCC-1165 VCC-1810 0.12 VEE +1.5 -40C Min Typ 18 26 Max 25 33 VCC-880 VCC-1475 1.3 VCC-0.65 150 0.5 -150 VCC-1165 VCC-1810 0.12 VEE +1.5 Min 0C to 85C Typ 18 26 Max 25 33 VCC-880 VCC-1475 1.3 VCC-0.65 150 0.5 Unit mA mA mV mV V V A A 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 661 MC100ES60T23 Table 4. LVTTL / LVCMOS Output DC Characteristics (VCC = 3.0 to 3.6 V) Symbol VOH V0L I0S Characteristic Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Condition IOH = -24 mA IOL = 24 mA -150 -40C Min 2.4 0.5 -150 Typ Max Min 2.4 0.5 0C to 85C Typ Max Unit V V mA Table 5. AC Characteristics (VCC = 3.0 to 3.6 V; VEE = 0 V)1 -40C Symbol fmax tPLH tPHL tSK++ tSK-tSKPP tSKPW tJITTER VPP tr / tf 1. 2. 3. 4. Characteristic Maximum Toggle Frequency2 Propagation Delay Min 180 1.0 1.5 2.5 Typ Max Min 180 1.0 1.7 2.5 25C Typ Max Min 180 1.0 1.7 2.5 85C Typ Max Unit MHz ns Data Path Skew++3 Data Path Skew--3 Skew3 Skew3 RMS (1 ) 200 120 800 Part-to-Part Pulse Width 60 25 500 250 1 1000 200 120 800 60 25 500 250 1 1000 200 120 800 60 25 500 250 1 1000 ps ps ps ps ps mV ps Cycle-to-Cycle Jitter Input Voltage Swing (Differential)4 Output Rise/Fall Times (0.8 V - 2.0 V) LVTTL output RL = 500 to GND and CL = 20 pF to GND. Refer to Figure 2. fmax guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only. Skews are measured between outputs under identical conditions. 200 mV input guarantees full logic swing at the output. APPLICATION CHARACTERISTIC TEST TTL RECEIVER CL* RL AC TEST LOAD GND *CL includes fixtures capacitance Figure 2. TTL Output Loading Used for Device Evaluation 662 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6030 Rev 0, 06/2004 Preliminary Information 2.5/3.3 V ECL Triple D Flip-Flop with Set and Reset The MC100ES6030 is a triple master-slave D flip-flop with differential outputs. When the clock input is low, data enters the master latch and transfers to the slave during a positive transition on the clock input. Each flip-flop has individual Reset inputs while the Set input is shared. The Set and Reset inputs are asynchronous and override the clock inputs. Features * * * * * * 1.2 GHz minimum toggle frequency 450 ps typical propagation delay LVPECL operating range: VCC = 2.375 V to 3.8 V, VEE = 0 V LVECL operating range: VCC = 0 V, VEE = -2.375 V to -3.8 V 20-lead SOIC package Ambient temperature range -40C to +85C MC100ES6030 DW SUFFIX 20-LEAD SOIC PACKAGE CASE 751D-06 OREDERING INFORMATION Device MC100ES6030DW MC100ES6030DWR2 Package SO-20 SO-20 PIN DESCRIPTION Pin VCC 20 Q0 19 Q0 18 VCC 17 Q1 16 Q1 15 VCC 14 Q2 13 Q2 12 VEE 11 D0-D2 R0-R2 CLK0-CLK2 Q S Q R S Q Q R S Q Q R SO12 Q0-Q2, Q0-Q2 VCC VEE Function ECL Data Inputs ECL Reset Inputs ECL Clock Inputs ECL Common Set Input ECL Differential Data Outputs Positive Supply Negative Supply 1 SO12 2 D0 3 CLK0 4 R0 5 D1 6 CLK1 7 R1 8 D2 9 CLK2 10 R2 TRUTH TABLE R L L H L H S L L L H H D L H X X X CLK Z Z X X X Q L H L H Undef Q H L H L Undef Figure 1. 20-Lead Pinout (Top View) and Logic Diagram Z = LOW to HIGH Transition X = Don't Care This document contains certain information on a new product. Specifications and information herein are subject to change without notice. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 663 MC100ES6030 Table 1. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model 0 LFPM, 20 SOIC 500 LFPM, 20 SOIC Value TBD TBD TBD TBD TBD TBD TBD JA Thermal Resistance (Junction-to-Ambient) Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 2. Absolute Maximum Ratings1 Symbol VSUPPLY VIN Iout TA Tstore Power Supply Voltage Input Voltage Output Current Operating Temperature Range Storage Temperature Range Rating Conditions Difference between VCC & VEE VCC - VEE 3.6 V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 -40 to +85 -65 to +150 Units V V V mA mA C C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. DC Characteristics (VCC = 0 V, VEE = -2.5 V 5% or -3.8 V to -3.135 V; VCC = 2.5 V 5% or 3.135 V to 3.8 V, VEE = 0 V) Symbol IEE VOH VOL VIH VIL IIN Characteristic Power Supply Current Output HIGH Voltage1 Output LOW Voltage1 Input HIGH Voltage Input LOW Voltage Input Current VCC-1085 VCC-1830 VCC-1165 VCC-1810 -40C Min Typ TBD VCC-1005 VCC-1695 VCC-880 VCC-1555 VCC-880 VCC-1475 150 VCC-1025 VCC-1810 VCC-1165 VCC-1810 Max Min 0C to 85C Typ TBD VCC-955 VCC-1705 VCC-880 VCC-1620 VCC-880 VCC-1475 150 Max Unit mA mV mV mV mV V 1. Outputs are terminated through a 50 resistor to VCC-2 volts. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported, but the power consumption of the device will increase. 664 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6030 Table 4. AC Characteristics (VCC = 0 V, VEE = -2.5 V 5% or -3.8 V to -3.135 V; VCC = 2.5 V 5% or 3.135 V to 3.8 V, VEE = 0 V) Symbol fmax tPLH tPHL ts th tRR tPW Characteristic Maximum Toggle Frequency Propagation Delay to Output Setup Time Hold Time Set/Reset Recovery Minimum Pulse Width CLK S, R CLK S, R 150 200 200 400 650 <2 TBD TBD TBD TBD 0 100 100 150 200 200 400 650 <2 TBD TBD TBD -40C Min 1.2 Typ Max Min 1.2 600 0 100 100 150 200 200 400 650 <2 TBD TBD 0 100 100 25C Typ Max Min 1.2 85C Typ Max Unit GHz ps ps ps ps ps ps ps ps tJITTER Cycle-to-Cycle Jitter tr/tf Output Rise/Fall Time (20%-80%) Figure 2. Q Driver Device Qb 50 50 D Receiver Device Db V TT Figure 3. Typical Termination for Output Driver and Device Evaluation FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 665 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6039 Rev 1, 06/2004 3.3 V ECL/PECL/HSTL/LVDS /2/4, /4/6 Clock Generation Chip The MC100ES6039 is a low skew /2/4, /4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple ES6039s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one ES6039, the MR pin need not be exercised as the internal divider design ensures synchronization between the /2/4 and the /4/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100ES Series contains temperature compensation. Features * * * * * * * * * Maximum Frequency >1.0 GHz Typical 50 ps Output-to-Output Skew PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE = -3.135 V to -3.8 V Open Input Default State Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips VBB Output LVDS and HSTL Input Compatible MC100ES6039 DW SUFFIX 20 LEAD SOIC PACKAGE CASE 751D-06 ORDERING INFORMATION Device MC100ES6039DW MC100ES6039DWR2 Package SO-20 SO-20 666 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6039 VCC 20 Q0 19 Q0 18 Q1 17 Q1 16 Q2 15 Q2 14 Q3 13 Q3 12 VEE 11 Table 1. Pin Description Pin CLK1, CLK1 EN1 MR1 VBB Q0, Q1, Q0, Q1 Q2, Q3, Q2, Q3 DIVSELa VCC VEE NC 1 Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff /2/4 Outputs ECL Diff /4/6 Outputs ECL Freq. Select Input /2/4 ECL Freq. Select Input /4/6 ECL Positive Supply ECL Negative Supply No Connect 1 VCC 2 EN 3 DIVSELb 4 CLK 5 CLK 6 VBB 7 MR 8 VCC 9 NC 10 DIVSELa Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. DIVSELb1 Figure 1. 20-Lead Pinout (Top View) 1. Pins will default low when left open. DIVSELa CLK CLK Q0 /2/4 R Q0 Q1 Q1 Q2 /4/6 R MR DIVSELb Q2 Q3 Q3 EN VEE Figure 2. Logic Diagram Table 2. Function Tables CLK Z ZZ X X = Don't Care Z = Low-to-High Transition ZZ = High-to-Low Transition DIVSELa L H DIVSELb L H Q0:1 Outputs Divide by 2 Divide by 4 Q2:3 Outputs Divide by 4 Divide by 6 EN L H X MR L L H Function Divide Hold Q0:3 Reset Q0:3 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 667 MC100ES6039 CLK Q (/2) Q (/4) Q (/6) Figure 3. Timing Diagram CLK tRR RESET Q (/n) Figure 4. Timing Diagram Table 3. Attributes Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 k 75 k > 4 kV > 200 V > 2 kV Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 668 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6039 Table 4. Maximum Ratings1 Symbol VCC VEE VI Iout IBB TA Tstg JA Parameter PECL Mode Power Supply ECL Mode Power Supply PECL Mode Input Voltage ECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) 0 LFPM 500 LFPM 20 SOIC 20 SOIC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 3.9 -3.9 3.9 -3.9 50 100 0.5 -40 to +85 -65 to +150 TBD TBD Units V V V V mA mA mA C C C/W C/W 1. Maximum Ratings are those values beyond which device damage may occur. Table 5. DC Characteristics (VCC = 0 V, VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)1 Symbol IEE VOH VOL VIH VIL VBB VPP VCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage2 Output LOW Voltage2 Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Reference Voltage Differential Input Voltage3 Differential Cross Point Voltage4 Input HIGH Current Input LOW Current 0.5 -40C Min Typ 35 VCC -1150 VCC -1020 Max 60 VCC -800 VCC -1200 Min 0C to 85C Typ 35 VCC -970 Max 60 VCC -750 Unit mA mV mV mV mV mV V V A A VCC -1950 VCC -1620 VCC -1250 VCC -2000 VCC -1680 VCC -1300 VCC -1165 VCC -1810 VCC -1400 0.12 VEE+0.2 VCC -880 VCC -1165 VCC -880 VCC -1475 VCC -1200 1.4 VCC-0.7 150 0.5 VCC -1475 VCC -1810 VCC -1200 VCC -1400 1.4 VCC-0.7 150 0.12 VEE+0.2 1. MC100ES6039 circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 2. All loading with 50 to VCC-2.0 volts. 3. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 669 MC100ES6039 Table 6. AC Characteristics (VCC = 0 V; VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V; VEE = 0 V)1 Symbol fmax tPLH, tPHL tRR ts th tPW tSKEW Characteristic Maximum Frequency Propagation Delay Reset Recovery Setup Time Hold Time Minimum Pulse Width Within Device Skew EN, CLK DIVSEL, CLK CLK, EN CLK, DIVSEL MR CLK, Q (Diff) MR, Q 575 500 200 200 400 100 200 550 100 120 180 50 140 450 80 50 300 1 150 VEE+0.2 Q, Q 50 1400 150 -40C Min Typ >1 875 850 575 500 200 200 400 100 200 550 100 120 180 50 140 450 80 50 300 1 1400 150 Max Min 25C Typ >1 875 850 575 500 200 200 400 100 200 550 100 120 180 50 140 450 80 50 300 1 1400 VCC-1.1 300 Max Min 85C Typ >1 875 850 Max Unit GHz ps ps ps ps ps ps ps ps ps ps ps ps mV V ps Q, Q Q, Q @ Same Frequency (RMS 1) Device-to-Device Skew2 tJITTER Cycle-to-Cycle Jitter VPP VCMR tr tf Input Voltage Swing (Differential) Differential Cross Point Voltage Output Rise/Fall Times (20% - 80%) VCC-1.1 VEE+0.2 300 50 VCC-1.1 VEE+0.2 300 50 1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V. 2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. Q Driver Device Q 50 50 D Receiver Device D V TT V TT = V CC - 2.0 V Figure 5. Typical Termination for Output Driver and Device Evaluation 670 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6039 Marking Notes: Device Nomenclature MC100ES6039DW 20-Lead SOIC W/B Marking MC100ES6039 Trace Code Identification for 20 SOIC: AWLYYWW "A" - The First character indicates the Assembly location. "WL" - The Second & Third characters indicate the Source Wafer Lot Tracking Code. "YY" - The Fourth & Fifth characters indicate the Year device was assembled. "WW" - The Sixth & Seventh characters indicate the Work Week device was assembled. The "Y" Year ALPHA CODES Year A = 2003 B = 2003 C = 2004 D = 2004 E = 2005 F = 2005 G = 2006 H = 2006 I = 2007 J = 2007 K = 2008 L = 2008 M = 2009 N = 2009 O = 2010 P = 2010 Q = 2011 R = 2011 S = 2012 T = 2012 U = 2013 V = 2013 W = 2014 X = 2014 Y = 2015 Z = 2015 Month FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS Work Week Code WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 The "W" Work Week ALPHA CODES 1st 6 Months (WW01 - WW26) A = WW01 B = WW02 C = WW03 D = WW04 E = WW05 F = WW06 G = WW07 H = WW08 I = WW09 J = WW10 K = WW11 L = WW12 M = WW13 N = WW14 O = WW15 P = WW16 Q = WW17 R = WW18 S = WW19 T = WW20 U = WW21 V = WW22 W = WW23 X = WW24 Y = WW25 Z = WW26 2nd 6 Months (WW27 - WW52) A = WW27 B = WW28 C = WW29 D = WW30 E = WW31 F = WW32 G = WW33 H = WW34 I = WW35 J = WW36 K = WW37 L = WW38 M = WW39 N = WW40 O = WW41 P = WW42 Q = WW43 R = WW44 S = WW45 T = WW46 U = WW47 V = WW48 W = WW49 X = WW50 Y = WW51 Z = WW52 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 671 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6056 Rev 3, 06/2004 2.5V / 3.3V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The device features both individual and common select inputs to address both data path and random logic applications. The 100ES Series contains temperature compensation. Features * * * * * * * * * 360 ps Typical Propagation Delays Maximum Frequency > 3 GHz Typical PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V Open Input Default State Separate and Common Select Q Output Will Default LOW with Inputs Open or at VEE VBB Outputs LVDS Input Compatible MC100ES6056 SCALE 2:1 DT SUFFIX 20 LEAD TSSOP PACKAGE CASE 948E-02 DW SUFFIX 20 LEAD SOIC PACKAGE CASE 751D-06 ORDERING INFORMATION Device MC100ES6056DT MC100ES6056DTR2 MC100ES6056DW MC100ES6056DWR2 Package TSSOP-20 TSSOP-20 SO-20 SO-20 672 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6056 VCC 20 Q0 19 Q0 18 SEL0 COM_SEL SEL1 17 16 15 VCC 14 Q1 13 Q1 12 VEE 11 1 0 1 0 1 D0a 2 D0a 3 VBB0 4 D0b 5 D0b 6 D1a 7 D1a 8 VBB1 9 D1b 10 D1b Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 20-Lead Pinout (Top View) and Logic Diagram * Input function will default LOW when left open. Table 1. Pin Description Pin D0a* - D1a* D0a* - D1a* D0b* - D1b* D0b* - D1b* SEL0* - SEL1* COM_SEL* VBB0, VBB1 Q0 - Q1 Q0 - Q1 VCC VEE ECL Input Data a ECL Input Data a Invert ECL Input Data b ECL Input Data b Invert ECL Indiv. Select Input ECL Common Select Input Output Reference Voltage ECL True Outputs ECL Inverted Outputs Positive Supply Negative Supply Function Table 2. Function Table SEL0 X L L H H SEL1 X L H H L COM_SEL H L L L L Q0, Q0 a b b a a Q1, Q1 a b a a b Table 3. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model 0 LFPM, 20 TSSOP 500 LFPM, 20 TSSOP 0 LFPM, 20 SOIC 500 LFPM, 20 SOIC Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Value 75 k 75 k > 4 kV > 400 V > 2 kV 140C/W 100C/W TBD TBD Thermal Resistance (Junction-to-Ambient) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 673 MC100ES6056 Table 4. Absolute Maximum Ratings1 Symbol VSUPPLY VIN IOUT IBB TA TSTG Characteristic Power Supply Voltage Input Voltage Output Current VBB Sink/Source Current Operating Temperature Range Storage Temperature Range Conditions Difference between VCC & VEE VCC - VEE 3.6 V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 0.5 -40 to +85 -65 to +150 Units V V mA mA C C C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 0 V, VEE = -2.5 V5% or 3.8 V to -3.135 V; VCC = 2.5 V5% or 3.135 V to 3.8 V, VEE = 0 V) -40C Symbol IEE VOH VOL VIH VIL VBB VPP VCMR IIH IIL Characteristics Power Supply Current Output HIGH Voltage1 Output LOW Voltage1 Input HIGH Voltage Input LOW Voltage Output Reference Voltage Differential Input Voltage2 Differential Cross Point Voltage3 Input HIGH Current Input LOW Current 0.5 VCC-1085 VCC-1950 VCC-1165 VCC-1810 VCC-1380 0.15 VCC -2.3 VCC-1290 Min Typ 30 VCC-960 VCC-1695 Max 60 VCC-880 VCC-1500 VCC-880 VCC-1475 VCC-1220 1.3 VCC-0.8 150 0.5 VCC-1025 VCC-1950 VCC-1165 VCC-1810 VCC-1380 0.15 VCC -2.3 VCC-1290 Min 0C to 85C Typ 30 VCC-930 VCC-1705 Max 60 VCC-860 VCC-1500 VCC-880 VCC-1475 VCC-1200 1.3 VCC-0.8 150 Unit mA mV mV mV mV mV V V A A 1. Output termination voltage VTT = 0V for VCC = 2.5V operation is supported but the power consumption of the device will increase. 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 674 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6056 Table 6. AC Characteristics (VCC = 0 V; VEE = -2.5 V 5% or -3.8 V to -3.135 V; VCC = 2.5 V 5% or 3.135 V to 3.8 V; VEE = 0 V)1 -40C to 85C Symbol fmax tPLH, tPHL Maximum Frequency Propagation Delay to Output Differential D to Q, Q SEL to Q, Q COM_SEL to Q, Q Output-to-Output2 Part-to-Part RMS (1) 200 VCC-2.1 70 120 800 300 300 300 Characteristics Min Typ >3 400 430 490 10 500 600 650 50 200 1 1200 VCC-1.1 230 Max Unit GHz ps ps ps ps ps ps mV V ps tSKEW tJITTER VPP VCMR tr / tf Skew Cycle-to-Cycle Jitter Minimum Input Swing Differential Cross Point Voltage Output Rise/Fall Time (20%-80%) 1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V. 2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. Q Driver Device Q 50 50 D Receiver Device D VTT Figure 2. Typical Termination for Output Driver and Device Evaluation FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 675 MC100ES6056 Marking Notes: Device Nomenclature MC100ES6056DT MC100ES6056DW 20-Lead TSSOP Marking 6056 20-Lead SOIC W/B Marking MC100ES6056 Trace Code Identification for 20 SOIC: AWLYYWW "A" - The First character indicates the Assembly location. "WL" - The Second & Third characters indicate the Source Wafer Lot Tracking Code. "YY" - The Fourth & Fifth characters indicate the Year device was assembled. "WW" - The Sixth & Seventh characters indicate the Work Week device was assembled. Trace Code Identification for 20 TSSOP: ALYW "A" - The First character indicates the Assembly location. "L" - The Second character indicates the Source Wafer Lot Tracking Code. "Y" - The Third character indicates the "ALPHA CODE" of the year device was assembled. "W" - The Fourth character indicates the "ALPHA CODE" of the Work Week device was assembled. Year A = 2003 B = 2003 C = 2004 D = 2004 E = 2005 F = 2005 G = 2006 H = 2006 I = 2007 J = 2007 K = 2008 L = 2008 M = 2009 N = 2009 O = 2010 P = 2010 Q = 2011 R = 2011 S = 2012 T = 2012 U = 2013 V = 2013 W = 2014 X = 2014 Y = 2015 Z = 2015 The "Y" Year ALPHA CODES Month Work Week Code FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 FIRST 6 MONTHS WW01 - WW26 SECOND 6 MONTHS WW27 - WW52 The "W" Work Week ALPHA CODES 1st 6 Months (WW01 - WW26) 2nd 6 Months (WW27 - WW52) A = WW01 A = WW27 B = WW02 B = WW28 C = WW03 C = WW29 D = WW04 D = WW30 E = WW05 E = WW31 F = WW06 F = WW32 G = WW07 G = WW33 H = WW08 H = WW34 I = WW09 I = WW35 J = WW10 J = WW36 K = WW11 K = WW37 L = WW12 L = WW38 M = WW13 M = WW39 N = WW14 N = WW40 O = WW15 O = WW41 P = WW16 P = WW42 Q = WW17 Q = WW43 R = WW18 R = WW44 S = WW19 S = WW45 T = WW20 T = WW46 U = WW21 U = WW47 V = WW22 V = WW48 W = WW23 W = WW49 X = WW24 X = WW50 Y = WW25 Y = WW51 Z = WW26 Z = WW52 20 TSSOP Tracecode Marking Example: 5ABR 5 A = Assembly Location = First Lot Assembled of this device in the designated Work Week B = 2003 Second 6 Months, WW27 - WW52 R = WW44 of 2003 676 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6111 Rev 2, 08/2004 Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer The MC100ES6111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6111 supports various applications that require distribution of precisely aligned differential clock signals. Using SiGe:C technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * * * * 1:10 differential clock distribution 35 ps maximum device skew Fully differential architecture from input to all outputs SiGe:C technology supports near-zero output skew Supports DC to 2.7 GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL/HSTL compatible differential clock inputs Single 3.3 V, -3.3 V, 2.5 V or -2.5 V supply Standard 32-lead LQFP package 32-lead Pb-free package available Industrial temperature range Pin and function compatible to the MC100EP111 MC100ES6111 LOW-VOLTAGE 1:10 DIFFERENTIAL ECL/PECL/HSTL CLOCK FANOUT DRIVER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MC100ES6111 is designed for low skew clock distribution systems and supports clock frequencies up to 2.7 GHz. The device accepts two clock sources. The CLKA input can be driven by ECL or PECL compatible signals, the CLKB input accepts HSTL compatible signals. The selected input signal is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA input and bypassed to GND by a 10 nF capacitor, the MC100ES6111 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6111 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the MC100ES6111 supports positive (PECL) and negative (ECL) supplies. The MC100ES6111 is pin and function compatible to the MC100EP111. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 677 MC100ES6111 Q3 Q3 Q4 Q4 Q5 Q5 Q6 18 VCC CLKA CLKA 0 VCC CLKB CLKB 1 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 VBB 24 VCC Q2 Q2 Q1 Q1 Q0 Q0 VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 Q6 17 16 15 14 VCC Q7 Q7 Q8 Q8 Q9 Q9 VCC 13 12 11 10 9 8 VEE MC100ES6111 2 3 4 5 6 7 CLK_SEL CLK_SEL CLKA CLKA VBB CLKB 1 Figure 1. MC100ES6111 Logic Diagram Figure 2. 32-Lead Package Pinout (Top View) Table 1. Pin Configuration Pin CLKA, CLKA CLKB, CLKB CLK_SEL Q[0-9], Q[0-9] VEE 1 I/O Input Input Input Output Supply Supply Output DC Type ECL/PECL HSTL ECL/PECL ECL/PECL Function Differential reference clock signal input Alternative differential reference clock signal input Active clock input select Differential clock outputs Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Reference voltage output for single ended ECL or PECL operation VCC VBB 1. In ECL mode (negative power supply mode), VEE is either -3.3 V or -2.5 V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC). Table 2. Function Table Control CLK_SEL Default 0 0 CLKA, CLKA input pair is active. CLKA can be driven by ECL or PECL compatible signals. CLKB, CLKB input pair is active. CLKB can be driven by HSTL compatible signals. 678 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA CLKB VCC MC100ES6111 Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS TFunc Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Functional Temperature Range -65 TA = -40 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 TJ = +110 Unit V V V mA mA C C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol VTT MM HBM CDM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-up Immunity Input Capacitance Thermal resistance junction to ambient JESD 51-3, single layer test board 200 4000 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 21 Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC TJ Thermal Resistance Junction to Case Operating Junction Temperature2 (Continuous Operation) MTBF = 9.1 years 110 C 1. Output termination voltage VTT = 0V for VCC = 2.5V operation is supported but the power consumption of the device will increase 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 and the application section in this data sheet for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6111 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6111 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 679 MC100ES6111 Table 5. PECL/HSTL DC Characteristics (VCC = 2.5 V 5% or VCC = 3.3 V 5%, VEE = GND, TJ = 0C to +110C) Symbol Control Input CLK_SEL VIL VIH IIN Input Voltage Low Input Voltage High Input Current1 VCC - 1.810 VCC - 1.165 VCC - 1.475 VCC - 0.880 100 V V A VIN = VIL or VIN = VIH Characteristics Min Typ Max Unit Condition Clock Input Pair CLKA, CLKA (PECL differential signals) VPP VCMR IIN Differential Input Voltage2 Differential Cross Point Voltage3 Input Current1 0.1 1.0 1.3 VCC - 0.3 100 V V A Differential operation Differential operation VIN = VIL or VIN = VIH Clock Input Pair CLKB, CLKB (HSTL differential signals) VDIF Differential Input Voltage4 VCC = 3.3V VCC = 2.5V VX IIN Differential Cross Point Voltage5 Input Current 0.4 0.4 0.68 0.9 200 V V V A VIN = VX 0.2V PECL Clock Outputs (Q0-9, Q0-9) VOH VOL Output High Voltage Output Low Voltage VCC = 3.3V5% VCC = 2.5V5% Supply Current and VBB IEE VBB Maximum Quiescent Supply Current without Output Termination Current7 Output Reference Voltage VCC - 1.4 VCC - 1.2 V 100 mA VEE pin IBB = 200 A VCC - 1.2 VCC - 1.9 VCC - 1.9 VCC - 1.005 VCC - 1.705 VCC - 1.705 VCC - 0.7 VCC - 1.5 VCC - 1.3 V V IOH = -30 mA6 IOL = -5 mA6 1. Input have internal pullup/pulldown resistors which affect the input current 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 4. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 5. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 6. Equivalent to a termination of 50 to VTT. 7. ICC calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE ICC = (number of differential output pairs used) x (VOH - VTT)/Rload + (VOL - VTT)/Rload + IEE. 680 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6111 Table 6. ECL DC Characteristics (VEE = -2.5 V 5% or VEE = -3.3 V 5%, VCC = GND, TJ = 0C to +110C) Symbol Control Input CLK_SEL VIL VIH IIN Input Voltage Low Input Voltage High Input Current1 -1.810 -1.165 -1.475 -0.880 100 V V A VIN = VIL or VIN = VIH Characteristics Min Typ Max Unit Condition Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals) VPP VCMR IIN Differential Input Voltage2 Differential Cross Point Voltage3 Input Current1 0.1 VEE + 1.0 1.3 -0.3 100 V V A Differential operation Differential operation VIN = VIL or VIN = VIH ECL Clock Outputs (Q0-9, Q0-9) VOH VOL Output High Voltage Output Low Voltage VEE = -3.3V 5% VEE = -2.5V 5% -1.2 -1.9 -1.9 -1.005 -1.705 -1.705 -0.7 -1.5 -1.3 V V IOH = -30 mA4 IOL = -5 mA6 Supply Current and VBB IEE VBB Maximum Quiescent Supply Current without Output Termination Current5 Output Reference Voltage VCC - 1.4 VCC - 1.2 V 100 mA VEE pin IBB = 200 A 1. Input have internal pullup/pulldown resistors which affect the input current 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 4. Equivalent to a termination of 50 to VTT. 5. ICC calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE ICC = (number of differential output pairs used) x (VOH - VTT)/Rload + (VOL - VTT)/Rload + IEE. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 681 MC100ES6111 Table 7. AC Characteristics(ECL: VEE = -3.3 V 5% or VEE = -2.5 V 5%, VCC = GND) or (HSTL/PECL: VCC = 3.3 V 5% or VCC = 2.5 V 5%, VEE = GND, TJ = 0C to +110C)1 Symbol Characteristics Min Typ Max Unit Condition Clock Input Pair CLKA, CLKA (PECL or ECL differential signals) VPP VCMR fCLK tPD Differential Input Voltage2 (peak-to-peak) Differential Input Crosspoint Voltage3 Input Frequency4 Propagation Delay CLKA or CLKB to Q0-9 280 400 PECL 0.15 VEE + 1.0 1.3 VCC - 0.3 2.7 530 V V GHz Differential ps Differential Clock Input Pair CLKB, CLKB (HSTL differential signals) VDIF VX fCLK tPD Differential Input Voltage (peak-to-peak)5 Differential Input Crosspoint Voltage6 Input Frequency Propagation Delay CLKB to Q0-9 280 400 0.4 VEE + 0.68 1.0 VEE + 0.9 2.7 530 V V GHz Differential ps Differential ECL Clock Outputs (Q0-9, Q0-9) VO(P-P) Differential Output Voltage (peak-to-peak) fO < 300 MHz fO < 1.5 GHz fO < 2.7 GHz Output-to-Output Skew Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Pulse Skew7 Output Rise/Fall Time 0.05 0.45 0.3 TBD 0.72 0.55 0.37 0.95 0.95 0.95 35 250 1 75 0.3 ps ns 20% to 80% V V V ps ps Differential Differential tsk(O) tsk(PP) tJIT(CC) tsk(P) tr, tf 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew 4. The MC100ES6111 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz. 5. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 6. VX (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew. 7. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT=GND DUT MC100ES6111 RT = 50 VTT=GND Figure 1. MC100ES6111 AC Test Reference 682 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6111 APPLICATIONS INFORMATION Understanding the Junction Temperature Range of the MC100ES6111 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6111, the MC100ES6111 is specified, characterized and tested for the junction temperature range of TJ = 0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this data sheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja Ptot Assuming a thermal resistance (junction to ambient) of 54.4 C/W (2s2p board, 200 ft/min airflow, see Table 4) and a typical power consumption of 610 mW (all outputs terminated 50 ohms to VTT, VCC = 3.3V, frequency independent), the junction temperature of the MC100ES6111 is approximately TA + 33 C, and the minimum ambient temperature in this example case calculates to -33 C (the maximum ambient temperature is 77 C, see Table 8). Exceeding the minimum junction temperature specification of the MC100ES6111 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6111 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Please see the application note AN1545 for a power consumption calculation guideline. Table 8. Ambient Temperature Range (Ptot = 610 mW) Rthja (2s2p board) Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 59.0C/W 54.4C/W 52.5C/W 50.4C/W 47.8C/W TA, Min1 -36C -33C -32C -30C -29C TA, Max 74C 77C 78C 79C 81C Maintaining Lowest Device Skew The MC100ES6111 guarantees low output-to-output bank skew of 35 ps and a part-to-part skew of max. 250 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6111 is a mixed analog/digital product. The differential architecture of the MC100ES6111 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VCC 33...100 nF 0.1 nF VCC MC100ES6111 Figure 2. VCC Power Supply Bypass 1. The MC100ES6111 device function is guaranteed from TA = -40C to TJ = 110C FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 683 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6130 Rev 1, 05/2004 2.5/3.3 V 1:4 PECL Clock Driver with 2:1 Input MUX The MC100ES6130 is a 2.5 GHz differential PECL 1:4 fanout buffer. The ES6130 offers a wide operating range of 2.5 V and 3.3 V and also features a 2:1 input MUX which is ideal for redundant clock switchover applications. This device also includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state to eliminate the possibility of a runt clock pulse. Features * * * * * * * * * 2 GHz maximum output frequency 25 ps maximum output-to-output skew 150 ps part-to-part skew 350 ps typical propagation delay 2:1 differential MUX input 2.5 / 3.3 V operating range LVPECL and HSTL input compatible 16-lead TSSOP package Temperature range -40C to +85C MC100ES6130 DT SUFFIX 16-LEAD TSSOP PACKAGE CASE 948F-01 ORDERING INFORMATION Device MC100ES6130DT MC100ES6130DTR2 Package TSSOP-16 TSSOP-16 Q0 Q0 1 2 3 16 15 14 VCC EN Q D Q1 Q1 Q2 Q2 IN1 4 13 IN1 1 5 0 12 IN0 IN0 6 7 8 11 Q3 Q3 10 IN_SEL 9 VEE Figure 1. 16-Lead Pinout (Top View) and Logic Diagram 684 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6130 Table 1. Pin Description Number 1, 2, 3, 4, 5, 6, 7, 8 9 10 Name Q0 to Q3 Q0 to Q3 VEE IN_SEL Description LVPECL differential outputs: Terminate with 50 to VCC-2V. For single-ended applications, terminate the unused output with 50 to VCC-2V. Negative power supply: For LVPECL applications, connect to GND. LVPECL compatible 2:1 mux input signal select: When IN_SEL is LOW, the IN0 input pair is selected. When IN_SEL is HIGH, the IN1 input pair is selected. Includes a 75k pulldown. Default state is LOW and IN0 is selected. LVPECL, HSTL clock or data inputs. Internal 75k pulldown resistors on IN0 and IN1. Internal 75k pullup and 75k pulldown resistors on IN0, IN1. IN0, IN1 default condition is VCC/2 when left floating. IN0, IN1 default condition is LOW when left floating. LVPECL compatible synchronous enable: When EN goes HIGH, QOUT will go LOW and QOUT will go HIGH on the next LOW input clock transition. Includes a 75k pulldown. Default state is LOW when left floating. The internal latch is clocked on the falling edge of the input (IN0, IN1). Positive power supply: Bypass with 0.1F//0.01F low ESR capacitors. 11, 12, 13, 14 IN0, IN0 IN1, IN1 EN 15 16 VCC Table 2. Truth Table1 IN0 L H X X Z X IN1 X X L H X Z IN_SEL L L H H L H EN L L L L H H Q L H L L L L 1. Z = HIGH to LOW Transition X = Don't Care Table 3. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model 0 LFPM, 16 TSSOP 500 LFPM, 16 TSSOP Value 75 k 75 k > 2000 V > 200 V > 1500 V 138C/W 108C/W JA Thermal Resistance (Junction-to-Ambient) Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 685 MC100ES6130 Table 4. Absolute Maximum Ratings1 Symbol VSUPPLY VIN Iout TA TSTG Rating Power Supply Voltage Input Voltage Output Current Operating Temperature Range Storage Temperature Range Conditions Difference between VCC & VEE VCC - VEE 3.6 V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 -40 to +85 -65 to +150 Units V V V mA mA C C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 0 V, VEE = -2.5 V 5% or VCC = 2.5 V 5%, VEE = 0 V) Symbol IEE VOH VOL VoutPP VIH VIL VPP VCMR IIN Characteristic Power Supply Current Output HIGH Voltage1 Output LOW Voltage1 Output Peak-to-Peak Voltage Input HIGH Voltage Input LOW Voltage Differential Input Voltage 2 -40C Min Typ 45 VCC - 1250 VCC - 990 Max 70 VCC - 800 VCC - 1200 Min 0C to 85C Typ 45 VCC - 960 Max 70 VCC - 750 Unit mA mV mV mV VCC - 2000 VCC - 1550 VCC - 1150 VCC - 1925 VCC - 1630 VCC - 1200 200 VCC - 1165 VCC - 1810 0.12 VEE + 0.2 VCC - 880 200 VCC - 1165 VCC - 880 VCC - 1475 1.3 VCC - 1.0 150 mV mV V V A VCC - 1475 VCC - 1810 1.3 VCC - 1.0 150 0.12 VEE + 0.2 Differential Cross Point Voltage3 Input Current 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Table 6. DC Characteristics (VCC = 0 V, VEE = -3.8 to 3.135 V or VCC = 3.135 to 3.8 V, VEE = 0 V) Symbol IEE VOH VOL VoutPP VIH VIL VPP VCMR IIN Characteristic Power Supply Current Output HIGH Voltage1 Output LOW Voltage1 Output Peak-to-Peak Voltage Input HIGH Voltage Input LOW Voltage Differential Input Voltage2 Differential Cross Point Voltage3 Input Current -40C Min Typ 48 VCC - 1150 VCC - 1020 Max 70 VCC - 800 VCC - 1200 Min 0C to 85C Typ 48 VCC - 970 Max 70 VCC - 750 Unit mA mV mV mV VCC - 880 VCC - 1475 1.3 VCC - 1.1 150 mV mV V V A VCC- 1950 VCC - 1620 VCC - 1250 VCC - 2000 VCC - 1680 VCC - 1300 200 VCC - 1165 VCC - 1810 0.12 VEE + 0.2 VCC - 880 200 VCC - 1165 VCC - 1475 VCC - 1810 1.3 VCC - 1.1 150 0.12 VEE + 0.2 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 686 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6130 Table 7. AC Characteristics (VCC = 0 V, VEE = -3.8 V to -2.375 V; VCC = 2.375 to 3.8 V, VEE = 0 V)1 Symbol fmax Characteristic Maximum Frequency -40C Min 2 300 340 15 450 25 125 1 200 VEE + 0.2 70 1200 200 Typ Max Min 2 300 350 15 450 25 150 1 1200 200 25C Typ Max Min 2 300 350 15 475 25 150 1 1200 VCC - 1.2 275 85C Typ Max Unit GHz ps ps ps ps mV V ps tPLH / tPHL Propagation Delay to Output Differential CLK to Q, Q tSKEW tJITTER VPP VCMR tr / tf Skew2 Cycle-to-Cycle Jitter Minimum Input Swing Differential Cross Point Voltage Output Rise/Fall Times (20% - 80% @ 50 MHz) output-to-output part-to-part RMS (1) VCC - 1.2 VEE + 0.2 225 70 VCC - 1.2 VEE + 0.2 250 70 1. Measured using a 750 mV source, 50% Duty Cycle clock source. All loading with 50 ohms to VCC -2.0V. 2. Skew is measured between outputs under identical transitions. Q Driver Device Qb 50 50 D Receiver Device Db V TT Figure 2. Typical Termination for Output Driver and Device Evaluation FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 687 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6139 Rev 1, 06/2004 3.3 V ECL/PECL/HSTL/LVDS /2/4, /4/5/6 Clock Generation Chip The MC100ES6139 is a low skew /2/4, /4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 F capacitor. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple ES6139s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one ES6139, the MR pin need not be exercised as the internal divider design ensures synchronization between the /2/4 and the /4/5/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100ES Series contains temperature compensation. Features * * * * * * * * * Maximum Frequency >1.0 GHz Typical 50 ps Output-to-Output Skew PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE = -3.135 V to -3.8 V Open Input Default State Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips VBB Output LVDS and HSTL Input Compatible MC100ES6139 SCALE 2 1 DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-02 DW SUFFIX 20-LEAD SOIC PACKAGE CASE 751D-06 ORDERING INFORMATION Device MC100ES6139DT MC100ES6139DTR2 MC100ES6139DW MC100ES6139DWR2 Package TSSOP-20 TSSOP-20 SO-20 SO-20 688 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6139 VCC 20 Q0 19 Q0 18 Q1 17 Q1 16 Q2 15 Q2 14 Q3 13 Q3 12 VEE 11 EN1 MR1 1 VCC 2 EN 3 DIVSELb0 4 CLK 5 CLK 6 VBB 7 MR 8 VCC 9 DIVSELb1 10 DIVSELa VBB Q0, Q1, Q0, Q1 Q2, Q3, Q2, Q3 DIVSELa 1 Table 1. Pin Description Pin CLK , CLK 1 1 Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff /2/4 Outputs ECL Diff /4/5/6 Outputs ECL Freq. Select Input /2/4 ECL Freq. Select Input /4/5/6 ECL Freq. Select Input /4/5/6 ECL Positive Supply ECL Negative Supply Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. DIVSELb01 DIVSELb11 VCC VEE Figure 1. 20-Lead Pinout (Top View) 1. Pins will default low when left open. DIVSELa CLK CLK Q0 /2/4 R Q0 Q1 Q1 Q2 /4/5/6 R MR DIVSELb0 DIVSELb1 VEE Q2 Q3 Q3 EN Figure 2. Logic Diagram Table 2. Function Tables CLK Z ZZ X X = Don't Care Z = Low-to-High Transition ZZ = High-to-Low Transition DIVSELa L H DIVSELb0 L H L H DIVSELb1 L L H H Q0:1 Outputs Divide by 2 Divide by 4 Q2:3 Outputs Divide by 4 Divide by 6 Divide by 5 Divide by 5 EN L H X MR L L H Function Divide Hold Q0:3 Reset Q0:3 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 689 MC100ES6139 CLK Q (/2) Q (/4) Q (/5) Q (/6) Figure 3. Timing Diagram CLK tRR RESET Q (/n) Figure 4. Timing Diagram Table 3. Attributes Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 k 75 k > 4 kV > 200 V > 2 kV Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 690 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6139 Table 4. Maximum Ratings1 Symbol VCC VEE VI Iout IBB TA Tstg JA Parameter PECL Mode Power Supply ECL Mode Power Supply PECL Mode Input Voltage ECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) 0 LFPM 500 LFPM 0 LFPM 500 LFPM 1. Maximum Ratings are those values beyond which device damage may occur. 20 TSSOP 20 TSSOP 20 SOIC 20 SOIC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 3.9 -3.9 3.9 -3.9 50 100 0.5 -40 to +85 -65 to +150 74 64 TBD TBD Units V V V V mA mA mA C C C/W C/W C/W C/W Table 5. DC Characteristics (VCC = 0 V, VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)1 Symbol IEE VOH VOL VIH VIL VBB VPP VCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage2 Output LOW Voltage2 Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Reference Voltage Differential Input Voltage3 Differential Cross Point Voltage4 Input HIGH Current Input LOW Current 0.5 -40C Min Typ 35 VCC -1150 VCC -1020 Max 60 VCC -800 VCC -1200 Min 0C to 85C Typ 35 VCC -970 Max 60 VCC -750 Unit mA mV mV mV mV mV V V A A VCC -1950 VCC -1620 VCC -1250 VCC -2000 VCC -1680 VCC -1300 VCC -1165 VCC -1810 VCC -1400 0.12 VEE +0.2 VCC -880 VCC -1165 VCC -880 VCC -1475 VCC -1200 1.3 VCC -1.1 150 0.5 VCC -1475 VCC -1810 VCC -1200 VCC -1400 1.3 VCC -1.1 150 0.12 VEE +0.2 1. MC100ES6139 circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 2. All loading with 50 to VCC-2.0 volts. 3. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 691 MC100ES6139 Table 6. AC Characteristics (VCC = 0 V, VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)1 Symbol fmax tPLH, tPHL tRR ts th tPW tSKEW Characteristic Maximum Frequency Propagation Delay Reset Recovery Setup Time Hold Time Minimum Pulse Width EN, CLK DIVSEL, CLK CLK, EN CLK, DIVSEL MR CLK, Q (Diff) MR, Q 550 400 200 200 400 100 200 550 100 120 180 50 140 450 100 50 300 1 200 VEE+0.2 50 1200 200 -40C Min Typ >1 850 850 550 400 200 200 400 100 200 550 100 120 180 50 140 450 100 50 300 1 1200 200 Max Min 25C Typ >1 850 850 550 400 200 200 400 100 200 550 100 120 180 50 140 450 100 50 300 1 1200 VCC-1.2 300 Max Min 85C Typ >1 850 850 Max Unit GHz ps ps ps ps ps ps Within Device Skew Q, Q Q, Q @ Same Frequency Device-to-Device Skew2 Cycle-to-Cycle Jitter (RSM 1) tJITTER VPP VCMR tr tf ps mV V ps Input Voltage Swing (Differential) Differential Cross Point Voltage Output Rise/Fall Times (20% - 80%) Q, Q VCC-1.2 VEE+0.2 300 50 VCC-1.2 VEE+0.2 300 50 1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC -2.0 V. 2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. Q Driver Device Q 50 50 D Receiver Device D V TT V TT = V CC - 2.0 V Figure 5. Typical Termination for Output Driver and Device Evaluation 692 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6139 Marking Notes: Device Nomenclature MC100ES6139DT MC100ES6139DW 20-Lead TSSOP Marking 6139 MC100ES6139 20-Lead SOIC W/B Marking Trace Code Identification for 20 SOIC: AWLYYWW "A" - The First character indicates the Assembly location. "WL" - The Second & Third characters indicate the Source Wafer Lot Tracking Code. "YY" - The Fourth & Fifth characters indicate the Year device was assembled. "WW" - The Sixth & Seventh characters indicate the Work Week device was assembled. Trace Code Identification for 20 TSSOP: ALYW "A" - The First character indicates the Assembly location. "L" - The Second character indicates the Source Wafer Lot Tracking Code. "Y" - The Third character indicates the "ALPHA CODE" of the year device was assembled. "W" - The Fourth character indicates the "ALPHA CODE" of the Work Week device was assembled. The "Y" Year ALPHA CODES Year A = 2003 B = 2003 C = 2004 D = 2004 E = 2005 F = 2005 G = 2006 H = 2006 I = 2007 J = 2007 K = 2008 L = 2008 M = 2009 N = 2009 O = 2010 P = 2010 Q = 2011 R = 2011 S = 2012 T = 2012 U = 2013 V = 2013 W = 2014 X = 2014 Y = 2015 Z = 2015 Month FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS FIRST 6 MONTHS SECOND 6 MONTHS Work Week Code WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 WW01 - WW26 WW27 - WW52 The "W" Work Week ALPHA CODES 1st 6 Months (WW01 - WW26) A = WW01 B = WW02 C = WW03 D = WW04 E = WW05 F = WW06 G = WW07 H = WW08 I = WW09 J = WW10 K = WW11 L = WW12 M = WW13 N = WW14 O = WW15 P = WW16 Q = WW17 R = WW18 S = WW19 T = WW20 U = WW21 V = WW22 W = WW23 X = WW24 Y = WW25 Z = WW26 2nd 6 Months (WW27 - WW52) A = WW27 B = WW28 C = WW29 D = WW30 E = WW31 F = WW32 G = WW33 H = WW34 I = WW35 J = WW36 K = WW37 L = WW38 M = WW39 N = WW40 O = WW41 P = WW42 Q = WW43 R = WW44 S = WW45 T = WW46 U = WW47 V = WW48 W = WW49 X = WW50 Y = WW51 Z = WW52 20 TSSOP Tracecode Marking Example: 5ABR 5 A = Assembly Location = First Lot Assembled of this device in the designated Work Week B = 2003 Second 6 Months, WW27 - WW52 R= WW44 of 2003 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 693 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6210 Rev 2, 08/2004 Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer The MC100ES6210 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6210 supports various applications that require to distribute precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low clock skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * * * * Dual 1:5 differential clock distribution 30 ps maximum device skew Fully differential architecture from input to all outputs SiGe technology supports near-zero output skew Supports DC to 3GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL compatible differential clock inputs Single 3.3 V, -3.3 V, 2.5 V or -2.5 V supply Standard 32 lead LQFP package Industrial temperature range Pin and function compatible to the MC100EP210 32-lead Pb-free Package Available MC100ES6210 LOW VOLTAGE DUAL 1:5 DIFFERENTIAL PECL/ECL/HSTL CLOCK FANOUT BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The device consists of two independent 1:5 clock fanout buffers. The input signal of each fanout buffer is distributed to five identical, differential ECL/PECL outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL compatible signals. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6210 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6210 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the MC100ES6210 supports positive (PECL) and negative (ECL) supplies. The is function and pin compatible to the MC100EP210. 694 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6210 QA4 QA3 QA3 AQ4 QB0 QB0 QB1 18 VCC CLKA CLKA QA0 QA0 QA1 QA1 QA2 QA2 QA3 QA3 QA4 QA4 QB0 QB0 QB1 QB1 QB2 QB2 QB3 QB3 QB4 QB4 VBB 24 23 22 21 20 19 QB1 17 16 15 14 VCC Q2 Q2 Q1 Q1 Q0 Q0 VCC 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 VCC QB2 QB2 QB3 QB3 QB4 QB4 VCC MC100ES6210 13 12 11 10 9 VCC CLKB CLKB CLKA CLKB CLKB N.C. CLKA VCC VBB Figure 1. MC100ES6210 Logic Diagram Table 1. Pin Configuration Pin CLKA, CLKA CLKB, CLKB QA[0-4], QA[0-4] QB[0-4], QB[0-4] VEE1 VCC VBB Input Input Output Output Supply Supply Output DC Figure 2. 32-Lead Package Pinout (Top View) I/O Type ECL/PECL ECL/PECL ECL/PECL ECL/PECL Function Differential reference clock signal input (fanout buffer A) Differential reference clock signal input (fanout buffer B) Differential clock outputs (fanout buffer A) Differential clock outputs (fanout buffer B) Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Reference voltage output for single ended ECL or PECL operation 1. In ECL mode (negative power supply mode), VEE is either -3.3 V or -2.5 V and VCC is connected to GND (0 V). In PECL mode (positive power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC) Table 2. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C VEE Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 695 MC100ES6210 Table 3. General Specifications Symbol VTT MM HBM CDM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model Latch-up Immunity Input Capacitance Thermal Resistance Junction to Ambient JESD 51-3, single layer test board Min Typ VCC - 2 1 Max Unit V V V V Condition 200 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 110 mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 JESD 51-6, 2S2P multilayer test board JC TJ Thermal Resistance Junction to Case Operating Junction Temperature2 (continuous operation) MTBF = 9.1 years 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6210 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6210 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. Table 4. PECL DC Characteristics (VCC = 2.5 V 5% or VCC = 3.3 V 5%, VEE = GND, TJ = 0C to +110C) Symbol VPP VCMR IIN VOH VOL Characteristics Differential Input Voltage1 Differential Cross Point Voltage2 Input Current1 Output High Voltage Output Low Voltage VCC = 3.3V5% VCC = 2.5V5% Min 0.1 1.0 Typ Max 1.3 VCC - 0.3 100 Unit V V A Condition Differential operation Differential operation VIN = VIL or VIN = VIH Clock input pair CLKA, CLKA, CLKB, CLKB (PECL differential signals) PECL clock outputs (QA0-4, QA0-4, QB0-4, QB0-4) VCC -1.2 VCC -1.9 VCC -1.9 VCC -1.005 VCC -1.705 VCC -1.705 VCC -0.7 VCC -1.5 VCC -1.3 V V IOH = -30 mA3 IOL = -5 mA3 Supply current and VBB IEE VBB Maximum Quiescent Supply Current without output termination current Output Reference Voltage VCC -1.38 60 VCC -1.26 100 VCC -1.14 mA V VEE pin IBB = 0.2 mA 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Equivalent to a termination of 50 to VTT. 696 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6210 Table 5. ECL DC Characteristics (VEE = -2.5 V 5% or VEE = -3.3 V 5%, VCC = GND, TJ = 0C to +110C) Symbol VPP VCMR IIN Characteristics Differential input voltage1 Differential cross point voltage2 Input Current1 Min 0.1 VEE + 1.0 Typ Max 1.3 -0.3 100 Unit V V A Condition Differential operation Differential operation VIN = VIL or VIN = VIH Clock input pair CLKA, CLKA, CLKB, CLKB (ECL differential signals) ECL clock outputs (QA0-4, QA0-4, QB0-4, QB0-4) VOH VOL Output High Voltage Output Low Voltage VCC = 3.3 V 5% VCC = 2.5 V 5% -1.2 -1.9 -1.9 -1.005 -1.705 -1.705 -0.7 -1.5 -1.3 V V IOH = -30 mA3 IOL = -5 mA3 Supply current and VBB IEE VBB Maximum Quiescent Supply Current without output termination current Output reference voltage -1.38 60 -1.26 100 -1.14 mA V VEE pin IBB = 0.2 mA 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Equivalent to a termination of 50 to VTT. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 697 MC100ES6210 Table 6. AC Characteristics (ECL: VEE = -3.3 V 5% or VEE = -2.5 V 5%, VCC = GND) or (PECL: VCC = 3.3 V 5% or VCC = 2.5 V 5%, VEE = GND, TJ = 0C to +110C)1 2 Symbol VPP VCMR Characteristics Differential Input Voltage3 (peak-to-peak) Differential Input Crosspoint Voltage 4 Min 0.3 PECL ECL 1.2 VEE + 1.2 Typ 0.3 Max 1.3 VCC - 0.3 -0.3V Unit V V V Condition Clock input pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals) ECL clock outputs (Q0-9, Q0-9) fCLK tPD VO(P-P) Input Frequency Propagation Delay CLKA to QAx or CLKB to QBx Differential Output Voltage (peak-to-peak) fO < 1.1 GHz fO < 2.5 GHz fO < 3.0 GHz Output-to-Output Skew (per bank) Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Pulse Skew5 Output Duty Cycle Output Rise/Fall Time fREF < 0.1 GHz fREF < 1.0 GHz 49.5 45.0 30 50 50 0 175 0.45 0.35 0.20 260 0.70 0.55 0.35 13 30 175 1 50 50.5 55.0 250 ps % % ps DCREF = 50% DCREF = 50% 20% to 80% 3000 350 MHz Differential ps V V V ps ps Differential Differential Differential tsk(O) tsk(PP) tJIT(CC) tSK(P) DCQ tr, tf 1. AC characteristics are design targets and pending characterization. 2. AC characteristics apply for parallel output termination of 50 to VTT. 3. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 4. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the V PP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 5. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT DUT MC100ES62 RT = 50 VTT Figure 3. MC100ES6210 AC Test Reference 698 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6220 Rev 2, 08/2004 Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer The MC100ES6220 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6220 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * * Two independent 1:10 differential clock fanout buffers 130 ps maximum device skew SiGe technology Supports DC to 1GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL compatible differential clock inputs Single 3.3 V, -3.3 V, 2.5 V or -2.5 V supply Standard 52-lead LQFP package with exposed pad for enhanced thermal characteristics Supports industrial temperature range Pin and function compatible to the MC100EP220 MC100ES6220 LOW VOLTAGE DUAL 1:10 DIFFERENTIAL ECL/PECL CLOCK FANOUT BUFFER TB SUFFIX 52-LEAD LQFP PACKAGE EXPOSED PAD CASE 1336A-01 Functional Description The MC100ES6220 is designed for low skew clock distribution systems and supports clock frequencies up to 1 GHz. The device consists of two independent clock fanout buffers. The CLKA and CLKB inputs can be driven by ECL or PECL compatible signals. The input signal of each clock buffer is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6220 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6220 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the MC100ES6220 supports positive (PECL) and negative (ECL) supplies. The MC100ES6220 is pin and function compatible to the MC100EP220. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 699 MC100ES6220 QB0 QB1 QB1 Fanout Buffer A VCC CLKA CLKA QA0 QA0 QA1 QA1 VCC QA5 QA5 QA4 QA4 QA3 QA3 QA2 QA2 QA1 QA1 QA0 QA0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 41 42 43 44 45 46 47 48 49 50 51 52 12 VCC VCC 3 VEE 4 CLKA 56 CLKA VBB 7 CLKB 8 25 24 23 22 QA9 QB0 QA7 QA7 QA8 QA8 QA9 QA6 QA6 VCC QB2 QB2 QB3 QB3 QB4 QB4 QB5 QB5 QB6 QB6 QB7 QB7 VCC VEE QA8 QA8 QA9 QA9 QB0 QB0 QB1 QB1 MC100ES6220 21 20 19 18 17 16 15 Fanout Buffer B VCC CLKB CLKB VEE QB9 QB9 VBB Figure 1. MC100ES6220 Logic Diagram Figure 2. 52-Lead Package Pinout (Top View) Table 1. Pin Configuration Pin CLKA, CLKA CLKB, CLKB QA[0-9], QA[0-9] QB[0-9], QB[0-9] VEE 1 I/O Input Input Output Output Supply Supply Output DC Type ECL/PECL ECL/PECL ECL/PECL ECL/PECL Function Differential reference clock signal input for fanout buffer A Differential reference clock signal input for fanout buffer B Differential clock outputs of fanout buffer A Differential clock outputs of fanout buffer B Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Reference voltage output for single ended ECL and PECL operation VCC VBB 1. In ECL mode (negative power supply mode), VEE is either -3.3 V or -2.5 V and VCC is connected to GND (0 V). In PECL mode (positive power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC). 700 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA CLKB VEE QB8 QB8 QB8 QB8 QB9 QB9 14 9 10 11 12 13 MC100ES6220 Table 2. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS TFUNC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Functional Temperature Range -65 TA = -40 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 TJ = +110 Unit V V V mA mA C C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. General Specifications Symbol VTT MM HBM CDM LU CIN Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model Latch-up immunity Input Capacitance Min Typ VCC - 21 Max Unit V V V V mA Condition 175 2000 TBD 200 4.0 See Table 8. Thermal Resistance 0 110 pF C/W C Inputs JA,JC, Thermal resistance (junction-to-ambient, junction-toboard, junction-to-case) JB TJ Operating junction temperature2 (continuous operation) MTBF = 9.1 years 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6220 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6220 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 701 MC100ES6220 Table 4. PECL DC Characteristics (VCC = 2.5 V 5% or VCC = 3.3 V 5%, VEE = GND, TJ = 0C to +110C) Symbol VPP VCMR IIN VIH VIL IIN VOH VOL Characteristics Differential Input Voltage1 Differential Cross Point Voltage2 Input Current 1 Min 0.1 1.0 Typ Max 1.3 VCC - 0.3 150 Unit V V A V V A V V Condition Differential operation Differential operation VIN = VIL or VIN = VIH Clock input pair CLKA, CLKA, CLKB, CLKB (PECL differential signals) Clock inputs (PECL single ended signals) Input Voltage High Input Voltage Low Input Current 3 VCC - 1.165 VCC - 1.810 VCC - 0.880 VCC - 1.475 150 VIN = VIL or VIN = VIH IOH = -30 mA4 IOL = -5 mA4 VEE pins IBB = 0.3 mA PECL clock outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9) Output High Voltage Output Low Voltage VCC - 1.1 VCC - 1.9 VCC - 1.005 VCC - 1.705 VCC - 0.7 VCC - 1.4 Supply current and VBB IEE5 VBB Maximum Quiescent Supply Current without output termination current Output Reference Voltage VCC - 1.42 80 130 VCC - 1.20 mA V 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Input have internal pullup/pulldown resistors which affect the input current. 4. Termination 50 to VTT. 5. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT) / Rload + (VOL - V TT) /Rload + IEE. Table 5. ECL DC Characteristics (VEE = -2.5 V 5% or VEE = -3.3 V 5%, VCC = GND, TJ = 0C to +110C) Symbol VPP VCMR IIN VIH VIL IIN VOH VOL Characteristics Differential Input Voltage1 Differential Cross Point Voltage2 Input Current1 Min 0.1 VEE + 1.0 Typ Max 1.3 -0.3 150 Unit V V A V V A V V Condition Differential operation Differential operation VIN = VIL or VIN = VIH Clock input pair CLKA, CLKA, CLKB, CLKB (ECL differential signals) Clock inputs (ECL single ended signals) Input Voltage High Input Voltage Low Input Current 3 -1.165 -1.810 -0.880 -1.475 150 VIN = VIL or VIN = VIH IOH = -30 mA4 IOL = -5 mA4 VEE pins IBB = 0.3 mA ECL clock outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9) Output High Voltage Output Low Voltage -1.1 -1.9 -1.005 -1.705 -0.7 -1.4 Supply current and VBB IEE5 VBB Maximum Quiescent Supply Current without output termination current Output Reference Voltage -1.42 80 130 -1.20 mA V 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Input have internal pullup/pulldown resistors which affect the input current. 4. Termination 50 to VTT. 5. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT) / Rload + (VOL - V TT) / Rload + IEE. 702 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6220 Table 6. AC Characteristics (ECL: VEE = -3.3 V 5% or VEE = -2.5 V 5%, VCC = GND) or (PECL: VCC = 3.3 V 5% or VCC = 2.5 V 5%, VEE = GND, TJ = 0C to +110C)1 Symbol VPP VCMR fCLK Characteristics Differential Input Voltage2 (peak-to-peak) Differential Input Crosspoint Voltage Input Frequency 3 Min 0.3 PECL ECL 1.1 VEE + 1.1 0 Typ Max 1.3 VCC - 0.3 -0.3 1000 Unit V V V MHz Condition Clock input pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals) Differential PECL/ECL clock outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9) tPD VO(P-P) tsk(O) tsk(PP) tJIT(CC) tSK(P) DCO tr, tf Propagation Delay CLKx to Qx0-9 Differential Output Voltage (peak-to-peak) Output-to-Output Skew Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Pulse Skew4 Output Duty Cycle Output Rise/Fall Time fREF < 0.1 GHz fREF < 1.0 GHz 49.65 46.5 50 50 50 285 400 600 60 130 200 1 35 50.35 53.5 350 550 ps mV ps ps ps ps % % ps DCREF = 50% DCREF = 50% 20% to 80% Differential Differential Differential 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. Differential Pulse Generator Z = 50 Z = 50 Z = 50 RT = 50 VTT DUT MC100ES6220 RT = 50 VTT Figure 3. MC100ES6220 AC Test Reference CLKN CLKN QX QX VPP = 0.8V VCMR = VCC - 1.3V tPD (CLKN to QX) Figure 4. MC100ES6220 AC Reference Measurement Waveform FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 703 MC100ES6220 APPLICATIONS INFORMATION Understanding the Junction Temperature Range of the MC100ES6220 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6220, the MC100ES6220 is specified, characterized and tested for the junction temperature range of TJ=0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this data sheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja Ptot Assuming a thermal resistance (junction to ambient) of 17 C/W (2s2p board, 200 ft/min airflow, see Table 8) and a typical power consumption of 1049 mW (all outputs terminated 50 ohms to VTT, VCC = 3.3V, frequency independent), the junction temperature of the MC100ES6220 is approximately TA + 18 C, and the minimum ambient temperature in this example case calculates to -18 C (the maximum ambient temperature is 92 C. See Table 7). Exceeding the minimum junction temperature specification of the MC100ES6220 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6220 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Please see the application note AN1545 for a power consumption calculation guideline. Table 7. Ambient Temperature Ranges (Ptot = 1049 mW) Rthja (2s2p board) Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 20 C/W 18 C/W 17 C/W 16 C/W 15 C/W The MC100ES6220 guarantees low output-to-output bank skew of 100 ps and a part-to-part skew of max. 200 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6220 is a mixed analog/digital product. The differential architecture of the MC100ES6220 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VCC 33...100 nF 0.1 nF VCC MC100ES6220 Figure 5. VCC Power Supply Bypass TA, min1 -21C -19C -18C -17C -16C TA, max 89C 91C 92C 93C 94C 1. The MC100ES6220 device function is guaranteed from TA = -40 C to TJ=110 C Maintaining Lowest Device Skew 704 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6220 APPLICATIONS INFORMATION Using the Thermally Enhanced Package of the MC100ES6220 The MC100ES6220 uses a thermally enhanced exposed pad (EP) 52 lead LQFP package. The package is molded so that the lead frame is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance that supports the power consumption of the MC100ES6220 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100ES6220. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is a requirement for MC100ES6220 applications on multi-layer boards. The recommended thermal land design comprises a 3 x 3 thermal via array as shown in Figure 6, providing an efficient heat removal path. all units mm shown in Figure 7. For the nominal package standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. all units mm 0.2 1.0 4.8 0.2 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern Figure 7. Recommended Solder Mask Openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Table 8. Thermal Resistance1 4.8 Convection LFPM Natural 100 200 400 4.8 800 Exposed pad land pattern RTHJA2 C/W 20 18 17 16 15 RTHJA3 C/W 48 47 46 43 41 1.0 RTHJC C/W RTHJB4 C/W 45 296 16 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Figure 6. Recommended thermal land pattern The via diameter is should be approx. 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. ` shows a recommend solder mask opening with respect to the recommended 3 x 3 thermal via array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as 1. Applicable for a 3 x 3 thermal via array 2. Junction to ambient, four conductor layer test board (2S2P), per JES51-7 and JESD 51-5 3. Junction to ambient, single layer test board, per JESD51-3 4. Junction to board, four conductor layer test board (2S2P) per JESD 51-8 5. Junction to exposed pad 6. Junction to top of package It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100ES6220 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 705 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6221 Rev 3, 08/2004 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer The MC100ES6221 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6221 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * * MC100ES6221 LOW VOLTAGE DUAL 1:20 DIFFERENTIAL ECL/PECL/HSTL CLOCK FANOUT BUFFER TB SUFFIX 1:20 differential clock fanout buffer 52-LEAD LQFP PACKAGE 100 ps maximum device skew EXPOSED PAD CASE 1336A-01 SiGe technology Supports DC to 2 GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL/HSTL compatible differential clock inputs Single 3.3V, -3.3V, 2.5V or -2.5V supply Standard 52 lead LQFP package with exposed pad for enhanced thermal characteristics Supports industrial temperature range Pin and function compatible to the MC100EP221 Functional Description The MC100ES6221 is designed for low skew clock distribution systems and supports clock frequencies up to 2 GHz. The device accepts two clock sources. The CLK0 input can be driven by ECL or PECL compatible signals, the CLK1 input accepts HSTL compatible signals. The selected input signal is distributed to 20 identical, differential ECL/PECL outputs. If VBB is connected to the CLK0 or CLK1 input and bypassed to GND by a 10 nF capacitor, the MC100ES6221 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6221 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the MC100ES6221 supports positive (PECL) and negative (ECL) supplies. The MC100ES6221 is pin and function compatible to the MC100EP221. 706 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6221 Q11 Q11 Q0 Q0 VCC CLK0 CLK0 VEE VCC CLK1 CLK1 VEE CLK_SEL 0 1 Q1 Q1 Q2 Q2 Q3 Q3 VCC Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 39 38 37 36 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Q9 Q10 Q10 VCC Q7 Q7 Q8 Q8 Q9 Q6 Q6 Q12 Q12 Q13 Q13 Q14 Q14 Q15 Q15 Q16 Q16 Q17 Q17 VCC * * * * * * Q16 Q16 Q17 Q17 Q18 Q18 Q19 Q19 MC100ES6221 21 20 19 18 17 16 15 5 6 7 8 9 14 10 11 12 13 CLK1 CLK0 CLK_SEL CLK0 VBB CLK1 VEE Q19 Q19 VEE Figure 1. MC100ES6221 Logic Diagram Table 1. Pin Configuration Pin CLK0, CLK0 CLK1, CLK1 CLK_SEL QA[0-19], QA[0-19] VEE1 VCC VBB Input Input Input Output Supply Supply Output DC I/O Type ECL/PECL HSTL ECL/PECL ECL/PECL Figure 2. 52-Lead Package Pinout (Top View) Function Differential reference clock signal input Alternative differential reference clock signal input Reference clock input select Differential clock outputs Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Reference voltage output for single ended ECL and PECL operation 1. In ECL mode (negative power supply mode), VEE is either -3.3 V or -2.5 V and VCC is connected to GND (0 V). In PECL mode (positive power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC). Table 2. Function Table Pin CLK_SEL 0 1 CLK0, CLK0 input pair is the reference clock. CLK0 can be driven CLK1, CLK1 input pair is the reference clock. CLK1 can be by ECL or PECL compatible signals. driven by HSTL compatible signals. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Q18 Q18 VCC VCC VBB 707 MC100ES6221 Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS TFUNC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Functional Temperature Range -65 TA = -40 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 TJ = +110 Unit V V V mA mA C C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol VTT MM HBM CDM LU CIN JA, JB, JC TJ Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up Immunity Input Capacitance Thermal Resistance (junction-to-ambient, junction-to-board, junction-to-case) Operating Junction Temperature2 (continuous operation) MTBF = 9.1 years 200 2000 TBD 200 4.0 See Table 9. Thermal Resistance Min Typ VCC - 21 Max Unit V V V V mA pF C/W Inputs Condition 0 110 C 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6221 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6221 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. 708 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6221 Table 5. PECL DC Characteristics (VCC = 2.5V 5% or VCC = 3.3V5%, VEE = GND, TJ = 0C to + 110C) Symbol Characteristics 1 Min Typ Max Unit Condition Clock input pair CLK0, CLK0 (PECL differential signals) VPP VCMR IIN Differential Input Voltage2 Differential Cross Point Voltage3 Input Current1 0.1 1.0 1.3 VCC - 0.3 100 V V A Differential operation Differential operation VIN = VIL or VIN = VIH Clock input pair CLK1, CLK14 (HSTL differential signals) VDIF VX VIH VIL IIN Differential Input Voltage5 Differential Cross Point Voltage6 Input High Voltage Input Low Voltage Input Current 0.2 0 VX + 0.1 VX - 0.7 0.68 - 0.9 1.4 VCC - 0.7 VX + 0.7 VX - 0.1 100 V V V V A VIN = VX 0.2V Clock inputs (PECL single ended signals) VIH VIL IIN Input Voltage High Input Voltage Low Input Current7 VCC - 1.165 VCC - 1.810 VCC - 0.880 VCC - 1.475 100 V V A VIN = VIL or VIN = VIH PECL clock outputs (Q0-19, Q0-19) VOH VOL Output High Voltage Output Low Voltage VCC - 1.1 VCC - 1.9 VCC - 1.005 VCC - 1.705 VCC - 0.7 VCC - 1.4 V V IOH = -30 mA8 IOL = -5 mA8 Supply current and VBB IEE9 VBB Maximum Quiescent Supply Current without output termination current Output Reference Voltage (fref < 1.0 GHz)10 VCC - 1.42 84 160 VCC - 1.20 mA V VEE pins IBB = 0.4 mA 1. The input pairs CLK0, CLK1 are compatible to differential signaling standards. CLK0 is compatible to LVPECL signals and CLK1 meets both HSTL differential signal specifications. The difference between CLK0 and CLK1 is the differential input threshold voltage (VCMR). 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 4. Clock inputs driven by differential HSTL compatible signals. Only applicable to CLK1, CLK1. 5. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 6. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 7. Inputs have internal pullup/pulldown resistors which affect the input current. 8. Equivalent to a termination of 50 to VTT. 9. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT) / Rload + (VOL - V TT) / Rload + IEE. 10. Using VBB to bias unused single-ended inputs is recommended only up to a clock reference frequency of 1 GHz. Above 1 GHz, only differential input signals should be used with the MC100ES6221. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 709 MC100ES6221 Table 6. ECL DC Characteristics (VEE = -2.5 V 5% or VEE = -3.3 V 5%, VCC = GND, TJ = 0C to + 110C) Symbol Characteristics Min Typ Max Unit Condition Differential operation Differential operation VIN = VIL or VIN = VIH Clock input pair CLK0, CLK0 (ECL differential signals) VPP VCMR IIN Differential Input Voltage1 Differential Cross Point Junction to top of package voltage Input Current1 2 0.1 VEE + 1.0 1.3 -0.3 100 V V A Clock inputs (ECL single ended signals) VIH VIL IIN Input Voltage High Input Voltage Low Input Current3 -1.165 -1.810 -0.880 -1.475 100 V V A VIN = VIL or VIN = VIH ECL clock outputs (Q0-A19, Q0-Q19) VOH VOL Output High Voltage Output Low Voltage -1.1 -1.9 -1.005 -1.705 -0.7 -1.4 V V IOH = -30 mA4 IOL = -5 mA4 Supply current and VBB IEE5 VBB Maximum Quiescent Supply Current without output termination current Output Reference Voltage (fref < 1.0 GHz)6 -1.42 84 160 -1.20 mA V VEE pins IBB = 0.4 mA 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Inputs have internal pullup/pulldown resistors which affect the input current. 4. Equivalent to a termination of 50 to VTT. 5. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT) / Rload + (VOL - V TT) / Rload + IEE. 6. VBB can be used to bias unused single-ended inputs up to a clock reference frequency of 1 GHz. Above 1 GHz, only differential signals should be used with the MC100ES6221. 710 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6221 Table 7. AC Characteristics (ECL: VEE = -3.3 V 5% or VEE = -2.5 V 5%, VCC = GND) or (PECL: VCC = 3.3 V 5% or VCC = 2.5 V 5%, VEE = GND, TJ = 0C to + 110C)1 Symbol Characteristics Min Typ Max Unit Condition Clock input pair CLK0, CLK0 (PECL or ECL differential signals) VPP VCMR fCLK tPD Differential Input Voltage2 (peak-to-peak) Differential Input Crosspoint Voltage3 Input Frequency Propagation Delay CLK0 to Q0-19 PECL ECL 0.2 1.0 VEE + 1.0 0 400 540 1.3 VCC - 0.3 -0.3V 2000 670 V V V MHz ps Differential Differential Clock input pair CLK1, CLK1 (HSTL differential signals) VDIF VX fCLK tPD Differential Input Voltage4 (peak-to-peak) Differential Input Crosspoint Voltage5 Input Frequency Propagation Delay CLK1 to Q0-19 0.2 0.1 0 650 780 0.68-0.9 1.3 VCC - 1.0 1000 950 V V MHz ps Differential Differential PECL/ECL clock outputs (Q0-19, Q0-19) VO(P-P) Differential Output Voltage (peak-to-peak) fO < 1.0 GHz fO < 2.0 GHz Output-to-Output Skew Output-to-Output Skew (part-to-part) using CLK0 using CLK1 parts at one given TJ, VCC, fref tJIT(CC) tSK(P) DCQ tr, tf Output Cycle-to-Cycle Jitter Output Pulse Skew6 Output Duty Cycle Output Rise/Fall Time fREF < 0.1 GHz fREF < 1.0 GHz 49.5 45.0 50 30 50 50 270 300 250 1 50 50.5 55.0 350 ps ps ps ps ps % % ps DCREF = 50% DCREF = 50% 20% to 80% 0.375 TDB 0.630 0.250 50 100 V V ps Differential Differential tsk(O) tsk(PP) 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the V PP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 4. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. Only applicable to CLKB. 5. VX (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the V DIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew. 6. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 711 MC100ES6221 Differential Pulse Generator Z = 50 Z0 = 50 Z0 = 50 RT = 50 VTT DUT MC100ES6221 RT = 50 VTT Figure 3. MC100ES6221 Test Reference CLKN CLKN QX QX VPP = 0.8V VCMR = VCC - 1.3V tPD (CLKN to QX) Figure 4. MC100ES6221 AC Test Reference Measurement Waveform 712 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6221 APPLICATIONS INFORMATION Understanding the Junction Temperature Range of the MC100ES6221 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6221, the MC100ES6221 is specified, characterized and tested for the junction temperature range of TJ=0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this data sheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja Ptot Assuming a thermal resistance (junction to ambient) of 17 C/W (2s2p board, 200 ft/min airflow, see Table 8) and a typical power consumption of 1148 mW (all outputs terminated 50 ohms to VTT, VCC = 3.3 V, frequency independent), the junction temperature of the MC100ES6221 is approximately TA + 21 C, and the minimum ambient temperature in this example case calculates to -21 C (the maximum ambient temperature is 89 C. See Table 8). Exceeding the minimum junction temperature specification of the MC100ES6221 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6221 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Please see the application note AN1545 for a power consumption calculation guideline. Table 8. Ambient Temperature Ranges (Ptot =1148 mW) Rthja (2s2p board) Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 20 C/W 18 C/W 17 C/W 16 C/W 15 C/W Maintaining Lowest Device Skew The MC100ES6221 guarantees low output-to-output bank skew of 50 ps and a part-to-part skew of max. 270 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6221 is a mixed analog/digital product. The differential architecture of the MC100ES6221 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VCC 33...100 nF 0.1 nF VCC MC100ES6221 Figure 5. VCC Power Supply Bypass TA, min1 -23 C -21 C -20 C -18 C -17 C TA, max 87 C 89 C 90 C 92 C 93 C 1. The MC100ES6221 device function is guaranteed from TA = -40 C to TJ = 110 C FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 713 MC100ES6221 APPLICATIONS INFORMATION Using the Thermally Enhanced Package of the MC100ES6221 The MC100ES6221 uses a thermally enhanced exposed pad (EP) 52 lead LQFP package. The package is molded so that the lead frame is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance that supports the power consumption of the MC100ES6221 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100ES6221. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is a requirement for MC100ES6221 applications on multi-layer boards. The recommended thermal land design comprises a 3 x 3 thermal via array as shown in Figure 6, providing an efficient heat removal path. all units mm standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. all units mm 0.2 1.0 4.8 0.2 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern Figure 7. Recommended Solder Mask Openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Table 9. Thermal Resistance1 Convection LFPM Natural 100 200 400 4.8 RTHJA2 C/W 20 18 17 16 15 RTHJA3 C/W 48 47 46 43 41 1.0 RTHJC C/W RTHJB4 C/W 45 296 16 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern 800 Figure 6. Recommended Thermal Land Pattern The via diameter is should be approx. 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. Figure 7 shows a recommend solder mask opening with respect to the recommended 3 x 3 thermal via array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as shown in Figure 7. For the nominal package 1. Applicable for a 3 x 3 thermal via array 2. Junction to ambient, four conductor layer test board (2S2P), per JES51-7 and JESD 51-5 3. Junction to ambient, single layer test board, per JESD51-3 4. Junction to board, four conductor layer test board (2S2P) per JESD 51-8 5. Junction to exposed pad 6. Junction to top of package It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100ES6221 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers. 714 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6222 Rev 2, 08/2004 Low Voltage 1:15 Differential ECL/PECL Clock Divider and Fanout Buffer The MC100ES6222 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6222 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * 15 differential ECL/PECL outputs (4 output banks) 2 selectable differential ECL/PECL inputs Selectable /1 or /2 frequency divider 130 ps maximum device skew Supports DC to 3 GHz input frequency Single 3.3 V, -3.3 V, 2.5 V or -2.5 V supply Standard 52-lead LQFP package with exposed pad for enhanced thermal characteristics Supports industrial temperature range Pin and function compatible to the MC100EP222 MC100ES6222 LOW-VOLTAGE 1:15 DIFFERENTIAL ECL/PECL CLOCK DIVIDER AND FANOUT DRIVER TB SUFFIX 52-LEAD LQFP PACKAGE EXPOSED PAD CASE 1336A-01 Functional Description The MC100ES6222 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The CLK0 and CLK1 inputs can be driven by ECL or PECL compatible signals. Each of the four output banks of two, three, four and six differential clock output pairs can be independently configured to distribute the input frequency or /2 of the input frequency. The FSELA, FSELB, FSELC, FSELD, and CLK_SEL are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the /2 outputs. For the functionality of the MR control input, see Figure 5. Functional Diagram. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6222 can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the MC100ES6222 supports positive (PECL) and negative (ECL) supplies. The MC100ES6222 is pin and function compatible to the MC100EP222. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 715 MC100ES6222 FSELA VCC CLK0 CLK0 VEE VCC CLK1 CLK1 VEE 0 VEE 1 0 1 QA0 QA1 VCC QC0 QC0 QC1 QC1 QC2 QC2 QC3 QC3 VCC /1 /2 0 1 QB0 QB1 QB2 QC0 QC1 VCC QB2 QB2 QB1 QB1 QB0 QB0 VCC QA1 QA1 QA0 QA0 VCC 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 25 24 23 22 21 QD0 QD0 QD1 QD1 QD2 QD2 QD3 QD3 QD4 QD4 QD5 QD5 VCC 0 1 CLK_SEL QC2 QC3 QD0 MC100ES6222 VEE FSELB FSELC VEE MR VEE FSELD VEE 0 1 QD1 QD2 QD3 VBB FSELA FSELB FSELC QD4 QD5 VBB Figure 1. MC100ES6222 Logic Diagram Figure 2. 52-Lead Package Pinout (Top View) Table 1. Function Table Control Pin FSELA (asynchronous) FSELB (asynchronous) FSELC (asynchronous) FSELD (asynchronous) CLK_SEL (asynchronous) MR (asynchronous) 0 /1 /1 /1 /1 CLK0 Active 1 /2 /2 /2 /2 CLK1 Reset. QX = L and QX = H. 716 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA CLK_SEL FSELD VCC CLK0 CLK0 CLK1 CLK1 VEE MR VCC 20 19 18 17 16 15 14 NC NC MC100ES6222 Table 2. Pin Configurations Pin CLK0, CLK0 CLK1, CLK1 FSELA, FSELB, FSELC, FSELD MR CLK_SEL QA[0:1], QA[0:1] QB[0:2], QB[0:2] QC[0:3], QC[0:3] QD[0:5], QD[0:5] VBB VEE 1 I/O Input Input Input Input Input Output Output Output Output Output Type ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL DC Power supply Power supply Differential reference clock signal input Description Alternative differential reference clock signal input Selection output frequency divider for bank A, B, C and D Reset Clock reference select input Bank A differential outputs Bank B differential outputs Bank C differential outputs Bank D differential outputs Reference voltage output for single ended ECL or PECL operation Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. VCC 1. In ECL mode (negative power supply mode), VEE is either -3.3 V or -2.5 V and VCC is connected to GND (0 V). In PECL mode (positive power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC). Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS TFUNC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Functional Temperature Range -65 TA = -40 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 TJ = +110 Unit V V V mA mA C C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol VTT MM HBM CDM LU CIN JA, JC JB TJ Characteristics Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model Latch-up Immunity Input Capacitance Thermal Resistance (junction-to-ambient, junction-to-board, junction-to-case) Operating Junction Temperature2 (continuous operation) MTBF = 9.1 years 175 2000 TBD 200 4.0 See Table 9. Thermal Resistance Min Typ VCC - 2 1 Max Unit V V V V mA pF C/W Condition Inputs 0 110 C 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6222 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6222 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 717 MC100ES6222 Table 5. PECL DC Characteristics (VCC = 2.5 V 5% or VCC = 3.3 V 5%, VEE = GND, TJ = 0C to +110C) Symbol VPP VCMR IIN VIH VIL IIN VOH VOL Characteristics Differential Input Voltage1 Differential Cross Point Voltage2 Input Current1 Input Voltage High Input Voltage Low Input Current 3 Min 0.1 1.0 Typ Max 1.3 VCC - 0.3 150 Unit V V A V V A V V Condition Differential operation Differential operation VIN = VIL or VIN = VIH Clock Input Pair CLK0, CLK0, CLK1, CLK1 (PECL differential signals) Clock Inputs MR, CLK_SEL, FSELA, FSELB, FSELC, FSELD (PECL single ended signals) VCC - 1.165 VCC - 1.810 VCC - 0.880 VCC - 1.475 150 VCC - 1.1 VCC - 1.9 VCC - 1.005 VCC - 1.705 VCC - 0.7 VCC - 1.4 VIN = VIL or VIN = VIH IOH = -30 mA4 IOL = -5 mA4 VEE pins IBB = 0.4 mA PECL clock outputs (QA[0:1], QA[0:1], QB[0:2], QB[0:2], QC[0:3], QC[0:3], QD[0:5], QD[0:5] Output High Voltage Output Low Voltage Supply current and VBB IEE5 VBB Maximum Quiescent Supply Current without Output Termination Current Output Reference Voltage VCC - 1.38 96 170 VCC - 1.22 mA V 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Input have internal pullup/pulldown resistors which affect the input current. 4. Equivalent to a termination of 50 to VTT. 5. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT) / Rload + (VOL - V TT) / Rload + IEE. Table 6. ECL DC Characteristics (VEE = -2.5 V 5% or VEE = -3.3 V 5%, VCC = GND, TJ = 0C to +110C) Symbol VPP VCMR IIN VIH VIL IIN VOH VOL Characteristics Differential Input Voltage1 Differential Cross Point Voltage2 Input Current 1 Min 0.1 VEE + 1.0 Typ Max 1.3 Unit V V A V V A V V Condition Differential operation Differential operation VIN = VIL or VIN = VIH Clock Input Pair CLK0, CLK0, CLK1, CLK1 (ECL differential signals) -0.3 150 Clock Inputs MR, CLK_SEL, FSELA, FSELB, FSELC, FSELD (PECL single ended signals) Input Voltage High Input Voltage Low Input Current 3 -1.165 -1.810 -0.880 -1.475 150 VIN = VIL or VIN = VIH IOH = -30 mA4 IOL = -5 mA4 VEE pins IBB = 0.4 mA ECL Clock Outputs (QA[0:1], QA[0:1], QB[0:2], QB[0:2], QC[0:3], QC[0:3], QD[0:5], QD[0:5] Output High Voltage Output Low Voltage -1.1 -1.9 -1.005 -1.705 -0.7 1.4 Supply Current and VBB IEE5 VBB Maximum Quiescent Supply Current without Output Termination Current Output Reference Voltage -1.38 96 170 -1.22 mA V 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Input have internal pullup/pulldown resistors which affect the input current. 4. Equivalent to a termination of 50 to VTT. 5. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT) / Rload + (VOL - V TT) / Rload + IEE. 718 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6222 Table 7. AC Characteristics (ECL: VEE = -3.3 V 5% or VEE = -2.5 V 5%, VCC = GND) or (PECL: VCC = 3.3 V 5% or VCC = 2.5 V 5%, VEE = GND, TJ = 0C to +110C)1 Symbol Characteristics Min Typ Max Unit Condition Clock Input Pair CLK0, CLK0, CLK1, CLK1 (PECL or ECL differential signals) VPP VCMR fCLK Differential Input Voltage2 (peak-to-peak) Differential Input Crosspoint Voltage3 Input Frequency PECL ECL 0.2 1.0 VEE+1.0 0 1.3 VCC - 0.3 V V V MHz Differential -0.3V 2000 ECL/PECL Clock Outputs (QA[0:1], QA[0:1], QB[0:2], QB[0:2], QC[0:3], QC[0:3], QD[0:5], QD[0:5] tPD VO(P-P) Propagation Delay CLK0 or CLK1 to Qx MR to Qx fO < 1.0 GHz fO < 2.0 GHz Output-to-Output Skew within QA[0:1] within QB[0:2] within QC[0:3] within QD[0:5] any output tsk(PP) tJIT(CC) tSK(P) DCO Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Pulse Skew4 Output Duty Cycle fREF < 0.1 GHz fREF < 1.0 GHz fREF < 2.0 GHz 49.85 48.50 47.00 50 5 50 50 50 670 820 970 ps ps mV mV 35 35 50 60 130 300 1 15 50.15 51.50 53.00 300 ps ps ps ps ps ps ps ps % % % ps DCREF = 50% DCREF = 50% DCREF = 50% 20% to 80% Differential Differential Differential Differential Output Voltage (peak-to-peak) TBD TBD tsk(O) tr, tf Output Rise/Fall Time 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 719 MC100ES6222 Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT DUT MC100ES6222 RT = 50 VTT Figure 3. MC100ES6222 AC Test Reference CLKN CLKN MR QX QX tPD (CLK to Q) 50% tPD (MR to Q) Figure 4. MC100ES6222 tPD Measurement Waveform APPLICATIONS INFORMATION Asynchronous Reset Functional Diagram CLKN MR QX (/2) QX (/1) Figure 5. Functional Diagram 720 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6222 APPLICATIONS INFORMATION Understanding the Junction Temperature Range of the MC100ES6222 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6222, the MC100ES6222 is specified, characterized and tested for the junction temperature range of TJ=0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this data sheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja Ptot Assuming a thermal resistance (junction to ambient) of 17C/W (2s2p board, 200 ft/min airflow, see Table 9. Thermal Resistance) and a typical power consumption of 1026 mW (all outputs terminated 50 ohms to VTT, VCC=3.3V, frequency independent), the junction temperature of the MC100ES6222 is approximately TA + 17C, and the minimum ambient temperature in this example case calculates to -17C (the maximum ambient temperature is 93C, see Table 8). Exceeding the minimum junction temperature specification of the MC100ES6222 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6222 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Please see the application note AN1545 for a power consumption calculation guideline. Table 8. Ambient Temperature Ranges (Ptot = 1026 mW) Rthja (2s2p board) Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 20C/W 18C/W 17C/W 16C/W 15C/W TA, Min1 -21C -18C -17C -16C -15C TA, Max 89C 92C 93C 94C 95C Maintaining Lowest Device Skew The MC100ES6222 guarantees low output-to-output bank skew of 130 ps and a part-to-part skew of max. 300 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6222 is a mixed analog/digital product. The differential architecture of the MC100ES6222 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VCC 33...100 nF 0.1 nF VCC MC100ES6222 Figure 6. VCC Power Supply Bypass 1. The MC100ES6222 device function is guaranteed from TA = -40C to TJ = 110C. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 721 MC100ES6222 APPLICATIONS INFORMATION Using the Thermally Enhanced Package of the MC100ES6222 The MC100ES6222 uses a thermally enhanced exposed pad (EP) 52 lead LQFP package. The package is molded so the lead frame is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance supporting the power consumption of the MC100ES6222 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100ES6222. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is a requirement for MC100ES6222 applications on multi-layer boards. The recommended thermal land design comprises a 3 x 3 thermal via array as illustrated in Figure 7. Recommended Thermal Land Pattern, providing an efficient heat removal path. All units mm array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as illustrated in Figure 8. Recommended Solder Mask Openings. For the nominal package standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. All units mm 0.2 1.0 4.8 0.2 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern Figure 8. Recommended Solder Mask Openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Table 9. Thermal Resistance1 Convection LFPM Natural 100 200 400 800 RTHJA2 C/W 20 18 17 16 15 RTHJA3 C/W 48 47 46 43 41 45 296 16 RTHJC C/W RTHJB4 C/W 4.8 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern Figure 7. Recommended Thermal Land Pattern The via diameter is should be approximately 0.3 mm with 1 ounce copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. Figure 8. Recommended Solder Mask Openings illustrates a recommend solder mask opening with respect to the recommended 3 x 3 thermal via 1. Applicable for a 3 x 3 thermal via array 2. Junction to ambient, four conductor layer test board (2S2P), per JES51-7 and JESD 51-5 3. Junction to ambient, single layer test board, per JESD51-3 4. Junction to board, four conductor layer test board (2S2P) per JESD 51-8 5. Junction to exposed pad 6. Junction to top of package It is recommended to employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100ES6222 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers. 722 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 1.0 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6226 Rev 2, 08/2004 2.5/3.3 V Differential LVPECL 1:9 Clock Distribution Buffer and Clock Divider The MC100ES6226 is a bipolar monolithic differential clock distribution buffer and clock divider. Designed for most demanding clock distribution systems, the MC100ES6226 supports various applications requiring a large number of outputs to drive precisely aligned clock signals. Using SiGe technology and a fully differential architecture, the device offers superior digital signal characteristics and very low clock skew error. Target applications for this clock driver are high performance clock distribution systems for computing, networking and telecommunication systems. Features * * * * * * * * * * * * * MC100ES6226 2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION BUFFER AND CLOCK DIVIDER Fully differential architecture from input to all outputs SiGe technology supports near-zero output skew Selectable 1:1 or 1:2 frequency outputs LVPECL compatible differential clock inputs and outputs LVCMOS compatible control inputs Single 3.3V or 2.5V supply Max. 35 ps maximum output skew (within output bank) Max. 50 ps maximum device skew Supports DC operation and up to 3 GHz (typ.) clock signals Synchronous output enable eliminating output runt pulse generation and metastability Standard 32-lead LQFP package Industrial temperature range 32-lead Pb-free Package Available FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description MC100ES6226 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0 GHz. Typical applications for the MC100ES6226 are primary clock distribution systems on backplanes of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. The MC100ES6226 can be operated from a 3.3 V or 2.5 V positive supply without the requirement of a negative supply line. Each of the output banks of three differential clock output pairs may be independently configured to distribute the input frequency or half of the input frequency. The FSEL0 and FSEL1 clock frequency selects are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the /2 outputs. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 723 MC100ES6226 VCC CLK CLK BANK A /1 /2 BANK B QA0 QA0 QA1 QA1 QA2 QA2 QB0 QB0 QB1 QB1 QB2 QB2 MR FSEL0 FSEL1 BANK C QC0 QC0 QC1 QC1 QC2 QC2 OE Sync Figure 1. MC100ES6226 Logic Diagram QB0 QB0 QB1 QB1 QB2 QB2 18 VCC 24 QA2 QA2 VCC QA1 QA1 QA0 QA0 VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 VCC 17 16 15 14 QC0 QC0 QC1 QC1 VCC QC2 QC2 VCC 13 12 11 10 9 8 MR MC100ES6226 2 3 4 5 6 7 CLK GND CLK VCC FSEL0 Figure 2. 32-Lead Package Pinout (Top View) 724 FSEL1 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA OE MC100ES6226 Table 1. Pin Configuration Pin CLK, CLK OE MR FSEL0, FSEL1 QA[0-2], QA[0-2] QB[0-2], QB[0-2] QC[0-2], QC[0-2] GND VCC I/O Input Input Input Input Output Type LVPECL LVCMOS LVCMOS LVCMOS LVPECL Differential reference clock signal input Output enable Device reset Output frequency divider select Differential clock outputs (banks A, B and C) Function Supply Supply GND VCC Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation Table 2. Function Table Control OE Default 0 0 1 Qx[0-2], Qx[0-2] are active. Deassertion of OE can be Qx[0-2] = L, Qx[0-2] =H (outputs disabled). Assertion asynchronous to the reference clock without generation of OE can be asynchronous to the reference clock of output runt pulses without generation of output runt pulses Normal operation See Table 3 Device reset (asynchronous) MR FSEL0, FSEL1 0 00 Table 3. Output Frequency Select Control FSEL0 0 0 1 1 FSEL1 0 1 0 1 QA0 to QA2 fQA0:2 = fCLK fQA0:2 = fCLK fQA0:2 = fCLK fQA0:2 = fCLK / 2 QB0 to QB2 fQB0:2 = fCLK fQB0:2 = fCLK fQB0:2 = fCLK / 2 fQB0:2 = fCLK / 2 QC0 to QC2 fQC0:2 = fCLK fQC0:2 = fCLK / 2 fQC0:2 = fCLK / 2 fQC0:2 = fCLK / 2 Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 725 MC100ES6226 Table 5. General Specifications Symbol VTT MM HBM CDM LU CIN JA Thermal Resistance Junction to Ambient JESD 51-3, single layer test board Characteristics Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up Immunity 200 2000 1000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 110 0 Min Typ VCC - 2 1 Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C Inputs Condition Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 JESD 51-6, 2S2P multilayer test board JC Thermal Resistance Junction to Case Operating Junction Temperature2 (continuous operation) MTBF = 9.1 years 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6226 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6226 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. 726 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6226 Table 6. DC Characteristics (VCC = 3.3 V 5% and 2.5 V 5%, TJ = 0C to +110C)1 Symbol Characteristics Min Typ Max Unit Condition LVCMOS Control Inputs (OE, FSEL0, FSEL1, MR) VIL VIH IIN Input voltage low Input voltage high Input Current2 VCC = 3.3 V VCC = 2.5 V VCC = 3.3 V VCC = 2.5 V 2.2 1.7 150 0.8 0.7 V V A VIN = VCC or VIN = GND LVPECL Clock Inputs (CLK, CLK)3 VPP VCMR VIH VIL IIN DC Differential Input Voltage4 Differential Cross Point Voltage5 Input High Voltage Input Low Voltage Input Current 0.1 1.0 TBD TBD 1.3 VCC - 0.3 TBD TBD 150 A VIN = TBD or VIN = TBD V V Differential operation Differential operation LVPECL Clock Outputs (QA[2:0], QB[2:0], QC[2:0]) VOH VOL Output High Voltage Output Low Voltage VCC - 1.1 VCC - 1.8 VCC - 0.8 VCC - 1.4 V V Termination 50 to VTT Termination 50 to VTT Supply Current IGND ICC 1. 2. 3. 4. 5. Maximum Quiescent Supply Current without Output Termination Current Maximum Quiescent Supply Current with Output Termination Current 65 325 110 400 mA mA GND pin All VCC pins AC characteristics are design targets and pending characterization. Input have internal pullup/pulldown resistors which affect the input current. Clock inputs driven by LVPECL compatible signals. VPP is the minimum differential input voltage swing required to maintain AC characteristic. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 727 MC100ES6226 Table 7. AC Characteristics (VCC = 3.3 V 5% and 2.5 V 5%, TJ = 0C to +110C)1, 2 Symbol VPP VCMR VX,OUT VO(P-P) Characteristics Differential Input Voltage3 (peak-to-peak) Differential Input Crosspoint Voltage4 Differential Output Crosspoint Voltage Differential Output Voltage (peak-to-peak) fO < 300 MHz fO < 1.5 GHz fO < 2.7 GHz Input Frequency Propagation Delay CLK to Qx[] Output-to-Output Skew (within QA[2:0]) (within QB[2:0]) (within QC[2:0]) (within device) (part-to-part) Min 0.2 1.0 VCC - 1.45 0.45 0.3 TBD 0 475 500 11 12 4 0.72 0.55 0.37 Typ 0.3 Max 1.3 VCC - 0.3 VCC - 1.1 0.95 0.95 0.95 30005 800 25 25 20 60 325 1 1 48 45 49 47.5 0.05 2.5T + tPD 3T + tPD 50 50 50 50 52 55 51 52.5 200 4.5T + tPD 5T + tPD % % % % ns ns ns 20% to 80% T=CLK period T=CLK period Unit V V V V V V MHz ps ps ps ps ps ps Differential Differential Condition fCLK tPD tsk(O) tsk(PP) tJIT(CC) Output-to-Output Skew Differential FSEL0 = FSEL1 FSEL0 FSEL1 DCfref= 50%7 Output Cycle-to-Cycle Jitter single frequency configuration /1//2 frequency configuration Output Duty Cycle Qx = /1, fO < 300 MHz Qx = /1, fO > 300 MHz Qx = /2, fO < 300 MHz Qx = /2, fO > 300 MHz DCO tr, tf tPDL 6 Output Rise/Fall Time Output Disable Time Output Enable Time tPLD7 1. 2. 3. 4. AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 5. The MC100ES6226 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz. 6. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high). 7. Propagation delay OE assertion to output enabled (active). CLK CLK 50% OE tPDL (OE to Qx) tPLD (OE to Qx) Outputs Disabled Qx Qx Figure 3. MC100ES6226 Output Disable/Enable Timing 728 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6226 Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT DUT MC100ES6226 RT = 50 VTT Figure 4. MC100ES6226 AC Test Reference APPLICATIONS INFORMATION Maintaining Lowest Device Skew The MC100ES6226 guarantees low output-to-output bank skew of 35 ps and a part-to-part skew of max. TBD ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6226 is a mixed analog/digital product. The differential architecture of the MC100ES6226 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VCC 33...100 nF 0.1 nF VCC MC100ES6226 Figure 5. VCC Power Supply Bypass FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 729 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6254 Rev 4, 08/2004 2.5/3.3 V Differential LVPECL 2x2 Clock Switch and Fanout Buffer The MC100ES6254 is a bipolar monolithic differential 2x2 clock switch and fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6254 supports various applications that require to drive precisely aligned clock signals. The device is capable of driving and switching differential LVPECL signals. Using SiGe technology and a fully differential architecture, the device offers superior digital signal characteristics and very low clock skew error. Target applications for this clock driver are high performance clock/data switching, clock distribution or data loopback in computing, networking and telecommunication systems. Features * * * * * * * * * * * Fully differential architecture from input to all outputs SiGe technology supports near-zero output skew Supports DC to 3GHz operation(1) of clock or data signals LVPECL compatible differential clock inputs and outputs LVCMOS compatible control inputs Single 3.3 V or 2.5 V supply 50 ps maximum device skew1 Synchronous output enable eliminating output runt pulse generation and metastability Standard 32 lead LQFP package Industrial temperature range 32-lead Pb-free Package Available MC100ES6254 2.5/3.3 V DIFFERENTIAL LVPECL 2x2 CLOCK SWITCH AND FANOUT BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description MC100ES6254 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0 GHz. Typical applications for the MC100ES6254 are primary clock distribution, switching and loopback systems of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. Primary purpose of the MC100ES6254 is high-speed clock switching applications. In addition, the MC100ES6254 can be configured as single 1:6 or dual 1:3 LVPECL fanout buffer for clock signals, or as loopback device in high-speed data applications. The MC100ES6254 can be operated from a 3.3 V or 2.5 V positive supply without the requirement of a negative supply line. 1. The device is functional up to 3 GHz and characterized up to 2.7 GHz. 730 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6254 VCC CLK0 CLK0 BANK A 0 1 QA0 QA0 QA1 QA1 QA2 QA2 VCC CLK1 CLK1 0 1 SEL0 SEL1 BANK B QB0 QB0 QB1 QB1 QB2 QB2 OEA OEB SYNC Figure 1. MC100ES6254 Logic Diagram CLK0 CLK0 SEL0 GND GND 18 OEA VCC 24 QA2 QA2 VCC QA1 QA1 VCC QA0 QA0 25 26 27 28 29 30 31 32 1 23 22 21 20 19 VCC 17 16 15 14 13 QB2 QB2 VCC QB1 QB1 VCC QB0 QB0 12 11 10 9 8 VCC MC100ES6254 2 3 4 5 6 7 VCC GND OEB Figure 2. 32-Lead Package Pinout (Top View) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA CLK1 CLK1 SEL1 GND 731 MC100ES6254 Table 1. Pin Configuration Pin CLK0, CLK0 CLK1, CLK1 OEA, OEB SEL0, SEL1 QA[0-2], QA[0-2] QB[0-2], QB[0-2] GND VCC I/O Input Input Input Input Output Supply Supply Type LVPECL LVPECL LVCMOS LVCMOS LVPECL GND VCC Differential reference clock signal input 0 Differential reference clock signal input 1 Output enable Clock switch select Differential clock outputs (banks A and B) Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation Function Table 2. Function Table Control OEA Default 0 0 QA[0-2], Qx[0-2] are active. Deassertion of OE can be asynchronous to the reference clock without generation of output runt pulses QA[0-2], Qx[0-2] are active. Deassertion of OE can be asynchronous to the reference clock without generation of output runt pulses 1 QA[0-2] = L, QA[0-2] = H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses QA[0-2] = L, QA[0-2] = H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses OEB 0 SEL0, SEL1 00 Refer to Table 4 Table 3. Clock Select Control SEL0 0 0 1 1 SEL1 0 1 0 1 CLK0 Routed to QA[0:2] and QB[0:2] -- QA[0:2] QB[0:2] CLK1 Routed to -- QA[0:2] and QB[0:2] QB[0:2] QA[0:2] Application Mode 1:6 fanout of CLK0 1:6 fanout of CLK1 Dual 1:3 buffer Dual 1:3 buffer (crossed) Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 732 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6254 Table 5. General Specifications Symbol VTT MM HBM CDM LU CIN JA Thermal resistance junction to ambient JESD 51-3, single layer test board Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up immunity 200 2000 1500 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 110 TA = -40 TJ = +110 Min Typ VCC-2 1 Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C C Inputs Condition Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 JESD 51-6, 2S2P multilayer test board JC Thermal resistance junction to case Operating junction temperature2 (continuous operation) MTBF = 9.1 years TFunc Functional temperature range 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 and the application section in this data sheet for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6254 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6254 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 733 MC100ES6254 Table 6. DC Characteristics (VCC = 3.3 V 5% or 2.5 V 5%, TJ = 0 to +110C) Symbol Characteristics Min Typ Max Unit Condition LVCMOS Control Inputs (OEA, OEB, SEL0, SEL1) VIL VIH IIN Input Voltage Low Input Voltage High Input Current 1 0.8 2.0 100 V V A VIN = VCC or VIN = GND -+ Clock Inputs (CLK0, CLK0, CLK1, CLK1) VPP VCMR AC differential input voltage2 Differential cross point voltage3 0.1 1.0 1.3 VCC-0.3 V V Differential operation Differential operation LVPECL Clock Outputs (QA0-2, QA0-2, QB0-2, QB0-2) VOH VOL Output High Voltage Output Low Voltage VCC = 3.3 V 5% VCC = 2.5 V 5% VCC-1.2 VCC-1.9 VCC-1.9 VCC-1.005 VCC-1.705 VCC-1.705 52 VCC-0.7 VCC-1.5 VCC-1.3 85 V V IOH = -30 mA4 IOL = -5 mA5 Supply Current IGND Maximum Quiescent Supply Current without output termination current mA GND pin 1. Inputs have internal pullup/pulldown resistors that affect the input current. 2. VPP is the minimum differential input voltage swing required to maintain AC characteristic. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 4. Equivalent to a termination 50 to VTT. 5. ICC calculation: ICC = (number of differential output pairs used) * (IOH + IOL) + IGND ICC = (number of differential output pairs used) * (VOH-VTT)/Rload +(VOL-VTT)/Rload) + IGND 734 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6254 Table 7. AC Characteristics (VCC = 3.3 V 5% or 2.5 V 5%, TJ = 0 to +110C)1 Symbol VPP VCMR VO(P-P) Characteristics Differential Input Voltage (peak-to-peak) Differential Input Crosspoint Voltage3 Differential Output Voltage (peak-to-peak) fO < 1.1 GHz fO < 2.5 GHz fO < 3.0 GHz Input Frequency Propagation Delay CLK, 1 to QA[] or QB[] Output-to-Output Skew Output-to-Output Skew Output Pulse Skew Output Duty Cycle Output Cycle-to-Cycle Jitter Output Rise/Fall Time Output Disable Time Output Enable Time 5 2 Min 0.3 1.2 0.45 0.35 0.20 0 360 Typ Max 1.3 VCC-0.3 Unit V V V V V Condition 0.7 0.55 0.35 30004 485 610 50 fCLK tPD tsk(O) tsk(PP) tSK(P) DCO tJIT(CC) tr, tf tPDL 6 MHz ps ps ps ps % % DCfref = 50% DCfref = 50% 20% to 80% T = CLK period T = CLK period Differential Differential Differential (part-to-part) 250 60 tREF < 100 MHz tREF < 800 MHz (SEL0 SEL1) 49.4 45.2 50.6 54.8 TBD 0.05 2.5T + tPD 3T + tPD 300 3.5T + tPD 4T + tPD ps ns ns tPLD7 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 4. The MC100ES6254 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz. 5. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. 6. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high). 7. Propagation delay OE assertion to output enabled (active). CLKX CLKX 50% OEX tPDL (OEX to Qx[]) tPLD (OEX to Qx[]) OUTPUTS DISABLED Qx[] Qx[] Figure 3. MC100ES6254 Output Disable/Enable Timing FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 735 MC100ES6254 DIFFERENTIAL PULSE GENERATOR Z = 50 ZO = 50 ZO = 50 RT = 50 VTT DUT MC100ES6254 RT = 50 VTT Figure 4. MC100ES6254 AC Test Reference APPLICATIONS INFORMATION Example Configurations 2 x 2 CLOCK SWITCH CLK0 CLK1 SEL0 SEL1 MC100ES6254 SEL0 SEL1 Switch Configuration 0 0 CLK0 clocks systems A and system B 0 1 CLK1 clocks system A and system B 1 0 CLK0 clocks system A and CLK1 clocks system B 1 1 CLK1 clocks system B and CLK1 clocks system A 1:6 CLOCK FANOUT BUFFER CLK0 CLK1 0 0 SEL0 SEL1 MC100ES6254 LOOPBACK DEVICE SYSTEM-Tx CLK0 SEL0 SEL1 SYSTEM-Rx QB[] CLK1 RECEIVER QA[] TRANSMITTER 3 SYSTEM A 3 SYSTEM B Understanding the Junction Temperature Range of the MC100ES6254 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6254, the MC100ES6254 is specified, characterized and tested for the junction temperature range of TJ = 0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this data sheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja Ptot Assuming a thermal resistance (junction to ambient) of 54.4C/W (2s2p board, 200 ft/min airflow, refer to Table 8) and a typical power consumption of 467 mW (all outputs terminated 50 to VTT, VCC = 3.3 V, frequency independent), the junction temperature of the MC100ES6254 is approximately TA + 24.5C, and the minimum ambient temperature in this example case calculates to -24.5C (the maximum ambient temperature is 85.5C, refer to Table 8). Exceeding the minimum junction temperature specification of the MC100ES6254 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6254 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Refer to the Application Note AN1545 for a power consumption calculation guideline. Table 8. Ambient Temperature Range (Ptot = 467 mW) Rthja (2s2p board) Natural Convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 59.0C/W 54.4C/W 52.5C/W 50.4C/W 47.8C/W TA, min1 -28C -25C -24.5C -23.5C -22C TA, max 82C 85C 85.5C 86.5C 88C MC100ES6254 SEL0 SEL1 Switch Configuration 0 0 System loopback 0 1 Line loopback 1 0 Transmit/Receive operation 1 1 System and line loopback 1. The MC100ES6254 device function is guaranteed from TA = -40C to TJ = 110C 736 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6254 Maintaining Lowest Device Skew The MC100ES6254 guarantees low output-to-output bank skew of 50 ps and a part-to-part skew of maximum 250 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6254 is a mixed analog/digital product. The differential architecture of the MC100ES6254 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VCC 33...100 nF 0.1 nF VCC MC100ES6254 Figure 5. VCC Power Supply Bypass FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 737 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES6535 Rev 2, 05/2004 3.3 V LVCMOS-to-LVPECL 1:4 Fanout Buffer The MC100ES6535 is a low skew, high performance 3.3 V 1-to-4 LVCMOS to LVPECL fanout buffer. The ES6535 has two selectable inputs that allow LVCMOS or LVTTL input levels which translate to LVPECL outputs. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. The ES6535 is ideal for high performance clock distribution applications. Features * * * * * * * * * 4 differential LVPECL outputs 2 selectable LVCMOS/LVTTL inputs 1 GHz maximum output frequency Translates LVCMOS/LVTTL levels to LVPECL levels 30 ps maximum output skew 190 ps part-to-part skew 3.3 V operating range 20-lead TSSOP package Ambient temperature range -40C to +85C MC100ES6535 DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-02 ORDERING INFORMATION Device MC100ES6535DT MC100ES6535DTR2 Package TSSOP-20 TSSOP-20 CLK_EN D Q LE VEE CLK_EN CLK_SEL 1 2 3 4 5 6 7 8 9 10 20 19 18 17 Q0 Q0 VCC Q1 Q1 Q2 Q2 VCC Q3 Q3 CLK0 0 Q0 Q0 CLK0 nc CLK1 NC NC NC CLK1 1 Q1 Q1 MC100ES6535 16 15 14 13 12 11 CLK_SEL Q2 Q2 Q3 Q3 VCC Figure 1. Logic Diagram Figure 2. 20-Lead Pinout (Top View) 738 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6535 Table 1. Pin Description Number 1 2 Name VEE CLK_EN Power Input Pullup1 Type Negative supply pin Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, Q outputs are forced high. LVCMOS/LVTTL interface levels Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input. LVCMOS/LVTTL interface levels LVCMOS/LVTTL clock input LVCMOS/LVTTL clock input No connect Positive supply pin LVPECL differential output pair LVPECL differential output pair LVPECL differential output pair LVPECL differential output pair Description 3 CLK_SEL Input Pulldown1 4 6 5, 7, 8, 9 10, 13, 18 11, 12 14, 15 16, 17 19, 20 CLK0 CLK1 NC VCC Q3, Q3 Q2, Q2 Q1, Q1 Q0, Q0 Input Input Unused Power Output Output Output Output Pulldown1 Pulldown1 1. Pullup and Pulldown refer to internal input resistors. Table 2. Control Input Function Table1 Inputs CLK_EN 0 0 1 1 CLK_SEL 0 1 0 1 Selected Source CLK0 CLK1 CLK0 CLK1 Q0:Q3 Disabled; LOW Disabled; LOW Enabled Enabled Outputs Q0:Q3 Disabled; HIGH Disabled; HIGH Enabled Enabled 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3. Table 3. Clock Input Function Table Inputs CLK0 or CLK1 0 1 Q0:Q3 LOW HIGH Outputs Q0:Q3 HIGH LOW FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 739 MC100ES6535 Table 4. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection JA Thermal Resistance (Junction-to-Ambient) Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Human Body Model Machine Model 0 LFPM, 20 TSSOP 500 LFPM, 20 TSSOP Value 75 k 75 k 4000 V 200 V 140C/W 100C/W Table 5. Absolute Maximum Ratings1 Symbol VSUPPLY VIN Power Supply Voltage Input Voltage Rating Conditions Difference between VCC & VEE VCC - VEE 3.6 V Rating 3.9 VCC +0.3 VEE -0.3 Iout TA Tstore Output Current Operating Temperature Range Storage Temperature Range Continuous Surge 50 100 -40 to +85 -65 to +150 Units V V V mA mA C C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 6. DC Characteristics (VCC = 3.135 V to 3.8 V; VEE = 0 V) -40C Symbol IEE VOH 1 0C to 85C Max 35 Min Typ Max 45 VCC -1200 VCC -2000 VCC -970 VCC -1680 VCC -750 VCC -1300 Unit mA mV mV Characteristic Power Supply Current Output HIGH Voltage Output LOW Voltage Min Typ VCC -1150 VCC -1950 VCC -1020 VCC -1620 VCC -800 VCC -1250 VOL 1. Outputs are terminated through a 50 resistor to VCC -2 volts. Table 7. LVTTL / LVCMOS Input DC Characteristics (VCC = 3.135 V to 3.8 V) Symbol IIN VIK VIH VIL Characteristic Input Current Input Clamp Voltage Input HIGH Voltage Input LOW Voltage Condition VIN = VCC IIN = -18 mA 2.0 -40C Min Typ Max 150 -1.2 VCC +0.3 0.8 2.0 Min 0C to 85C Typ Max 150 -1.2 VCC +0.3 0.8 Unit A V V V 740 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES6535 Table 8. AC Characteristics (VCC = 3.135 V to 3.8 V, VEE = 0 V) -40C Symbol fmax tPD tSKEW tJITTER VoutPP tr/tf Characteristic Maximum Toggle Frequency Propagation Delay to Output Differential Skew Output-to-Output Part-to-Part Cycle-to-Cycle JitterRMS (1) Output Peak-to-Peak Voltage Output Rise/Fall Time (20%-80% @ 50 MHz) 350 50 750 400 150 350 20 Min Typ Max 1 500 30 190 1 350 50 750 400 175 360 20 Min 25C Typ Max 1 550 30 190 1 350 50 750 400 200 380 20 Min 85C Typ Max 1 600 30 190 1 Unit GHz ps ps ps ps mV ps Q Driver Device Qb 50 50 D Receiver Device Db V TT Figure 3. Typical Termination for Output Driver and Device Evaluation FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 741 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES7011H Rev 0, 05/2004 Product Preview Low Voltage 1:2 Differential HSTL/LVDS-to-LVDS Clock Fanout Buffer The MC100ES7011H is a low voltage 1:2 Differential HSTL/LVDS to LVDS clock fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES7011H supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are in high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * 1:2 differential clock fanout buffer 50 ps maximum device skew SiGe Technology Supports DC to 1000 MHz operation LVDS compatible differential clock outputs HSTL/LVDS compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 8 lead SOIC package MC100ES7011H 1:2 DIFFERENTIAL HSTL/LVDS TO LVDS CLOCK FANOUT DRIVER D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 ORDERING INFORMATION Device MC100ES7011HD MC100ES7011HDR2 Package SO-8 SO-8 PIN DESCRIPTION VCC 1 Pin 8 Q0 D, D Qn, Qn D 2 7 Q0 VCC VEE Function HSTL/LVDS Data Inputs LVDS Data Outputs Positive Supply Negative Supply D 3 6 Q1 VEE 4 5 Q1 Figure 1. 8-Lead Pinout (Top View) and Logic Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. 742 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES7011H Table 1. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC Value TBD TBD TBD TBD JA Thermal Resistance (Junction to Ambient) Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 2. Absolute Maximum Ratings1 Symbol VSUPPLY VIN IOUT TA TSTG Parameter Power Supply Voltage Input Voltage Output Current Operating Temperature Range Storage Temperature Range Conditions Difference between VCC & VEE VCC - VEE 3.6V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 -40 to +85 -65 to +150 Unit V V V mA mA C C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. DC Characteristics (VCC = 3.3V5%; TJ = 0C to 110C)1 Symbol VDIF VX, IN VIH VIL IIN Characteristic Min Typ Max Unit Condition HSTL/LVDS differential input signals (D, D) Differential input voltage2 Differential cross point voltage3 Input high voltage Input low voltage Input current 0.2 0.25 VX + 0.1 VX - 0.1 150 0.68 - 0.9 VCC - 1.3 V V V V mA VIN = VX 0.1V LVDS clock outputs (Q[0:4], Q[0:4]) VPP VOS ICC Output differential voltage (peak-to-peak) Output offset voltage 250 1125 1275 mV mV LVDS LVDS VCC pin (core) Supply Current Maximum Quiescent Supply Current without output termination current TBD TBD mA 1. DC characteristics are design targets and pending characterization. 2. VDIF (DC) is the minimum differential HSTL/LVDS input voltage swing required for device functionality. 3. VX (DC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 743 MC100ES7011H Table 4. AC Characteristics (VCC = 3.3V5%; TJ = 0C to 110C)1 2 Symbol VDIF VX, IN fCLK tPD tSK(O) tSK(PP) tJIT(CC) DCO tr / tf Characteristic Min Typ Max Unit Condition HSTL/LVDS differential input signals (D, D) Differential input voltage (peak-to-peak)3 Differential cross point voltage4 Input Frequency Propagation Delay D to Q[0:1} 0.4 0.68 1000 1.275 TBD TBD V V MHz ps Differential Differential LVDS clock outputs (Q[0:1], Q[0:1]) Output-to-output skew Output-to-output skew (part-to-part) Output cycle-to-cycle jitter Output duty cycle Output Rise/Fall Times TBD 0.05 50 50 TBD TBD TBD TBD % ns DCfref = 50% 20% to 80% ps ps Differential Differential 1. AC characteristics are design targets and pending characterization. 2. AC characteristics apply for parallel output termination of 50 to VTT. 3. VDIF (AC) is the minimum differential HSTL/LVDS input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. 4. VX (AC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew. 744 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES7011H Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT=GND DUT MC100ES7011H RT = 50 VTT=GND Figure 2. MC100ES7011H AC Test Reference D D Q[0-1] Q[0-1] VDIF=0.6V VX=0.75V tPD (D to Q[0-1]) Figure 3. MC100ES7011H AC Reference Measurement Waveform (HSTL Input) D D Q[0-1] Q[0-1] VDIF=0.6V VX=1.2V tPD (D to Q[0-1]) Figure 4. MC100ES7011H AC Reference Measurement Waveform (LVDS Input) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 745 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES7011P Rev 0, 05/2004 Product Preview Low Voltage 1:2 Differential PECL Clock Fanout Buffer The MC100ES7011P is a low voltage 1:2 Differential PECL to LVDS clock fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES7011P supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are in high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * 1:2 differential clock fanout buffer 50 ps maximum device skew SiGe Technology Supports DC to 1000 MHz operation LVDS compatible differential clock outputs PECL compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 8 lead SOIC package MC100ES7011P 1:2 DIFFERENTIAL PECL TO LVDS CLOCK FANOUT DRIVER D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 ORDERING INFORMATION Device MC100ES7011PD MC100ES7011PDR2 Package SO-8 SO-8 PIN DESCRIPTION VCC 1 8 Q0 Pin D, D Qn, Qn D 2 7 Q0 VCC VEE D 3 6 Q1 Function ECL Data Inputs LVDS Data Outputs Positive Supply Negative Supply VEE 4 5 Q1 Figure 1. 8-Lead Pinout (Top View) and Logic Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. 746 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES7011P Table 1. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC Value TBD TBD TBD TBD JA Thermal Resistance (Junction to Ambient) Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 2. Absolute Maximum Ratings1 Symbol VSUPPLY VIN IOUT TA TSTG Parameter Power Supply Voltage Input Voltage Output Current Operating Temperature Range Storage Temperature Range Conditions Difference between VCC & VEE VCC - VEE 3.6V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 -40 to +85 -65 to +150 Unit V V V mA mA C C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. DC Characteristics (VCC = 3.3V5%; TJ = 0C to 110C)1 Symbol VPP VCMR VIH VIL IIN Characteristic Min Typ Max Unit Condition PECL differential input signals (D, D) Differential Input Voltage2 Differential Cross Point Voltage3 Input High Voltage Input Low Voltage Input Current 0.15 1.0 VCC - 1.165 VCC - 1.810 1.0 VCC - 0.6 VCC - 0.880 VCC - 1.475 150 V V V V mA VIN = VIH or VIN Differential Operation Differential Operation LVDS clock outputs (Q[0:1], Q[0:1]) VPP VOS ICC Output Differential Voltage (peak-to-peak) Output Offset Voltage 250 1125 1275 mV mV LVDS LVDS VCC pin (core) Supply Current Maximum Quiescent Supply Current without output termination current TBD TBD mA 1. DC characteristics are design targets and pending characterization. 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 747 MC100ES7011P Table 4. AC Characteristics (VCC = 3.3V5%; TJ = 0C to 110C)1 2 Symbol VPP VCMR fCLK tPD tSK(O) tSK(PP) tJIT(CC) DCO tr / tf 1. 2. 3. 4. Characteristic Min Typ Max Unit Condition PECL differential input signals (D, D) Differential Input Voltage (peak-to-peak)3 Differential Cross Point Voltage4 Input Frequency Propagation Delay D to Q[0:1] 0.2 1 1000 TBD 1.0 VCC - 0.6 V V MHz ps Differential Differential LVDS clock outputs (Q[0:1], Q[0:1]) Output-to-Output Skew Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Duty Cycle Output Rise/Fall Times TBD 0.05 50 50 TBD TBD TBD TBD % ns DCfref = 50% 20% to 80% ps ps Differential Differential AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. VCMR (AC) is the crosspoint of the differential PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 748 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES7011P Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT=GND DUT MC100ES7011P RT = 50 VTT=GND Figure 2. MC100ES7011P AC Test Reference D D Q[0-1] Q[0-1] VDIF=0.8V VCMR=VCC-1.3V tPD (D to Q[0-1]) Figure 3. MC100ES7011P AC Reference Measurement Waveform (PECL Input) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 749 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES7014 Rev 1, 05/2004 Product Preview Low Voltage 1:5 Differential LVDS Clock Fanout Buffer The MC100ES7014 is a LVDS differential clock fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES7014 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are in high performance clock distribution in computing, networking and telecommunication systems. The MC100ES7014 is designed for low skew clock distribution systems and supports clock frequencies up to 1000MHz. The device accepts two clock sources. The CLK0 input accepts LVDS or HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 5 identical, differential LVDS compatible outputs. Features * * * * * * * * * 1:5 differential clock fanout buffer 50 ps maximum device skew SiGe Technology Supports DC to 1000 MHz operation LVDS compatible differential clock outputs PECL and HSTL/LVDS compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 20 lead TSSOP package MC100ES7014 1:5 DIFFERENTIAL LVDS CLOCK FANOUT DRIVER DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-02 ORDERING INFORMATION Device MC100ES7014DT MC100ES7014DTR2 Package TSSOP-20 TSSOP-20 VCC 20 NC 19 VEE 18 CLK1 CLK1 17 16 EN 15 CLK0 CLK0 CLK_SEL VCC 14 13 12 11 1 0 1 Q0 2 Q0 3 Q1 Q 4 Q1 D 5 Q2 6 Q2 7 Q3 8 Q3 9 Q4 10 Q4 Figure 1. 20-Lead Pinout (Top View) and Logic Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. 750 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES7014 Table 1. Pin Description Pin CLK0, CLK0 CLK1, CLK1 Q[0:4], Q[0:4] CLK_SEL EN VCC VEE nc Function HSTL/LVDS Data Inputs PECL Data Inputs LVDS Data Outputs LVCMOS Active Clock Select Input LVCMOS Sync Enable Positive Supply Negative Supply no connect Table 2. Function Table Control CLK_SEL EN Default 0 0 0 CLK0, CLK0 (HSTL/LVDS) is the active differential clock input Q[0:4], Q[0:4] are active. Deassertion of EN can be asynchronous to the reference clock without generation of output runt pulses. 1 CLK1, CLK1 (PECL) is the active differential clock input Q[0:4] = L, Q[0:4] = H (outputs disabled). Assertion of EN can be asynchronous to the reference clock without generation of output runt pulses. Table 3. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC Value TBD TBD TBD TBD JA Thermal Resistance (Junction to Ambient) Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 4. Absolute Maximum Ratings1 Symbol VSUPPLY VIN IOUT TA TSTG Parameter Power Supply Voltage Input Voltage Output Current Operating Temperature Range Storage Temperature Range Conditions Difference between VCC & VEE VCC - VEE 3.6V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 -40 to +85 -65 to +150 Unit V V V mA mA C C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 751 MC100ES7014 Table 5. DC Characteristics (VCC = 3.3V5%; TJ = 0C to 110C)1 Symbol VDIF VX, IN VIH VIL IIN Characteristic Min Typ Max Unit Condition HSTL/LVDS differential input signals (CLK0, CLK0) Differential Input Voltage2 Differential Cross Point Voltage3 Input High Voltage Input Low Voltage Input Current 0.2 0.25 VX + 0.1 VX - 0.1 150 0.68 - 0.9 VCC - 1.3 V V V V mA VIN = VX 0.1V PECL differential input signals (CLK1, CLK1) VPP VCMR VIH VIL IIN Differential input Voltage4 Differential Cross Point Voltage5 Input High Voltage Input Low Voltage Input Current 0.15 1.0 VCC - 1.165 VCC - 1.810 1.0 VCC - 0.6 VCC - 0.880 VCC - 1.475 150 V V V V mA VIN = VIH or VIN Differential Operation Differential Operation LVCMOS control inputs EN, CLK_SEL VIL VIH IIN Input Low Voltage Input High Voltage Input Current 2.0 150 0.8 V V mA VIN = VIH or VIN LVDS clock outputs (Q[0:4], Q[0:4]) VPP VOS ICC Output Differential Voltage (peak-to-peak) Output Offset Voltage 250 1125 1275 mV mV LVDS LVDS VCC pin (core) Supply Current Maximum Quiescent Supply Current without output termination current TBD TBD mA 1. DC characteristics are design targets and pending characterization. 2. VDIF (DC) is the minimum differential HSTL/LVDS input voltage swing required for device functionality. 3. VX (DC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 4. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 5. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 752 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES7014 Table 6. AC Characteristics (VCC = 3.3V5%; TJ = 0C to 110C)1 2 Symbol VDIF VX, IN fCLK tPD VPP VCMR fCLK tPD tSK(O) tSK(PP) tJIT(CC) DCO tr / tf tPDL tPLD Characteristic Min Typ Max Unit Condition HSTL/LVDS differential input signals (CLK0, CLK0) Differential Input Voltage (peak-to-peak)3 Differential Cross Point Voltage4 Input Frequency Propagation Delay 0.4 0.68 1000 1.275 TBD TBD V V MHz ps Differential Differential PECL differential input signals (CLK1, CLK1) Differential Input Voltage (peak-to-peak)5 Differential Cross Point Voltage6 Input Frequency Propagation Delay 0.2 1 1000 TBD 1.0 VCC - 0.6 V V MHz ps Differential Differential LVDS clock outputs (Q[0:4], Q[0:4]) Output-to-Output Skew Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Duty Cycle Output Rise/Fall Times Output Disable Time 7 50 TBD TBD TBD 0.05 2.5*T +tPD 3*T +tPD 50 TBD TBD 3.5*T +tPD 4*T +tPD ps ps Differential Differential % ns ns ns DCfref = 50% 20% to 80% T = CLK period T = CLK period Output Enable Time8 1. AC characteristics are design targets and pending characterization. 2. AC characteristics apply for parallel output termination of 50 to VTT. 3. VDIF (AC) is the minimum differential HSTL/LVDS input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. 4. VX (AC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. 5. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. 6. VCMR (AC) is the crosspoint of the differential PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 7. Propagation delay EN deassertion to differential output disabled (differential low: true output low, complementary output high). 8. Propagation delay EN assertion to output enabled (active). FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 753 MC100ES7014 CLKx CLKx 50% EN tPDL (EN to Qx[]) tPLD (EN to Qx[]) Outputs disabled Qx[] Qx[] Figure 2. MC100ES7014 AC Test Reference Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT=GND DUT MC100ES7014 RT = 50 VTT=GND Figure 3. MC100ES7014 AC Test Reference CLK0 CLK0 Q[0-4] Q[0-4] tPD (CLK0 to Q[0-4]) CLK1 VX=0.75V CLK1 Q[0-4] Q[0-4] tPD (CLK1 to Q[0-4]) VDIF=0.6V VDIF=0.8V VCMR=VCC-1.3V Figure 4. MC100ES7014 AC Reference Measurement Waveform (HSTL Input) CLK0 CLK0 Q[0-4] Q[0-4] Figure 5. MC100ES7014 AC Reference Measurement Waveform (PECL Input) VDIF=0.6V VX=1.2V tPD (CLK0 to Q[0-4]) Figure 6. MC100ES7014 AC Reference Measurement Waveform (LVDS Input) 754 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES7111 Rev 0, 12/2002 Preliminary Information Low Voltage 1:10 Differential LVDS Clock Fanout Buffer The MC100ES7111 is a LVDS differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES7111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * 1:10 differential clock fanout buffer 50 ps maximum device skew1 SiGe technology Supports DC to 1000 MHz operation(1) of clock or data signals LVDS compatible differential clock outputs PECL and HSTL/LVDS compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 32-lead LQFP package MC100ES7111 LOW VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK FANOUT DRIVER FA SUFFIX 32-LEAD TQFP PACKAGE CASE 873A-03 Functional Description The MC100ES7111 is designed for low skew clock distribution systems and supports clock frequencies up to 1000 MHz1. The device accepts two clock sources. The CLK0 input accepts LVDS or HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 10 identical, differential LVDS compatible outputs. The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a 7x7 mm2 32-lead LQFP package. 1. AC specifications are design targets and subject to change FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 755 MC100ES7111 Q3 Q3 Q4 Q4 Q5 Q5 Q6 18 VCC CLK0 CLK0 0 VCC CLK1 CLK1 1 OE CLK_SEL Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 24 VCC Q2 Q2 Q1 Q1 Q0 Q0 VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 Q6 17 16 15 14 VCC Q7 Q7 Q8 Q8 Q9 Q9 VCC 13 12 11 10 9 8 GND MC100ES7111 2 3 4 5 6 7 CLK_SEL VCC CLK0 CLK0 OE CLK1 1 Figure 1. MC100ES7111 Logic Diagram Figure 2. 32-Lead Package Pinout (Top View) Table 1. Pin Configuration Pin CLK0, CLK0 CLK1, CLK1 CLK_SEL OE Q[0-9], Q[0-9] GND VCC I/O Input Input Input Input Output Supply Supply PECL LVCMOS LVCMOS LVDS Type HSTL/LVDS Function Differential HSTL or LVDS reference clock signal input Differential PECL reference clock signal input Reference clock input select Output enable/disable. OE is synchronous to the input reference clock which eliminates possible output runt pulses when the OE state is changed. Differential clock outputs Negative power supply Positive power supply of the device (3.3V) Table 2. Function Table Control CLK_SEL OE Default 0 0 0 CLK0, CLK0 (HSTL/LVDS) is the active differential clock input CLK1, CLK1 (PECL) is the active differential clock input Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of Q[0-9], Q[0-9] are active. Deassertion of OE can be asynchronous to the reference clock without generation OE can be asynchronous to the reference clock of output runt pulses. without generation of output runt pulses. 756 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA CLK1 OE MC100ES7111 Table 3. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS TFunc Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Functional Temperature Range -65 TA = -40 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 TJ = +110 Unit V V V mA mA C C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol MM HBM CDM LU CIN JA Characteristics ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up Immunity Input Capacitance Thermal Resistance Junction to Ambient JESD 51-3, single layer test board Min 200 2000 TBD 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Typ Max Unit V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC TJ Thermal Resistance Junction to Case Operating Junction Temperature1 (continuous operation) MTBF = 9.1 years 110 C 1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 and the application section in this data sheet for more information). The device AC and DC parameters are specified up to 110xC junction temperature allowing the MC100ES7111 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES7111 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 757 MC100ES7111 Table 5. DC Characteristics (VCC = 3.3V 5%, TJ = 0C to +110C)1 Symbol Characteristics Min Typ Max Unit Condition Clock Input Pair CLK0, CLK0 (HSTL/LVDS differential signals) VDIF VX, IN VIH VIL IIN Differential Input Voltage2 Differential Cross Point Voltage3 Input High Voltage Input Low Voltage Input Current 0.2 0.25 VX+0.1 VX-0.1 150 0.68 - 0.9 VCC-1.3 V V V V mA VIN = VX 0.1V Clock input pair CLK1, CLK1 (PECL differential signals) VPP VCMR VIH VIL IIN Differential Input Voltage4 Differential Cross Point Voltage5 Input Voltage High Input Voltage Low Input Current1 0.15 1.0 VCC-1.165 VCC-1.810 1.0 VCC-0.6 VCC-0.880 VCC-1.475 150 V V V V mA VIN = VIH or VIN Differential operation Differential operation LVCMOS Control Inputs OE, CLK_SEL VIL VIH IIN Input Voltage Low Input Voltage High Input Current 2.0 150 0.8 V V mA VIN = VIH or VIN LVDS clock outputs (Q[0-9], Q[0-9]) VPP VOS Output Differential Voltage (peak-to-peak) Output Offset Voltage 250 1125 1275 mV mV LVDS LVDS Supply current ICC Maximum Quiescent Supply Current without Output Termination Current TBD TBD mA VCC pin (core) 1. DC characteristics are design targets and pending characterization. 2. VDIF (DC) is the minimum differential HSTL/LVDS input voltage swing required for device functionality. 3. VX (DC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 4. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 5. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 758 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES7111 Table 6. AC Characteristics (VCC = 3.3 V 5%, TJ = 0C to 110C)1 2 Symbol VDIF VX, IN fCLK tPD VPP VCMR fCLK tPD tsk(O) tsk(PP) tJIT(CC) DCO tr, tf tPDL7 tPLD8 1. 2. 3. 4. 5. 6. Characteristics Differential Input Voltage3 (peak-to-peak) Differential Cross Point Voltage4 Input Frequency Propagation Delay CLK0 to Q[0-9] Min 0.4 0.68 1000 1.275 TBD TBD Typ Max Unit V V MHz ps Condition Clock input pair CLK0, CLK0 (HSTL/LVDS differential signals) Clock input pair CLK1, CLK1 (PECL differential signals) Differential Input Voltage5 (peak-to-peak) Differential Input Cross Point Voltage6 Input Frequency Propagation Delay CLK1 to Q[0-9] 0.2 1 1000 TBD 1.0 VCC-0.6 V V MHz ps Differential Differential LVDS clock outputs (Q[0-9], Q[0-9]) Output-to-Output Skew Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time TBD 0.05 2.5T + tPD 3T + tPD 50 50 TBD TBD TBD TBD 3.5T + tPD 4T + tPD % ns ns ns DCfref = 50% 20% to 80% T = CLK period T = CLK period ps ps Differential Differential 7. 8. AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. VDIF (DC) is the minimum differential HSTL/LVDS input voltage swing required for device functionality. VX (DC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VDIF (DC) specification. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high). Propagation delay OE assertion to output enabled (active). FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 759 MC100ES7111 CLKx CLKx 50% OE tPDL (OE to Qx[]) tPLD (OE to Qx[]) Outputs disabled Qx[] Qx[] Figure 3. MC100ES7111 AC Test Reference ZO = 50 ZO = 50 RT = 100 DUT MC100ES7111 Differential Pulse Generator Z = 50 RT = 50 VTT=GND Figure 4. MC100ES7111 AC Test Reference CLK0 CLK0 CLK1 VX=0.75V CLK1 VDIF=0.6V VPP=0.8V VCMR=VCC-1.3V Q[0-9] Q[0-9] tPD (CLK0 to Q[0-9]) Q[0-9] Q[0-9] tPD (CLK1 to Q[0-9]) Figure 5. MC100ES7111 AC Reference Measurement Waveform (HSTL Input) CLK0 CLK0 Figure 6. MC100ES7111 AC Reference Measurement Waveform (PECL Input) VDIF=0.6V VX=1.2V Q[0-9] Q[0-9] tPD (CLK0 to Q[0-9]) Figure 7. MC100ES7111 AC Reference Measurement Waveform (LVDS Input) 760 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES8011H Rev 0, 05/2004 Product Preview Low Voltage 1:2 Differential HSTL Clock Fanout Buffer The MC100ES8011H is a low voltage 1:2 Differential HSTL fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES8011H supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are in high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * 1:2 differential clock fanout buffer 50 ps maximum device skew SiGe Technology Supports DC to 400 MHz operation HSTL compatible differential clock outputs HSTL compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 8 lead SOIC package MC100ES8011H 1:2 DIFFERENTIAL HSTL CLOCK FANOUT DRIVER D SUFFIX 8 LEAD SOIC PACKAGE CASE 751-06 ORDERING INFORMATION Device MC100ES8011HD MC100ES8011HDR2 Package SO-8 SO-8 VCC 1 8 Q0 Pin D, D PIN DESCRIPTION Function HSTL Data Inputs HSTL Data Outputs Positive Supply Negative Supply D2 7 Q0 Qn, Qn VCC VEE D3 6 Q1 VEE 4 5 Q1 Figure 1. 8-Lead Pinout (Top View) and Logic Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 761 MC100ES8011H Table 1. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC Value TBD TBD TBD TBD JA Thermal Resistance (Junction to Ambient) Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 2. Absolute Maximum Ratings1 Symbol VSUPPLY VIN IOUT TA TSTG Parameter Power Supply Voltage Input Voltage Output Current Operating Temperature Range Storage Temperature Range Conditions Difference between VCC & VEE VCC - VEE 3.6V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 -40 to +85 -65 to +150 Unit V V V mA mA C C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. DC Characteristics (VCC = 3.3 V 5%; TJ = 0C to 110C)1 Symbol VDIF VX, IN VIH VIL IIN Characteristic Min Typ Max Unit Condition HSTL differential input signals (D, D) Differential Input Voltage2 Differential Cross Point Voltage3 Input High Voltage Input Low Voltage Input Current 0.2 0.25 VX + 0.1 VX - 0.1 150 0.68 - 0.9 VCC - 1.3 V V V V mA VIN = VX 0.1V HSTL clock outputs (Q[0:1], Q[0:1]) VX, OUT VOH VOL ICC Output Differential Crosspoint Output High Voltage Ouput Low Voltage 0.68 1 0.4 0.75 0.9 V V V VCC pin (core) Supply Current Maximum Quiescent Supply Current without output termination current TBD TBD mA 1. DC characteristics are design targets and pending characterization. 2. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 762 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES8011H Table 4. AC Characteristics (VCC = 3.3 V 5%; TJ = 0C to 110C)1 2 Symbol VDIF VX, IN fCLK tPD VX, OUT VOH VOL VO(P-P) tSK(O) tSK(PP) tJIT(CC) DCO tr / tf 1. 2. 3. 4. Characteristic Min Typ Max Unit Condition HSTL differential input signals (D, D) Differential Input Voltage (peak-to-peak)3 Differential Cross Point Voltage4 Input Frequency Propagation Delay D to Q[0:1} 0.4 0.68 0 - 400 0.9 TBD TBD V V MHz ps Differential Differential HSTL clock outputs (Q[0:1], Q[0:1]) Output Differential Crosspoint Output High Voltage Ouput Low Voltage Differential Output Voltage (peak-to-peak) Output-to-Output Skew Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Duty Cycle Output Rise/Fall Times TBD 0.05 50 0.5 50 TBD TBD TBD TBD % ns DCfref = 50% 20% to 80% 0.68 1 0.5 0.75 0.9 V V V V ps ps Differential Differential AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. VX (AC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 763 MC100ES8011H Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT=GND DUT MC100ES8011H RT = 50 VTT=GND Figure 2. MC100ES8011H AC Test Reference D D Q[0-1] Q[0-1] VDIF=1.0V VX=0.75V tPD (D to Q[0-1]) Figure 3. MC100ES8011H AC Reference Measurement Waveform (HSTL Input) 764 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES8011P Rev 0, 05/2004 Product Preview Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer The MC100ES8011P is a low voltage 1:2 Differential PECL-to-HSTL clock fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES8011P supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are in high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * 1:2 differential clock fanout buffer 50 ps maximum device skew SiGe Technology Supports DC to 400 MHz operation HSTL compatible differential clock outputs PECL compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 8 lead SOIC package MC100ES8011P 1:2 DIFFERENTIAL PECL TO HSTL CLOCK FANOUT DRIVER D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 ORDERING INFORMATION Device MC100ES8011PD MC100ES8011PDR2 Package SO-8 SO-8 VCC 1 8 Q0 Pin D, D PIN DESCRIPTION Function ECL Data Inputs LVDS Data Outputs Positive Supply Negative Supply D 2 7 Q0 Qn, Qn VCC VEE D 3 6 Q1 VEE 4 5 Q1 Figure 1. 8-Lead Pinout (Top View) and Logic Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 765 MC100ES8011P Table 1. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC Value TBD TBD TBD TBD JA Thermal Resistance (Junction to Ambient) Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 2. Absolute Maximum Ratings1 Symbol VSUPPLY VIN IOUT TA TSTG Parameter Power Supply Voltage Input Voltage Output Current Operating Temperature Range Storage Temperature Range Conditions Difference between VCC & VEE VCC - VEE 3.6V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 -40 to +85 -65 to +150 Unit V V V mA mA C C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. DC Characteristics (VCC = 3.3 V 5%; TJ = 0C to 110C)1 Symbol VPP VCMR VIH VIL IIN Characteristic Min Typ Max Unit Condition PECL differential input signals (D, D) Differential Input Voltage2 Differential Cross Point Voltage3 Input High Voltage Input Low Voltage Input Current 0.15 1.0 VCC - 1.165 VCC - 1.810 1.0 VCC - 0.6 VCC - 0.880 VCC - 1.475 150 V V V V mA VIN = VIH or VIN Differential Operation Differential Operation HSTL clock outputs (Q[0:1], Q[0:1]) VX, OUT VOH VOL ICC Output Differential Crosspoint Output High Voltage Ouput Low Voltage 0.68 1 0.4 0.75 0.9 V V V VCC pin (core) Supply Current Maximum Quiescent Supply Current without output termination current TBD TBD mA 1. DC characteristics are design targets and pending characterization. 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 766 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES8011P Table 4. AC Characteristics (VCC = 3.3 V 5%; TJ = 0C to 110C)1 2 Symbol VPP VCMR fCLK tPD VX, OUT VOH VOL VO(P-P) tSK(O) tSK(PP) tJIT(CC) DCO tr / tf tPDL tPLD Characteristic Min Typ Max Unit Condition PECL differential input signals (D, D) Differential Input Voltage (peak-to-peak)3 Differential Cross Point Voltage4 Input Frequency Propagation Delay D to Q[0:1] 0.2 1 0 - 400 TBD 1.0 VCC - 0.6 V V MHz ps Differential Differential HSTL clock outputs (Q[0:1], Q[0:1]) Output Differential Crosspoint Output High Voltage Ouput Low Voltage Differential Output Voltage (peak-to-peak) Output-to-Output Skew Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Duty Cycle Output Rise/Fall Times Output Disable Time 5 0.68 1 0.75 0.9 V V 0.5 0.5 50 TBD TBD TBD 0.05 2.5*T +tPD 3*T +tPD 50 TBD TBD 3.5*T +tPD 4*T +tPD V V ps ps Differential Differential % ns ns ns DCfref = 50% 20% to 80% T = CLK period T = CLK period Output Enable Time6 1. AC characteristics are design targets and pending characterization. 2. AC characteristics apply for parallel output termination of 50 to VTT. 3. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. 4. VCMR (AC) is the crosspoint of the differential PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 5. Propagation delay EN deassertion to differential output disabled (differential low: true output low, complementary output high). 6. Propagation delay EN assertion to output enabled (active). FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 767 MC100ES8011P Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT=GND DUT MC100ES8011P RT = 50 VTT=GND Figure 2. MC100ES8011P AC Test Reference D D Q[0-1] Q[0-1] VDIF=0.8V VCMR=VCC-1.3V tPD (D to Q[0-1]) Figure 3. MC100ES8011P AC Reference Measurement Waveform (PECL Input) 768 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES8014 Rev 0, 05/2004 Product Preview Low Voltage 1:5 Differential LVDS Clock Fanout Buffer The MC100ES8014 is a HSTL differential clock fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES8014 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are in high performance clock distribution in computing, networking and telecommunication systems. The MC100ES8014 is designed for low skew clock distribution systems and supports clock frequencies up to 400MHz. The device accepts two clock sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 5 identical, differential HSTL compatible outputs. Features * * * * * * * * * 1:5 differential clock fanout buffer 50 ps maximum device skew SiGe Technology Supports DC to 400 MHz operation 1.5V HSTL compatible differential clock outputs PECL and HSTL compatible differential clock inputs 3.3V power supply for device core, 1.5V or 1.8V HSTL output supply Supports industrial temperature range Standard 20 lead TSSOP package MC100ES8014 1:5 DIFFERENTIAL HSTL CLOCK FANOUT DRIVER DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-02 ORDERING INFORMATION Device MC100ES8014DT MC100ES8014DTR2 Package TSSOP-20 TSSOP-20 VCCO 20 NC 19 VEE 18 CLK1 CLK1 17 16 EN 15 CLK0 CLK0 CLK_SEL VCC 14 13 12 11 1 0 1 Q0 2 Q0 3 Q1 Q 4 Q1 D 5 Q2 6 Q2 7 Q3 8 Q3 9 Q4 10 Q4 Figure 1. 20-Lead Pinout (Top View) and Logic Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 769 MC100ES8014 Table 1. Pin Description Pin CLK0, CLK0 CLK1, CLK1 Q[0:4], Q[0:4] CLK_SEL EN VCC VCCO VEE nc Function HSTL Data Inputs PECL Data Inputs HSTL Data Outputs LVCMOS Active Clock Select Input LVCMOS Sync Enable Positive Supply of device core (3.3V) Positive power supply of the HSTL outputs. All VCCO pins must be connected to the positive power supply (1.5V or 1.8V) for correct DC and AC operation. Negative Supply no connect Table 2. Function Table Control CLK_SEL EN Default 0 0 0 CLK0, CLK0 (HSTL) is the active differential clock input Q[0:4], Q[0:4] are active. Deassertion of EN can be asynchronous to the reference clock without generation of output runt pulses. 1 CLK1, CLK1 (PECL) is the active differential clock input Q[0:4] = L, Q[0:4] = H (outputs disabled). Assertion of EN can be asynchronous to the reference clock without generation of output runt pulses. Table 3. General Specifications Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC Value TBD TBD TBD TBD JA Thermal Resistance (Junction to Ambient) Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 4. Absolute Maximum Ratings1 Symbol VSUPPLY VIN IOUT TA TSTG Parameter Power Supply Voltage Input Voltage Output Current Operating Temperature Range Storage Temperature Range Conditions Difference between VCC & VEE VCC - VEE 3.6V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 -40 to +85 -65 to +150 Unit V V V mA mA C C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 770 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES8014 Table 5. DC Characteristics (VCC = 3.3 V 5%; TJ = 0C to 110C)1 Symbol VDIF VX, IN VIH VIL IIN Characteristic Min Typ Max Unit Condition HSTL differential input signals (CLK0, CLK0) Differential Input Voltage2 Differential Cross Point Voltage3 Input High Voltage Input Low Voltage Input Current 0.2 0.25 VX + 0.1 VX - 0.1 150 0.68 - 0.9 VCC - 1.3 V V V V mA VIN = VX 0.1V PECL differential input signals (CLK1, CLK1) VPP VCMR VIH VIL IIN Differential Input Voltage4 Differential Cross Point Voltage5 Input High Voltage Input Low Voltage Input Current 0.15 1.0 VCC - 1.165 VCC - 1.810 1.0 VCC - 0.6 VCC - 0.880 VCC - 1.475 150 V V V V mA VIN = VIH or VIN Differential Operation Differential Operation LVCMOS control inputs EN, CLK_SEL VIL VIH IIN Input Low Voltage Input High Voltage Input Current 2.0 150 0.8 V V mA VIN = VIH or VIN HSTL clock outputs (Q[0:4], Q[0:4]) VX, OUT VOH VOL ICC ICCO Output Differential Crosspoint Output High Voltage Ouput Low Voltage 0.68 1 0.4 0.75 0.9 V V V VCC pin (core) VCCO pin (outputs) Supply Current Maximum Quiescent Supply Current without output termination current Maximum Quiescent Supply Current, outputs terminated 50 to VTT TBD TBD TBD TBD mA mA 1. DC characteristics are design targets and pending characterization. 2. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 4. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 5. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 771 MC100ES8014 Table 6. AC Characteristics (VCC = 3.3 V 5%; TJ = 0C to 110C)1 2 Symbol Characteristic Min Typ Max Unit Condition HSTL/LVDS differential input signals (CLK0, CLK0) VDIF VX, IN fCLK tPD Differential Input Voltage (peak-to-peak)3 Differential Cross Point Voltage4 Input Frequency Propagation Delay 0.4 0.68 0 - 400 0.9 TBD TBD V V MHz ps Differential Differential PECL differential input signals (CLK1, CLK1) VPP VCMR fCLK tPD VX, OUT VOH VOL VO(P-P) tSK(O) tSK(PP) tJIT(CC) DCO tr / tf tPDL tPLD 1. 2. 3. 4. Differential Input Voltage (peak-to-peak)5 Differential Cross Point Voltage6 Input Frequency Propagation Delay 0.2 1 0 - 400 TBD 1.0 VCC - 0.6 V V MHz ps Differential Differential HSTL clock outputs (Q[0:4], Q[0:4]) Output Differential Crosspoint Output High Voltage Ouput Low Voltage Differential Output Voltage (peak-to-peak) Output-to-Output Skew Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Duty Cycle Output Rise/Fall Times Output Disable Time7 Output Enable Time8 TBD 0.05 2.5*T +tPD 3*T +tPD 50 0.5 50 TBD TBD TBD TBD 3.5*T +tPD 4*T +tPD % ns ns ns DCfref = 50% 20% to 80% T = CLK period T = CLK period 0.68 1 0.5 0.75 0.9 V V V V ps ps Differential Differential 5. 6. 7. 8. AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VX (AC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. Propagation delay EN deassertion to differential output disabled (differential low: true output low, complementary output high). Propagation delay EN assertion to output enabled (active). 772 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES8014 CLKx CLKx 50% EN tPDL (EN to Qx[]) tPLD (EN to Qx[]) Outputs disabled Qx[] Qx[] Figure 2. MC100ES8014 AC Test Reference Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT=GND DUT MC100ES8014 RT = 50 VTT=GND Figure 3. MC100ES8014 AC Test Reference CLK0,1 CLK0,1 VDIF=1.0V CLK0,1 VX=0.75V CLK0,1 VPP=0.8V VCMR=VCC-1.3V Q[0-4] Q[0-4] tPD (CLK0,1 to Q[0-4]) Q[0-4] Q[0-4] tPD (CLK0,1 to Q[0-4]) Figure 4. MC100ES8014 AC Reference Measurement Waveform (HSTL Input) Figure 5. MC100ES8014 AC Reference Measurement Waveform (PECL Input) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 773 Freescale Semiconductor, Inc. TECHNICAL DATA Order number: MC100ES8111 Rev 1, 08/2004 Preliminary Information Low Voltage 1:10 Differential HSTL Clock Fanout Buffer The MC100ES8111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES8111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * 1:10 differential clock fanout buffer 50 ps maximum device skew1 SiGe technology Supports DC to 400 MHz operation1 of clock or data signals 1.5V HSTL compatible differential clock outputs PECL and HSTL compatible differential clock inputs 3.3V power supply for device core, 1.5V or 1.8V HSTL output supply Supports industrial temperature range Standard 32 lead LQFP package MC100ES8111 LOW-VOLTAGE 1:10 DIFFERENTIAL HSTL CLOCK FANOUT DRIVER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MC100ES8111 is designed for low skew clock distribution systems and supports clock frequencies up to 400 MHz1. The device accepts two clock sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 10 identical, differential HSTL compatible outputs. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all 10 outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The HSTL compatible output levels are generated with an open emitter architecture. This minimizes part-to-part and output-tooutput skew. The open-emitter outputs require a 50 DC termination to GND (0 V). The output supply voltage can be either 1.5 V or 1.8 V, the core voltage supply is 3.3 V. The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a 7x7 mm2 32-lead LQFP package. 1. AC specifications are design targets and subject to change 774 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES8111 Q3 Q3 Q4 Q4 Q5 Q5 Q6 18 VCC CLK0 CLK0 0 VCC CLK1 CLK1 1 OE CLK_SEL Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 24 VCCO Q2 Q2 Q1 Q1 Q0 Q0 VCCO 25 26 27 28 29 30 31 32 1 23 22 21 20 19 Q6 17 16 15 14 VCC0 Q7 Q7 Q8 Q8 Q9 Q9 VCCO 13 12 11 10 9 8 GND MC100ES8111 2 3 4 5 6 7 CLK_SEL VCC CLK0 CLK0 OE CLK1 1 Figure 1. MC100ES8111 Logic Diagram Figure 2. 32-Lead Package Pinout (Top View) Table 1. Pin Configuration Pin CLK0, CLK0 CLK1, CLK1 CLK_SEL OE Q[0-9], Q[0-9] GND VCC VCCO I/O Input Input Input Input Output Supply Supply Supply HSTL PECL LVCMOS LVCMOS HSTL Type Function Differential HSTL reference clock signal input Differential PECL reference clock signal input Reference clock input select Output enable/disable. OE is synchronous to the input reference clock which eliminates possible output runt pulses when the OE state is changed. Differential clock outputs Negative power supply Positive power supply of the device core (3.3V) Positive power supply of the HSTL outputs. All VCCO pins must be connected to the positive power supply (1.5 V or 1.8 V) for correct DC and AC operation. Table 2. Function Table Control CLK_SEL OE Default 0 0 0 CLK0, CLK0 (HSTL) is the active differential clock input CLK1, CLK1 (PECL) is the active differential clock input Q[0-9], Q[0-9] are active. Deassertion of OE can be Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of asynchronous to the reference clock without generation OE can be asynchronous to the reference clock of output runt pulses. without generation of output runt pulses. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA CLK1 OE 775 MC100ES8111 Table 3. Absolute Maximum Ratings1 Symbol VCC VCCO VIN VOUT IIN IOUT TS TFunc Supply Voltage Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Functional Temperature Range -65 TA = -40 Characteristics Min -0.3 -0.3 -0.3 -0.3 Max 3.6 3.1 VCC + 0.3 VCC + 0.3 20 50 125 TJ = +110 Unit V V V V mA mA C C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol VTT MM HBM CDM LU CIN JA Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up Immunity Input Capacitance Thermal resistance junction to ambient JESD 51-3, single layer test board 200 2000 TBD 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ 0 Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC TJ Thermal Resistance Junction to Case Operating Junction Temperature1 (continuous operation) MTBF = 9.1 years 110 C 1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 and the application section in this datasheet for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES8111 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES8111 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. 776 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES8111 Table 5. DC Characteristics (VCC = 3.3 V5%, VCCO = 1.5 V0.1 V or VCCO = 1.8 V0.1 V, TJ = 0C to +110C)1 Symbol Characteristics Min Typ Max Unit Condition Clock input pair CLK0, CLK0 (HSTL differential signals) VDIF VX, IN VIH VIL IIN Differential Input Voltage2 Differential Cross Point Voltage3 Input High Voltage Input Low Voltage Input Current 0.2 0.25 VX+0.1 VX-0.1 150 0.68 - 0.9 VCC-1.3 V V V V mA VIN = VX 0.1V Clock input pair CLK1, CLK1 (PECL differential signals) VPP VCMR VIH VIL IIN Differential Input Voltage4 Differential Cross Point Voltage5 Input Voltage High Input Voltage Low Input Current1 0.15 1.0 VCC-1.165 VCC-1.810 1.0 VCC-0.6 VCC-0.880 VCC-1.475 150 V V V V mA VIN = VIH or VIN Differential operation Differential operation LVCMOS control inputs OE, CLK_SEL VIL VIH IIN Input Voltage Low Input Voltage High Input Current 2.0 150 0.8 V V mA VIN = VIH or VIN HSTL clock outputs (Q[0-9], Q[0-9]) VX, OUT VOH VOL Output Differential Crosspoint Output High Voltage Output Low Voltage 0.68 1 0.4 0.75 0.9 V V V Supply current ICC ICCO6 Maximum Quiescent Supply Current without output termination current Maximum Quiescent Supply Current, outputs terminated 50 to VTT 100 TBD TBD TBD mA mA VCC pin (core) VCCO pins (outputs) 1. DC characteristics are design targets and pending characterization. 2. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 4. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 5. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 6. ICC includes current through the output resistors (all outputs terminated to VTT). FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 777 MC100ES8111 Table 6. AC Characteristics (VCC = 3.3 V5%, VCCO = 1.5 V 1 V or VCCO = 1.8 V 0.1 V, TJ = 0C to +110C)1, 2 Symbol Characteristics Min Typ Max Unit Condition Clock input pair CLK0, CLK0 (HSTL differential signals) VDIF VX, IN fCLK tPD Differential Input Voltage (peak-to-peak)3 Differential Cross Point Voltage4 Input Frequency Propagation Delay CLK0 to Q[0-9] 0.4 0.68 0-400 0.9 TBD TBD V V MHz ps Clock input pair CLK1, CLK1 (PECL differential signals) VPP VCMR fCLK tPD Differential Input Coltage (peak-to-peak)5 Differential Input Crosspoint Voltage6 Input Frequency Propagation Delay CLK1 to Q[0-9] 0.2 1 0-400 TBD 1.0 VCC-0.6 V V MHz ps Differential Differential HSTL clock outputs (Q[0-9], Q[0-9]) VX, OUT VOH VOL VO(P-P) tsk(O) tsk(PP) tJIT(CC) DCO tr, tf tPDL7 tPLD8 1. 2. 3. 4. 5. 6. Output Differential Crosspoint Output High Voltage Output Low Voltage Differential Output Voltage (peak-to-peak) Output-to-Output Skew Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time TBD 0.05 2.5T + tPD 3T + tPD 50 0.5 50 TBD TBD TBD TBD 3.5T + tPD 4T + tPD % ns ns ns DCfref= 50% 20% to 80% T=CLK period T=CLK period 0.68 1 0.5 0.75 0.9 V V V V ps ps Differential Differential 7. 8. AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VDIF (DC) specification. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high). Propagation delay OE assertion to output enabled (active). 778 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA MC100ES8111 CLKx CLKx 50% OE tPDL (OE to Qx[]) tPLD (OE to Qx[]) Outputs disabled Qx[] Qx[] Figure 3. MC100ES8111 AC Test Reference Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT=GND DUT MC100ES8111 RT = 50 VTT=GND Figure 4. MC100ES8111 AC Test Reference CLK0,1 CLK0,1 VDIF=1.0V CLK0,1 VX=0.75V CLK0,1 VPP=0.8V VCMR=VCC-1.3V Q[0-9] Q[0-9] tPD (CLK0,1 to Q[0-9]) Q[0-9] Q[0-9] tPD (CLK0,1 to Q[0-9]) Figure 5. MC100ES8111 AC Reference Measurement Waveform (HSTL Input) Figure 6. MC100ES8111 AC Reference Measurement Waveform (PECL Input) FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 779 MC100ES8111 END 780 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Chapter Nine Packaging Information The packaging information for each device type can be determined in one of two ways: by the specific case number indicated on the individual data sheet (for example, the case number for MPC9600 is 932), or by using the Case Dimensions Cross-Reference Tables provided at the beginning of this chapter. Case dimension information is presented in numerical order; by case number. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 781 Case Dimension Cross-Reference Tables Table 1. Clock Generators Device MC88915T MC88LV915T MC88LV926 MPC9315 MPC9330 MPC9331 MPC9350 MPC9351 MPC93H51 MPC93R51 MPC9352 MPC93H52 MPC93R52 MPC9600 MPC9772 MPC9773 MPC97H73 MPC9774 MPC97H74 MPC992 MPC9992 Package 28 PLCC 28 PLCC 20 SOIC 32 LQFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 52 LQFP 52 LQFP 52 LQFP 52 LQFP 52 LQFP 32 LQFP 32 LQFP Case Number 776-02 776-02 751D-06 873A-03 873A-03 873A-03 873A-03 873A-03 873A-03 873A-03 873A-03 873A-03 873A-03 932-03 848D-03 848D-03 848D-03 848D-03 848D-03 873A-03 873A-03 Page 787 787 786 789 789 789 789 789 789 789 789 789 789 790 788 788 788 788 788 789 789 MPC92459 MPC926508 MPC9994 MPC92432 MPC92439 MPC92430 MPC9239 MPC92429 MPC9230 MC12430 MC12439 MPC9229 Table 4. Clock Synthesizers Device MC12429 Package 28 PLCC 32 LQFP 32 LQFP 28 PLCC 28 PLCC 32 LQFP 28 PLCC 32 LQFP 28 PLCC 28 PLCC 32 LQFP 28 PLCC 32 LQFP 32 LQFP 28 PLCC 32 LQFP 32 LQFP 20 LQFP 32 LQFP Case Number 776-02 873A-03 873A-03 776-02 776-02 873A-03 776-02 873A-03 776-02 776-02 873A-03 776-02 873A-03 932-03 776-02 873A-03 873A-03 1461-01 873A-03 Page 787 789 789 787 787 789 787 789 787 787 789 787 789 790 787 789 789 795 789 Table 5. Zero-Delay Buffers Device Package 32 LQFP 32 LQFP 32 LQFP 8 SOIC 8 SOIC 8 TSSOP 16 SOIC 16 TSSOP Case Number 873A-03 873A-03 873A-03 751-06 751-06 948J-01 751B-05 948F-01 751B-05 948F-01 873A-03 873A-03 873A-03 1544-01 1545-01 Page 789 789 789 784 784 793 785 792 785 792 789 789 789 797 798 MPC9608 Table 2. QUICCClock Generators Device MPC9817 MPC9850 MPC9855 Package 20 SSOP 20 LQFP 20 LQFP Case Number 1461-01 1462-01 1462-01 Page 795 796 796 MPC961C MPC961P MPC962304 MPC962305 Table 3. Failover or Redundant Clock Device MPC9892 MPC9893 MPC9894 MPC9895 MPC9993 MPC99J93 Package 32 LQFP 48 LQFP 100 MAPBGA 100 MAPBGA 32 LQFP 32 LQFP Case Number 873A-03 932-03 1462-01 1462-01 873A-03 873A-03 Page 789 790 796 796 789 789 MPC9653 MPC9653A MPC9658 MPC96877 MPC962308 16 SOIC 16 TSSOP 32 LQFP 32 LQFP 32 LQFP 52 MAPBGA 40 MLF/QFN 782 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Case Dimension Cross-Reference Tables (continued) Table 6. LVCMOS Fanout Buffers Device MPC905 MPC9109 MPC940L MPC941 MPC942C MPC942P MPC9443 MPC9446 MPC9447 MPC9448 MPC9449 MPC94551 MPC9456 Package 16 SOIC 32 QFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 32 LQFP 52 LQFP 8 SOIC 32 LQFP Case Number 751B-05 873A-03 873A-03 932-03 873A-03 873A-03 932-03 873A-03 873A-03 873A-03 848D-03 751-06 873A-03 Page 785 789 789 790 789 789 790 789 789 789 788 784 789 MC100ES6210 MC100ES6220 MC100ES6221 MC100ES6222 MC100ES6226 MC100ES6254 MC100ES6535 MC100ES7011H MC100ES7011P MC100ES7014 MC100ES7111 MC100ES8011H MC100ES8011P MC100ES8014 MC100ES8111 MC100ES6111 MC100ES6130 MC100ES6139 MC100ES60T22 MC100ES60T23 MC100ES6030 MC100ES6039 MC100ES6056 Table 7. Differential Fanout Buffers Device MC100ES6011 MC100ES6014 Package 8 SOIC 20 SOIC 20 TSSOP 8 SOIC 8 SOIC 20 SOIC 20 SOIC 20 SOIC 20 TSSOP 32 LQFP 16 TSSOP 20 TSSOP 20 SOIC 32 LQFP 52 LQFP 52 LQFP 52 LQFP 32 LQFP 32 LQFP 20 TSSOP 8 SOIC 8 SOIC 20 TSSOP 32 LQFP 8 SOIC 8 SOIC 20 TSSOP 32 LQFP Case Number 751-06 751D-06 948E-02 751-06 751-06 751D-06 751D-06 751D-06 948E-02 873A-03 948F-01 948E-02 751D-06 873A-03 1336A-01 1336A-01 1336A-01 873A-03 873A-03 948E-02 751-06 751-06 948E-02 873A-03 751-06 751-06 948E-02 873A-03 Page 784 786 791 784 784 786 786 786 791 789 792 791 786 789 794 794 794 789 789 791 784 784 791 789 784 784 791 789 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 783 Case Dimensions D SUFFIX PLASTIC 8 SOIC PACKAGE CASE 751-06 ISSUE T A 8 D 5 C E 1 4 H 0.25 M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0 7 h B C e A SEATING PLANE X 45 L 0.10 A1 B 0.25 M CB S A S DIM A A1 B C D E e H h L q STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3 COLLECTOR STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3 COLLECTOR #2 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3 DRAIN #2 STYLE 4: PIN 1. ANODE 2. ANODE 3 ANODE 784 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Case Dimensions D SUFFIX PLASTIC 16 SOIC PACKAGE CASE 751B-05 ISSUE K 0.25 PIN'S NUMBER 1 8X M B A 6.2 5.8 16 1.75 1.35 0.25 0.10 16X 0.49 0.35 0.25 6 M TAB PIN 1 INDEX 14X 1.27 10.0 4 9.8 A A NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62MM. 8 9 T 4.0 3.8 5 0.50 0.25 B 16X SEATING PLANE 0.1 T X45 0.25 0.19 1.25 0.40 SECTION A-A 7 0 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 785 Case Dimensions D SUFFIX PLASTIC 20 SOIC PACKAGE CASE 751D-06 ISSUE H 10X PIN NUMBER 10.55 10.05 0.25 M B 2.65 2.35 A 0.25 0.10 20X 1 20 0.49 0.35 0.25 6 M TAB PIN 1 INDEX 18X 1.27 A 4 12.95 12.65 A 10 11 T 20X SEATING PLANE 7.6 7.4 5 B 0.1 T 0.75 X45 0.25 0.32 0.23 1.0 0.4 SECTION A-A 7 0 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE WIDTH TO EXCEED 0.62 MM. 786 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Case Dimensions FN SUFFIX PLASTIC 28 PLCC PACKAGE CASE 776-02 ISSUE D B -NY BRK U D Z -L-M0.007 (0.180) M 0.007 (0.180) M T L-M S N S S T L-M N S W 28 1 D V X G1 0.010 (0.250) S T L-M S N S VIEW D-D A Z R C 0.007 (0.180) M 0.007 (0.180) M T L-M T L-M S N S S H 0.007 (0.180) M T L-M S N S N S E 0.004 (0.100) G G1 0.010 (0.250) S K1 J -TVIEW S SEATING PLANE K F 0.007 (0.180) VIEW S M T L-M S N S T L-M S N S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXISTS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DEMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASITC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MILLIMETERS MAX MIN MAX MIN 12.57 0.485 0.495 12.32 12.57 0.485 0.495 12.32 4.20 4.57 0.165 0.180 2.29 2.79 0.090 0.110 0.33 0.48 0.013 0.019 0.050 BSC 1.27 BSC 0.81 0.026 0.032 0.66 --0.51 --0.020 0.64 --0.025 --0.450 0.456 11.43 11.58 11.58 0.450 0.456 11.43 0.042 0.048 1.07 1.21 0.048 1.07 1.21 0.042 0.042 0.056 1.07 1.42 --0.020 --0.50 2 10 2 10 10.92 0.410 0.430 10.42 0.040 --1.02 --- CASE 776-02 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 787 Case Dimensions FA SUFFIX PLASTIC 52 LQFP PACKAGE CASE 848D-03 ISSUE D 4X 4X 13 TIPS 0.20 (0.008) H L-M N 0.20 (0.008) T L-M N -XX=L, M, N 52 1 40 39 C L AB G 3X VIEW Y -L- -MB V AB VIEW Y F BASE METAL B1 13 14 26 27 V1 PLATING J D 0.13 (0.005) M U A1 S1 A S -N- T L-M S N S SECTION AB-AB ROTATED 90 CLOCKWISE C -H-TSEATING PLANE 4X 2 0.10 (0.004) T 4X 3 VIEW AA 0.05 (0.002) S NOTES: 1. CONTROLLING DIMENSIONS: MILLIMETER. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSTION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0 7 --0 12 REF 12 REF INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0 7 --0 12 REF 12 REF W 1 C2 2X R R1 0.25 (0.010) GAGE PLANE K C1 E Z VIEW AA DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3 CASE 848D-03 788 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Case Dimensions FA SUFFIX PLASTIC 32 LQFP PACKAGE CASE 873A-03 ISSUE B 4X 6 D1 PIN 1 INDEX 0.20 H A-B D e/2 3 A, B, D D1/2 32 25 1 E1/2 A 6 E1 DETAIL G 8 B E E/2 4 F F 17 DETAIL G NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. 7 9 D D 4 D/2 4X 0.20 C A-B D H 28X e 32X 0.1 C SEATING PLANE C DETAIL AD PLATING BASE METAL b1 c c1 b 8X 5 8 (1) R R2 R R1 0.20 M C A-B D SECTION F-F A A2 0.25 GAUGE PLANE A1 (S) (L1) L DETAIL AD DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 q q1 R1 R2 S MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0 7 12 REF 0.08 0.20 0.08 --0.20 REF FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 789 Case Dimensions FA SUFFIX PLASTIC 32 LQFP PACKAGE CASE 932-03 ISSUE F 4X 0.200 AB T-U Z 9 A1 48 37 A DETAIL Y P 1 36 T B B1 12 25 U V AE V1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5m, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLAN AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATAUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL AE NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0 7 12 REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF 13 24 Z S1 S 4X T, U, Z DETAIL Y 0.200 AC T-U Z AB G 0.080 AC AD AC BASE METAL M TOP & BOTTOM R 0.250 C F D 0.080 M N J E AC T-U Z H W DETAIL AD AA K L SECTION AE-AE 790 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA GAUGE PLANE Case Dimensions DT SUFFIX PLASTIC 20 TSSOP PACKAGE CASE 948E-02 ISSUE A 20X K REF M 0.15 (0.006) T U S 0.10 (0.004) TU S V S K K1 2X L/2 20 11 L PIN 1 IDENT B -U10 J J1 SECTION N-N 0.25 (0.010) N 0.15 (0.006) T U S A -VN M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND BE ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 F DETAIL E C D 0.100 (0.004) -T- SEATING PLANE -WG H DETAIL E DIM A B C D F G H J J1 K K1 L M INCHES MIN MAX 0.252 0.260 0.169 0.177 0.047 --0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 8 0 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 791 Case Dimensions DT SUFFIX PLASTIC 16 TSSOP PACKAGE CASE 948F-01 ISSUE O K 0.15 (0.006) T U S 16X REF M 0.10 (0.004) TU S V S K K1 2X L/2 16 9 J1 B -USECTION N-N J L PIN 1 IDENT. 1 8 N 0.25 (0.010) 0.15 (0.006) T U S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. A -VN F DETAIL E M DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 C 0.10 (0.004) -TSEATING PLANE -W- H D G DETAIL E CASE 948F 01 792 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Case Dimensions DT SUFFIX PLASTIC 8 TSSOP PACKAGE CASE 948J-01 ISSUE O K 0.15 (0.006) T U S 8x REF M 0.10 (0.004) TU S V S K 2X L/2 8 K1 5 J J1 L PIN 1 IDENT. 1 4 B -USECTION N-N N 0.25 (0.010) 0.15 (0.006) T U S A -VN F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. M DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 _ 8_ INCHES MIN MAX 0.114 0.122 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 _ 8_ C 0.10 (0.004) -TSEATING PLANE -WG H D SEE DETAIL E CASE 948J-01 ISSUE O FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 793 Case Dimensions FA SUFFIX PLASTIC 52 LQFP EXPOSED PAD PACKAGE CASE 1336A-01 ISSUE O 4X 4X 13 TIPS 0.2 H A-B D D PIN 1 INDEX 1 52 40 39 0.2 C A-B D 7 1.5 1.3 0.05 B 10 6 12 5 6 6 4 X 4 0.20 R 0.08 (0.2) 0 MIN 0.20 R 0.08 0.25 GAUGE PLANE A 0.20 0.05 0.75 0.45 (1) VIEW AA 7 0 13 14 26 27 X=A, B OR D 5 6 64 10 6 12 4 C L B B VIEW Y 48X 0.65 H 1.7 MAX 4X (12) VIEW AA 52X 8 (0.3) BASE METAL 0.1 C 8 J C SEATING PLANE 0.40 52X 0.22 5 0.08 M C A-B D 4X (12) J PLATING 0.20 0.09 0.35 0.20 SECTION B-B 0.16 0.07 8 8 4.78 4.58 4.78 4.58 EXPOSED PAD VIEW Y NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSION TO BE DETERMINED AT SEATING PLANE C. 5. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 mm. 6. THIS DIMENSION DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. THIS DIMENSION IS MAXIMUM PLSTIC BODY SIZE DIMENSION INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP. VIEW J-J 794 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Case Dimensions SD SUFFIX PLASTIC 20 LQFP SSOP PACKAGE CASE 1461-01 ISSUE O .236 .157 .150 PIN 1 ID 5 D 4 .061 .055 18X 1 20 .025 B 4 B B 4 A .0125 .344 .337 5 C L 10 11 .118 2X 10 TIPS 2X 3 .003 H A-B D H C 20X SEATING PLANE .010 C A-B D .004 C 7 A NOTES: 1. DIMENSIONS ARE IN INCHES. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUM PLANE H LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE. 4. DATUM A, B AND D TO BE DETRMINED WHERE CENTERLINE BETWEEN LEADS EXITS PLASTIC BODY AT DATUM PLANE H. 5. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006 INCHES FOR ENDS AND .008 INCHES FOR SIDES. 6. THIS DIMENSION IS LENGTH OF TERMINAL FOR SOLDERING A SUBSTRATE. 7. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN .004 INCHES AT SEATING PLANE. 8. THIS DIMENSION IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY. A 0 (.010) .010 .007 .012 .008 .007 M MIN BASE METAL R.003 MIN (.008) .010 GAUGE PLANE PLATING .0098 .0040 8 C A-B D 8 0 .035 .016 6 SECTION A-A SECTION B-B CASE 1461 01 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 795 Case Dimensions VF SUFFIX 100 MAP PBGA PACKAGE CASE 1462-01 ISSUE O 11 A1 INDEX AREA B C K NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGING. 11 TOP VIEW 4X 0.2 SIDE VIEW 9X 1 0.5 5 0.35 A (1.18) K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 100X 9X 1 1.7 MAX 0.43 0.29 0.5 0.55 0.45 0.25 0.10 3 M M 4 A SEATING PLANE 100X 0.12 A DETAIL K ABC A ROTATED 90 CLOCKWISE A1 INDEX AREA BOTTOM VIEW CASE 1462-01 ISSUE O DATE 11/26/02 796 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Case Dimensions VK SUFFIX 52-BALL FP-MAPBGA NON-LEADED PACKAGE CASE 1544-01 ISSUE O 4.5 B C A1 INDEX AREA 52X 0.1 A A SEATING PLANE 4 0.1 A 7 5 0.1 A TOP VIEW 5X ALL AROUND NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A. THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. 0.65 0.325 9X K J H G F E 0.65 0.325 D C B A 1 2 3 4 5 6 52X 0.35 0.25 (0.65) 1 MAX 0.45 0.35 3 ABC A A1 INDEX AREA 0.15 M 0.08 M SIDE VIEW BOTTOM VIEW FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 797 Case Dimensions EP SUFFIX 40-PIN MLF/QFN PACKAGE CASE 1545-01 ISSUE O 6 PIN 1 INDEX AREA A DETAIL G 5.75 2X 7 8 0.1 C 2X M 0.1 C 6 5.75 2X 12 0.1 C M B 2X 0.1 C 3.05 2.75 31 40 1 EXPOSED DIE ATTACH PAD DETAIL M 0.60 7 0.24 6 30 0.25 3.05 2.75 36X 21 40X 0.30 20 10 11 40X 40X 0.5 0.60 0.24 (0.45) 7 BACKSIDE PIN 1 INDEX 0.5 (R0.2) (0.4) 0.18 0.1 M M CAB C VIEW M-M 0.3 DETAIL M PREFERRED BACKSIDE PIN 1 INDEX 0.05 0.9 0.90 0.8 0.75 (0.2) 0.70 MAX 7 7 0.5 C 6 0.05 0.00 (0.25) C (0.5) SEATING PLANE DETAIL G VIEW ROTATED 90 CW NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. MAXIMUM PACKAGE WARPAGE IS 0.05 mm. 4. MAXIMUMALLWABLE BURRS IS 0.0706 mm IN ALL DIRECTIONS. 5. THIS DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THIS DIMENSION SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 6. COPLANARITY APPLIES TO LEADS, CORNER LEADS AND DIE ATTACH PAD. 7. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL. 8. THE PIN #1 IDENTIFIER MUST BE EXISTED ON THE TOP SURFACE OF THE PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF PACKAGE BODY. 9. DIE THICKNESS ALLOWABLE IS 0.3.05 mm MAXIMUM. 798 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Chapter Ten Application Notes Application Notes Document Number Page Document Number Page AN1091 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 AN1405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 AN1406 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 AN1545 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 AN1934 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 AN1939 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 AN1993 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 799 Freescale Semiconductor, Inc. APPLICATION NOTE Order number: AN1091 Rev 4, 09/2001 AN1091 Low Skew Clock Drivers and Their System Design Considerations ABSTRACT This application note addresses various system design issues to help ensure that Motorola's low skew clock drivers are used effectively in a system environment. Several varieties of clock drivers with 1 ns or less skew from output-to-output are available from Motorola. Microprocessorbased systems are now running at 33 MHz and beyond, and system clock distribution at these frequencies mandate the use of low skew clock drivers. Unfortunately, just plugging a high performance clock driver into a system does not guarantee trouble free operation. Only careful board layout and consideration of system noise issues can guarantee reliable clock distribution. This application note addresses these system design issues to help ensure that Motorola's low skew clock drivers are used effectively in a system environment. for clock distribution or clock `uncertainty,' which is an unacceptable penalty from a system designer's point of view. At 50 MHz this penalty becomes 25%. A maximum of 10% of the period allotted for clock distribution is an acceptable standard. If multiple levels of clock distribution (one clock driver's output feeding the inputs of several other clock drivers) are necessary due to large clock fan-outs, the additional part-to-part skew variations add even more to the clock uncertainty. Standard logic has always been specified with a large (and conservative) delta between the minimum and maximum propagation delays. This delta creates the excessive amount of clock `uncertainty' which the system designer has been forced to design into his system, even though it is not realistic. When system frequencies were below 16 MHz this large clock penalty could be tolerated, but as the above example points out, not anymore. A clock driver's specs guarantee this min/max delta to be a specific, small value. To reduce the clock overhead to manageable levels, a clock driver with minimal variation (<5%) from a 50% duty cycle and guaranteed low output-to-output and part-to-part skew must be used. INTRODUCTION With frequencies regularly reaching 33 MHz and approaching 40-50 MHz in today's CISC and RISC microprocessor systems, well controlled and precise clock signals are required to maintain a synchronous system. Many microprocessors also require input clock duty cycles very close to 50%. These stringent timing requirements mandate the use of specially designed, low skew clock distribution circuits or `clock drivers.' However, just plugging one of these parts into your board does not ensure a trouble free system. Careful system and board design techniques must be used in conjunction with a low skew clock driver to meet system timing requirements and provide clean clock signals. Why are Low Skew Clock Drivers Necessary An MPU system designer wants to utilize as much of a clock cycle as possible without adding unnecessary timing guardbands. Propagation delays of peripheral logic do not scale with frequency. Therefore, as the clock period decreases, the system designer has less time but the same logic delays to accomplish the function. How can he get more time? A viable option is to use a special clock source that minimizes clock `uncertainty.' A simple example illustrates this concept. At 33 MHz, tcycle = 30 ns. An FCT240A, for example, has a High-Low uncertainty of the min/max spread of tPLH to tPHL of approximately 3.3 ns. If 1.7 ns of pin-to-pin skew due to the actual part and PCB trace delays is also considered, then only 25 ns of the clock period is still available. The worst case tP of clock-to-data valid on the 88200 M-Bus is 12 ns, which leaves only 13 ns to accomplish additional functions. In this case 17% of a cycle is required DEFINITIONS A typical clock driver has a single input which is usually driven by a crystal oscillator. The clock driver can have any number of outputs which have a certain frequency relationship to the clock input. Clock driver skew is typically defined by three different specs. These specs are graphically illustrated in Figure 1. The first spec, tOS, measures the difference between the fastest and slowest propagation delays (any transition) between the outputs of a single part. This number must be 1ns or less for high-end systems. The second, tPS, measures the difference between the high-to-low and low-to-high transition for a single output (pin). This spec defines how close to a 50% duty cycle the outputs of the clock driver will be. For example, if this spec is 1 ns (0.5 ns), at 33 MHz the output duty cycle is 50% 3.5%. A clock driver which only buffers the crystal input, creating a 1:1 input to output frequency relationship, can be a problem if a very tight tolerance to a 50% duty cycle is required. In this situation the output duty cycle is directly dependent on the input duty cycle, which is not well controlled in most crystal oscillators. The clock driver's outputs switching at half the input frequency (/2) is a common relationship, which means that the outputs switch on only one edge of the oscillator, eliminating the output's dependence on the duty cycle of the input (crystal oscillator frequency is very stable). 800 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1091 66 MHz tPLH 33 MHz tOS 33 MHz tPV 33 MHz Notes: 1) tPS measures |tPLH-tPHL| for any single output on a part. 2) tOS measures the maximum difference between any tPHL or tPLH between any output on a single part. tPHL CLOCK INPUT PART #1 Q1 PART #1 Qn PART #1 Qn 3) tPV measures the maximum difference between any tPHL or tPLH between any output on any part. Figure 1. Timing Diagram Depicting Clock Skew Specs Within One Part and Between Any Two Parts The third spec, tPV, measures the maximum propagation delay delta between any given pin on any part. This spec defines the part to part variation between any clock driver (of the same device type) which is ever shipped. This number reflects the process variation inherent in any technology. For CMOS, this spec is usually 3 ns or less. High performance ECL technologies can bring this number down into the 1-2 ns range. Another way to minimize the part-to-part variation is to use a phase-locked loop clock driver, which are just now becoming available. An important consideration when designing a clock driver into a system is that the skew specs described above are usually specified at a fixed, lumped capacitive load. In a real system environment the clock lines usually have various loads distributed over several inches of PCB trace which can contribute additional delay and sometimes act like transmission lines, so the system designer must use careful board layout techniques to minimize the total system skew. In other words, just plugging a low skew clock driver into a board will not solve all your timing problems. for simplicity's sake all calculations in this article will assume a microstrip line. The equations in Figure 3 are valid only for an unloaded trace; loading down a line will increase its delay and lower its impedance. The signal propagation delay (tPD) and characteristic impedance (ZO) due to a loaded trace are calculated by the following formulas: tPD = tPD ZO = 1+ Cd CO ZO 1+ Cd CO Cd is the distributed load capacitance per unit length, which is the total input capacitance of the receiving devices divided by the length of the trace. CO is the intrinsic capacitance of the trace, which is defined as: CO = tPD ZO DESIGN CONSIDERATIONS Figure 2 is a scale replication of a section of an actual 88000 RISC system board layout. The section shown in Figure 2 includes the MC88100 MPU and the MC88200 CMMU devices and the MC88914 CMOS clock driver. The only PCB traces shown are the clock output traces from the MC88914 to the various loads. For this clock driver the output-to-output skew (tOS) is guaranteed to be less than 1 ns at any given temperature, supply voltage, and fixed load up to 50 pF. In calculating the total system skew, the difference in clock PCB trace length and loading must be taken into account. For an unloaded PCB trace, the signal delay per unit length, tPD, is dependent only on the dielectric constant, er. of the board material. The characteristic impedance, ZO, of the line is dependent upon er and the geometry of the trace. These relationships are depicted in Figure 3 for a microstrip line.1 The formulas for tPD and ZO are slightly different for other types of strip lines, but Assuming typical microstrip dimensions and characteristics as w = 0.01 in, t = 0.002 in, h = 0.012 in, and er = 4.7, the equations of Figure 3 yield ZO = 69.4 and tPD = 0.144 ns/in CO is then calculated as 2.075 pF/in. If it is assumed that an MC88100 or 88200 clock input load is 15 pF, and that two of these loads, in addition to a 7 pF FAST TTL load, are distributed along a 9.6 in clock trace, Cd = (2 x 15 + 7)pF/9.6 in = pF/in. The loaded trace propagation delay and characteristic impedance are then calculated as tPD = 0.243 ns/in and ZO = 41 . Looking at trace C in Figure 2, the two MC88200's are approximately 3 inches apart. Using the calculated value of tPD, the clock signal skew due to the trace is about 0.7 ns. Since these two devices are on the same trace, this is the total clock FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 801 AN1091 skew between these devices. Upon careful inspection of all the clock traces, it can be seen that clock signal skew was accounted for and minimized on this board layout. The longest distance between any 88 K devices on a single clock trace is about 4.5 inches, which translates to approximately 1.1 ns of skew. The two 88 K devices farthest away from the clock driver (traces a and c), are located at almost exactly the same distance along their respective traces, making the clock skew between them the 1 ns guaranteed from output to output of the clock driver. This means that the worst case clock skew between any two devices on this board is approximately 2.1 ns, which at 33 MHz is 7% of the period. Without careful attention to matching the clock traces on the board, this number could easily exceed 3 ns and the 10% cut-off point, even if a low skew clock driver is used. CLOCK TRACE LINE LENGTHS: A -- 9.4 INCHES B -- 8.6 INCHES C -- 9.6 INCHES D -- 7.8 INCHES -- TERMINATION SYMBOL -- DEVICE INPUT CONNECTION MC88914 CLOCK DRIVER A D C B PROPRIETARY ASIC PROPRIETARY ASIC MC88100 CPU MC88200 CMMU MC88200 CMMU PROPRIETARY ASIC MC88200 CMMU Figure 2. Scale Representation of an Actual 88000 System PCB Layout (Only sections of the board related to the clock driver outputs are shown.) W MICROSTRIP LINE CROSS-SECTION T DIELECTRIC H GROUND OR POWER PLANE ZO = 87 er +1.41 In ( 5.98h 0.8w + t ) tPD = 1.017 0.475 er + 0.67 ns/ft WHERE: er = Relative Dielectric Constant of the Board Material w, h, t = Dimensions Indicated in a Microstrip Diagram Figure 3. Formulas for the Characteristic Impedance and Propagation Delay of a Microstrip Line (Ref. 1) 802 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1091 CLOCK SIGNAL TERMINATIONS Transmission line effects occur when a large mismatch is present between the characteristic impedance of the line and the input or output impedances of the receiving or driving device. The basic guidelines used to determine if a PCB trace needs to be examined for transmission line effects is that if the smaller of the driving device's rise or fall time is less than three times the propagation delay of a switching wave through a trace, the transmission line effects will be present.2 This relationship can be stated in equation form as:3 3 X tPD X trace length tRISE or tFALL For the MC88914 CMOS clock driver described in this article, rise and fall times are typically 1.5 ns or less (from 20% to 80% of VCC). Analyzing the clock trace characteristics presented earlier for transmission line effects, 3 x 0.243 ns/in x trace length 1 ns (1 ns is used as `fastest' rise or fall time). Therefore the trace length must be less than 1.5 inches for the transmission line effects to be masked by the rise and fall times. A. UNTERMINATED 0.5-INCH, 41 TRANSMISSION LINE 10 5 VOLTAGE 0 -5 0 10 20 TIME (ns) 30 40 B. UNTERMINATED 9-INCH, 41 TRANSMISSION LINE 10 5 VOLTAGE 0 -5 0 10 20 TIME (ns) 30 40 Figure 4. SPICE Simulation Results of `Short' and `Long' Transmission Lines. Simulations Were Run with Typical Parameters @ 25C and VCC = 5.0 V Figure 4 shows the clock signal waveform seen at the receiver end of an unterminated 0.5 inch trace and an unterminated 9 inch trace. These results were obtained using SPICE simulations, which may not be exact, but are adequate to predict trends and for comparison purposes. The 9 inch trace, which is well beyond the 1.5 inch limit where transmission line effects come into play, exhibits unacceptable switching characteristics caused by reflections going back and forth on the trace. Even the 0.5 inch line exhibits substantial overshoot and undershoot. Any unterminated line will exhibit some overshoot and undershoot at these edge rates. Clock lines shorter than 1-1.5 inches are unrealistic on a practical board layout, therefore it is recommended that CMOS clock lines be terminated if the driver has 1-2 ns edge rates. Termination, which is used to more closely match the line to the load or source impedances, has been a fact of life in the ECL world for many years (reference 1 is an excellent source for transmission line theory and practice in ECL systems), but CMOS and TTL devices have only recently reached the speeds and edge rates which require termination. CMOS outputs further complicate the issue by driving from rail to rail (5 V), with slew rates exceeding those of high performance ECL devices. Since clock lines are only driven from a single location, they lend themselves to termination more easily than bus lines which are commonly driven from multiple locations. Termination of bus lines with multiple drivers is a complicated manner which will not be addressed in this article. The most common types of termination in digital systems are shown in Figure 5. Since no single termination scheme is optimal in all cases, the tradeoffs involving the use of each will be discussed, and recommendations specific to clock drivers will be made. Reference 2 is a comprehensive and practical treatment of transmission line theory and analysis of CMOS signals, and is recommended reading for those who want to gain a better understanding of transmission lines. Figure 6 shows SPICE simulated waveforms of the different termination schemes to be discussed. The driving device in the simulations was the MC88914 output buffer; in all simulations it drove a 9 inch 41 transmission line. The simulations were run using typical model parameters at 25C and VCC = 5 V. Series termination, depicted in Figure 5b, is recommended if the load is lumped at the end of the trace and the output impedance of the driving device is less than the loaded characteristic impedance of the trace, or when a minimum number of components is required. The main problem with series termination occurs when the driving device has different output impedance values in the low and high states, which is a problem in TTL and some CMOS devices. A well designed CMOS clock driver should have nearly equal output impedances in the high and low states, avoiding this problem. An additional advantage is that series termination does not create a DC current path, thus the VOL and VOH levels are not degraded. The SPICE generated waveforms of series termination in Figure 6a show that series termination effectively masks the transmission line effects exhibited in Figure 4. If each clock output is driving only one device, series termination would be recommended, but this is not a realistic case in most systems, so series termination is not generally recommended for termination of clock lines. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 803 AN1091 Parallel termination utilizes a single resistor tied to ground or VCC whose value is equal to the characteristic impedance of the line. Its major disadvantage is the DC current path it creates when the driver is in the high state (if the resistor is tied to ground). This causes excessive power dissipation and VOH level degradation. Since a clock driver output is always switching, the DC current draw argument loses some credibility at higher frequencies because the AC switching current becomes a major component of the overall current. Therefore the main consideration in parallel termination is how much VOH degradation can be tolerated by the receiving devices. Figure 6b demonstrates that this termination technique is effective in minimizing the switching noise, but Thevenin termination has some advantages over parallel termination. Thevenin termination utilizes one resistor tied to ground and a second tied to VCC. An important consideration when using this type of termination is choosing the resistor values to avoid settling of the voltage between the high and low logic levels of the receiving device.2 TTL designers commonly use a 220/330 resistor value ratio, but CMOS is a little tricky because the switch point is at VCC/2. With a 1:1 resistor ratio a failure at the driver output would cause the line to settle at 2.5 V, causing system debug problems and also potential damage to the receiving devices. In Thevenin termination, the parallel equivalent value of the two resistors should be equal to the characteristic impedance of the line. A DC path does exist in both the high and low states, but it is not as bad as parallel termination because the resistance in the Thevenin DC path is at least 2 times greater. Figure 6c shows the termination waveforms, which exhibit characteristics similar to parallel termination, but with less VOH degradation. The only real advantage of parallel over Thevenin is less resistors (1/2 as many) and less space taken up on the board by the resistors. If this is not a factor, Thevenin termination is recommended over parallel. AC termination, shown in Figure 5e, normally utilizes a resistor and capacitor in series to ground. The capacitor blocks DC current flow, but allows the AC signal to flow to ground during switching. The RC time constant of the resistor and capacitor must be greater than twice the loaded line delay. AC termination is recommended because of its low power dissipation and also because of the availability of the resistor and capacitor in single- in-line packages (SIP). A pullup resistor to VCC is sometimes added to set the DC level at a certain point because of the failure condition described in regards to Thevenin termination. As discussed earlier, the argument of lower DC current is less convincing at high frequencies. The AC terminated waveform walks out slightly toward the end of a high-to-low or low-to-high transition as seen in Figure 6d, making it slightly less desirable than Thevenin termination. Thevenin and AC termination are the two recommended termination schemes for clock lines, but it depends on what frequency the clock is running at when making a decision between these types of termination. Although hard data is not provided to back this statement up, it is a safe assumption that at frequencies of 25 MHz and below AC is the best choice. If the system frequency could reach 40 MHz and beyond, Thevenin becomes the better choice. ADDITIONAL CONSIDERATIONS WHEN TERMINATING CLOCK LINES The results presented might imply that terminating the clock lines will completely solve noise problems, but termination can cause secondary problems with some logic devices. Termination acts to reduce the noise seen at the receiver, but that noise actually is seen as additional current and noise at the output of the driving device. If the internal and input logic on the source device is not sufficiently decoupled on chip from the high current outputs, internal threshold problems can occur. This phenomenon is commonly known as `dynamic threshold.' It is usually evidenced by glitches appearing on the outputs of a fast, high current drive logic device as it switches high or low. This is most severe on `ACT' devices which have high current and high slew rate CMOS outputs along with TTL inputs which have low noise immunity. This problem can be minimized by decoupling the internal ground and VCC supplies on-chip and in the package. This decoupling is accomplished by having separate `quiet' ground and VCC pads on chip which supply the input circuitry's ground and VCC references. These pads are then tied to extra `quiet' ground and `quiet' VCC pins on the package, or to special `split leads' which resemble a tuning fork and utilize the leadframe inductance to accomplish the decoupling. When choosing a clock source, make sure that the part has one of these decoupling schemes. References 1. Blood, William R., MECL System Design Handbook, Motorola Inc., 1983. 2. Application Note AN1051, Transmission Line Effects in PCB Applications, Motorola Inc., 1990. 3. Motorola FACT Data Book DL138, Motorola Inc., 1990. 804 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1091 ZO CMOS DRIVING DEVICE CMOS OR TTL RECEIVING INPUT CMOS DRIVING DEVICE RT ZO CMOS OR TTL RECEIVING INPUT RT = ZO - ZD A. TRANSMISSION LINE WITH NO TERMINATION WHERE, ZD = DRIVING DEVICE OUTPUT IMPEDANCE B. TRANSMISSION LINE WITH SERIES TERMINATION ZO VCC CMOS DRIVING DEVICE RT RT = Z O CMOS OR TTL RECEIVING INPUT ZO CMOS DRIVING DEVICE RT C. TRANSMISSION LINE WITH PARALLEL TERMINATION RT RT = 2 ZO CMOS OR TTL RECEIVING INPUT D. TRANSMISSION LINE WITH THEVENIN TERMINATION ZO CMOS DRIVING DEVICE RT RT = Z O CT CMOS OR TTL RECEIVING INPUT E. TRANSMISSION LINE WITH AC TERMINATION Figure 5. Schematic Representation of Common Termination Techniques FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 805 AN1091 A. SERIES TERMINATION B. PARALLEL TERMINATION 5 4 VOLTAGE VOLTAGE 3 2 1 0 -1 0 10 20 TIME (ns) 30 40 5 4 3 2 1 0 -1 0 10 20 TIME (ns) 30 40 DRIVER OUTPUT WAVEFORM RECEIVER INPUT WAVEFORM C. THEVENIN TERMINATION D. AC TERMINATION 5 4 VOLTAGE 0 10 20 TIME (ns) 30 40 3 VOLTAGE 2 1 0 -1 5 4 3 2 1 0 0 10 20 TIME (ns) 30 40 Figure 6. SPICE Simulation Results for Various Terminations of a 9-Inch 41 transmission Line. (Simulations Were Run with Typical Model Parameters @ 25C and VCC = 5.0 V) 806 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. APPLICATION NOTE Order number: AN1405 Rev 1, 09/2001 AN1405 ECL Clock Distribution Techniques By: Todd Pearson ECL Applications Engineering ABSTRACT This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL technologies. INTRODUCTION The ever increasing performance requirements of today's systems has placed an even greater emphasis on the design of low skew clock generation and distribution networks. Clock skew, the difference in time between "simultaneous" clock transitions within a system, is a major component of the constraints which form the upper bound for the system clock frequency. Reductions in system clock skew allow designers to increase the performance of their designs without having to resort to more complicated architectures or more costly, faster logic. ECL logic technologies offer a number of advantages for reducing system clock skew over the alternative CMOS and TTL technologies. straint on this measurement is the requirement that the output transitions are identical, therefore if the skew between all edges produced by a device is important the output-to-output skew would need to be added to the duty cycle skew to get the total system skew. Typically the output-to-output skew will be smaller than the duty cycle skew for TTL and CMOS devices. Because of the near zero duty cycle skew of a differential ECL device the output-to-output skew will generally be larger. The output-to-output skew is important in systems where either a single device can provide all of the necessary clocks or for the first level device of a nested clock distribution tree. In these two situations the only parameter of importance will be the relative position of each output with respect to the other outputs on that die. Since these outputs will all see the same environmental and process conditions the skew will be significantly less than the propagation delay windows specified in the standard device data sheet. IN OUTa OUTb OUTc OUTPUT-TO-OUTPUT SKEW SKEW DEFINITIONS The skew introduced by logic devices can be divided into three parts: duty cycle skew, output-to-output skew and part-to-part skew. Depending on the specific application, each of the three components can be of equal or overriding importance. Duty Cycle Skew The duty cycle skew is a measure of the difference between the TPLH and TPHL propagation delays (Figure 1). Because differences in TPLH and TPHL will result in pulse width distortion the duty cycle skew is sometimes referred to as pulse skew. Duty cycle skew is important in applications where timing operations occur on both edges or when the duty cycle of the clock signal is critical. The later is a common requirement when driving the clock inputs of advanced microprocessors. Figure 2. Output-to-Output Skew Part-to-Part Skew The part-to-part skew specification is by far the most difficult performance aspect of a device to minimize. Because the part-to-part skew is dependent on both process variations and variations in the environment the resultant specification is significantly larger than for the other two components of skew. Many times a vendor will provide subsets of part-to-part skew specifications based on non-varying environmental conditions. Care should be taken in reading data sheets to fully understand the conditions under which the specified limits are guaranteed. If the part-to-part skew is specified and is different than the specified propagation delay window for the device one can be assured there are constraints on the part-to-part skew specification. Power supply and temperature variations are major contributors to variations in propagation delays of silicon devices. Constraints on these two parameters are commonly seen in part-to-part skew specifications. Although there are situations where the power supply variations could be ignored, it is difficult for this author to perceive of a realistic system whose devices are all under identical thermal conditions. Hot spots on boards or IN OUT TPLH PWhi fin = fout TPLH PWlo Figure 1. Duty Cycle Skew Output-to-Output Skew Output-to-output skew is defined as the difference between the propagation delays of all the outputs of a device. A key con- FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 807 AN1405 cabinets, interruption in air flow and variations in IC density of a board all lead to thermal gradients within a system. These thermal gradients will guarantee that devices in various parts of the system are under different junction temperature conditions. Although it is unlikely that a designer will need the entire commercial temperature range, a portion of this range will need to be considered. Therefore, a part-to-part skew specified for a single temperature is of little use, especially if the temperature coefficient of the propagation delay is relatively large. For designs whose clock distribution networks lie on a single board which utilizes power and ground planes an assumption of non-varying power supplies would be a valid assumption and a specification limit for a single power supply would be valuable. If, however, various pieces of the total distribution tree will be on different boards within a system there is a very real possibility that each device will see different power supply levels. In this case a specification limit for a fixed VCC will be inadequate for the design of the system. Ideally the data sheets for clock distribution devices should include information which will allow designers to tailor the skew specifications of the device to their application environment. ECL output buffers inherently show very little difference between TPLH and TPHL delays. What differences one does see are due mainly to switching reference levels which are not ideally centered in the input swing (see Figure 3). For worst case switching reference levels the pulse skew of an ECL device will still be less than 300 ps. If the ECL device is used differentially the variation in the switching reference will not impact the duty cycle skew as it is not used. In this case the pulse skew will be less than 50 ps and can generally be ignored in all but the highest performance designs. The problem of generating clocks which are capable of meeting the duty cycle requirements of the most advanced microprocessors, would be a trivial task if differential ECL compatible clock inputs were used. TTL and CMOS clock drivers on the other hand have inherent differences between the TPLH and TPHL delays in addition to the problems with non-centered switching thresholds. In devices specifically designed to minimize this parameter it generally cannot be guaranteed to anything less than 1 ns. The major contributors to output-to-output skew is IC layout and package choice. Differences in internal paths and paths through the package generally can be minimized regardless of the silicon technology utilized at the die level, therefore ECL devices offer less of an advantage in this area than for other skew parameters. CMOS and TTL output performance is tied closely to the power supply levels and the stability of the power busses within the chip. Clock distribution trees by definition always switch simultaneously, thus creating significant disturbances on the internal power busses. To alleviate this problem multiple power and ground pins are utilized on TTL and CMOS clock distribution devices. However even with this strategy TTL and CMOS clock distribution devices are limited to 500 ps - 700 ps output-to-output skew guarantees. With differential ECL outputs very little if any noise is generated and coupled onto the internal power supplies. This coupled with the faster propagation delays of the output buffers produces output-to-output skews on ECL clock chips as low as 50 ps. Two aspects of ECL clock devices will lead to significantly smaller part-to-part skews than their CMOS and TTL competitors: faster propagation delays and delay insensitivity to environmental variations. Variations in propagation delays with process are typically going to be based on a percentage of the typical delay of the device. Assuming this percentage is going to be approximately equivalent between ECL, TTL and CMOS processes, the faster the device the smaller the delay variations. Because state-of-the-art ECL devices are at least 5 times faster than TTL and CMOS devices, the expected delay variation would be one fifth those of CMOS and TTL devices without even considering environmental dependencies. The propagation delays of an ECL device are insensitive to variations in power supply while CMOS and TTL device propagation delays vary significantly with changes in this parameter. Across temperature the percentage variation for all technologies is comparable, however, again the faster propagation delays of ECL will reduce the magnitude of the variation. Figure 4 on the following page represents normalized propagation delay versus temperature and power supply for the three technologies. SYSTEM ADVANTAGES OF ECL Skew Reductions ECL devices provide superior performance in all three areas of skew over their TTL or CMOS competitors. A skew reducing mechanism common to all skew parameters is the faster propagation delays of ECL devices. Since, to some extent, all skew represent a percentage of the typical delays faster delays will usually mean smaller skews. ECL devices, especially clock distribution devices, can be operated in either single-ended or differential modes. To minimize the skew of these devices the differential mode of operation should be used, however even in the single-ended mode the skew performance will be significantly better than for CMOS or TTL drivers. IN VBBlo VBBnom OUT DELAYlo DELAYnom Figure 3. VBB Induced Duty Cycle Skew 808 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1405 1.05 PROPAGATION DELAY (NORMALIZED) 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 0. 0.9 1. 1.0 9 8 02 6 POWER SUPPLY (NORMAL4 1. 10 ECL CMOS/TTL PROPAAGATION DELAY (NORMALIZED) 1.15 CMOS/TT L 1.10 ECL 1.05 1.20 1.00 0 2 0 4 6 0 0 TEMPERATURE 8 0 1 0 0 Figure 4. TPD vs Environmental Condition Comparison Low Impedance Line Driving The clock requirements of today's systems necessitate an almost exclusive use of controlled impedance interconnect. In the past this requirement was unique to the performance levels associated with ECL technologies, and in fact precluded its use in all but the highest performance systems. However the high performance CMOS and TTL clock distribution chips now require care in the design and layout of PC boards to optimize their performance, with this criteria established the migration from these technologies to ECL is simplified. In fact, the difficulties involved in designing with these "slower" technologies in a controlled impedance environment may even enhance the potential of using ECL devices as they are ideally suited to the task. The low impedance outputs and high impedance inputs of an ECL device are ideal for driving 50 to 130 controlled impedance transmission lines. The specified driving impedance of ECL is 50 , however this value is used only for convenience sake due to the 50 impedance of most commonly used measurement equipment. Utilizing higher impedance lines will reduce the power dissipated by the termination resistors and thus should be considered in power sensitive designs. The major drawback of higher impedance lines (delays more dependent on capacitive loading) may not be an issue in the point to point interconnect scheme generally used in low skew clock distribution designs. Differential Interconnect The device skew minimization aspects of differential ECL have already been discussed however there are other system level advantages that should be mentioned. Whenever clock lines are distributed over long distances the losses in the line and the variations in power supply upset the ideal relationship between input voltages and switching thresholds. Because differential interconnect "carries" the switching threshold information from the source to the load the relationship between the two is less likely to be changed. In addition for long lines the smaller swings of an ECL device produce much lower levels of cross-talk between adjacent lines and minimizes EMI radiation from the PC board. There is a cost associated with fully differential ECL, more pins for equivalent functions and more interconnect to be laid on a typically already crowded PC board. The first issue is really a non-issue for clock distribution devices. The output-to-output and duty cycle skew are very much dependent on quiet internal power supplies. Therefore the pins sacrificed for the complimentary outputs would otherwise have to be used as power supply pins, thus functionality is actually gained for an equivalent pin count as the inversion function is also available on a differential device. The presence of the inverted signal could be invaluable for a design which clocks both off the positive and negative edges. Figure 5 shows a method of obtaining very low skew (<50 ps) 180 shifted two phase clocks. It is true that differential interconnect requires more signals to be routed on the PC board. Fortunately with the wide data and address buses of today's designs the clock lines represent a small fraction of the total interconnect. The final choice as to whether or not to use differential interconnect lies in the level of skew performance necessary for the design. It should be noted that although single-ended ECL provides less attractive skew performance than differential ECL, it does provide significantly better performance than equivalent CMOS and TTL functions. D Q 0 D Q 8 CL Kb CL Ka Q Q E111 CLKa CLKb Figure 5. 180 Shifted Two Phase Clocks FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 809 AN1405 USING ECL WITH POSITIVE SUPPLIES It is hard to argue with the clock distribution advantages of ECL presented thus far, but it may be argued that except for all ECL designs it is too costly to include ECL devices in the distribution tree. This claim is based on the assumption that at least two extra power supplies are required; the negative VEE supply and the negative VTT termination voltage. Fortunately both these assumptions are false. PECL (Positive ECL) is an acronym which describes using ECL devices with a positive rather than negative power supply. It is important to understand that all ECL devices are also PECL devices. By using ECL devices as PECL devices on a +5 volt supply and incorporating termination techniques which do not require a separate termination voltage (series termination, thevenin equivalent) ECL can be incorporated in a CMOS or TTL design with no added cost. The reason for the choice of negative power supplies as standard for ECL is due to the fact that all of the output levels and internal switching bias levels are referenced to the VCC rail. It is generally easier to keep the grounds quieter and equal potential throughout a system than it is with a power supply. Because the DC parameters are referenced to the VCC rail any disturbances or voltage drops seen on VCC will translate 1:1 to the output and internal reference levels. For this reason when communicating with PECL between two boards it is recommended that only differential interconnect be used. By using differential interconnect VCC variations within the specified range will not in any way affect the performance of the device. Finally mentioning ECL to a CMOS designer invariably conjures up visions of space heaters as their perception of ECL is high power. Although it is true that the static power of ECL is higher than for CMOS the dynamic power differences between the technologies narrows as the frequency increases. As can be seen in Figure 6 at frequencies as low as 20 MHz the per gate power of ECL is actually less than for CMOS. Since clock distribution devices are never static it does not make sense to compare the power dissipation of the two technologies in a static environment. 20 ECL Clock Distribution Networks Clock distribution in a ECL system is a relatively trivial matter. Figure 7 illustrates a two level clock distribution tree which produces nine differential ECL clocks on six different cards. The ECLinPS E211 device gives the flexibility of disabling each of the cards individually. In addition the synchronous registered enables will disable the device only when the clock is already in the LOW state, thus avoiding the problem of generating runt pulses when an asynchronous disable is used. The device also provides a muxed clock input for incorporating a high speed system clock and a lower speed test or scan clock within the same distribution tree. The ECLinPS E111 device is used to receive the signals from the backplane and distribute it on the card. The worst case skew between all 54 clocks in this situation would be 275 ps assuming that all the loads and signal traces are equalized. E111 Q0 E211 Q0 BACKPLANE Q8 E111 Q0 Q5 Q8 Figure 7. ECL Clock Distribution Tree Mixed Technology Distribution Networks Building clock networks in TTL and CMOS systems can be a little more complicated as there are more alternatives available. For simple one level distribution trees fanout devices like the MECL 10H645 1:9 TTL to TTL fanout tree can be used. However as the number of levels of fanout increases the addition of ECL devices in an other wise TTL or CMOS system becomes attractive. In Figure 8 on the next page an E111 device is combined with a MECL H641 device to produce 81 TTL level clocks. Analyzing the skew between the 81 clocks yields a worst case skew, allowing for the full temperature and VCC range variation, of 1.25 ns. Under ideal situations, no variation in temperature or VCC supply, the skew would be only 750 ps. When compared with distribution trees utilizing only TTL or CMOS technologies these numbers represent 50% improvement, more if the environmental conditions vary to any degree. For a 50 MHz clock the total skew between the 81 TTL clocks is less than 6.5% of the clock period, thus providing the designer extra margin for layout induced skew to meet the overall skew budget of the design. 15 ICC (mA) CM OS 10 5 ECL 0 0 2 0 4 6 0 0 FREQUENCY 8 0 1 0 0 Figure 6. ICC/Gate vs Frequency Comparison MIXED SIGNAL CLOCK DISTRIBUTION 810 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1405 Many designers have already realized the benefits of ECL clock distribution trees and thus are implementing them in their designs. Furthermore where they have the capability, i.e. ASICs, they are building their VLSI circuits with ECL compatible clock inputs. Unfortunately other standard VLSI circuits such as microprocessors, microprocessor support chips and memory still cling to TTL or CMOS clock inputs. As a result many systems need both ECL and TTL clocks within the same system. Unlike the situation outlined in Figure 8 the ECL levels are not merely intermediate signals but rather are driving the clock inputs of the logic. As a result the ECL edges need to be matched with the TTL edges as pictured in Figure 9. H641 used. The value of the delay element would be a best guess estimate of the differences in the two propagation delays. It is highly unlikely that the temperature coefficients of the propagation delays of the ECL devices, TTL devices and delay devices would be equal. Although these problems will add skew to the system, the resultant total skew of the distribution network will be less than if no ECL chips were used. PLL Based Clock Drivers A potential solution for the problem outlined in Figure 9 is in the use of phase locked loop based clock distribution chips. Because these devices feedback an output and lock it to a reference clock input the delay differences between the various technology output buffers will be eliminated. One might believe that with all of the euphoria surrounding the performance of PLL based clock distribution devices that the need for any ECL in the distribution tree will be eliminated. However when analyzed further the opposite appears to be the case. For a single board design with a one level distribution system there obviously is no need for ECL. When, however, a multiple board system is required where nested levels of devices are needed ECL once again becomes useful. One major aspect of part-to-part skew for PLL based clock chips often overlooked is the dependence on the skew of the various reference clocks being locked to. As can be seen in Figure 10 the specified part-to-part skew of the device would necessarily need to be added to the reference clock skew to get the overall skew of the clock tree. From the arguments presented earlier this skew will be minimized if the reference clock is distributed in ECL. It has not been shown as of yet where a PLL based ECL clock distribution chip can provide the skew performance of the simple fanout buffer. From a system standpoint the buffer type circuits are much easier to design with and thus given equivalent performance would represent the best alternative. The extra features provided by PLL based chips could all be realized if they were used in only the final stage of the distribution tree. REFa REFb OUTb Q0 T T L Q8 ECL E111 Q0 BACKPLANE Q8 H641 ECL Q0 T T L Q8 Figure 8. ECL to TTL Clock Distribution E111 DELAY E111 Q0 BACKPLANE DELAY Q0 T T L Q8 Q8 H641 ECL Q0 T T L OUTa Q8 DEVICE SYSTEM Figure 9. Mixed ECL and TTL Distribution An ECL clock driver will be significantly faster than a TTL or CMOS equivalent function. Therefore to de-skew the ECL and TTL signals of Figure 9 a delay needs to be added to the input of the ECL device. Because a dynamic delay adjust would not lend itself to most production machines a static delay would be Figure 10. System Skew for PLL Clock Distribution The MPC973 is a PLL based clock driver which features differential PECL reference clock inputs. When combined with the very low skew MC10E111 fanout buffer, very low skew clock trees can be realized for multiprocessor MPP designs. There will be a family of devices featuring various technology compat- FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 811 AN1405 ible inputs and outputs to allow for the building of precisely aligned clock trees based on either ECL, TTL, CMOS or differential GTL (or a mixture of all four) compatible levels. the performance of a system. Unfortunately the VLSI world is not yet ECL clock based so that the benefits of a totally ECL based distribution tree cannot be realized for many systems. However there are methods of incorporating ECL into the intermediate levels of the tree to significantly reduce the overall skew. In addition the system designers can utilize their new found knowledge to incorporate ECL compatible clocks on those VLSI chips of which they have control while at the same time pressuring other VLSI vendors in doing the same so that future designs can enjoy fully the advantages of distributing clocks with ECL. CONCLUSION The best way to maximize the performance of any synchronous system is to spend the entire clock period performing value added operations. Obviously any portion of the clock period spent idle due to clock skew limits the potential performance of the system. Using ECL technology devices in clock distribution networks will minimize all aspects of skew and thus maximize 812 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. APPLICATION NOTE Order number: AN1406 Rev 2, 08/2001 AN1406 Designing With PECL (ECL at +5.0 V) The High Speed Solution for the CMOS/TTL Designer By: Cleon Petty, Todd Pearson ECL Applications Engineering ABSTRACT This application note provides detailed information on designing with Positive Emitter Coupled Logic (PECL) devices. INTRODUCTION PECL, or Positive Emitter Coupled Logic, is nothing more than standard ECL devices run off of a positive power supply. Because ECL, and therefore PECL, has long been the "black magic" of the logic world many misconceptions and falsehoods have arisen concerning its use. However, many system problems which are difficult to address with TTL or CMOS technologies are ideally suited to the strengths of ECL. By breaking through the wall of misinformation concerning the use of ECL, the TTL and CMOS designers can arm themselves with a powerful weapon to attack the most difficult of high speed problems. It has long been accepted that ECL devices provide the ultimate in logic speed; it is equally well known that the price for this speed is a greater need for attention to detail in the design and layout of the system PC boards. Because this requirement stems only from the speed performance aspect of ECL devices, as the speed performance of any logic technology increases these same requirements will hold. As can be seen in Table 1 the current state-of-the-art TTL and CMOS logic families have attained performance levels which require controlled impedance interconnect for even relatively short distances between source and load. As a result system designers who are using state-of-the-art TTL or CMOS logic are already forced to deal with the special requirements of high speed logic; thus it is a relatively small step to extend their thinking from a TTL and CMOS bias to include ECL devices where their special characteristics will simplify the design task. Table 1. Relative Logic Speeds Logic Family Typical Output Rise/Fall Maximum Open Line Length (Lmax) 1 delays of six to seven nanoseconds for translating between technologies, a significant portion of the logic would need to be realized using ECL for the overall system performance to improve. However, for very high speed subsystem requirements ECL may very well provide the best system solution. Transmission Line Driving Many of the inherent features of an ECL device make it ideal for driving long, controlled impedance lines. The low impedance of the open emitter outputs and high input impedance of any standard ECL device make it ideally suited for driving controlled impedance lines. Although designed to drive 50 lines an ECL device is equally adept at driving lines of impedances of up to 130 without significant changes in the AC characteristics of the device. Although some of the newer CMOS/TTL families have the ability to drive 50 lines many require special driver circuits to supply the necessary currents to drive low impedance transmission interconnect. In addition the large output swings and relatively fast output slew rates of today's high performance CMOS/TTL devices exacerbate the problems of crosstalk and EMI radiation. The problems of crosstalk and EMI radiation, along with common mode noise and signal amplitude losses, can be alleviated to a great degree with the use of differential interconnect. Because of their architectures, neither CMOS nor TTL devices are capable of differential communication. The differential amplifier input structure and complimentary outputs of ECL devices make them perfectly suited for differential applications. As a result, for systems requiring signal transmission between several boards, across relatively large distances, ECL devices provide the CMOS/TTL designer a means of ensuring reliable transmission while minimizing EMI radiation and crosstalk. Figure 1 shows a typical application in which the long line driving, high bandwidth capabilities of ECL can be utilized. The majority of the data processing is done on wide bit width words with a clock cycle commensurate with the bandwidth capabilities of CMOS and TTL logic. The parallel data is then serialized into a high bandwidth data stream, a bandwidth which requires ECL technologies, for transmission across a long line to another box or machine. The signal is received differentially and converted back to relatively low speed parallel data where it can be processed further in CMOS/TTL logic. By taking advantage of the bandwidth and line driving capabilities of ECL the system minimizes the number of lines required for interconnecting the subsystems without sacrificing the overall performance. Furthermore by taking advantage of PECL this application can be realized with a single five volt power supply. The configuration of Figure 1 illustrates a situation where the mixing of logic technologies can produce a design which maximizes the overall performance while managing power dissipation and minimizing cost. 10KH ECLinPS FAST FACT 1 1.0 ns 400 ps 2.0 ns 1.5 ns 3" 1" 6" 4" Approximate for stripline interconnect (Lmax = Tr/2Tpd) SYSTEM ADVANTAGES OF ECL The most obvious area to incorporate ECL into an otherwise CMOS/TTL design would be for a subsystem which requires very fast data or signal processing. Although this is the most obvious it may also be the least common. Because of the need for translation between ECL and CMOS/TTL technologies the performance gain must be greater than the overhead required to translate back and forth between technologies. With typical FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 813 AN1406 device will inherently be smaller than similar CMOS or TTL functions. The virtues of differential interconnect in line driving have already been addressed, however the benefits of differential interconnect are even more pronounced in clock distribution. The propagation delay of a signal through a device is intimately tied to the switching threshold of that device. Any deviations of the threshold from the center of the input voltage swing will increase or decrease the delay of the signal through the device. This difference will manifest itself as rise-to-fall skew in the device. The threshold levels for both CMOS and TTL devices are a function of processing, layout, temperature and other factors which are beyond the control of the system level designer. Because of the variability of these switching references, specification limits must be relaxed to guarantee acceptable manufacturing yields. The level of relaxation of these specifications increases with increasing logic depth. As the depth of the logic within a device increases the input signal will switch against an increasing number of reference levels; each encounter will add skew when the reference level is not perfectly centered. These relaxed timing windows add directly to the overall system skew. Differential ECL, both internal and external to the die, alleviates this threshold sensitivity as a DC switching reference is no longer required. Without the need for a switching reference the delay windows, and thus system skew, can be significantly reduced while maintaining acceptable manufacturing yields. What does this mean to the CMOS/TTL designer? It means that CMOS/TTL designers can build their clock generation card and backplane clock distribution using ECL. Designers will not only realize the benefits of driving long lines with ECL but will also be able to realize clock distribution networks with skew specs unheard of in the CMOS/TTL world. Many specialized functions for clock distribution are available from Motorola (MC10/100E111, MC10/100E211, MC10/100EL11). Care must be taken that all of the skew gained using ECL for clock distribution is not lost in the process of translating into CMOS/TTL levels. To alleviate this problem the MC10/100H646 can be used to translate and fanout a differential ECL input signal into TTL levels. In this way all of the fanout on the backplane can be done in ECL while the fanout on each card can be done in the CMOS/TTL levels necessary to drive the logic. Figure 2 illustrates the use of specialized fanout buffers to design a CMOS/TTL clock distribution network with minimal skew. With 50ps output-to-output skew of the MC10/100E111 and 1ns part-to-part skew available on the MC10/100H646 or MC10/100H641, a total of 72 or 81 TTL clocks, respectively, can be generated with a worst case skew between all outputs of only 1.05 ns. A similar distribution tree using octal CMOS or TTL buffers would result in worst case skews of more than 6 ns. This 5 ns improvement in skew equates to about 50% of the up/down time of a 50 MHz clock cycle. It is not difficult to imagine situations where an extra 50% of time to perform necessary operations would be either beneficial or even a life saver. For more information about using ECL for clock distribution, refer to application note AN1405/D -- ECL Clock Distribution Techniques. ECL Serial Data > 200 MHz Serial/Parallel Conversion CMOS/TTL Parallel Data < 50 MHz Low Frequency Information Processing CMOS/TTL Parallel Data < 50 MHz Parallel/Serial Conversion ECL Serial Data > 200 MHz Figure 1. Typical Use of ECL's High Bandwidth, Line Driving Capabilities Clock Distribution Perhaps the most attractive area for ECL in CMOS/ TTL designs is in clock distribution. The ever increasing performance capabilities of today's designs has placed an even greater emphasis on the design of low skew clock generation and distribution networks. Clock skew, the difference in time between "simultaneous" clock transitions throughout an entire system, is a major component of the constraints which form the upper bound for the system clock frequency. Reductions in system clock skew allow designers to increase the performance of their designs without having to resort to more complicated architectures or costly, faster logic. ECL logic has the capability of significantly reducing the clock skew of a system over an equivalent design utilizing CMOS or TTL technologies. The skew introduced by a logic device can be broken up into three areas; the part-to-part skew, the within-part skew and the rise-to-fall skew. The part-to-part skew is defined as the differences in propagation delays between any two devices while the within-device skew is the difference between the propagation delays of similar paths for a single device. The final portion of the device skew is the rise-to-fall skew or simply the differences in propagation delay between a rising input and a failing input on the same gate. The within-device skew and the rise-to-fall skew combine with delay variations due to environmental conditions and processing to comprise the part-to-part skew. The part-to-part skew is defined by the propagation delay window described in the device data sheets. Careful attention to die layout and package choice will minimize within-device skew. Although this minimization is independent of technology, there are other characteristics of ECL which will further reduce the skew of a device. Unlike their CMOS/TTL counterparts, ECL devices are relatively insensitive to variations in supply voltage and temperature. Propagation delay variations with environmental conditions must be accounted for in the specification windows of a device. As a result because of ECLs AC stability the delay windows for a 814 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1406 Part-Part Skew = 1 ns Output-Output Skew = 50 ps Differential ECL H641 TTL Outputs 1 of 9 Differential ECL Input E111 H641 TTL Outputs 9 of 9 Figure 2. Low Skew Clock Fanout Tree PECL VERSUS ECL Nobody will argue that the benefits presented thus far are not attractive, however the argument will be made that the benefits are not enough to justify the requirements of including ECL devices in a predominantly CMOS/TTL design. After all the inclusion of ECL requires two additional negative voltage supplies; VEE and the terminating voltage VTT. Fortunately this is where the advantages of PECL come into play. By using ECL devices on a positive five volt CMOS/TTL power supply and using specialized termination techniques ECL logic can be incorporated into CMOS/TTL designs without the need for additional power supplies. What about power dissipation you ask, although it is true that in a DC state ECL will typically dissipate more power than a CMOS/TTL counterpart, in applications which operate continually at frequency, i.e. clock distribution, the disparity between ECL and CMOS/TTL power dissipation is reduced. The power dissipation of an ECL device remains constant with frequency while the power of a CMOS/TTL device will increase with frequency. As frequencies approach 50 MHz the difference between the power dissipation of a CMOS or TTL gate and an ECL gate will be minimal. 50 MHz clock speeds are becoming fairly common in CMOS/TTL based designs as today's high performance MPUs are fast approaching these speeds. In addition, because ECL output swings are significantly less than those of CMOS and TTL the power dissipated in the load will be significantly less under continuous AC conditions. It is clear that PECL can be a powerful design tool for CMOS/TTL designers, but where can one get these PECL devices. Perhaps the most confusing aspect of PECL is the misconception that a PECL device is a special adaptation of an ECL device. In reality every ECL device is also a PECL device; there is nothing magical about the negative voltage supply used for ECL devices. The only real requirement of the power supplies is that the potential difference described in the device data sheets appears across the upper and lower power supply rails (VCC and VEE respectively). A potential stumbling block arises in the specified VEE levels for the various ECL families. The 10 H and 100 K families specify parametric values for potential differences between VCC and VEE of 4.94 V to 5.46 V and 4.2 V to 4.8 V respectively; this poses a problem for the CMOS/TTL designer who works with a typical VCC of 5.0 V 5%. However, because both of these ECL standards are voltage compensated both families will operate perfectly fine and meet all of the performance specifications when operated on standard CMOS/TTL power supplies. In fact, Motorola is extending the VEE specification ranges of many of their ECL families to be compatible with standard CMOS/TTL power supplies. Unfortunately earlier ECL families such as MECL 10 K are not voltage compensated and therefore any reduction in the potential difference between the two supplies will result in an increase in the VOL level, and thus a decreased noise margin. For the typical CMOS/TTL power supplies a 10 K device will experience an 50 mV increase in the VOL level. Designers should analyze whether this loss of noise margin could jeopardize their designs before implementing PECL formatted 10 K using 5.0 V 5% power supplies. The traditional choice of a negative power supply for ECL is the result of the upper supply rail being used as the reference for the I/0 and internal switching bias levels of the technology. Since these critical parameters are referenced to the upper rail any noise on this rail will couple 1:1 onto them; the result will be reduced noise margins in the design. Because, in general, it is a simpler task to keep a ground rail relatively noise free, it is beneficial to use the ground rail as this reference. However when careful attention is paid to the power supply design, PECL can be used to optimize system performance. Once again the use of differential PECL will simplify the designer's task as the noise margins of the system will be doubled and any noise riding on the upper VCC rail will appear as common mode noise; common mode noise will be rejected by the differential receiver. MECL TO PECL DC LEVEL CONVERSION Although using ECL on positive power supplies is feasible, as with any high speed design there are areas in which special attention should be placed. When using ECL devices with positive supplies the input output voltage levels need to be translated. This translation is a relatively simple task. Since these levels are referenced off of the most positive rail, VCC, the following equation can be used to calculate the various specified DC levels for a PECL device: PECL Level = VCCNEW - |Specification Level| As an example, the VOHMAX level for a 10H device operating with a VCC of 5.0 V at 25C would be as follows: PECL Level = 5.0 V - |-0.81 V| PECL Level = (5.0 - 0.81)V = 4.19 V The same procedure can be followed to calculate all of the DC levels, including VBB for any ECL device. Table 2 outlines the various PECL levels for a VCC of 5.0 V for both the 10H and 100K ECL standards. As mentioned earlier any changes in VCC will show up 1:1 on the output DC levels. Therefore any tolerance values for VCC can be transferred to the device I/0 levels by simply adding or subtracting the VCC tolerance values from those values provided in Table 2. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 815 AN1406 Table 2. ECL/PECL DC Level Conversion for VCC = 5.0 V 10E Characteristics Symbol 0C Min VOH VOL VOHA VOLA VIH VIL VBB Max 25C Min Max 85C Min Max 100E Characteristics 0 to 85C Min Max Unit -1.02/3.98 -1.95/3.05 -- -- -1.17/3.83 -1.95/3.05 -1.38/3.62 -0.84/4.16 -1.63/3.37 -- -- -0.84/4.16 -1.48/3.52 -1.27/3.73 -0.98/4.02 -1.95/3.05 -- -- -1.13/3.87 -1.95/3.05 -1.35/3.65 -0.81/4.19 -1.63/3.37 -- -- -0.81/4.19 -1.48/3.52 -1.25/3.75 -0.92/4.08 -1.95/3.05 -- -- -1.07/3.93 -1.95/3.05 -1.31/3.69 -0.735/4.26 5 -1.600/3.40 0 -- -- -0.735/4.26 5 -1.450/3.55 0 -1.190/3.81 0 -1.025/3.97 5 -1.810/3.19 0 -- -1.035/3.96 5 -1.165/3.83 5 -1.810/3.19 0 -1.380/3.62 0 -0.880/4.12 0 -1.620/3.38 0 -1.610/3.39 0 -- -0.880/4.12 0 -1.475/3.52 5 -1.260/3.74 0 V V V V V V V PECL TERMINATION SCHEMES PECL outputs can be terminated in all of the same ways standard ECL, this would be expected since an ECL and a PECL device are one in the same. Figure 3 illustrates the various output termination schemes utilized in typical ECL systems. For best performance the open line technique in Figure 3 would not be used except for very short interconnect between devices; the definition of short can be found in the various design guides for the different ECL families. In general for the fastest performance and the ability to drive distributive loads the parallel termination techniques are the best choice. However occasions may arise where a long uncontrolled or variable impedance line may need to be driven; in this case the series termination technique would be appropriate. For a more thorough discourse on when and where to use the various termination techniques the reader is referred to the MECL System Design Handbook (HB205/D) and the design guide in the ECLinPS Databook (DL140/D). The parallel termination scheme of Figure 3 requires an extra VTT power supply for the impedance matching load resistor. In a system which is built mainly in CMOS/TTL this extra power supply requirement may prohibit the use of this technique. The other schemes of Figure 3 use only the existing positive supply and ground and thus may be more attractive for the CMOS/ TTL based machine. Parallel Termination Schemes Because the techniques using an extra VTT power supply consume significantly less power, as the number of PECL devices incorporated in the design increases the more attractive the VTT supply termination scheme becomes. Typically ECL is specified driving 50 into a -2.0 V, therefore for PECL with a VCC supply different than ground the VTT terminating voltage will be VCC -2.0 V. Ideally the VTT supply would track 1:1 with VCC, however in theory this scenario is highly unlikely. To ensure proper operation of a PECL device within the system the tolerances of the VTT and the VCC supplies should be considered. Assume for instance that the nominal case is for a 50 load (Rt) into a +3.0 V supply; for a 10H compatible device with a VOHmax of -0.81 V and a realistic VOLmin of -1.85 V the following can be derived. IOHmax = (VOHmax - VTT)/Rt IOHmax = ({5.0 - 0.81} - 3.0)/50 = 23.8 mA IOLmin = (VOLmin - VTT)/Rt IOLmin = ({5.0 - 1.85} -3.0)/50 = 3.0 mA If +5% supplies are assumed a VCC of VCCnom -5% and a VTT of VTTnom +5% will represent the worst case. Under these conditions, the following output currents will result. IOHmax = ({4.75 - 0.81} - 3.15)/50 = 15.8 mA IOLmin = ({4.75 - 1.85} - 3.15)/50 = 0 mA Using the other extremes for the supply voltages yields: IOHmax = 31.8 mA IOLmin = 11 mA The changes in the IOH currents will affect the DC VOH levels by 40mV at the two extremes. However in the vast majority of cases the DC levels for ECL devices are well centered in their specification windows, thus this variation will simply move the level within the valid specification window and no loss of worst case noise margin will be seen. The IOL situation on the other hand does pose a potential AC problem. In the worst case situation the output emitter follower could move into the cutoff state. The output emitter followers of ECL devices are designed to be in the conducting "on" state at all times. If cutoff, the delay of the device will be increased due to the extra time required to pull the output emitter follower out of the cutoff state. Again this situation will arise only under a number of simultaneous worst case situations and therefore is highly unlikely to occur, but because of the potential it should not be overlooked. 816 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1406 Thevenin Equivalent Termination Schemes The Thevenin equivalent parallel termination technique of Figure 3 is likely the most attractive scheme for the CMOS/TTL designer who is using a small amount of ECL. As mentioned earlier this technique will consume more power, however the absence of an additional power supply will more than compensate for the extra power consumption. In addition, this extra power is consumed entirely in the external resistors and thus will not affect the reliability of the IC. As is the case with standard parallel termination, the tolerances of the VTT and VCC supplies should be addressed in the design phase. The following equations provide a means of determining the two resistor values and the resulting equivalent VTT terminating voltage. R1 = R2 ({VCC - VTT}/{VTT - VEE}) R2 = ZO ({VCC - VEE}/{VCC - VTT}) VTT = VCC (R2/{R1 + R2}) ZO Rpd VEE Open Line Termination ZO For the typical setup: VCC = 5.0 V; VEE = GND; VTT = 3.0 V; and ZO = 50 R2 = 50 ({5-0}/{5-3}) = 125 R1 = 125 ({5-3}/{3-0}) = 83.3 Checking for VTT: VTT = 5 (125/{125-83.3}) = 3.0 V Because of the resistor divider network used to generate VTT the variation in V will be intimately tied to the variation in VCC. Differentiating the equation for VTT with respect to VCC yields: dVTT/dVCC = R2/(R1 + R2) dVCC Again for the nominal case this equation reduces to: VTT = 0.6 VCC So that for VCC = 5% = 0.25 V, VTT = 0.15 V. As mentioned previously the real potential for problems will be if the VOL level can potentially put the output emitter follower into cutoff. Because of the relationship between the VCC and VTT levels the only situation which could present a problem will be for the lowest value of VCC. Applying the equation for IOLmin under this condition yields: IOLmin = ({VOLmin - VTT}/Rt IOLmin = ({4.75 - 1.85}-2.85)/50 = 1.0 mA From this analysis it appears that there is no potential for the output emitter follower to be cutoff. This would suggest that the Thevenin equivalent termination scheme is actually a better design to compensate for changes in VCC due to the fact that these changes will affect VTT, although not 1:1 as would be ideal, in the same way. To make the design even more immune to potential output emitter follower cutoff the designer can design for nominal operation for the worst case situation. Since the designer has the flexibility of choosing the VTT level via the selection of the R1 and R2 resistors the following procedure can be followed. Let VCC = 4.75 V and VTT = VCC - 2.0 V = 2.75 V Therefore: R2 = 119 and R1 = 86 thus: IOHmax = 23 mA and IOLmin = 3.0 mA Plugging in these values for the equations at the other extreme for VCC = 5.25 V yields: VTT = 3.05 V, IOHmax = 28 mA and IOLmin = 5.2 mA Although the output currents are slightly higher than nominal, the potential for performance degradation is much less and the results of any degradation present will be significantly less dramatic than would be the case when the output emitter follower is cutoff. Again in most cases the component manufactures will provide devices with typical output levels; typical levels significantly reduces any chance of problems. However it is important that the system designer is aware of where any potential problems may come from so they can be dealt with during the initial design. Rs Rpd VEE RS = Z O Series Termination ZO Rt VTT Rt = ZO Parallel Termination VCC ZO R1 R2 VEE Thevenin Parallel Termination Figure 3. Termination Techniques for ECL/PECL Devices FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 817 AN1406 Differential ECL Termination Differential ECL outputs can be terminated using two different strategies. The first strategy is to simply treat the complimentary outputs as independent lines and terminate them as previously discussed. For simple interconnect between devices on a single board or short distances across the backplane this is the most common method used. For interconnect across larger distances or where a controlled impedance backplane is not available the differential outputs can be distributed via twisted pair of ribbon cable (use of ribbon cable assumes every other wire is a ground so that a characteristics impedance will arise). Figure 4 illustrates common termination techniques for twisted pair/ ribbon cable applications. Notice that Thevenin equivalent termination techniques can be extended to twisted pair and ribbon cable applications as pictured in Figure 4. However for twisted pair/ribbon cable applications the standard termination technique picture in Figure 4 is somewhat simpler and also does not require a separate termination voltage supply. If however the Thevenin techniques are necessary for a particular application the following equations can be used. R1 = R2 = ZO/2 R3 = R1 (VTT - VEE)/(VOH + VOL - 2VTT) VTT = (R3{VOH + VOL} + R1{VEE})/(R1 + 2R3) where VOH, VOL, VEE and VTT are PECL voltage levels. VEE Rpd ZO Rt Rpd VEE Standard Twisted Pair Termination VTT ZO Rt Rt = ZO Plugging in the various values for VCC will show that the VTT tracks with VCC at a rate of approximately 0.7:1. Although this rate is approaching ideal it would still behoove the system designer to ensure there are no potential situations where the output emitter follower could become cutoff. The calculations are similar to those performed previously and will not be repeated. The same equations with the change R1 = R2 = ZO can be used to calculate a "Y" termination for differential outputs into separate microstrip, strip or coaxial cables. NOISE AND POWER SUPPLY DISTRIBUTION Since ECL devices are top rail referenced it is imperative that the VCC rail be kept as noise free and variation free as possible. To minimize the VCC noise of a system liberal bypassing techniques should be employed. Placing a bypass capacitor of 0.01F to 0.1 F on the VCC pin of every device will help to ensure a noise free VCC supply. In addition when using PECL in a system populated heavily with CMOS and TTL logic the two power supply planes should be isolated as much as possible. This technique will help to keep the large current spike noise typically seen in CMOS and TTL drivers from coupling into the ECL devices. The ideal situation would be multiple power planes; two dedicated to the PECL VCC and ground and the other two to the CMOS/TTL VCC and ground. However if these extra planes are not feasible due to board cost or board thickness constraints common planes with divided subplanes can be used (Figure 5). In either case the planes or sub planes should be connected to the system power via separate paths. Use of separate pins of the board connectors is one example of connecting to the system supplies. For single supply translators or dual supply translators which share common power pins the package pins should be connected to the ECL VCC and ground planes to ensure the noise introduced to the part through the power plane is minimal. For translating devices with separate TTL and ECL power supply pins, the pins should be tied to the appropriate power planes. Another concern is the interconnect between two cards with separate connections to the VCC supply. If the two boards are at the opposite extremes of the VCC tolerance, with the driver being at the higher limit and the receiver at the lower limit, there is potential for soft saturation of the receiver input. Soft saturation will manifest itself as degradation in AC performance. Although this scenario is unlikely, again the potential should be examined. For situations where this potential exists there are devices available which are less susceptible to the saturation problem. This variation in VCC between boards will also lead to variations in the input switching references. This variation will lead to switching references which are not ideally centered in the input swing and cause rise/fall skew within the receiving device. Obviously the later skew problem can be eliminated by employing differential interconnect between boards. When using PECL to drive signals across a backplane, situations may arise where the driver and the receiver are on different power supplies. A potential problem exists if the receiver is powered down independent of the driver. Figure 6, represents a generic driver/receiver pair. A current path exists through the receiver's VCC plane when the receiver is powered-down and the driver is powered-on, as shown in Rt = ZO/2 Rt VTT Parallel Twisted Pair Termination ZO R2 Rt = ZO/2 VEE Thevenin Twisted Pair Termination R1 R3 Figure 4. Twisted Pair Termination Techniques 818 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1406 Figure 6. If the receiver has ESD protection, the current will flow though the ESD diode to VCC. If the receiver has NO ESD protection, the current will flow through the input transistor and emitter-follower base-collector junctions to VCC. The amount of current flow, in either case, will be enough to damage both the driver and receiver devices. Either of these situations could lead to degradation of the reliability of the devices. Because different devices have different ESD protection schemes, and input architectures, the extent of the potential problem will vary from device to device. CMOS/TTL +5.0 V PLANE Another issue that arises in driving backplanes is situations where the input signals to the receiver are lost and present an open input condition. Many differential input devices will become unstable in this situation, however, most of the newer designs, and some of the older designs, incorporate internal clamp circuitry to guarantee stable outputs under open input conditions. All of the ECLinPS (except for the E111), ECLinPS Lite, and H600 devices, along with the MC10125, 10H125 and 10114 will maintain stable outputs under open input conditions. ** CMOS Sub System ** TTL Sub System CMOS/TTL GROUND PLANE * System +5.0 V System Ground PECL +5.0 V PLANE ** ECL Sub System PECL GROUND PLANE * * Low frequency bypass at the board input ** High frequency bypass at the individual device level Figure 5. Power Plane Isolation in Mixed Logic Systems 5.0 V VCC = 0 V 5.0 V Driver VEE = GND VEE = GND Figure 6. Generic Driver/Receiver Pair CONCLUSION The use of ECL logic has always been surrounded by clouds of misinformation; none of those clouds have been thicker than the one concerning PECL. By breaking through this cloud of misinformation the traditional CMOS/TTL designers can approach system problems armed with a complete set of tools. For areas within their designs which require very high speed, the driving of long, low impedance lines or the distribution of very low skew clocks, designers can take advantage of the built in features of ECL. By incorporating this ECL logic using PECL methodologies this inclusion need not require the addition of more power supplies to unnecessarily drive up the cost of their systems. By following the simple guidelines presented here CMOS/TTL designers can truly optimize their designs by utilizing ECL logic in areas in which they are ideally suited. Thus bringing to market products which offer the ultimate in performance at the lowest possible cost. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 819 Freescale Semiconductor, Inc. APPLICATION NOTE Order number: AN1545 Rev 1, 08/2001 AN1545 Thermal Data for MPC Clock Drivers By: Todd Pearson Applications Engineering INTRODUCTION This application note provides general information on thermal and related reliability issues with respect to the MPC family of clock driver products. In addition, methods are presented to estimate power dissipation and junction temperatures for the MPC product family. Package Choice The Motorola Timing Solutions products are offered in a variety of surface mount plastic packages. These packages include the 16 and 20 lead SOIC, 20 and 28 lead PLCC and the 32 and 52 lead TQFP packages. The bulk of the newer products are being introduced in the SOIC and TQFP packages with the PLCC being used for the older mature products. The surface mount plastic packages were selected as the optimum combination of performance, physical size and thermal handling in a low cost standard package. While more exotic packages exist to improve the thermal and electrical performance the cost of these are prohibitive for many applications. Long Term Failure Mechanisms in Plastic Packages When analyzing a design for its long term reliability it is important that the dominant failure mechanisms are well understood. Although today's plastic packages are as reliable as ceramic packages under most environmental conditions, as the junction temperature increases a failure mode unique to plastic packages becomes a significant factor in the long term reliability of the device. Modern plastic package assembly utilizes gold wire bonded to aluminum bonding pads throughout the electronics industry. Because plastic packages use injection molding the bond wires used must be extremely ductile to keep from breaking or being pulled from the bond pad during the injection process. Gold wire has far better ductility than aluminum wire and therefore is used in the process of plastic packaging. Aluminum is the metal used in the majority of low cost digital IC processes for transistor and bond wire interconnect. As the temperature of the silicon (junction temperature) increases an intermetallic forms between the gold and aluminum interface. This intermetallic formation results in a significant increase in the impedance of the wire bond and can lead to performance failure of the affected pin. With this relationship between intermetallic formation and junction temperature established, it is incumbent on the designer to ensure that the junction temperature for which a device will operate is consistent with the long term reliability goals of the system. Reliability studies were performed at elevated ambient temperatures (125C) from which an arrhenius equation relating junction temperature to bond failure was established. The application of the equation yields Table 1. This table relates the junction temperature of a device in a plastic package to the continuous operating time before 0.1% bond failure (1 failure per 1000 bonds). Note that this equation only holds for continuous elevated junction temperature levels, as the curve is quite steep if a system cycles through a temperature range but spends a relatively short amount of time at the extreme the numbers provided in this table will grossly underestimate the lifetime of the device based solely on the worst case junction temperature seen. Table 1. Package Junction Temperatures Junction Temperature (C) Time (Hours) Time (Years) 80 90 100 110 120 130 140 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 117.8 47.9 20.4 9.1 4.2 2.0 1.0 The Motorola Timing solutions products are designed with chip power levels that permit acceptable reliability levels, in most systems, under conventional 500lfpm (2.5m/s) airflow. However because of their flexibility and programmability there may be some situations where special thermal considerations may be required. Thermal Management In any system design proper thermal management is essential to establish the appropriate trade-off between performance, density, reliability and cost. In particular the designer should be aware of the reliability implication of continuously operating semiconductor devices at high junction temperatures. The increasing popularity of plastic, small outline surface mount packages is putting a greater emphasis on the need for better thermal management of a system. This is due to the fact that the newer SMD packages generally require less board space than their first generation brethren. Thus designs incorporating the latest generation SMD packaging technologies have a higher thermal density. To optimize the thermal management of a system it is imperative that the user understand all of the variables which contribute to the junction temperature of the device. The variables involved in determining the junction temperature of a device are both supplier and user defined. The supplier, through lead frame design, mold compounds, die size and die attach can positively impact the thermal resistance and thus, the junction temperature of a device. Motorola continually experiments with new package designs and assembly techniques in an attempt to further enhance the thermal performance of its products. 820 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1545 It can be argued that the user has the greatest control of the variables which commonly impact the thermal performance of a device. Ambient temperature, air flow and related cooling techniques are the obvious user controlled variables, however PCB substrate material, layout density, amount of exposed copper and weight of copper used in the power planes can all have significant impacts on the thermal performance of a system. PCB substrates all have different thermal characteristics, these characteristics should be considered when exploring the PCB alternatives. Users should also account for the different power dissipation of the different devices in their systems and space them accordingly. In this way the heat load is spread across a larger area and "hot spots" do not appear in the layout. Copper interconnect and power planes act as heat radiators, therefore significant thermal dissipation can be achieved by paying special attention to the copper elements of a PCB. The thermal resistance of copper (package leadframes are made from copper) is significantly lower than that of the epoxy used for the body of plastic packages. As a result the dominant mode of heat flow out of a package is through the leads. By employing techniques at the board level to enhance the transfer of this heat from the package leads to the PCB one can reduce the effective thermal resistance of the plastic package. Copper interconnect traces on the top layer of the PCB are excellent radiators for transferring heat to the ambient air, especially if these traces are exposed to even moderate air flow. In addition using thick copper power planes not only reduces the electrical resistance but also enhances their thermal carrying capabilities. The power planes can be thermally enhanced further by employing special edge connectors which draw the heat from the planes and again dissipate it into the ambient. Finally, the use of thermal conductive epoxies between the underneath of a device and thermal vias to a power plane can accelerate the transfer of heat from the device to the PCB where once again it can more easily be passed to the ambient. The advent of small outline SMD packaging and the industry push towards smaller, denser designs makes it incumbent on the designer to provide for the removal of thermal energy from the system. Users should be aware that they control many of the variables which impact the junction temperatures and, thus, to some extent, the long term reliability of their designs. Calculating Junction Temperature Since the reliability of a device is directly related to junction temperature and that temperature cannot be measured directly there needs to be a means of calculating the approximate junction temperature from measurable parameters. There are two equations which can be used: TJ = TA + PDJA or TJ = TC + PDJC where: TJ = Junction Temperature TA = Ambient Temperature (C) TC = Case Temperature (C) PD = Internal Power Dissipation of the Device (W) JA = Avg Pkg Thermal Resistance (Junction - Ambient) JC = Avg Pkg Thermal Resistance (Junction -Case) The JC numbers are determined by submerging a device in a liquid bath and measuring the temperature rise of the bath, it therefore represents an average case temperature. The difficulty in using this method arises in the determination of the case temperature in an actual system. The case temperature is a function of the location on the package at which the temperature is measured. Therefore, to use the JC method the case temperature would have to be measured at several different points and averaged to represent the TC of the device. This in practice could prove difficult and relatively inaccurate. To alleviate this problem manufacturers will sometimes provide a Jref value for a package. This number represents the thermal resistance between the die and a specific spot on the package (usually the top dead center). This measure of thermal resistance typically has a much wider standard deviation than the standard resistance parameters and therefore is sometimes avoided, however it is the most easily measured parameter from which junction temperatures can be calculated. The JA method of estimating junction temperature is the most widely used. To use this method one need only measure the ambient air temperature in the vicinity of the device in question and calculate the internal power dissipation of that device. The total power dissipation in a device is made up of two parts; the static power and the dynamic power. The two components can be calculated separately and then added together. Another source of power is the termination power as clock drivers are generally used to drive terminated transmission lines. For an ECL output this can be significant however for CMOS outputs the termination load current is pulled through very little voltage (the output HIGH and LOW voltages are very near the rail) so that most of the power is dissipated in the actual load. With this in mind we will address calculating power for ECL and CMOS/BiCMOS separately. Because clock drivers generally drive transmission lines we will not assume any lumped capacitive load at the outputs. Lumped capacitive loads on outputs add significantly to the power dissipated on chip, when however the capacitive loads are at the end of transmission lines they are buffered from the driving device and thus do not add to the power dissipation above that attributed to driving the transmission line. Note that for the purpose of power dissipation calculations it is not equivalent to calculate the distributed capacitance of a transmission line and treat it as a lumped load at the output of the device. This technique will significantly overestimate the calculated power of a device. Calculating Power Dissipation in CMOS/BiCMOS Devices The total power dissipated in a device can be represented as follows: PD = ICC(static)*VCC + ICC(dynamic)*VCC + n(IOH*(VCC - VOH) + IOL*(VOL))/2 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 821 AN1545 In general rather than using dynamic ICC numbers the dynamic power is calculated using power dissipation capacitance numbers (CPD). Using CPD numbers the above equation becomes: PD = ICC(static)*VCC + CPD*VCC2*f + n(IOH*(VCC - VOH) + IOL*(VOL))/2 As mentioned previously since the output logic levels are very nearly rail to rail, the third part of the above equation can be ignored. Note that although this assumption may be true for series terminated lines it may not be true for parallel termination where the relatively large DC currents will drive the output voltage levels away from the rails. If we assume series termination then the equation reduces to the following: PD = ICC(static)*VCC + CPD*VCC2*f The dynamic dissipation may be a function of the number of outputs switching, if this is the case a CPD number may be provided for each output buffer. In this case the equation would expand to: PD = ICC(static)*VCC + CPD(internal)*VCC2*f + CPD(output)*VCC2*f*n where n = number of outputs at the given frequency f. Finally for a CMOS device the ICC(static) = 0 and for a BiCMOS device which utilizes ECL gates internal the CPD(internal) = 0 so that the equations reduce to: CMOS PD = CPD(internal)*VCC2*f + CPD(output)*VCC BiCMOS PD = ICC(static)*VCC + CPD(output)*VCC2*f*n Calculating Power Dissipation in ECL Devices Starting from the same basic equation: PD = ICC(static)*VCC + ICC(dynamic)*VCC + n(IOH*(VCC - VOH) + IOL*(VCC - VOL))/2 For ECL devices the static current is equal to the dynamic current (ICC is independent of frequency) therefore the equation reduces to: PD = ICC*VCC + n(IOH*(VCC - VOH) + IOL*(VCC - VOL))/2 The above equation assumes a 50% duty cycle on a single ended output and thus takes the average of the high state and low state power dissipation. For differential outputs it is simpler to calculate the power per output pairs. Since the pairs are always in complementary states the output power for the pair is simply the addition of the low state and high state power consumption. The only time one will see a difference between a single ended and differential output calculation is under worst case conditions. For say an 18 single ended output device the worst case condition would be for all 18 to be in the worst case logic state for power dissipation purposes. For a device on the other hand with 9 pairs of complimentary outputs (18 total) only 9 of the outputs can be in the worst case condition at a time so that the worst case power dissipation of a complimentary output device will be less than a device with an equivalent number of single ended outputs. 2*f*n The only issue left is determining IOL and IOH. These values are a function of the termination technique and the pull down voltage used. The currents are easily calculated based on the VOH/VOL levels the pull down resistance and the pull down voltage used. For a standard termination of 50 to a voltage of 2.0 V below VCC: IOH = (VCC - 0.98) - (VCC - 2.0)/50 = 20.4 mA IOL = (VCC - 1.7) - (VCC - 2.0)/50 = 6.0 mA Thermal Resistance of Plastic Packages With the power estimates calculated the JA of the appropriate package is the only required parameter left to estimate the junction temperature of a device. The JA number for a package is expressed in C per Watt (C/W) and is used to determine the temperature elevation of the die (junction) over the external ambient temperature. Standard lab measurements of this parameter for the various timing solution packages are provided in the graphs of Figure 1 through Figure 3. 100 90 RJA (C/W) 80 70 60 50 40 0 100 200 300 AIR FLOW (lfpm) 400 500 32-Lead 52-Lead Figure 1. Thermal Resistance of the TQFP Packages 75 70 65 RJA (C/W) 60 55 50 45 40 0 100 200 300 AIR FLOW (lfpm) 400 500 20-Lead 28-Lead Figure 2. Thermal Resistance of the PLCC Packages 120 110 RJA (C/W) 100 90 80 70 60 0 100 200 300 AIR FLOW (lfpm) 400 500 16-Lead 20-Lead Figure 3. Thermal Resistance of the SOIC Packages 822 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1545 Junction Temperature Calculation Example As an example the junction temperature of the MPC951 will be calculated. The static ICC of the MPC951 is 95 mA and the CPD per output is 25 pf. From these numbers the following results: PD = 95 mA*3.3 V + 3.3 V*3.3 V*25 pf*f *n = 315 mW + 2.72 e-10*f*n Assume we will configure all 9 outputs to the same frequency, the curve in Figure 4 shows the power dissipation vs frequency for the MPC951. 600 POWER DISSIPATION (mW) 550 500 450 400 350 300 0 10 20 30 40 50 60 70 80 90 100 cations. If airflow was added (200lfpm) the junction temperature would reduce to: TJ = TA + 60C/W * 0.555W = TA + 33C This drops the junction temperature down into the same range as the 66 MHz output case. The second example will use an ECL output device; the MC100LVE111. The device has 9 differential output pairs and an ICC of 65 mA. Assume that the outputs are terminated 50 to 2.0 V below VCC. PD = 65 mA * 3.3 V + 9((0.98*1.02/50)+(1.7*0.3/50)) = 215 mW + 270 mW = 485 mW The MC100LVE111 is packaged in the 28 lead PLCC; from the JA tables the JA at 500lfpm is 45C/W. This yields the following approximate junction temperature: TJ = TA + 45C/W*0.485 W = TA + 22C For a maximum ambient of 70C the LVE111 exhibits more than satisfactory long term reliability for most systems under standard operating conditions. Note in both cases the most efficient way to lower the junction temperature is to reduce the ambient temperature of the system. Unit changes in ambient temperature result in unit changes in junction temperature no other parameter is this tightly coupled to junction temperature. Limitations to Junction Temperature Calculations The use of the previously described technique for estimating junction temperatures is intimately tied to the measured values of the JA of the package. Since this parameter is a function of not only the package, but also the test fixture the results may not be applicable for every environmental condition. As mentioned previously the JA of a package in a system could be somewhat higher or lower depending on the thermal design of the board. In addition the reliability numbers derived for the intermetallic formation assumes constant usage at the specific conditions. In the real world devices will not be exposed to worst case conditions continuously but rather will cycle between the worst case and a lower junction temperature. The MTBF table does not take into account this cycling so that simply calculating the worst case junction temperature and applying it to the table directly will significantly underestimate the long term reliability of the device. Because reliability and environmental conditions are statistical in nature it is important that statistical analysis be applied to any long term reliability studies done on the clock driver products. FREQUENCY (MHz) Figure 4. MPC951 Junction Temperature Calculation Assume that one is building a design with all nine outputs operating at 66 MHz. From the graph this corresponds to a power dissipation of 470 mW. The MPC951 is packaged in the 32 lead TQFP; from the JA chart (assume zero air flow) the thermal resistance of the package is 97C/W. Plugging these into the TJ equation yields the following: TJ = TA + 80C/W*0.470 W = TA + 38C. For a worst case ambient temperature of 70C the resulting junction temperature would be 108C. From the MTBF table this would correspond to a lifetime of greater than nine years, a lifetime which is well within the requirements of most systems. If however the user needed a little higher performance of 100 MHz on the outputs the TJ would be: TJ = TA + 80C/W*0.555W = TA + 44C Under these conditions the worst case junction temperature would be 114C and the worst case lifetime would be approaching 4 years. This may not be a satisfactory lifetime and the user would have to do some thermal management to reduce the junction temperature. Obvious enhancements would be providing airflow or perhaps reducing the maximum ambient specifi- FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 823 Freescale Semiconductor, Inc. APPLICATION NOTE Order number: AN1934 Rev 0, 09/2001 AN1934 Effects of Skew and Jitter on Clock Tree Design By: Don Aldridge and Tom Borr Applications Engineering ABSTRACT This application note discusses the parametrics of skew and jitter as these terms apply to PLL clock drivers and clock buffers. The application note covers the definition of the various types of skew and jitter, the measurement techniques and values associated with these parameters, and concludes with an example clock tree design and analysis of the skew and jitter. INTRODUCTION At first glance, clock distribution trees are relatively simple. As shown in Figure 1, a typical clock distribution tree consists of a clock source and a series of clock distribution buffers that deliver multiple copies of the clock source to many locations in an electronic system. The clock source may be a crystal oscillator (Figure 1) or an external clock source. This clock source may be at the desired frequency or may need to be translated to the desired frequency or frequencies as part of the clock tree circuitry. The clock tree will consist of some combination of PLL clock drivers and/or fanout buffers providing multiple outputs. The clock tree may consist of several devices or be composed of a single integrated circuit. Individual clock outputs deliver the clock signal to various locations on a PC board. Fanout Buffer FOUT1 CLOCK GENERATOR FOUT2 After a more detailed look at the requirements of the clock system and the data sheet specifications of the devices used to implement the clock tree, the design appears a bit more complicated and requires a more detailed analysis. The specifications that are most important for this type of analysis are usually found in the AC parameter portion of the clock driver data sheet and consist of parameters such as propagation delay, skew, and jitter. This application note discusses these parameters by reviewing the definition, the measurement techniques, and their effects on system performance. The application note concludes with the analysis of a typical clock distribution tree based upon these parameters. Standards for Skew, Jitter Definitions, and Notations The reference used to determine the standards for skew, jitter definitions, and notations for this application note are the EIA specification EIA/JESD65. This EIA specification documents the current industry standard for these parameters. This document is available in a downloadable PDF format at the web site of: http://www.jedec.org/. Clock Driver Devices Clock driver devices consist of both clock fanout buffers and PLL based clock generators. Typical fanout buffers are shown in Figure 2 and consist of an input buffer driving many outputs though individual output buffers. The specific devices shown are the MPC942C and MPC942P which offer 18 LVCMOS outputs and have either a LVCMOS input or a LVPECL input. Some fanout buffers have an optional internal divider network to produce an input clock divided by two. A Phase Lock Loop device is shown in Figure 4 and may or may not have built-in fanout buffers. It is not the intention of this application note to explain all of the fundamentals of a PLL; however, a quick review of the components is covered. FOUT3 Figure 1. Typical Clock Distribution Tree Q0 PECL LVCMOS_CLK Q1:Q16 PECL Q17 Q17 Q1:Q16 Q0 OE MPC942C OE MPC942P Figure 2. Fanout Buffer 824 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1934 A basic PLL clock architecture (Figure 3) consists of a phase detector, a low pass filter, a VCO, and (in this diagram) two divider networks. Both dividers are at the inputs of the phase detector. The input to the clock driver, or the reference frequency, may be external or sourced from a crystal oscillator that is included as part of the clock driver architecture. This input frequency may be divided by an optional P divider block and then applied to the input of the phase detector. The phase detector produces a correction signal based upon the difference in phase in its two inputs. The correction signal or the output of the phase detector is filtered and applied to the input of the voltage controlled oscillator; VCO. The output of the VCO is applied to the M divider and becomes feedback and the second of the two inputs to the phase detector. When the loop is in "lock," the two inputs to the phase detector are the same frequency and the same phase. The output frequency, or FOUT, is the reference frequency divided by P and then multiplied by M and will continually track the reference frequency. With a few additions to the basic PLL clock architecture, we can create a multi-frequency and multi-clock distribution device as shown in Figure 4. The more complex divider network shown provides the M divide value for the feedback path to the input of the phase detector and, also, the N divider divides down the VCO frequency to the desired system frequency or frequencies. Multiple outputs from the clock divider may provide for the generation of multiple frequencies. Note that fanout buffers are included for each output to provide the required system clock drive. Also note that an equivalent fanout buffer is included for the feedback path. The feedback connection for the PLL is external to the device and thus equalizes the delay through the main clock outputs. As is discussed later, the external feedback path may also include compensating trace delay which allows the phase of FOUT clock to be advanced forward or backward with respect to the input clock. FREF /P FFB Phase Detector Low Pass Filter VCO FOUT FREF Low Pass Filter /N Clock Dividers /M /P FFB Phase Detector FOUT VCO FOUT = (FREF / P) * (M/N) Figure 4. PLL Based Clock Driver Clock Driver Parametrics The clock driver parameters that are of interest in this application note are Buffer Propagation Delay, Zero Reference Delay, Skew, Jitter, and PLL Bandwidth and Jitter. These parameters are typically found in the AC parameter portion of a clock driver data sheet. Fanout buffers have output skew, jitter, and propagation delay. PLL clock driver devices are characterized with jitter, output skew, and an effective input to output propagation delay called Zero Reference Phase Delay. In a clock tree design, the parameters that complicate the analysis is skew between the outputs of a clock fanout buffer and edge or frequency jitter. Jitter commonly is generated in the very early stages of a clock tree and potentially at each stage of the clock tree. These jitter sources may or may not be cumulative and be passed to the outputs. Buffer Propagation Delay Clock distribution buffers have a propagation delay from input to output. Typical values for this delay are in the order of a few nanoseconds. Data sheet specifications may be given for a single propagation delay or as separate values given for a low to high edge; versus a high to low edge. The low to high edge value and the high to low edge value should be very similar but not necessarily the same. The notation for propagation delay is tpd. Also the notations of tplh and tphl are used to indicate the propagation delay for a low to high transition and a high to low transition of a waveform, respectively. Reference Zero Delay Reference Zero Delay is the JEDEC term for the effective PLL buffer delay. This parameter is also referred to as Static Phase Offset (or SPO). The JEDEC notation is t(). The value of SPO is defined as the average difference in phase between the input reference clock and the feedback input signal, when the PLL is locked. The value of the Reference Zero Delay can be compensated for by including PC board trace delay in the feedback path of the PLL. Specially constructed PLL clock drivers called Zero-delay Buffers make use of this occurrence and can produce a clock edge at the output that is exactly in phase with the input. /M FOUT = (FREF / P) * M Figure 3. Basic PLL FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 825 AN1934 Skew Clock fanout buffers and PLL clock drivers with built-in fanout buffers offer multiple outputs. These clock outputs are routed across a PC board to various devices. A typical fanout buffer may have as many as 18 to 20 clock outputs. Typically, these outputs are designed to drive a 50 ohm cable or a 50 ohm PC board trace. Ideally, all of the outputs are timed such that clock edges on each output switch at exactly the same time. However, real life devices do not. Small amounts of skew exist between the high to low or low to high transition on one output as compared to another output. For systems that require synchronization between data and clocks or multiple clocks on the PC board, this skew is a bad thing. Clock integrated circuit designers try to minimize the amount of skew in a device. However, skew does exist and the device data sheet usually specifies the amount of skew. This output skew is typically defined in three ways: output-to-output, process, or part-to-part skew. Output-to-output skew is defined as the skew between the various output edges on a single device. Process skew is defined as the skew between the same output pin on two different devices. Finally, the part-to-part skew is defined as the skew between any output on two different devices. Figure 5 illustrates output skew types for both single-ended and differential output waveforms. Typically, both output-to-output and part-to-part skew are specified on a data sheet. The JEDEC specification states that the skew values are to be determined with the outputs driving identical specified loads. Output 1 Output 2 tsk(o) Device 1 1 . . n In PLL based systems, the value of the cycle-to-cycle jitter is usually small since the PLL does not quickly respond to changes on its input. Since cycle-to-cycle jitter is the difference in the period from one cycle to the next, this jitter is at the clock frequency. This jitter is also referred to as short term jitter. tn tn tJit(CC) = |tn - tn+1| Figure 6. Cycle-to-Cycle Jitter Clock integrated circuits have an inherent jitter generated within the device. In addition, external sources contribute to this jitter. Specifically, power supply noise may be a source of jitter in both PLL based and non-PLL based clock driver devices. Power supply design, power supply filtering, and board layout contributes to the overall jitter values measured on the output of the clock device. The second type of jitter is period jitter, which is defined in the JEDEC specification as the deviation in cycle time of a signal with respect to an ideal period. Figure 7 shows the definition and calculation of period jitter. This jitter type is reported as an absolute maximum value as measured over a long time period. The JEDEC symbol for period jitter is tjit(per). The long time period varies from measurement system to measurement system. Typical time periods are 64 microseconds which, at a frequency of 100 MHz or so, yields many (6400) clock cycle period values. This type of jitter represents the random movement in the instantaneous output frequency or output period of the clock source. 1/f0 Ideal Output Differential Output 1 Differential Output 2 tsk(o) Device 2 1 . . n tcycle n Actual Output tjit(per) = |tcycle n - 1/f0| Figure 7. Period Jitter The last jitter type covered is that of phase jitter. Phase jitter is associated with PLL based clock drivers. The JEDEC specification notation is tjit(). This value represents the input to output jitter associated with a PLL clock driver. The value is given as an absolute value of the range or variation in the difference between the phase of the reference input and the phase of the feedback input to the integrated circuit. (See Figure 8.) Reference Clock Input Figure 5. Output-to-Output Skew Jitter Jitter is a deviation of the edge location on the output of the clock buffer. As with skew, jitter is a bad thing and is usually measured in picoseconds. There are three categories of jitter that are of interest: cycle-to-cycle, period, and phase jitter. Cycle-to-cycle jitter is the difference in the period of any two adjacent clock cycles. The difference is reported as an absolute value according to the JEDEC specification. However, quite often a value is used. The JEDEC symbol for cycle-to-cycle jitter is tjit(cc). Cycle-to-cycle is usually measured over some large sampling of cycles and specified as the maximum difference. Figure 6 shows the measurement and calculation of cycle-tocycle jitter. Feedback Input tjit() = |t()) - t() mean| t() Figure 8. Phase Jitter 826 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1934 Jitter Values and Data Sheets Definitions of the various types of jitter and the equations for calculating the values are necessary for an understanding of jitter and how it relates to a clock design. However, another important factor in understanding clock drivers is the metrics and methods used of the published specifications. These metrics may vary from manufacturer to manufacturer and also within a manufacturer's clock driver offering. The values may be given as RMS values or as a peak-to-peak value. They may be listed as typicals or as actual maximum values. Understanding of the background of the jitter values on a data sheet are necessary for circuit design as well as comparing clock driver devices. Jitter measurements, whether cycle-to-cycle period or phase, are measured over some large number of samples. The data for a typical device, when plotted, represents a classic distribution Gausian or bell shaped curve where most of the clock cycles are close to the ideal frequency (in the case of period jitter) with fewer and fewer devices having increasing deviation from the ideal period. In classical statistics, the distance from the center of the Gausian curve is defined in values of standard deviation or sigma; and the higher the sigma multiplier, the higher the confidence level is that a device will not exhibit a jitter value greater than a predefined amount. Data sheet specifications that list RMS values imply a 1 sigma deviation above the mean and 1 sigma deviation below the mean or a total of 2 sigma confidence level. Table 1 lists these confidence factors for 1 sigma through 6 sigma. If data sheet values are specified as RMS values and higher levels of confidence are desired, then the data sheet values for jitter must be multiplied by the desired confidence factor. Figure 9 shows the Gausian distribution curve and sigma points for a device with an output frequency of 400 MHz (period of 2.5 ns). A value of 3 sigma or 6 sigma gives a confidence level or a probability that the clock edge is within the distribution of 0.9970007%. The 3 sigma limits define the upper period limit of approximately 2.52 ns and the lower period limit of approximately 2.48 ns. Figure 10 shows actual measurements made for the period jitter of a 400 MHz clock device. In this example, the mean period is 2.49921 ns (approximately 2.5 ns) with the standard deviation being 6.48 ps and the peak-to-peak jitter being 57 ps. This data was captured with a sample size of 13100 samples. Table 1. Confidence Factor Sigma Value Confidence Factor 1 2 3 4 5 6 (2 sigma) (3 sigma) (6 sigma) (8 sigma) (10 sigma) (12 sigma) 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 RMS values for jitter look better on the data sheet than peak-to-peak. However, peak-to-peak values may be needed for clock jitter analysis. If RMS values are specified, peak-to-peak values may be derived based upon the required system reliability for the specific applications. If the other cases where peak values are specified, these values may be used directly. However, the question that must be asked in order to use the manufacturer's peak-to-peak values is what level of uncertainty is being specified. These parameters may be specified differently on each manufacturer data sheet. Therefore, care must be taken to insure that when one is comparing values, the values are specified and measured in a similar fashion. The above discussion assumes the jitter measurements have the classic Gausian curve or statistical distribution. This would be the case if the jitter is completely random. However, clock driver devices may have internal mechanisms that produce jitter that deviates from the classic bell curve. In this case, the total jitter is composed of the addition of a series of bell curves providing a more complex distribution. With care, the terms of RMS and the various sigma levels may still apply. Figure 9. Classic Gausian Distribution Curve FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 827 AN1934 Figure 10. Period Jitter for Typical PLL Clock Device with FOUT = 400 MHz PLL Bandwidth and Jitter The PLL based clock driver locks on to a reference frequency and maintains an output frequency based upon that reference frequency. If the reference frequency changes, the PLL attempts to follow the change in the reference frequency. However, if the change is faster than the PLL can follow, the PLL based clock driver acts as a low pass filter and ignores or effectively filters out the higher frequency changes on its input. As with any low pass filters, the PLL has a cutoff frequency, or bandwidth, associated with it. This bandwidth becomes important to our clock tree design. High frequency noise and jitter will not pass through the PLL. The actual bandwidth of the locked PLL is dependent on many factors, including the feedback divider ratio. The higher the divide ratio, the lower the bandwidth. Thus, those PLL clock driver devices that have selectable feedback divide ratios will have varying bandwidth values. Bandwidth may or may not be specified by the PLL clock driver manufacturer. If not specified, the information is usually available on request. Figure 11 is a typical PLL frequency modulation bandwidth waveform. Note the cutoff frequency is about 300 kHz. As mentioned before, the cutoff frequency will vary with a change in the divide ratio in the feedback loop. Bandwidths of PLL-based clock drivers vary from low values of a few kHz to higher values of a MHz or more depending upon the intended application of the device. Clock synthesizers typically have the lowest bandwidth. Bandwidths of these devices are in the order of 30 to 50 kHz. Clock generators are next with bandwidths of a few hundred kHz. The devices with the highest bandwidth are the Zero-Delay-Buffers. The bandwidths of these devices are typically a MHz and above. 828 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1934 10 1 Gain (OOUT/OIN) 0.1 0.01 0.001 1,000 10,000 100,000 Modulation Frequency (Hz) Ideal Transfer 1,000,000 10,000,000 PLL Bandwidth "K" Figure 11. PLL Bandwidth Clock Tree Application Example Analysis Figure 12 shows an example clock tree application which is used to show the effects of skew and jitter in a system. The goal of this design is to provide multiple phase aligned HSTL and LVCMOS outputs. The reference for this clock tree is a crystal oscillator while the outputs of the tree provide both HSTL and LVCMOS to various system locations. The tree starts with a crystal oscillator in the MC12430 integrated circuit. The MC12430 is a PLL based clock synthesizer that allows very fine control of the output frequency in 1 MHz steps. 16 MHz XTAL MC12430 LVPECL LVPECL HSTL MC100 EP111 1a 1b Delay MC100 EP223 2 3 LVPECL LVCMOS MPC961P 6 5 The LVPECL output of the MC12430 drives the LVPECL input to the MC100EP111 fanout buffer. The MC100EP111 consists of 10 LVPECL differential pairs of which one pair is connected to a MC100EP223 input and another pair connected to the MPC961P input. The MC100EP223 fanout buffer provides HSTL outputs while the MPC961P is a PLL-based clock generator that provides several LVCMOS outputs. Notice there is an introduced delay from the LVPECL output of the EP111 to the LVPECL input of the MPC961P zero-delay buffer. This introduced delay is due to backplane or cable distance which will skew the LVCMOS outputs to later than the HSTL outputs. To compensate for this delay, the MPC961P zero-delay buffer is used in conjunction with a PC board delay line in the feedback path. Figure 13 provides an analysis of the example clock tree for the situation where we have no (or choose to ignore both) jitter and skew in the devices. Later, in Figure 14, an analysis with both jitter and skew is shown. The circled numbers in Figure 12 are used as reference points on the clock analysis waveforms. 4 Delay Line Figure 12. Example Clock Tree FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 829 AN1934 1a 1b EP223 FIN (EP111 FOUT) 2 EP223 FOUT 1 tpd @ 223 1b EP223 FIN (EP111 FOUT) 2 EP223 FOUT 1a tpd @ 223 tpd(0) @ 223 3 961P FIN delay 4 961P Ffb delay line 5 961P QFB 3 961P FIN delay t(0) + tjit(0) 961 4 961P Ffb delay line 5 961P QFB 6 961P FOUT 6 961P FOUT tsk(0) @ 961 Figure 13. Example Clock Tree Analysis without Jitter and Skew The first analysis of the clock tree is with the assumption that there is zero output-to-output skew and zero jitter. With zero skew between the outputs of the MC100EP111, the signals 1a and 1b are identical. The waveform at point 2 is delayed due to propagation delay, tpd, of the MC100EP223. The waveform at point 3 is delayed due to the delay associated with the backplane or cable distribution. By using the MPC961P zero-delay buffer and placing the appropriate trace delay in the feedback path of the PLL, we can compensate for the backplane trace and bring the waveform for points 5 and 6 back in line with the output of the MC100EP223. Next, we will do the same analysis but we will include the output skew on the MC100EP111, the MC100EP223, and the phase jitter for the MPC961. (See Figure 14.) Initially, we have the output-to-output skew for the EP111. We will assume that the output connected to the MC100EP223 is the slowest and thus the longest delay output and that the output connected through the delay line to the input of the MPC961C is the fastest or shortest delay output. This analysis must also be done for the opposite situation; where the MPC961P is connected to the slowest output and the MC100EP223 is connected to the fastest output. Figure 14. Example Clock Tree Analysis with Jitter and Skew The waveform at point 2 is delayed from point 1a by the propagation delay, tpd, of the MC100EP223 as we had in Figure 13. However, by including the output-to-output skew for the MC100EP223, we find uncertainty in the location of point 2 as shown in the waveform of point 2 of Figure 14. Point 3 shows the waveform arriving at the input to the MPC961P. Point 4 is the feedback input to the MPC961P and, in the ideal case, is exactly the same as point 3. However, in this situation, we have the uncertainty caused by the combination of the static phase offset, t() and the phase jitter for the MPC961P. Figure 14 depicts these two values added together. The waveform of point 5 now moves back in time due to the delay line in the feedback path of the PLL such that the nominal output now coincides with the HSTL outputs of point 2. Point 6 shows the added uncertainty of the outputs due to the output-to-output skew from the MPC961P. Note that Figure 14 is not to scale and the magnitudes of the skew and jitter are actually much smaller than indicated. 830 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1934 Table 2 lists the skew and jitter values for the 3 devices used in the example. The MC100EP111 has a specification for output-to-output skew. The MPC961P has parametric values for Static Phase Offset, phase jitter and output-to-output skew. The MC100EP223 has values for propagation delay and output-to-output skew. Table 2. Confidence Factor Device Parameter analysis. This value was ignored for this example due to the fact that all of the clock outputs are derived from the same source, and jitter that occurs on one output would show up on all outputs. Applications that have clock outputs derived from different sources, or have the clock source compared to a frequency standard, would mandate the need to include the source jitter in the analysis. SUMMARY Skew and jitter are real characteristics of clock driver devices and may or may not be of importance to a clock tree design. Understanding data sheet values and applying this knowledge to clock tree design can sometimes be a real challenge. With a bit of analysis, one can determine which parameters are critical to a specific clock tree design and be able to compare the values of these parameters from one device/vendor to another. Lastly, data sheet values of jitter are often measured in a lab environment under the best of conditions. Real designs with clock drivers on PC boards with other digital circuitry, noisy power supplies, long traces, and other clock sources can make the overall jitter worse. Careful design practices are a must for the best clock driver design. MC100EP111 MPC961P MC100EP223 tsk(o): 70 ps t() : -50 to 225 ps tjit() AF 100 ps tsk(o) AFA @ 150 ps tpd: estimated 700 ps tsk(o): estimated 50 ps A similar analysis can be done for the case where the MC100EP111 outputs connected to the MC100EP223 and MPC961P are reversed in time. Thus, the MC100EP111 output connected to the MC100EP223 is the fastest and the output connected to the MPC961P is the slowest. One last comment on the example is that the jitter associated with the clock source, MC12429, was not mentioned in the FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 831 Freescale Semiconductor, Inc. APPLICATION NOTE Order number: AN1939 Rev 0, 11/2001 AN1939 Clock Driver Primer -- Functionality and Usage By: Don Aldridge and Tom Borr Applications Engineering ABSTRACT This application note focuses on the fundamentals of clock drivers, including definitions, applications, and characteristics of integrated devices. This application note is intended for the system designer that is tasked with creating a clock source for a microprocessor-based system. Although the clock may be a small portion of the system schematic, its design becomes a fundamental contributor to the overall system performance. INTRODUCTION Tucked away in the corner of a complex microprocessor PC board is the clock source that provides the timing for the entire PC board. This clock source may be simple or it may be complex. It may only consist of a crystal, a couple of integrated circuits, and some traces on the PC board. It may also be very complex with many clock outputs, zero-delay buffers and precise timing delays that are built into the PC board. This application note covers the basics of a clock tree design for microprocessor applications. These basics include the definitions of terms used in clock driver applications, how Phase Locked Loops (PLL) work, what makes the basic PLL into a clock driver, what distinguishes one clock driver from another, and how to select the appropriate devices for a specific application. Also, this application note covers a few of the clock tree design "gotchas." Applications for clock trees abound in the electronics for telecommunications and computer systems. The system requirements are for clocks of several megahertz to hundreds of megahertz. There are many common frequencies that need to be generated based upon the application for the clock. Frequencies of 33 MHz, 66 MHz, 100 MHz, and others are common in most applications. Figure 1 shows two clock trees. A simple clock tree on the left that has a crystal input of 16.66 MHz and a 200 MHz output, but is selectable from 25 MHz to 400 MHz. The clock on the right is more complex, with 16 MHz as its input, and provides as its output several clock outputs of varying drive levels. To compensate for the delay in routing the clock across a backplane or PC board, a zero-delay buffer is used to provide a clock with aligned edges. XTAL 16.66 MHz Clock Synthesizer 200 MHz Clock Distribution Buffer . . . 33.33 MHz 16.66 MHz Clock Generator HSTL Clock Distribution Buffer 200 MHz . . . . . . . . . 33.33 MHz Delay LVCMOS Zero Delay Buffer Delay Line 66.66 MHz 66.66 MHz Figure 1. Typical Clock Trees PLL CLOCK DEVICES The Basic Phase Locked Loop A phase locked loop or PLL is one of the fundamental elements of clock drivers. Although PLLs get used in many different electronic circuit applications, their usage in clock driver circuits dictate certain unique characteristics. It is not the intention of this application note to have complete coverage of phase lock loops. However, the fundamental operation of the PLL circuitry for clock driver applications is covered. A phase locked loop has, as its input, a clock frequency source of which the PLL locks on to and produces, as its output, another clock signal. The output clock may be at the same frequency as the input or at some multiple of the input frequency. If the input clock should change in frequency or phase, the output clock follows this change. A basic PLL clock architecture consists of a phase detector, a low pass filter, and a voltage-controlled oscillator or VCO, which are connected as shown in Figure 2. In addition to these blocks, the PLL has a frequency divider network which, in Figure 2, is called the M divider. This divider network is connected between the output of the VCO and one of the inputs of the phase detector. The other input to the phase detector is the reference frequency to which the PLL is to lock. The output of the PLL is FOUT, which is the clock that is distributed throughout the clock tree system. 832 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1939 FREF FFB Low Pass Filter VCO FOUT Phase Detector network on the output of the VCO provides the M divide value for the feedback path to the input of the phase detector and also divides down the VCO frequency to the desired system frequency or frequencies. Low Pass Filter /N Clock Dividers /M Fanout Buffer FOUT FREF /M FOUT = FREF * M FFB Phase Detector Figure 2. Basic Phase Locked Loop (PLL) The phase detector has two inputs which are compared and used to produce a correction or error signal based upon the difference in the phase of those two inputs. One of these inputs is the previously mentioned reference frequency. The other input is the feedback signal from the VCO/divider network. The PLL correction signal, which is the output of the phase detector, is filtered and applied to the input of a voltage-controlled oscillator or VCO. This filtered correction signal sets the VCO frequency. The output of the VCO is applied to the M (or feedback) divider and becomes the second of the two inputs to the phase detector. When the loop is in "lock," the two inputs to the phase detector are the same frequency and the same phase. This is due to the phase detector correction signal approaching zero and thus stabilizing the input control voltage to the VCO. The VCO output frequency, or FOUT, becomes the reference frequency multiplied by M and continually tracks the reference frequency. The equation for FOUT is the reference frequency multiplied by M. If M is 1, then the output frequency is the same as the input reference frequency. By changing the value of M, the VCO frequency changes in increments of the reference frequency. Thus a lower reference frequency input can be multiplied up to the desired output frequency. The VCO has a limited frequency range over which it can operate. The input frequency multiplied by the feedback divide value must produce a frequency that is within the allowable range of the VCO. If this condition is not met, the VCO is considered to be "railed" high or "railed" low and the PLL is no longer in lock. Basic PLL Clock Driver Figure 3 depicts additions to the previous basic PLL Clock Architecture circuitry, which creates a multi-frequency and multi-clock distribution source. The more complex divider VCO FOUT = FREF * M/N Figure 3. PLL Based Clock Generator The outputs from this example clock generator provide multiple outputs and multiple frequencies for distribution in the application. Fanout buffers are included for each output to provide the required system drive. Also, if the device has a special feedback output, then an equivalent fanout buffer is included for the feedback path. The feedback connection may be external to the device, and this buffer equalizes the delay through the main clock outputs. By incorporating the M divider with the output dividers, the phase relationship is known between the input reference clock and the output clock(s). Also, both the feedback divider and the output divider(s) may be selectable; this allows the user to adjust the output frequency or frequencies. Later in this application note, we will discuss how the external feedback path may also include some PC board trace delay. Design of this external trace delay allows the phase of the output clock to be aligned forward or backward (relative to the input clock phase). A Look at an Actual Clock Driver -- MPC9351 Next, let's look at an actual clock driver. Figure 4 is the block diagram of a typical clock driver, the MPC9351. This device has a PLL block which contains the phase detector and VCO. The input to the MPC9351 can be either a differential clock on the PCLK and ~PCLK inputs or on the single ended input TCLK. The MPC9351 has a total of nine LVCMOS level outputs for system clock usage. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 833 AN1939 PCLK PCLK TCLK REF_SEL EXT_FB (PULLUP) (PULLDOWN) (PULLDOWN) (PULLDOWN) 0 Ref 1 PLL 0 /2 0 D 1 Q QA 1 /4 /8 FB 200 - 400 MHz 0 D 1 Q QB PLL_EN (PULLUP) QC0 0 (PULLDOWN) (PULLDOWN) (PULLDOWN) (PULLDOWN) 0 D 1 QD3 QD4 Q QD2 D 1 QD0 QD1 Q QC1 FSELA FSELB FSELC FSELD OE (PULLDOWN) Figure 4. MPC9351 Clock Generator Block Diagram Of special interest is the divider network and output circuitry. The VCO output of the MPC9351 is available through four banks of outputs where each bank of outputs has a selectable divide value. The first bank of outputs (labeled QA) consists of a single output. This output may provide a clock output frequency of the VCO frequency divided by either 2 or 4. The second bank of outputs (labeled QB) also consists of a single output which can be at the VCO frequency divided by 4 or 8. The third bank of 2 outputs (labeled QC0 and QC1) has the same selectable divide values of 4 or 8. Lastly, the fourth bank has four outputs (labeled QD0 - QD4) with the same divide by either 4 or 8. Although this clock driver does not have specific outputs for the feedback, typically one of the QD outputs would be used for the feedback input to the PLL. The FSELA through FSELD inputs are used to select the output divide ratios for each of the four banks. A typical connection of the MPC9351 is shown in Figure 5. Here, a 33.33 MHz input frequency is multiplied by the feedback divide value of 8 which produces a VCO frequency of 266 MHz. This is in the allowable range of the MPC9351 VCO. The 266 MHz VCO frequency is then divided by 2 for the QA output to produce 133 MHz. Separately, the 266 MHz VCO frequency is divided by 4 for the QB output. Likewise, the 266 MHz VCO is divided by 4 for the QC outputs. This provides one clock output at 133 MHz, four clock outputs at 66.66 MHz, and four clock outputs at 33.33 MHz. 200 MHz < VCO < 400 MHz 33.33 MHz TCLK0 FBin /2 /4 /4 /8 QA QB QC[0:1] QD[0:3] QD4 0 0 0 1 FBSelA FBSelB FBSelC FBSelD VCO QA QB QC0:1 QD0:3 = 33.33 MHz * 8 = 266.66 MHz = 266.66 / 2 = 133 MHz = 266.66 / 4 = 66.66 MHz = 266.66 / 4 = 66.66 MHz = 266.66 / 8 = 33.33 MHz Figure 5. MPC9351 Clock Generator Application 834 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1939 Clock Drivers -- The Differences The Motorola Advanced Clock Driver Selector Guide (SG392) has over 30 PLL clock driver devices. Each of these devices is similar in functionality but each is unique in features and the specifics of their functionality. These devices differ in the number of outputs, how the outputs are divided into banks, what feedback divider ratios are offered, and whether the device has crystal oscillator circuitry or uses an external reference input. The devices differ on whether they have differential or single-ended outputs, the frequency range of the VCO, the output duty cycle, and whether the device has an input divider for the reference. Also, the AC electrical specifications of jitter, skew, and bandwidth vary from one device to the next. The next few sections discuss some of these characteristics. Outputs Typically, a clock driver output is used to deliver a timing signal source to a single location in a design. If multiple locations require clock signals then multiple outputs are used. This simplifies the electrical design and the PC board design. For example, the usage of individual clock outputs eliminates the requirement of matching PC board trace lengths and worrying about trace stubs that one would have to consider when routing a single clock output to many different locations of a PC board. Application requirements of multiple outputs result in clock drivers with different numbers of outputs. Some devices have a few outputs while others have as many as 21 individual outputs. In addition to the number of outputs, the grouping of these outputs into banks differ from one device to the next. Grouping the outputs into banks, with taps to the output divider at different values in the divider chain, allows the device to produce different output frequencies. Therefore, a device may be configured with one bank of outputs to provide a high frequency processor clock, a second bank to provide PCI clock outputs, and a third to provide specific frequencies associated with various I/O peripherals. VDDQ VOH VOL GND LVCMOS VDDQ VOH VOL VTT I = 3.3 = 2.0 = 0.55 = VDDQ/2 = 24 mA 2.5 1.8 0.6 VDDQ/2 8 mA 1.8 1.6 0.2 VDDQ/2 100 A VDDQ VOH VOL VTT I VOH VOL VOH VOL Input/Output Voltage Levels The voltage threshold levels on the input and output of the clock driver differ from one clock driver to the next. Popular logic voltage levels are LVCMOS, LVPECL and HSTL. Also, the clock drivers may have one level for the input clock and a different level for the output clock. Some clocks offer a selection of input levels. For instance, a clock input selection pin would allow the user to select between a differential pair of LVPECL inputs or a single-ended LVCMOS input. LVCMOS is usually used as a single ended input or output. It is specified at 3.3, 2.5, and 1.8 Volts. The voltage levels are compatible to many of the inputs to microprocessors, FPGA or ASIC devices, and peripheral devices. LVCMOS is specified in JEDEC specifications EIA/JESD36 and 80. LVPECL is typically used in differential input and output signaling. It is the low voltage, 3.3 V, version of the 5 V PECL logic specification. (PECL is the positive level specification for ECL logic.) The signal swing is approximately 600 mV and is centered at 1 volt below the supply voltage. The differential nature of LVPECL offers advantages over single ended levels. These advantages are discussed later in this application note. The logic level specification of HSTL stands for High Speed Transceiver Logic. It is specified in EIA/JESD8-6 and is titled "A 1.5 V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits." It may be used as a single-ended logic interface but is more commonly used as a differential signal. HSTL has a differential voltage value Vx and common mode voltage Vcmr. Figure 6 shows the output levels for LVCMOS, LVPECL, and HSTL. For the LVCMOS clocks, the voltage levels of 3.3, 2.5, and 1.8 are shown with the output drive levels as taken from the JEDEC specifications. Other JEDEC specifications also specify LVCMOS drive levels; however, the specifications shown here have the capability of driving 50 ohm transmission lines as would be used in clock distribution. LVPECL = 3.3 = VDDQ - 1.025 = VDDQ - 1.62 = VDDQ - 2 = mA VDDQ VOH VOL VTT I HSTL = 1.5 = VDDQ - 0.5 = 0.5 = VDDQ/2 = mA Figure 6. Logic Levels FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 835 AN1939 AC Characteristics -- Skew and Jitter Two important, but often misunderstood, characteristics of clock drivers are output skew and jitter. Output skew is the difference in the timing of coincident edges between outputs for multiple outputs of a clock driver. Jitter is a deviation in the frequency or period of the output clock from the specified frequency or period. There are three different types of skew defined per the JEDEC specifications. Output-to-output skew is defined as the skew between the various output edges on a single device. Process skew is defined as the skew between the same output pin on different devices due to process variation. Finally, part-to-part skew is defined as the skew between any output on two different devices. Figure 7 illustrates output skew types for both single-ended and differential output waveforms. Typically, both output-to-output and part-to-part skew is specified on a data sheet. Output 1 Output 2 tsk(o) 1 n tn tn+1 tJit(CC) = |tn - tn+1| Cycle-to-Cycle Jitter 1/f0 Ideal Output tcycle n Actual Output tjit(per) = |tcycle n - 1/f0| Period Jitter Reference Clock Input Output 1 Differential Output 2 tsk(o) Feedback Input 1 n t() tjit() = |t()) - t() mean| Phase Jitter Figure 7. Output Skew Jitter is a deviation of the edge location on the output of the clock buffer. There are three categories of jitter that are of interest: cycle-to-cycle, period, and phase jitter. One, two or all three may be specified on a clock driver data sheet. The first two are associated with both PLL and non-PLL clock drivers. The third, phase jitter, is only associated with PLL based clock drivers. Cycle-to-cycle jitter is the difference in time between the periods of any two adjacent clock cycles. Period jitter is the deviation of time of individual periods of a signal with respect to an ideal period. Phase jitter represents the timing variation of the output with respect to the input associated with a PLL clock driver. Figure 8 shows the three types of jitter along with the associated mathematical definitions. Additional details of skew and jitter may be found in the Motorola Application Note, AN1934. Figure 8. Clock Jitter AC Characteristics -- Tracking Bandwidth PLL clock drivers lock on to an input reference frequency and remain locked to that frequency. If that reference frequency varies, the PLL will follow that frequency and remain locked to the new input frequency. However, if the input frequency varies at a rate faster than the PLL can keep up with, then the output frequency will not track the input reference change and the PLL with appear to ignore the variation in the input frequency. The point that the PLL does not follow input frequency changes defines the upper bound of the PLL bandwidth. The bandwidth of a PLL has a transfer characteristic much like a transfer characteristic of a lowpass filter. The bandwidth characteristic can be used to an advantage in certain clock applications. Higher frequency noise or jitter on the reference clock input can be filtered by this characteristic. Input jitter above the bandwidth will not pass to the output of the VCO while input jitter below the bandwidth will pass through to the output. 836 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1939 Bandwidth of the PLL clock driver varies based upon the actual design of the PLL. One of the components that affect the bandwidth is the feedback divide ratio. Figure 9 shows a typical PLL clock generator and its bandwidth curves. PLL clock driv10 5 0 -5 -10 -15 -20 1 10 100 1,000 Modulation Frequency (kHz) ers that have selectable feedback divide ratios also have variable bandwidths. Higher divide ratios lower the bandwidth of the PLL clock driver. Phase Gain (dB) Figure 9. PLL Clock Generator Bandwidth PLL Clock Driver Categories Motorola PLL clock drivers are sorted into three different categories. The three categories are frequency synthesizers, clock generators, and zero-delay buffers. Although the categories are based upon the intended application, each category also reflects some uniqueness of the AC characteristics of the PLL. Frequency Synthesizers The first category of PLL based clock drivers is clock synthesizers. Clock synthesizers usually start with a low frequency clock source, which may come from an external source or from a crystal oscillator. This low frequency source may be further divided to produce an even lower PLL input reference frequency. With the use of the PLL, the low frequency reference frequency is multiplied up to the desired output frequency. If the device has a crystal oscillator as a reference, the oscillator circuitry would typically be part of the IC circuitry with the only required external component that of a crystal. The clock synthesizer usually has output frequency steps with fine granularity or resolution such as 1 MHz. The overall output frequency of the clock synthesizer may be as high as 850 MHz. Examples of Motorola clock synthesizers are MPC9229, MPC9230, and MPC9239. The MPC9229 and MPC9230 each start with a midrange clock source, typically 16 MHz. This input frequency is divided by 16, which then becomes a 1 MHz input reference to the PLL. A programmable feedback divider then effectively multiplies this reference to the VCO frequency. The VCO frequency is then divided to produce the desired output frequency, as shown in Figure 10. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 837 AN1939 XTAL_IN XTAL_OUT XTAL 10 - 20 MHz /16 Ref VCO /4 PLL 800 - 1800 MHz FB /0 TO /511 9-BIT M-DIVIDER 9 /1 /2 /4 /8 00 01 10 11 OE FOUT FOUT SYNC TEST 2 N-LATCH 3 T-LATCH TEST VCC P_LOAD S_LOAD LE P/S M-LATCH 0 BITS 5-13 S_DATA S_CLOCK VCC M[0:8] N[1:0] OE 1 BITS 3-4 0 14-BIT SHIFT REGISTER 1 BITS 0-2 Figure 10. MPC9229 Frequency Synthesizer A frequency synthesizer usually has a limited number of outputs; either one or two. The output frequency may be configurable in the user application. The ability to change the output frequency in small steps allows the circuit designer to do frequency margining. This is a technique where the system frequency is gradually increased/decreased while analyzing system performance. The bandwidth of frequency synthesizers is usually the lowest of the three clock driver categories. Typical bandwidths for clock synthesizers are usually 30 to 50 kHz. The clock synthesizer allows the system design to use a low frequency and low cost crystal oscillator and multiply the frequency up to the actual desired frequency, thus reducing the cost of the high frequency clock generation. 838 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1939 Clock Generators Clock generators are used to generate clocks that are synchronous and phase aligned to an input reference clock. The category of clock generators make up the largest portion of Motorola's portfolio of the three categories of PLL based devices. These devices typically have multiple outputs which are often grouped into multiple banks of outputs. Each bank can be set up for a different frequency. The previously discussed MPC9351 device is in the category of clock generators and, as we saw from the block diagram, it had nine outputs which were spread across four banks of outputs. The output frequency adjustment step is usually more coarse than with the clock synthesizer. The reference frequency for a clock generator might be 15, 20, or 25 MHz, which would set the frequency step to a minimum of 15, 20, or 25 MHz. In some applications the previously discussed clock synthesizer might be used to generate the input clock for clock generators. Some clock generators have a crystal oscillator circuitry built-in. The bandwidth of a clock generator is higher than that of a clock synthesizer and may be in the range of 300 to 500 kHz. This is considered to be a midrange bandwidth device. Clock generators maintain a phase relationship between the input clock and the output clock. FREF Low Pass Filter /N Clock Dividers /M FB Trace Delay Ref_to_output_delay = t() - (tFB_DELAY - tLOAD_DELAY) or Ref_to_output_delay = t() + (tLOAD_DELAY - tFB_DELAY) LOAD Trace Delay FOUT Zero-Delay Buffers The third category of PLL clock drivers is zero-delay buffers. The concept of a zero-delay clock buffer for clock distribution may be a bit foreign, but with the use of a PLL, the concept is quite possible. The category of zero-delay buffers offers a higher bandwidth PLL than the clock generator category. Typical bandwidths are 1 to 2 MHz. The zero-delay buffer maintains a known and precise phase relationship between the input and output clock waveforms. By adjustment of the feedback path delay, the output clock waveform may be aligned exactly to the input clock. This feedback path delay would typically be produced by the length of the PC board trace. Knowing the characteristics of the PC board material and the construction of the trace on the board can produce precise delays. Typical trace delays might be 1 to 2 ns per foot. Thus, a few inches of PC board trace can shift a clock output relative to the clock input by a significant amount. Figure 11 shows a zero-delay buffer and the equations that define the effective delay of the clock through the device. The parameter of t() is the effective delay of the zero-delay buffer. The Load Trace Delay shown on one of the clock outputs is the normal trace delay that is produced by routing the clock across the PC board. The effect of this delay can be effectively eliminated with the use of a zero-delay buffer. Phase Detector VCO Figure 11. Zero-Delay Buffer Although the zero-delay clock buffer is PLL based and shares many of the same characteristics with the clock generator, it typically has better jitter and skew performance. Clock Distribution Buffers In addition to the PLL based clock drivers, Motorola offers a number of devices classified as distribution buffers. There are two categories: LVCMOS single-ended output and differential clock output buffers. Figure 12 shows two of the LVCMOS output devices. The MPC961C and the MPC961P have the same number of outputs with the same output AC characteristics; however, they differ on the type of inputs. The MPC961C has LVCMOS inputs while the MPC961P has LVPECL compatible inputs. The devices can distribute an "at frequency" clock to many locations on a PC board. Some of these clock buffers offer a built-in divider block to be able to optionally divide the input clock by two. Care should be used when using this optional divider as a half frequency output can induce additional noise and thus cause jitter to the full frequency clock. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 839 AN1939 Q0 PECL LVCMOS_CLK Q1:Q16 PECL Q17 Q0 Q1:Q16 Q17 OE MPC961C OE MPC961P Figure 12. LVCMOS Clock Buffers, MPC942C and MPC42P As previously mentioned, one of these categories of clock buffers have differential outputs. These outputs, and typically the input, are LVPECL or HSTL levels. Differential input and output signals offer many advantages as are discussed in the following section. An example of a differential output buffer is the MC100ES6111 differential clock driver shown in Figure 13. It has LVPECL inputs and 10 pairs of LVPECL outputs. CLK0 CLK0 CLK1 CLK1 CLK_SEL 0 1 10 Q0:Q9 Q0:Q9 Figure 13. Differential Output Buffer MC100ES6111 Clock Redundancy Some systems require a backup or redundant clock to be generated. Figure 14 shows two applications of a redundant clock system. Clock Source #1 Clock Source #2 System Distributed Clock The diagram on the left of Figure 14 shows a redundant main clock being sourced from two different central clock generation points and distributed over a cable or backplane. In this application, the redundant clock switch assures that a clock is available in the event of a removed clock board or a dead clock source. The diagram on the right of Figure 14 shows a locally generated clock is available as a backup clock and must be switched in when the main clock fails. The redundant clock switch must make the transition from the current clock source to the backup clock in a smooth manner. While the transition takes place, the output of the clock generator must be stable with no disruption in the clock signal. The generation of runt pulses or short cycle clock periods must be avoided. Motorola offers the MPC9993 Intelligent Dynamic Clock Switch as shown in Figure 15. The input clock sources come through the differential pair inputs of CLK0 and CLK1. The device automatically selects the good input and supplies this to the PLL. On detection of a clock failure, the device smoothly switches to the second input and continues to supply a clock to the PLL. A clock failure is defined as the input clock pins stuck high or low for at least one clock period. Status outputs from the Dynamic Switch Logic provide an indication of the current clock source. Redundant Clock Switch Local Clock Source Redundant Clock Switch Figure 14. Redundant Clock Applications 840 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1939 PLL_En Clk_Selected Inp1bad Inp0bad Man_Override Alarm_Reset Sel_Clk CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR PLL DYNAMIC SWITCH LOGIC Qb0 Qb0 Qb1 Qb1 /2 /4 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 Bank B Bank A Figure 15. MPC9993 Redundant Clock Generator The specification for the MPC9993 lists the maximum rate of period change as this clock switch is made. The data sheet also lists the typical delta period/cycle of 200ps/cycle. An actual clock switch may take as many as 100 to 200 clock cycles to complete. And as a result, the output will appear to be a "graceful" change from one clock source to the next. The automatic valid clock reference detection function may optionally be disabled and the clocks may be selected/switched manually. The multiple outputs of the MPC9993 provide drive capability for several application system interfaces for the output clock as well as providing the feedback input to the PLL. The VCO for this device runs at 4X the input clock frequency. The outputs of the MPC9993 are grouped into two banks. Bank A is the input clock divided by 4 and has two outputs. The output of this bank is typically used for the feedback to the phase detector. Bank B consists of 3 separate outputs and is the input reference divided by 2. Figure 16 shows a possible connection for a redundant clock system using the MPC9993. The main clock reference comes externally from the system while the backup clock comes from a MPC9229 crystal oscillator based source. One pair of the differential Bank A outputs are routed back to the EXT_FB inputs. The remaining Bank A pair of outputs and Bank B outputs are available for system usage. Clk_Selected Inp1bad Inp0bad Man_Override Alarm_Reset Sel_Clk MPC9993 Main Clock CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB M[8:0] N[1:0] Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 X 2 Outputs Qa0 Qa0 X 1 Outputs Qa1 Qa1 16 MHz MPC9229 50-90 MHz Figure 16. MPC9993 Redundant Clock Application FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 841 AN1939 Figure 17 shows the "switchover" from the current clock to the backup clock. Clock A and Clock B represent the two available clock sources. When Clock A fails, this triggers the switch to Clock B. The MPC9993 slowly slews to the phase of Clock B and, after many input clock cycles, the output clock is in phase with Clock B. connections for the outputs and the PLL analog circuitry. The example shown in Figure 18 separates out the analog supply, VCCA, from the supply driving the rest of the chip. A simple RC filter decreases the noise injected into the analog supply pin, minimizing the jitter due to power supply noise. The value of RS must be calculated based up the maximum ICCA current. Filter caps should be of high quality for best overall frequency characteristics. Noisy power supplies may significantly compromise good clock tree designs on paper. 2.5 V or 3.3 V Clock A Transition occurs over many cycles Phase aligned Clock B RS VCCA 0.1 F 22 F Output Clock Figure 17. MPC9993 Clock Switch Clock Tree Design and Layout Clock performance can be predicted by understanding the clock functionality and data sheet parameters for jitter and skew, but the overall clock performance is highly dependent on design of the clock circuitry and its environment on the PC board. The following sections point out areas of clock design that need special attention to ensure the best clock performance obtainable from the design. The first of these topics is that of power supplies. Power Supplies Noisy power supplies have an affect on clock trees by generating jitter on the clock outputs. This is due to the noise on the power supply affecting the input-switching threshold and/or modulating the input control voltage to the VCO. Many of the Motorola clock generators offer separate PLL power pins, allowing for the isolation of the PLL power from the output driver supply. Use lots of high quality filter caps and (physically) place them as close to the clock driver package as possible. Most of the PLL clock driver devices are analog devices. These drivers are designed with separate power supply VCC 0.1 F Figure 18. Power Supply Filtering PC Board Trace Impedance Matching In system applications utilizing high frequency clocks and/or microprocessor bus speeds, the PC board traces are characteristic transmission lines and must be treated appropriately. Termination of the transmission line must be done in order to minimize reflections and maintain proper signals in the system. Either parallel termination or series termination may terminate clock-signaling lines. Each method has advantages. Parallel termination places a resistor on the load end of the transmission line. The value of the termination resistor is equal to the impedance of the transmission line. Figure 19 depicts the parallel termination on a clock line with the associated waveform of a clock edge propagating down the line. Since the parallel termination is equal to the characteristic impedance of the line, there is no reflection when the clock edge reaches the load. 842 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1939 tpd VA VB VA tpd VB Rl-Ro Ro VTT V VA Gnd V VB tpd tpd = propagation delay of transmission line Gnd VB tpd tpd VA V V/2 Gnd V V/2 Gnd tpd = propagation delay of transmission line Figure 19. Parallel Termination with Waveform Series termination places a resistor on the source end of the transmission line and in series with the transmission line. The resistor value is chosen such that the output impedance of the clock driver output buffer, plus this resistor, equals the characteristic impedance of the transmission line. No termination impedance is placed at the load end of the transmission line. Figure 20 shows the waveform of a clock edge as it appears on the output of the clock driver and as it propagates down the transmission line. As the clock edge starts down the transmission line, the series resistor and the impedance of the transmission line act as a voltage divider causing an edge of amplitude V/2 to be propagated. After tpd time period, the edge arrives at the load end of the transmission line. This point appears to be an open line to the propagated edge causing a reflection of the edge of amplitude V/2 to be sent back to the source. On arrival at the source, the reflected waveform encounters the series termination which damps the reflected voltage and the waveform establishes a steady state. Since the voltage at the source is V and the voltage at the load is also V, there is no current flow down the transmission line other than the initial charging of the line. The advantage of series termination is that there is no steady state loading on the line and thus the steady state drive requirements of the clock driver is low. Single-Ended Verses Differential Clock Lines Distribution of clock signals via differential paths has several advantages over single-ended clocks. Most of these advantages relate to noise immunity. Figure 20. Series Termination with Waveform Even though the differential clock complicates the routing of the PC board by doubling the number of traces, differential clocks may ease the PC board layout due to ground plane issues. All currents are in the signal traces for the differential pair and not in the underlying ground plane. Thus, the effects of breaks or discontinuities in the PC board ground plane within the vicinity of the clock drive circuitry are minimized. In addition, since one output or the other is always driving a signal, the constant supply current leads to VCC/Ground Bounce reduction. There are many detailed references dealing with the subject of PC board layout and transmission line characteristics, which should be consulted for additional information. Steps in Selecting a Clock Driver Now that we have looked at the definitions, characteristics, and categories of clock driver devices, the question is, "How do I choose the devices or devices that fit into my application?" The following list of questions should be answered in order to understand what type of clock drivers are required. 1. What are the input and output requirements for logic levels in the application? 2. Does the application have or require differential input or output? 3. What is the clock source? Is it externally provided? What is the frequency? 4. Is a PLL based clock driver required? 5. What are the output frequency requirement(s)? 6. What number of outputs at each frequency is required? FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 843 AN1939 Once these user application questions are answered, the next step in the clock design is to consult the Advanced Clock Driver Selector Guide for devices that match these requirements. If a PLL clock driver is needed, determine the feedback divide ratio and determine if the allowable VCO range is met. Once the VCO frequency is determined, next determine the output divide ratios required meeting output frequency requirement(s). Once a potential device has been selected, evaluate the jitter and skew specifications of that device based upon the system parametrics. SUMMARY Whether the clock design is simple or complex, the performance of the clock circuitry can best be optimized by an understanding of the parameters of the clock devices involved in the design. Many parameters may be of little or no importance to the design; however, the designer should understand these parameters and make that determination. Finally, clock tree design should be given proper attention to ensure the reliability of the system design. Clock Driver Resources AN1934/D -- Effects of Skew and Jitter on Clock Tree Design DL207/D -- Advanced Clock Drivers Device Data Book SG392/D -- Advanced Clock Drivers Selector Guide 844 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Freescale Semiconductor, Inc. APPLICATION NOTE Order number: AN1933 Rev 0, 07/2004 AN1993 Clock Generation for PowerQUICC III By: Don Aldridge INTRODUCTION The MPC8560/40 or PowerQUICC III processors are the latest in a family of communications and control processor devices produced by the Motorola Semiconductor Networking and Communications Systems Group. These processors provide high-end computing and networking communications platforms for Telecom, Networking, and other communications applications. The purpose of this document is to discuss clock requirements for this family of microprocessors and to provide reference methods to generate these clocks. Included in this document is the introduction and discussion of a single-chip clock generator designed specifically to meet the PowerQUICC III clock requirements. POWER QUICC III CLOCK REQUIREMENTS The clock requirements for the MPC8560/40 or PowerQUICC III family are three-fold and consist of: 1. A system clock for the processor CPU. 2. A RapidIOTM interface clock 3. One or more communications clocks for Ethernet, Gigibit Ethernet etc. All three of these clock inputs are typically independent of each other in both frequency and phase. Also, the exact frequency of each clock is overall system dependent. The system clock input of the PowerQUICC III drives the main CPU or what is referred to as the e500 core. The exact frequency of this input clock is set by the system bus frequency requirement and is at a lower frequency than the core frequency. This bus frequency is then internally multiplied by the PowerQUICC III architecture to the final CPU frequency. Figure 1 shows the system clock generation circuitry internal to the MPC8560 PowerQUICC III. The system clock input is labeled SYSCLK/PCI_CLK and the PowerQUICC III internally multiplies this input frequency to the desired internal CPU frequency with an internal PLL (Phase Lock Loop). This multiplication is actually performed in a two-step process with two separate PLLs. The intermediate clock frequency, labeled CCB_clk is the core complex clock and is also referred to as the platform clock. This clock is used by the synchronous system logic of the PowerQUICC III. The e500 core clock is labeled core_clk and is generated from the CCB_clk with a separate internal PLL. e500 CORE cfg_core_pll[0:1] CORE PLL core_clk CCB_clk DLL cfg_sys_pll[0:3] SYSCLK/PCI_CLK MSYNC_IN MSYNC_OUT MCK[0:5] MCK[0:5] LSYNC_IN LSYNC_OUT LCK0 LCK1 DEVICE PLL DLL CCB_clk TO REST OF PLATFORM Figure 1. PowerQUICC III System Clock FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 845 AN1993 Configuration inputs to the PowerQUICC III are used for setting the ratio of the CCB_clk to the SYSCLK and for setting the ratio of the core_clk to the CCB_clk. Details of these inputs and the allowable clock configurations are found in the PowerQUICC III Electrical Characteristics document. The SYSCLK frequency may range from 16 MHz up to 133 MHz. The system clock for the PowerQUICC III is a single-ended 3.3 V LVCMOS voltage input. The RapidIOTM transmit clock input sets the data rate for the RapidIOTM data transfer bus. This clock input is a differential LVDS clock and may be configured for up to 500 MHz. This single differential LVDS input pair to the PowerQUICC III is used to drive the entire RapidIOTM circuitry. Figure 2 shows the RapidIOTM clock circuitry internal to PowerQUICC III. RIO_RCK RIO_RCK CCB_clk CLOCK SYNTHESIS CHIP RIO_TX_CLK_IN RIO_TX_CLK_IN RIO_TCK RIO_TCK cfg_rio_clk Figure 2. PowerQUICC III RapidIOTM Transmit Clock The Gigibit Ethernet Interface input clock requirement is a LVCMOS clock at 125 MHz. This clock may be sourced directly to the PowerQUICC III or more typically comes from the externally supplied "PHY" for the Gigibit Ethernet Interface. The input frequency to the PHY may be at 125 MHz or as is quite often the case, derived from a lower frequency such as 25 MHz. The PHY then provides the 125 MHz required by the Gigibit Ethernet clock input. The data sheet for the desired PHY should be consulted for this information. Other communication interfaces for the PowerQUICC III may require other clock inputs, however these frequencies vary and are dependent on the specific communications interface. The PowerQUICC III memory clock requirements are handled by two DLLs (Delay Lock Loop) contained in the PowerQUICC III. The PowerQUICC III has two memory bus types, which are main and local memory. Main memory uses DDR memory and local memory uses SDRAM memory. The Main Memory DLL has six differential clock outputs for connection to memory modules. In addition a delay loop for adjusting the timing of the clock waveforms is provided. This delay loop consists of an MSYNC_OUT output and a MSYNC_IN input. A trace on the PC board will be used to connect the MSYNC_OUT to the MSYNC_IN with the trace length based upon specific board layout. The length of delay loop trace is used to adjust the edge timing of the memory clock at the clock module input. The Local Memory DLL has two LVCMOS clock outputs and similar delay loop input and output signals. CLOCK GENERATOR FOR THE POWERQUICC III Deriving these clocks for the PowerQUICC III may be done in a variety of ways. A separate crystal oscillator, at the required frequency, for each clock input may be considered. Crystal oscillators are available in a wide range of frequencies up to approximately 150 MHz. If multiple copies of a specific clock are required, the oscillator output should be buffered with a clock fanout buffer such as the MPC9443 1:16 fanout buffer, or the MPC9446 1:10 fanout buffer. Also a PLL based clock generator or frequency synthesizer may be used to produce the desired clock tree by multiplying a lower frequency oscillator to the desired frequency or frequencies. Recommended clock generators are the MPC9772/3 or the MPC9600. The MPC9772/3 are 12 output LVCMOS output clock generators. The MPC9772 accepts either a LVCMOS clock input or has a crystal oscillator requiring only a user supplied crystal for frequency selection. The MPC9773 accepts either a differential LVPECL clock or a single-ended LVCMOS clock input. The MPC9600 PLL based clock generator has a total of 21 clock outputs and uses either a LVCMOS or LVPECL clock input. The high frequency requirements of the RapidI/O clock would typically require the use of a clock synthesizer. Devices such as the MPC9239 are capable of producing up to 900 MHz clocks. This synthesizer uses as a reference a 16 MHz user-supplied crystal and has a single LVPECL output. This output may be programmed to any frequency across its output range 846 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1993 in 16 MHz steps. A special derivative of this synthesizer, the MPC9259, provides LVDS outputs matching the input requirements of the PowerQUICC III. Motorola has created a clock generator specifically for the PowerQUICC III. The following information provides details on this single PLL based clock generator/fanout buffer that supplies all of the PowerQUICC III clock inputs. This unique clock generator/fanout buffer is the MPC9850 and is discussed in the following section. 0 1 0 1 Ref PLL 2000 MHz OSC MPC9850 CLOCK GENERATOR The MPC9850 has been designed to supply the clocking requirements for the MPC8560/MPC8540 PowerQUICC III processor series in a single low cost package. This clock uses commonly available reference sources for the clock source and is packaged in a 100-ball MAPBGA package. This package is targeted for both low cost and high functionality applications. Figure 3 shows a block diagram of the MPC9850. CLK0 PCLK1 PCLK1 REF_CLK_SEL XTAL_IN XTAL_OUT REF_SEL 1 0 /N QA0 QA1 QA2 QA3 /N PLL_BYPASS REF_33MHz QB0 QB1 QB2 QB3 /4, 8, 16 CLK_A[0:5] CLK_B[0:5] RIO_C[0:1] MR POR QC0 QC0 QC1 QC1 REF_OUT Figure 3. MPC9850 Block Diagram The MPC9850 has a total of 8 LVCMOS outputs divided into two banks of four outputs per bank. Output Bank A and B provides LVCMOS output clocks and each bank is selectable between 3.3 V and 2.5 V operation. The two banks are independently programmable to any of the large selection of output frequencies. Commonly used system frequencies available include 16, 33, 50, 66, 83, 100, 111, 125, 133, 166 and 200 MHz. A series of six (for each bank) frequency selection pins are used for configuration of the output frequency on each bank. A table in the data sheet lists the programming values for the above listed commonly used system frequencies. Additional output frequencies are available from the MPC9850. Although not listed in the table the programming configuration of the additional frequencies can be calculated with a simple output frequency equation as shown in the MPC9850 data sheet. These two banks of outputs would typically provide the system clock for the PowerQUICC III with additional outputs available for other system frequency inputs. A third bank of outputs, Bank C, delivers the RapidIOTM clock output of up to 500 MHz. Output levels on this bank provide the required LVDS I/O levels. LVDS (short for Low Voltage Differential Signaling) provides a differential clock drive that is intended for higher frequency clock distribution. Two frequency configuration pins are used to select between the three standard RapidIOTM frequencies of 125, 250 or 500 MHz. A fourth frequency of 50 MHz is used for factory test. The clock input for the MPC9850 may be provided by any one of 3 source types. These are either a single-ended LVCMOS reference, a LVPECL differential reference or an crystal oscillator. For crystal oscillator operation an externally supplied crystal is connected to the MPC9850s internal oscillator. The frequency source may be either 25 MHz or 33 MHz. For crystal oscillator operation a 25 MHz crystal must be supplied. The crystal should be specified as a fundamental mode crystal with a 20 pF load. The reference output is also buffered to an output pin for system usage. The MPC9850 is a PLL (phase locked loop) based clock generator. PLL based clock generators work by multiplying a low frequency reference to a frequency that is typically higher than the highest desired output frequency. This higher frequency is then divided down to the desired output frequency or frequencies. Using the high frequency capabilities of SiGe:C FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 847 AN1993 technology, the MPC9850 PLL multiplies the 25 or 33 MHz reference input to 2000 MHz. The multiplication factor is either 80, for a 25 MHz reference or 66 for a 33 MHz reference. By using configurable output dividers the 2000 MHz VCO frequency is divided to the required output frequency(s). Separate dividers are used for output banks A and B, thus making these two output banks independently configurable. The MPC9850 requires no external loop filter components for the PLL. Each output is capable of driving a single 50-ohm transmission line for clock distribution on the PC board. Proper termination of each output is required to minimize transmission line reflections. Multiple copies of PCIx clock MPC9850 XTAL_INQA1 QA0 Q1 XTAL_OUT 3.3 REF_SEL PLL_33 MHz QB5 QB0 AVAILABLE FOR SYSTEM USAGE QC5 001111 001111 CLK_A[0:5] CLK_B[0:5] QC0 QC0 3652 11 R10_C[0:1] 25 MHz 125 MHz 500 MHz 100 500 MHz RAPID I/O LVDS LCK0 LCK1 LSYNC_OUT LSYNC_IN LOCAL MEMORY AVAILABLE FOR SYSTEM USAGE PLL PLATFORM CLOCK PLL CORE CLOCK 36 The 100 lead MAPBGA package provides an optimal number of power and ground connections to minimize jitter, output skew and ground bounce. The package pitch is 1.0 mm spacing to ease PC board layout and manufacturing. PowerQUICC III CLOCK SYSTEM CONFIGURATION Figure 4 shows the MPC9850 clock generator supplying the clocks to a MPC8560/40 PowerQUICC III processor system. In this application the MPC9850 supplies a 66 MHz system clock, a 500 MHz RapidIOTM clock and a 25 MHz Gigabit Ethernet PHY clock. Platform max = 333 MHz Platform clock X 2, 2.5, 3, or 3.5 = core clock Core max freq = 833 MHz MPC8560 SYS_CLK 25 MHz PHY G_Ethernet MCK[0:5] MCK[0:5] MSYNC_OUT MSYNC_IN MAIN MEMORY Figure 4. System Block Diagram MPC8560/40 w/MPC9850 Clock Generator For this reference design, the clock source is a 25 MHz reference, generated by a crystal attached to the MPC9850's XTAL_IN and XTAL_OUT oscillator pins. The crystal requirements are parallel resonance fundamental crystal with a specified load capacitance of 20pf. This crystal is of a standard frequency and load specifications and readily available from most any crystal manufacturer or electronics parts supplier. The REF_SEL input is configured for a crystal oscillator source and the Ref_33MHz pin is configured for a 25 MHz reference frequency. Output banks A and B drive the processor system. The bank A output, QA0, is connected to the PowerQUICC III SYS_CLK input leaving the remainder of Bank A and all of Bank B for other system clock applications. Both banks are configured for 66 MHz; however, Bank B could be configured for 33 MHz if the 33-MHz PCI clock is needed. All outputs should be properly terminated for the PC trace impedance. Termination may be either series or parallel terminated. In this design, series termination is used and based upon a board trace impedance of 50 ohms, a 36-ohm series resistor is used. For optimum signal integrity it is recommended that any unused outputs be terminated. If not terminated, these unused outputs should remain completely unconnected to any PC board trace. Transmission line termination will be further discussed in a following paragraph. The RapidIOTM input of the PowerQUICC III is connected to one of the two Bank C outputs and is configured for a 500 MHz clock. This output should be terminated with a differential connection of a 100-ohm resistor at the input of the MPC8560/40. The REF_OUT output of the MPC9850 is used to supply a 25 MHz reference to the input of the typical user selected Gigibit Ethernet PHY. This reference clock output is a buffered copy of the input reference and does not go through the clock generator PLL. This provides a frequency accurate and jitter free source for Ethernet applications. 848 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA AN1993 TRANSMISSION LINES As previously mentioned, all clock outputs should be properly terminated according to the PC board transmission line characteristics. Either series or parallel termination method may be used. The above reference design uses the popular series termination technique. Series termination uses a small valued resistor in series with the clock driver output. This resistor is located close to the clock output. The value of this resistor is chosen in conjunction with the output impedance of the clock driver output such that the sum of the driver output impedance plus the series resistor equals the PC board characteristic impedance. A clock driver output impedance of approximately 14 to 18 ohms would be POINT A tPD POINT B combined with 32 to 36 ohms to match a 50-ohm transmission line. The far end of the clock transmission line directly connects to the high impedance input of the microprocessor or other receiver input. For series termination, there is no resistor at the clock receiver input. Series termination relies on the fact that there is a high impedance at the far end of the transmission line and a 100% waveform reflection occurs when the clock edge reaches the far end of the transmission line. Advantages of series termination are a single resistor requirement and the steady state current draw due to the transmission line is zero. Disadvantages are the resistor value is dependant on the clock driver output impedance. POINT A POINT B POINT C RS tPD R0 POINT A tPD POINT B VDDQ POINT A VTT VDD POINT B tPD tPD VDDQ VDDQ VDDQ/2 VDDQ VDDQ POINT C Parallel Terminated Lines Series Terminated Lines Figure 5. Transmission Line Termination Parallel termination uses a termination resistor equal to the characterization impedance of the PC board transmission line and is located at the receiver end of the transmission line. This resistor is located at the input of the PowerQUICC III input and is connected from the input to a constant voltage source referred to as VTT. VTT for a LVCMOS input is typically defined as VDD/2. The parallel termination resistor value is independent of the output impedance of the clock driver output. Therefore, for a 50 ohm PC board trace impedance the parallel termination would use 50-ohm termination resistors. If a VTT source is not readily available a Thevenin equivalent resistor combination may be used instead. This requires two resistors, one from input to VDD and one from input to GND. The advantage of parallel termination is the independence of the resistor value from the clock driver output. The disadvantages are the requirement of the VTT supply or two resistors, and the large steady state current draw of the transmission line. Termination of the LVDS differential output requires a 100-ohm resistor. This resistor is located at the LVDS receiver input and is connected between the differential inputs. Unused outputs should either be terminated (recommended) or left unconnected. If unconnected, the output pins of the MPC9850 should not have any PC board trace connected to them. POWER SUPPLIES The MPC9850 operates from a 3.3 V supply with either a 3.3 V or 2.5 V supply for the output drive. The power supply connections should be made with heavily bypassed supply planes. The MPC9850 has four types of power supply pins. These are VDD, VDDOA, VDDOB, and the VDDA pin. VDD is the main supply of 3.3 V to the MPC9850. The MAPBGA package provides several VDD leads and all should be connected to the 3.3 V supply plane. The VDD power plane should be heavily bypassed with small valued and small physical size capacitors with good high frequency characteristics. The capacitors should be located as close to the MPC9850 package as possible. VDDOA and VDDOB are used to supply either 3.3 V or 2.5 V to Banks A and B output drivers. As with VDD the MPC9850 has several pins dedicated to VDDOA and VDDOB, and all should be connected to the desired supply and properly bypassed. Two VDDA pins are used to supply a separate and noise filtered 3.3 V supply voltage to the analog sections of the MPC9850. These pins should be connected to the 3.3 V supply through the recommended RC filter for the best isolation of PC board generated power supply noise. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 849 AN1993 3.3 V RS = 10 to 15 VDDA 0.1 F 22 F In addition to the MPC9850, low cost derivatives of the MPC9850 are available. These are the MPC9855 and the MPC9817. The MPC9855 is a MPC9850 pin compatible clock generator that provides the same functionality of the MPC9850 without the RapidIOTM clock outputs. The MPC9817 clock generator is designed to provide common PCI clock frequencies in a low-cost 20-pin SSOP package. The device offers a single bank of 5 clock outputs that maybe configured for 25, 33, 50 or 66 MHz. The MPC9817 also offers a single bank of 3 outputs that provide the 25 MHz for I/O applications. References (1) MPC8560 User Manual (2) MPC8560 Electrical Characteristics Guide (3) MPC9443 Fanout Buffer Data Sheet (4) MPC9446 Fanout Buffer Data Sheet (5) MPC9772 Clock Generator Data Sheet (6) MPC9773 Clock Generator Data Sheet (7) MPC9600 Clock Generator Data Sheet (8) MPC9239 Clock Synthesizer Data Sheet (9) MPC9259 Clock Synthesizer Data Sheet (10) MPC9850 Clock Generator Data Sheet (11) MPC9855 Clock Generator Data Sheet (12) MPC9817 Clock Generator VDD 0.1 F Figure 6. VDD Analog Supply Pin SUMMARY AND SUPPORT OF OTHER MICROCONTROLLERS AND MICROPROCESSORS The MPC9850 was designed to supply the entire clock input requirements to a PowerQUICC III processor. Although the MPC9850 was specifically designed for the PowerQUICC III, many features make this clock generator applicable to other PowerPC, PowerQUICC or other industry standard microprocessors. The selectable output frequencies of the MPC9850 are also the system frequencies typically found in other processor based system designs. 850 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 1 2 3 4 5 6 7 8 9 10 Advanced Clock Drivers Selector Guide Clock Generator Data Sheets QUICCClock Generator Data Sheets Failover or Redundant Clock Data Sheets Clock Synthesizer Data Sheets Zero-Delay Buffer Data Sheets LVCMOS Fanout Buffer Data Sheets Differential Fanout Buffer Data Sheets Packaging Information Application Notes How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-0047, Japan 0120 191014 or +81 3 3440 3569 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2004. All rights reserved. xxxxxx DL207 Rev. 0 Rev. 2 8/2004 xx/2004 |
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