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Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Datasheet Product Features s s s s High Performance Processor based on Intel(R) XScaleTM Microarchitecture -- 7-8 stage Intel(R) Superpipelined Technology -- 32-Entry Instruction Memory Management Unit -- 32-Entry Data Memory Management Unit -- 32 KByte, 32-way Set Associative Instruction Cache -- 32 KByte, 32-way Set Associative Data Cache -- 2 KByte, 2-way Set Associative Mini-Data Cache -- 128-Entry Branch Target Buffer -- 8-Entry Write Buffer -- 4-Entry Fill and Pend Buffers Intel(R) Dynamic Voltage Management -- Core Voltage Range: 0.95 V to 1.55 V -- Internal Clock Scalable by Software up to 733 MHz -- Input Clock: 33-66 MHz ARM* Version 5TE Compliant Application-Code Compatible with Intel(R) StrongARM* SA-110 s s s s s Power Management -- Core Power is ~500mW at 600MHz -- Core Voltage Operation Down to 0.95 V -- Idle and Sleep Modes Intel(R) Media Processing Technology -- Multiply-Accumulate Coprocessor High Performance External Bus -- 64- or 32-Bit Data Interface -- Optional ECC Protection -- Frequency up to 100 MHz -- Asynchronous to Processor Clock Performance Monitoring Unit -- Two 32-Bit Event Counters -- One 32-Bit Clock Counter -- Monitors Occurrence and Duration Events Debug Unit -- Accessible through JTAG Port -- Hardware Breakpoints -- 256-Entry Trace Buffer August 2002 Reference Number: 273414-004 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright(c) Intel Corporation, 2002 AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 2 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Contents 1.0 2.0 About this Document ..........................................................................................................5 Functional Overview........................................................................................................... 5 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3.0 Superpipeline ........................................................................................................ 7 Branch Target Buffer (BTB)................................................................................... 8 Instruction Memory Management Unit (IMMU) ..................................................... 8 Data Memory Management Unit (DMMU) .............................................................9 Instruction Cache (I-Cache) .................................................................................. 9 Data Cache (D-Cache)........................................................................................ 10 Mini-Data Cache.................................................................................................. 10 Fill Buffer (FB) and Pend Buffer (PB) ..................................................................11 Write Buffer (WB) ................................................................................................ 11 Multiply-Accumulate Coprocessor (CP0) ............................................................ 11 Clock and Power Management ........................................................................... 12 Performance Monitoring Unit (PMU) ................................................................... 12 Debug Unit .......................................................................................................... 12 Package Information ........................................................................................................13 3.1 Package Introduction........................................................................................... 13 3.1.1 Functional Signal Definitions ..................................................................13 3.1.1.1 Signal Pin Descriptions ............................................................. 13 3.1.2 241 Lead PBGA Package ...................................................................... 17 Package Thermal Specifications .........................................................................22 Package Thermal Resistance ............................................................................. 22 3.2 3.3 4.0 Electrical Specifications.................................................................................................... 24 4.1 4.2 4.3 4.4 Absolute Maximum Ratings................................................................................. 24 VCCA Pin Requirements ...................................................................................... 25 Targeted DC Specifications................................................................................. 26 Targeted AC Specifications................................................................................. 27 4.4.1 Clock Signal Timings ..............................................................................27 4.4.2 Bus Signal Timings................................................................................. 28 4.4.3 Boundary Scan Test Signal Timings ...................................................... 29 AC Timing Waveforms ........................................................................................ 30 Power Sequence .................................................................................................32 Reset Timing ....................................................................................................... 34 AC Test Conditions ............................................................................................. 34 Typical Power Dissipation ................................................................................... 35 4.5 4.6 4.7 4.8 4.9 Datasheet August 2002 3 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Intel(R) 80200 Processor Block Diagram ................................................................. 6 241-Lead PBGA Package ................................................................................... 17 Case Temperature with No Air Flow ................................................................... 23 Case Temperature at Nominal Power Dissipation .............................................. 23 VCCA Lowpass Filter............................................................................................ 25 CLK Waveform .................................................................................................... 30 MCLK Waveform ................................................................................................. 30 TOV Output Delay Waveform .............................................................................. 31 Correct Power Sequence for VCC, VCCP ............................................................. 32 Another Correct Power Sequence for VCC, VCCP ............................................... 32 Incorrect Power Sequence for VCC, VCCP ........................................................... 32 Preferred Power Sequence for VCC, VCCa ....................................................... 33 Correct Power Sequence for VCC, VCCa........................................................... 33 Pins' State at Reset............................................................................................. 34 AC Test Load ...................................................................................................... 34 Typical Pin Power Dissipation ............................................................................. 35 Typical Core Power Dissipation .......................................................................... 35 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Related Documentation......................................................................................... 5 Pin Description Nomenclature............................................................................. 13 Power Pins .......................................................................................................... 14 Signal Pin Description ......................................................................................... 14 JTAG Pins ........................................................................................................... 16 241-Lead PBGA Pinout -- Ballpad Number Order ............................................. 18 241-Lead PBGA Pinout -- Signal Name Order .................................................. 20 Package Thermal Resistance -- C/Watt ........................................................... 22 Operating Conditions .......................................................................................... 24 Voltage Range Requirements for Intel(R) 80200 Processor Product Options ....... 24 DC Characteristics .............................................................................................. 26 ICC Characteristics .............................................................................................. 26 Input Clock Timings............................................................................................. 27 Output Timings .................................................................................................... 28 Input Timings....................................................................................................... 28 Boundary Scan Test Signal Timings ................................................................... 29 4 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture About this Document 1.0 About this Document This is the Advance Information data sheet for the Intel(R) 80200 processor based on Intel(R) XScaleTM microarchitecture (ARM* architecture compliant). This data sheet contains a functional overview, mechanical data (package signal locations and simulated thermal characteristics), targeted electrical specifications (simulated), and bus functional waveforms. Detailed functional descriptions other than parametric performance is published in the Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Developer's Manual. Table 1. Related Documentation Document Title Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Developer's Manual Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Specification Update Intel(R) 80310 I/O Processor Chipset Design Guide Intel 80312 I/O Companion Chip Developer's Manual Intel 80312 I/O Companion Chip Datasheet Intel(R) 80312 I/O Companion Chip Specification Update (R) (R) Document # 273411 273415 273354 273410 273425 273416 2.0 Functional Overview The Intel(R) 80200 processor technology is compliant with the ARM* Version 5TE instruction set architecture (ISA). The Intel(R) 80200 processor is designed with Intel state-of-the-art 0.18 micron production semiconductor process technology. This process technology, along with the compactness of the ARM RISC ISA, enables the Intel(R) 80200 processor to operate over a wide speed/power range, producing industry-leading mW/MIPS performance. * 7-8 stage Superpipeline promotes high speed, efficient core performance * 128-entry Branch Target Buffer keeps pipeline filled with statistically correct branch choices * 32-entry Instruction Memory Management Unit for logical-to-physical address translation, access permissions, I-Cache attributes * 32-entry Data Memory Management Unit for logical-to-physical address translation, access permissions, D-Cache attributes * 32 KB Instruction Cache can hold entire programs, preventing core stalls caused by multicycle memory accesses * 32 KB Data Cache reduces core stalls caused by multicycle memory accesses * 2 KB Minidata Cache for frequently changing data streams avoids "thrashing" of the D-Cache * 4-entry Fill and Pend Buffers promote core efficiency by allowing "hit-under- miss" operation with Data Caches * Power Management Unit gives power savings via idle, and sleep modes * 8-entry Write Buffer allows the core to continue execution while data is written to memory * Multiply-Accumulate Coprocessor can do two simultaneous 16-bit SIMD multiplies with 40-bit accumulation for efficient, high quality audio Datasheet August 2002 5 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Functional Overview * Performance Monitoring Unit furnishes two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc. * JTAG Debug Unit uses Hardware Breakpoints and 256-entry Trace History Buffer (for flow change messages) to debug programs * Dynamic clocking allows optimized performance Figure 1. Intel(R) 80200 Processor Block Diagram Branch Target Cache FIQ# IRQ# BCU Registers Interrupt Controller FIQ# IRQ# Interrupt Request Instruction Execution Core Data Address Instruction M Cache M 32 Kb U Bus Control Unit External Bus MAC Data Data Cache M 32 Kb M Mini-Data U Cache: 2 Kb Performance Monitor System Management JTAG A8158-01 6 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Functional Overview 2.1 Superpipeline The Superpipeline is composed of Integer, Multiply-Accumulate (MAC), and memory pipes. The Integer pipe has seven stages: * * * * * * * Branch Target Buffer (BTB)/Fetch 1 Fetch 2 Decode Register File/Shift ALU Execute State Execute Integer Writeback The Memory pipe has eight stages: * the first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute) . . . then finish with Memory stages: * Data Cache 1 * Data Cache 2 * Data Cache Writeback The MAC pipe has six to nine stages: * the first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift) . . . then finish with MAC stages: * * * * * MAC1 MAC2 MAC3 MAC4 Register Writeback The MAC pipe supports a data-dependent early terminate where stages MAC2, MAC3, and/or MAC4 are by-passed. Deep pipes promote high instruction execution rates only when a means exists to successfully predict the outcome of branch instructions. The Branch Target Buffer provides such a means. Datasheet August 2002 7 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Functional Overview 2.2 Branch Target Buffer (BTB) Each entry of the 128-entry BTB contains the address of a branch instruction, the target address associated with the branch instruction, and a previous history of the branch being taken or not taken. The history is recorded as one of four states: strongly taken, weakly taken, weakly not-taken, or strongly not-taken. The BTB can be enabled or disabled via coprocessor 15, register 1. When the address of the branch instruction hits in the BTB and its history is strongly or weakly taken, the instruction at the branch target address is fetched; when its history is strongly or weakly not-taken, the next sequential instruction is fetched. In either case the history is updated. Data associated with a branch instruction enters the BTB the first time the branch is taken. This data enters the BTB in a slot with a history of strongly not-taken (overwriting previous data when present). Successfully predicted branches avoid any branch-latency penalties in the superpipeline. Unsuccessfully predicted branches result in a 4-5 cycle branch-latency penalty in the superpipeline. 2.3 Instruction Memory Management Unit (IMMU) For instruction prefetches the IMMU controls logical-to-physical address translation, memory access permissions, memory domain identifications, and attributes (governing operation of the instruction cache). The IMMU contains a 32-entry, fully associative Instruction Translation Look-A-Side Buffer (ITLB) that has a round-robin replacement policy. ITLB entries 0-30 can be locked. When an instruction prefetch misses in the ITLB, the IMMU invokes an automatic table-walk mechanism that fetches an associated descriptor from memory and loads it into the ITLB. The descriptor contains information for logical-to-physical address translation, memory access permissions, memory domain identifications, and attributes governing operation of the i-cache. The IMMU then continues the instruction prefetch by using the address translation just entered into the ITLB. When an instruction prefetch hits in the ITLB, the IMMU continues the prefetch using the address translation already resident in the ITLB. Access permissions for each of up to sixteen memory domains can be programmed. When an instruction prefetch is attempted to an area of memory in violation of access permissions, then the attempt is aborted and a prefetch abort is sent to the core for exception processing. The IMMU and DMMU can be enabled or disabled together. 8 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Functional Overview 2.4 Data Memory Management Unit (DMMU) For data fetches, the DMMU controls logical-to-physical address translation, memory access permissions, memory domain identifications, and attributes (governing operation of the data cache or mini-data cache and write buffer). The DMMU contains a 32-entry, fully associative data translation look-a-side buffer (DTLB) that has a round-robin replacement policy. DTLB entries 0-30 can be locked. When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk mechanism that fetches an associated descriptor from memory and loads it into the DTLB. The descriptor contains information for logical-to-physical address translation, memory access permissions, memory domain identifications, and attributes (governing operation of the d-cache or mini-data cache and write buffer). The DMMU then continues the data fetch by using the address translation just entered into the DTLB. When a data fetch hits in the DTLB, the DMMU continues the fetch using the address translation already resident in the DTLB. Access permissions for each of up to sixteen memory domains can be programmed. When a data fetch is attempted to an area of memory in violation of access permissions, then the attempt is aborted and a data abort is sent to the core for exception processing. The IMMU and DMMU can be enable or disable together. 2.5 Instruction Cache (I-Cache) The I-Cache can contain high-use multiple code segments or entire programs, allowing the core access to instructions at core frequencies. This prevents core stalls caused by multicycle accesses to external memory. The 32 KByte i-cache is 32-set/32-way associative, where each set contains 32-ways and each way contains a tag address, a cache line (eight 32-bit words and one parity bit per word) of instructions, and a line-valid bit. For each of the 32 sets, 0-28 ways can be locked. Unlocked ways are replaceable via a round robin policy. The i-cache can be enabled or disabled. Attribute bits within the descriptors contained in the ITLB of the IMMU provide some control over an enabled i-cache. When a needed line (eight 32-bit words) is not present in the i-cache, the line is fetched (critical word first) from memory via a two-level-deep fetch queue. Datasheet August 2002 9 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Functional Overview 2.6 Data Cache (D-Cache) The D-Cache can contain high-use data such as lookup tables and filter coefficients, allowing the core access to data at core frequencies. This prevents core stalls caused by multicycle accesses to external memory. The 32 KByte d-cache is 32-set/32-way associative, where each set contains 32-ways and each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty bits (one for each of two 8-byte groupings in a line), and one valid bit. For each of the 32 sets, 0-28 ways can be locked, unlocked, or used as local SRAM. Unlocked ways are replaceable via a round robin policy. The d-cache (together with the mini-data cache) can be enabled or disabled. Attribute bits within the descriptors contained in the DTLB of the DMMU provide significant control over an enabled d-cache. These bits specify cache operating modes such as read and write allocate, write-back, write-through, and d-cache versus mini-data cache targeting The d-cache (and mini-data cache) work with the load buffer and pend buffer to provide "hit-under- miss" capability that allows the core to access other data in the cache after a "miss" is encountered (see Section 2.8, "Fill Buffer (FB) and Pend Buffer (PB)" on page 11 for more information). The d-cache (and mini-data cache) works in conjunction with the write buffer for data that is to be stored to memory (see Section 2.9, "Write Buffer (WB)" on page 11 for more information). 2.7 Mini-Data Cache The Mini-data Cache can contain frequently changing data streams such as MPEG video, allowing the core access to data streams at core frequencies. This prevents core stalls caused by multicycle accesses to external memory. The mini-data cache relieves the d-cache of data "thrashing" caused by frequently changing data streams. The 2 KByte mini-data cache is 32-set/2-way associative, where each set contains 2-ways and each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty bits (one for each of two 8-byte groupings in a line), and a valid bit. The mini-data cache uses a round robin replacement policy, and cannot be locked. The mini-data cache (together with the d-cache) can be enabled or disabled. Attribute bits contained within a coprocessor register specify operating modes write and/or read allocate, write-back, and write-through. The mini-data cache (and d-cache) work with the load buffer and pend buffer to provide "hit-under-miss" capability that allows the core to access other data in the cache after a "miss" is encountered (see Section 2.8, "Fill Buffer (FB) and Pend Buffer (PB)" on page 11 for more information). The mini-data cache (and d-cache) works in conjunction with the write buffer for data that is to be stored to memory (see Section 2.9, "Write Buffer (WB)" on page 11 for more information). 10 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Functional Overview 2.8 Fill Buffer (FB) and Pend Buffer (PB) The 4-entry Fill Buffer works with the core to hold loads until the bus controller can act on them. The FB and the 4-entry Pend Buffer work with the d-cache and mini-data cache to provide "hit-under-miss" capability, allowing the core to seek other data in the caches while "miss" data is being fetched from memory. The FB can contain up to four unique "miss" addresses (logical), allowing four "misses" before the core is stalled. The PB holds up to four addresses (logical) for additional "misses" to those addresses that are already in the FB. A coprocessor register can specify draining of the Fill and Pend (Write) Buffers. 2.9 Write Buffer (WB) The Write Buffer holds data for storage to memory until the bus controller can act on it. The WB is 8-entries deep, where each entry holds 16 bytes. The WB is constantly enabled, and accepts data from the core, d-cache, or mini-data cache. Coprocessor 15, register 1 specifies whether WB coalescing is enabled or disabled. When coalescing is disabled, stores to memory occur in program order regardless of the attribute bits within the descriptors located in the DTLB. When coalescing is enabled, the attribute bits within the descriptors located in the DTLB are examined to determine when coalescing is enabled for the destination region of memory. When coalescing is enabled in both CP15, R1 and the DTLB, then data entering the WB can coalesce with any of the 8-entries (16 bytes) and then be stored to the destination memory region, but possibly out of program order. Stores to a memory region specified to be non-cacheable and non-bufferable by the attribute bits within the descriptors located in the DTLB causes the Core to stall until the store completes. A coprocessor register can specify draining of the write buffer. 2.10 Multiply-Accumulate Coprocessor (CP0) For efficient processing of high-quality audio algorithms, CP0 provides 40-bit accumulation of 16x16, dual-16x16 (SIMD), and 32x32 signed multiplies. Special MAR and MRA instructions are implemented to Move 40-bit Accumulator to Two Core General Registers (MAR) and Move Two Core General Registers to 40-bit Accumulator (MRA). The 40-bit accumulator can be stored or loaded to or from d-cache, mini-data cache, or memory using two STC or LDC instructions. 16x16 signed multiply-accumulates (MIAxy) multiply either the high/high, low/low, high/low, or low/high 16 bits of a 32-bit core general register (multiplier) and another 32-bit core general register (multiplicand) to produce a full 32-bit product which is sign-extended to 40 bits and then added to the 40-bit accumulator. Dual signed 16x16 (SIMD) multiply-accumulates (MIAPH) multiply the high/high and low/low 16-bits of a packed 32-bit core general register (multiplier) and another packed 32-bit core general register (multiplicand) to produce two 16-bits products which are both sign-extended to 40 bits and then both added to the 40-bit accumulator. 32x32 signed multiply-accumulates (MIA) multiply a 32-bit core general register (multiplier) and another 32-bit core general register (multiplicand) to produce a 64-bit product where the 40 LSBs are added to the 40-bit accumulator. 16x32 versions of the multiply-accumulate instructions complete in a single cycle. Datasheet August 2002 11 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Functional Overview 2.11 Clock and Power Management The Intel(R) 80200 processor was designed with power saving techniques that power-up a functional block only when it is needed. Low power modes are selectable by programming CP 14, register 6. The Intel(R) 80200 processor was designed to allow dynamic clocking. The core clock frequency is set by programming CP14, Register 7. This enables software to conserve power by matching the core clock frequency to the current workload. 2.12 Performance Monitoring Unit (PMU) The Performance Monitoring Unit contains two 32-bit event counters and one 32-bit clock counter. The event counters can be programmed to monitor i-cache hit rate, data caches hit rate, ITLB hit rate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and instruction execution count. 2.13 Debug Unit The Debug Unit is accessed through the JTAG port. The industry-standard IEEE1149.1 JTAG port consists of a Test Access Port (TAP) controller, Boundary-Scan register, instruction and data registers, and dedicated signals TDI, TDO, TCK, TMS, and TRST#. The debug unit, when used with debugger application code running on a host system outside of the Intel(R) 80200 processor, allows a program running on the Intel(R) 80200 processor to be debugged. It allows the debugger application code or a debug exception to stop program execution and re-direct execution to a debug handling routine. Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint, external debug breakpoint, exception vector trap, and trace buffer full breakpoint. Once execution has stopped, the debugger application code can examine or modify the core's state, co-processor state, or memory. The debugger application code can then restart program execution. The debug unit has two hardware instruction breakpoint registers, two hardware data breakpoint registers, and a hardware data breakpoint control register. The second data breakpoint register can be alternatively used as a mask register for the first data breakpoint register. A 256-entry trace buffer provides the ability to capture control flow messages or addresses. A JTAG instruction (LDIC) can be used to download a debug handler via the JTAG port to the mini-instruction cache (the i-cache has a 2 KByte mini-instruction cache, like the mini-data cache, that is used only to hold a debug handler). 12 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Package Information 3.0 3.1 Package Information Package Introduction The Intel(R) 80200 processor is offered in a Plastic Ball Grid Array (PBGA) package. See Figure 2 "241-Lead PBGA Package" on page 17. 3.1.1 Functional Signal Definitions This section defines the pins and signals in the following tables: * * * * 3.1.1.1 Table 2. Table 2 "Pin Description Nomenclature" on page 13 Table 3 "Power Pins" on page 14 Table 4 "Signal Pin Description" on page 14 Table 5 "JTAG Pins" on page 16 Signal Pin Descriptions Pin Description Nomenclature Symbol I O I/O N/C Rst(...) Input pin only Output pin only Pin can be either an input or output Pin must be connected as described NO CONNECT. Do not make electrical connections to these balls. While the RESETOUT# pin is asserted, the pin: * Rst(1) Is driven to Vcc * Rst(0) Is driven to Vss * Rst(X) Is driven to unspecified state (1 or 0, buses may contain a mix of 1 and 0 signals) * Rst(H) Is pulled up to Vcc * Rst(L) Is pulled down to Vss * Rst(Z) Floats * Rst(Q) Is a valid output Since RESET# is asynchronous, these are asynchronous events. Hld(...) While the Intel(R) 80200 processor is in HOLD mode (HOLD asserted and took effect), the pin: * Hld(Z) Floats * Hld(Q) is a valid output * Hld(1) is driven to Vcc Note: When both HLDA and RESETOUT# are asserted, then HOLD mode takes priority; the output pins assume the state specified by Hld(...). The HOLD pin is also honored during Idle and Sleep modes; the output pins assume the state specified by Hld(...). Slp(...) While the Intel(R) 80200 processor is in Idle or Sleep mode (software selected), pin: * Slp(1) Is driven to Vcc * Slp(0) Is driven to Vss * Slp(X) Is driven to unspecified state * Slp(Q) Is a valid output Description Datasheet August 2002 13 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Package Information Table 3. Power Pins Name VCC V SS VCCP V CCA Count 17 70 25 1 Description Positive supply for the core. Ground. Positive supply for the I/O pins. Positive supply for the analog circuitry (PLL). Table 4. Signal Pin Description (Sheet 1 of 2) Name Count 16 A[15:0] Type O Rst(X) Hld(Z) Slp(X) I Description Address Bus: Conveys either the upper or lower half of a 32-bit address during the issue phase of a bus transaction. Abort Transaction: When asserted during the data phase of a transaction, this signal causes the remainder of that transaction to be aborted. Address Strobe/Length: During the first cycle of the issue phase, this signal indicates the start of a bus request. During the second cycle of the issue phase, this signal is the MSB of a value which indicates the length of the transaction. Byte Enable: Signifies which bytes are valid during a write transaction. When not in use, this bus is floated (Z). CLK: Clock input for the core logic. Critical Word First: When active during a data read transaction, CWF informs the core of the data wrap order. DBusWidth: While RESET# is asserted, this pin is sampled by the Intel(R) 80200 processor to determine when the data bus is to be configured as 32-bits or 64-bits. When the pin is sampled as `0' during reset, the 80200 assumes a 64-bit bus. When the pin is `1' at reset, a 32-bit bus is assumed. 64 D[63:0] I/O Rst(Z) Hld(Q)1 Slp(Z) I/O Rst(Z) Hld(Q)1 Slp(Z) I I Data Bus: Carries data to/from the processor during a bus transaction. When not in use, this bus is floated (Z). 1 ABORT 1 ADS#/LEN[2] O Rst(1) Hld(Z) Slp(1) O Rst(Z) Hld(Q)1 Slp(Z) I I 8 BE[7:0]# CLK 1 1 CWF/ DBusWidth (Config. Pin) 8 DCB[7:0] Data Check Byte: Carries the optional ECC information associated with the data on the Data bus. When not in use, this bus is floated (Z). Data Valid: Asserted when the Data bus carries valid data. Fast Interrupt Request: When FIQs are enabled, the processor responds to a low level on this input by taking the FIQ interrupt exception. HLDA: This output is asserted when the 80200 has floated the shared bus signals in response to HOLD. DVALID FIQ# 1 1 1 HLDA O Rst(0) Hld(1) Slp(0) 14 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Package Information Table 4. Signal Pin Description (Sheet 2 of 2) Name HOLD Count 1 1 IRQ# 1 LOCK/LEN[1] O Rst(X) Hld(Z) Slp(X) I Type I I Description HOLD: Requests the Intel(R) 80200 processor to float shared bus signals. Interrupt Request: When IRQs are enabled, the processor responds to a low level on this input by taking the IRQ interrupt exception. Atomic Transaction Indicator/Length: During the first cycle of the issue phase, this signal indicates the current transaction is part of an atomic read-write pair. During the second cycle of the issue phase, this signal is the middle bit of a value which indicates the length of the transaction. Pad Voltage Level: When tied to the same level as VCCP, indicates voltage for the device pins (VCCP) is less than 2.5V. When tied to VSS, indicates voltage at the device pins is greater than or equal to 2.5V. Core Voltage Level: When tied to the same level as VCCP, indicates voltage for the core (VCC) is less than 1.0V. When tied to VSS, indicates voltage for the core is greater than or equal to 1.0V. Memory Clock: all bus signals must be synchronous to this clock. NO CONNECT. Do not make electrical connections to these balls. PLL Configuration: While RESET# is asserted, this pin is sampled by the 80200 to select the initial clock multiplier value. When tied high, the initial clock multiplier is 6. When tied low, the initial clock multiplier is 3. This signal must be tied to a valid level at all times. When using the Intel 80312 I/O companion chip, this signal must be tied high. Power Status Indicator: Indicates the current power mode of the Intel(R) 80200 processor. This signal contains an encoded value to indicate the current power state: 00 for Normal 01 for Idle 10 for Reserved (Do Not Use) 11 for Sleep 1 RESET# 1 RESETOUT# O Rst(0) Hld(Q) Slp(1) O Rst(X) Hld(Z) Slp(X) I Reset: When asserted, this signal resets the processor. This signal must be asserted for at least 32 consecutive MCLK cycles to achieve a valid reset. Reset Status Output: This signal is asserted when the processor detects RESET#, and deasserts when the processor has completed resetting. Address Strobe/Length: During the first cycle of the issue phase, this signal indicates that the current transaction is a read (W_R# = 0) or a write (W_R# = 1). During the second cycle of the issue phase, this signal is the LSB of a value which indicates the length of the transaction. 1 LOWVPP 1 LOWVCC MCLK N/C 1 8 1 PLLCFG (Config. Pin) I I N/C I 2 PWRSTATUS[1: 0] O Rst(0) Hld(Q) Slp(Q) 1 W_R#/LEN[0] 1. For signals D, DCB, BE# during Hold mode, these continue to carry valid data until all pending transactions from the 80200 have been completed. Then these signals float. Datasheet August 2002 15 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Package Information Table 5. JTAG Pins Name Count 1 TCK Type I Description TEST CLOCK is an input which provides the clocking function for the IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the component on the rising edge and data is clocked out of the component on the falling edge. TEST DATA INPUT is the serial input pin for the JTAG feature. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port. This signal has a weak internal pullup to ensure proper operation when this signal is unconnected. TEST DATA OUTPUT is the serial output pin for the JTAG feature. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At other times, TDO floats. TEST RESET asynchronously resets the Test Access Port (TAP) controller function of IEEE 1149.1 Boundary Scan Testing (JTAG). This signal has a weak internal pullup to ensure proper operation when this signal is unconnected. TRST# must be driven low during processor reset to ensure proper operation. Additionally, before performing JTAG test, the processor should be reset and should have a valid clock at CLK to ensure it does not enter a low-power mode. TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak internal pullup to ensure proper operation when this signal is unconnected. 1 TDI I 1 TDO 1 O I TRST# 1 TMS I 16 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Package Information 3.1.2 Figure 2. 241 Lead PBGA Package 241-Lead PBGA Package A8276-01 Datasheet August 2002 17 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Package Information Table 6. 241-Lead PBGA Pinout -- Ballpad Number Order (Sheet 1 of 2) Ball # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 VSS V CCP V CC DCB1 DCB2 DCB6 BE0# BE3# BE5# BE6# LOCK NC RESETOUT# PWRSTATUS0 VSS VCCP VSS VCCP VSS VSS DVALID VSS DCB4 VCCP BE2# VSS BE7# VCCP CWF VSS HLDA VCC VSS VCC VCC VCCP VSS VCCP DCB0 DCB3 DCB7 Signal Ball # C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E5 E6 E7 E9 E11 E12 E13 E14 E15 E16 BE1# BE4# ADS# W/R# ABORT PWRSTATUS1 VSS VSS VSS NC D0 D1 D2 NC VSS VSS DCB5 VSS VCCP VSS HOLD VCC VSS VSS NC LOWVCC VCCP D3 VCC D4 D5 VCCP VSS VCC VSS VSS VSS VCCP VSS IRQ# VSS Signal Ball # E17 F1 F2 F3 F4 F5 F13 F14 F15 F16 F17 G1 G2 G3 G4 G5 G13 G14 G15 G16 G17 H1 H2 H3 H4 H8 H9 H10 H14 H15 H16 H17 J1 J2 J3 J4 J5 J8 J9 J10 J13 FIQ# D32 D6 D7 VSS VSS VSS VSS VSS VSS VCC D33 VSS D34 D35 VCC VCC VSS VSS VCCP RESET# D36 D37 D38 VSS VSS VSS VSS VCCP VSS PLLCFG NC D39 VCCP D8 D9 VCCP VSS VSS VSS VCCP Signal 18 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Package Information Table 6. 241-Lead PBGA Pinout -- Ballpad Number Order (Sheet 2 of 2) Ball # J14 J15 J16 J17 K1 K2 K3 K4 K8 K9 K10 K14 K15 K16 K17 L1 L2 L3 L4 L5 L13 L14 L15 L16 L17 M1 M2 M3 M4 M5 M13 M14 M15 M16 M17 N1 N2 N3 N4 N5 N6 VSS NC VSS NC D10 D11 D12 VSS VSS VSS VSS VCCA VSS CLK MCLK D13 VSS D14 D40 VCC VCC VSS TRST# VCCP TCK D15 D41 D42 VCC VSS VSS VCCP VSS LOWVPP TDI D43 VCCP D44 VSS VCCP VSS Signal Ball # N7 N9 N11 N12 N13 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 VCC VCCP VCC VSS VCCP VSS VSS VSS VCCP D45 D46 D16 VSS D21 VSS D55 VSS D56 VSS A13 A8 A4 VSS TMS NC TD0 D47 VSS D17 D22 D52 D54 D26 D29 D31 D59 D61 A12 A9 A6 A2 Signal Ball # R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 VCC A0 D18 D19 VCC D50 VSS D53 VCCP D28 VSS D58 VCCP D63 VSS A10 VSS A3 A1 D20 D23 D48 D49 D51 D24 D25 D27 D30 D57 D60 D62 A15 A14 A11 A7 A5 Signal Datasheet August 2002 19 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Package Information Table 7. 241-Lead PBGA Pinout -- Signal Name Order (Sheet 1 of 2) Signal A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 ABORT BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# CLK CWF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Ball # R17 T17 R15 T16 P13 U17 R14 U16 P12 R13 T14 U15 R12 P11 U14 U13 C12 A7 C8 B8 A8 C9 A9 A10 B10 K16 B12 D1 D2 D3 E1 E3 E4 F2 F3 J3 J4 K1 K2 K3 L1 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 Signal Ball # L3 M1 P3 R3 T1 T2 U1 P5 R4 U2 U6 U7 R7 U8 T8 R8 U9 R9 F1 G1 G3 G4 H1 H2 H3 J1 L4 M2 M3 N1 N3 P1 P2 R1 U3 U4 T4 U5 R5 T6 R6 D55 D56 D57 D58 D59 D60 D61 D62 D63 DCB0 DCB1 DCB2 DCB3 DCB4 DCB5 DCB6 DCB7 DVALID HLDA HOLD LOCK LOWVCC LOWVPP MCLK ADS# NC NC NC NC NC NC NC NC FIQ# IRQ# RESET# RESETOUT# TRST# PLLCFG PWRSTATUS0 PWRSTATUS1 Signal Ball # P7 P9 U10 T10 R10 U11 R11 U12 T12 C5 A4 A5 C6 B6 D7 A6 C7 B4 B14 D11 A11 D16 M16 K17 C10 A12 C17 D4 D15 J15 J17 H17 P16 E17 E15 G17 A13 L15 H16 A14 C13 20 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Package Information Table 7. 241-Lead PBGA Pinout -- Signal Name Order (Sheet 2 of 2) Signal TCK TD0 TDI TMS VCCA VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball # L17 P17 M17 P15 K14 A16 A2 B1 B11 B7 C2 C4 D17 D9 E13 E5 G16 H14 J13 J2 J5 L16 M14 N13 N17 N2 N5 N9 T11 T7 A3 B15 B17 C1 D12 E2 E7 F17 G13 G5 L13 VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Signal Ball # L5 M4 N11 N7 R16 T3 A1 A15 A17 B13 B16 B2 B3 B5 B9 C14 C15 C16 C3 D10 D13 D14 D5 D6 D8 E11 E12 E14 E16 E6 E9 F13 F14 F15 F16 F4 F5 G14 G15 G2 H10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W/R# Signal Ball # H15 H4 H8 H9 J10 J14 J16 J8 J9 K10 K15 K4 K8 K9 L14 L2 M13 M15 M5 N12 N14 N15 N16 N4 N6 P10 P14 P4 P6 P8 R2 T13 T15 T5 T9 C11 Datasheet August 2002 21 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Package Information 3.2 3.3 Package Thermal Specifications Package Thermal Resistance The Intel(R) 80200 processor is specified for operation when TC (case temperature) is within the range of 0C to 90C. Case temperature may be measured in any environment to determine whether the device is within its specified operating range. The case temperature should be measured at the center of the top surface, opposite the pins. CA is the thermal resistance from case to ambient. Use the following equation to calculate TA, the maximum ambient temperature to conform to a particular case temperature: TA = TC - P (CA) Junction temperature (TJ) is commonly used in reliability calculations. TJ can be calculated from JC (thermal resistance from junction to case) using the following equation: TJ = TC + P (JC) Similarly, when TA is known, the corresponding case temperature (TC) can be calculated as follows: TC = TA + P (CA) Table 8. Package Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter 0 (0) 1.5 28.5 200 (1.01) 1.5 20.0 400 (2.03) 1.5 18.1 600 (3.04) 1.5 17.1 JC (Junction-to-Case) CA (Case-to-Ambient) (No Heatsink) JA JC CA NOTES: 1. This table applies to an PBGA device soldered directly into a board with all VSS connections. 2. JA = JC + CA Figure 3 and Figure 4 show an application of the supplied thermal data. Here, we plot the case temperature under several conditions. 22 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Package Information Figure 3. Case Temperature with No Air Flow Case Temperature withNoAir F low, Various Ambient Temperatures 140 Case Temperature (degrees C) 120 100 80 60 40 20 0 0.00 1.00 2.00 3.00 Ta =0C Ta =30C Ta =60C Total Power D issipation Figure 4. Case Temperature at Nominal Power Dissipation Case Temperature vs. Air Flow, Various Ambient Temperatures, Nominal Power Dissipation (1 W) 100 Case Temperature (degrees C) 90 80 70 60 50 40 30 20 10 0 0 100 200 300 400 500 Ta = 0C Ta = 30C Ta = 60C Air Flow (LFM) Datasheet August 2002 23 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications 4.0 4.1 Electrical Specifications Absolute Maximum Ratings Parameter Storage Temperature Case Temperature Under Bias Supply Voltage VCC wrt. VSS Supply Voltage VCCP wrt. VSS Supply Voltage VCCA wrt. VSS Voltage on Any Ball wrt. VSS Maximum Rating -55C to + 125C 0C to + 90C 2.1V 5.0V 2.1V -0.5 V to VCCP + 0.5 V WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTICE: This data sheet contains information on products in the design phase of development. Do not finalize a design with this information. Revised information is published when the product becomes available. The specifications are subject to change without notice. Contact your local Intel representative before finalizing a design. Table 9. Operating Conditions Symbol VCC VCCP VCCA FP_CLK TC Parameter Core Supply Voltage Periphery Supply Voltage Analog Supply Voltage Input Clock Frequency Case Temperature Under Bias Min 0.95 3.0 0.95 33.33 0 Max 1.55 3.6 1.55 66.66 90 Units V V V MHz C Notes Table 10. Voltage Range Requirements for Intel(R) 80200 Processor Product Options Product Options 80200M733 80200M600 80200M400 Operating @ 333MHz 1.0v -- 1.5v 1.1v -- 1.5v 1.1v -- 1.3v Operating @ 400MHz 1.1v -- 1.5v 1.3v --1.5v 1.3v 5% Operating @ 600MHz 1.3v -- 1.5v 1.5v 5% -- Operating @ 733MHz 1.5v 5% -- -- NOTES: 1. Processor operation beyond the voltage and frequency (as marked on the device) is not guaranteed. 2. Includes VCC and VCCA. 24 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications 4.2 VCCA Pin Requirements To reduce voltage supply noise on the Intel(R) 80200 processor, the VCC A pin for the Phase Lock Loop (PLL) circuit is isolated on the pinout. The lowpass filter, as shown in Figure 5, reduces noise induced clock jitter and its effects on timing relationships in system designs. The trace lengths between the 4.7F capacitor, the 0.01F capacitor, and VCCA must be as short as possible. Figure 5. VCCA Lowpass Filter 10, 5%, 1/8W VCC (Board Plane) + 4.7F 0.01F VCCA (On Intel(R) 80200 Processor) Datasheet August 2002 25 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications 4.3 Table 11. Targeted DC Specifications DC Characteristics Symbol VIL V IH V OL V OH C IN C OUT C CLK LPIN Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Capacitance I/O or Output Capacitance CLK Capacitance Ball Inductance VCCP - 0.3 5 5 5 TBD Min -0.5 2.4 2.1 Max 0.8 VCCP + 0.5 V CCP + 0.5 0.3 V V pF pF pF nH Units V V A-1 step D-0 step 1 2 Notes NOTES: 1. VOL measured at IOL = 3mA 2. VOH measured at IOH = 2mA Table 12. ICC Characteristics Symbol ILO ILI Parameter Output Leakage Current Input Leakage Current Core and Analog Current 733MHz at 1.5v Icc Icca 600MHz at 1.3v ICC Active (Power Supply) Icc Icca 400MHz at 1.3v Icc Icca Periphery Current 100MHz at 3.6v Iccp Idle Mode at 1.5v ICC Active (Idle Mode) Icc Icca at 1.3v Icc Icca ICC Active (Sleep Mode) TBD Sleep Mode 135 600 TBD mA A mA 190 700 mA A 165 mA 410 13 mA mA 520 65 mA mA For typical power dissipation, see section 4.9 720 95 mA mA Typ Max 220 220 Units A A Notes 0.4 VOUT VCC 0 VIN VCC 26 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications 4.4 4.4.1 Table 13. Targeted AC Specifications Clock Signal Timings Input Clock Timings Symbol TF TC TCS TCH TCL TCR TCF TMF TMC TMCS TMCH TMCL TMCR TMCF Parameter CLK Frequency CLK Period CLK Period Stability CLK High Time CLK Low Time CLK Rise Slew Rate CLK Fall Slew Rate MCLK Frequency MCLK Period MCLK Period Stability MCLK High Time MCLK Low Time MCLK Rise Slew Rate MCLK Fall Slew Rate 2.5 2.5 1.5 1.5 4.5 4.5 5 5 1.5 1.5 0 10 250 3.5 3.5 100 Min 33.33 15 Max 66.66 30 20 Units MHz ns ps ns ns V/ns V/ns MHz ns ps ns ns V/ns V/ns (1) Adjacent Clocks (2) Measured at 1.5 V (2) Measured at 1.5 V (2) 0.4 V to 2.4 V (2) 2.4 V to 0.4 V (2) (1) Adjacent Clocks (2) Measured at 1.5 V (2) Measured at 1.5 V (2) 0.4 V to 2.4 V (2) 2.4 V to 0.4 V (2) Notes NOTES: 1. See Figure 6 and Figure 7. 2. Not tested. Datasheet August 2002 27 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications 4.4.2 Table 14. Bus Signal Timings Output Timings Symbol TOV1 TOF1 TOS1 TOV2 Parameter Output valid delay from MCLK -D[63:0], DCB, and BE# Output float delay from MCLK -D[63:0], DCB, and BE# Output Slew Rate -- D[63:0], DCB, and BE# Output valid delay from MCLK -A[15:0], HLDA, W/R#, LOCK, and ADS# Output float delay from MCLK -A[15:0], HLDA, W/R#, LOCK, ADS#, RESETOUT#, and PWRSTATUS Output Slew Rate -- A[15:0], HLDA, W/R#, LOCK, ADS#, RESETOUT#, and PWRSTATUS Min 1.5 1.1 1.0 1.5 Max 6.9 6.0 4.0 6.8 Units ns ns V/ns ns (1, 2, 4) 1.1 6.0 ns (1, 2, 3, 4) (1, 2) (1, 2, 3) 0.4 V to 2.4 V (1, 2, 4) Notes TOF2 1.0 4.0 V/ns 0.4 V to 2.4 V (1, 2, 4) TOS2 NOTES: 1. Minimum values characterized with a 10 pF load at 3.6 V, 0C 2. Maximum values characterized with a 30 pF load at 2.9 V., 110C 3. Pin is floating when its output falls to ILO 4. Not tested Table 15. Input Timings Symbol TIS Parameter Input setup time to MCLK -ABORT, CWF, DVALID, D, and DCB Input hold time from MCLK -ABORT, CWF, DVALID, D, and DCB Input setup time to MCLK -HOLD Input hold time from MCLK -HOLD Min 1.2 Max Units ns Notes 1.5 ns TIH TISH TIHH 1.3 0.9 ns ns 28 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications 4.4.3 Table 16. Boundary Scan Test Signal Timings Boundary Scan Test Signal Timings Symbol TBSF TBSCH TBSCL TBSCR TBSCF TBSIS1 TBSIH1 TBSIS2 TBSIH2 TBSOV1 TOF1 TOV12 TOF2 TIS10 TIH8 Parameter TCK Frequency TCK High Time TCK Low Time TCK Rise Time TCK Fall Time Input Setup to TCK -- TDI, TMS Input Hold from TCK -- TDI, TMS Input Setup to TCK -- TRST# Input Hold from TCK -- TRST# TDO Valid Delay TDO Float Delay All Outputs (Non-Test) Valid Delay All Outputs (Non-Test) Float Delay Input Setup to TCK -- All Inputs (Non-Test) Input Hold from TCK -- All Inputs (Non-Test) 4.0 6.0 25.0 3.0 1.5 1.1 1.5 1.1 4.0 6.0 6.9 5.4 6.9 5.4 Min 0.0 12.5 12.5 5.0 5.0 Max 40.0 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Relative to falling edge of TCK Relative to falling edge of TCK Relative to falling edge of TCK Relative to falling edge of TCK Measured at 1.5 V Measured at 1.5 V 0.8 V to 2.0 V 2.0 V to 0.8 V Notes Datasheet August 2002 29 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications 4.5 Figure 6. AC Timing Waveforms CLK Waveform TCR TCF 2.4V 1.5V 0.4V TCH TCL TC Figure 7. MCLK Waveform TMCR TMCF 2.4V 1.5V 0.4V TMCH TMCL TMC 30 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications Figure 8. TOV Output Delay Waveform MCLK 1.5V 1.5V TOVX Max TOVX Minimum Output 1.5V Valid 1.5V Datasheet August 2002 31 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications 4.6 Power Sequence Power must be supplied to the component's pads (VCCP) before or concurrently with power to the components core (V CC). Power must not be applied to VCC prior to VCCP. Figure 9 and Figure 10 show correct power sequences. Figure 11 shows an incorrect power sequence; do not allow this. Figure 9. Correct Power Sequence for VCC, VCCP Voltage 3.3 VCCP VCC 1.3 Time Figure 10. Another Correct Power Sequence for VCC, VCCP Voltage 3.3 VCCP VCC 1.3 Time Figure 11. Incorrect Power Sequence for VCC, VCCP Voltage 3.3 VCCP VCC 1.3 Time 32 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications VCC and VCCA (PLL supply) should be brought up concurrently. When this cannot be attained, VCC should be brought up before VCCA. Figure 12 shows the preferred method where VCC and VCCA are brought up at the same time. Figure 13 shows the alternative. Figure 12. Preferred Power Sequence for VCC, VCCa Voltage 1.3 VCC and VCCA Time Figure 13. Correct Power Sequence for VCC, VCCa Voltage 1.3 VCC VCCA Time Datasheet August 2002 33 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications 4.7 Reset Timing Figure 14 shows the sequence of pin states that may be assumed at processor reset. See the Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Developer's Manual for more information on reset timing. Figure 14. Pins' State at Reset ~ ~ CLK ~ ~ ~ ~ MCLK ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ADS# PWRSTATUS HOLD HLDA ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 4.8 AC Test Conditions The AC specifications in Section 4.4, "Targeted AC Specifications" on page 27 are tested with a 30 pF load indicated in Figure 15. Figure 15. AC Test Load Output Ball CL CL = 30 pF ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ RESETOUT# ~ ~ ~ ~ ~ ~ RESET# ~ ~ ~ ~ ~ ~ 34 August 2002 Datasheet Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications 4.9 Typical Power Dissipation The total dissipated power is the sum of the power requirements from the device pins and the internal logic. Both are dependent on the operating frequency, voltage, and activity. Because the device pins are operating under different conditions than the internal logic, the typical power dissipation curves for both are in this section. Figure 16. Typical Pin Power Dissipation1 Bus Speed vs. Power (M oderate Bus Utilization) 0.60 0.50 Pin Power (Watts) 0.40 66 MHz bus 0.30 100MHz bus 0.20 0.10 0.00 3.00 3.10 3.20 3.30 3.40 3.50 3.60 Vccp (Volts) 1. Assume system driving one PC-100 DIMM and a companion chip with 10pF/pin capacitance. Figure 17. Typical Core Power Dissipation C or e P o we r ( on D h r y st on e 2 . 1: h i g h c o r e a c t i v i t y ) 0.700 0.600 Core Power (Watts) 0.500 0.400 400 MHz 600 MHz 0.300 0.200 0.100 0.000 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 Vcc (Volts) Datasheet August 2002 35 Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Electrical Specifications This Page Intentionally Left Blank 36 August 2002 Datasheet |
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