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UC3842T UC3843T UC3844T UC3845T
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
.TRI .OSCI .CURRENT .AUTOMATI .LATCHI .I .HI .UNDERVOLTAGE .LOW
DESCRIPTION
MMED OSCILLATOR FOR PRECISE FREQUENCY CONTROL LLATOR FREQUENCY GUARANTEED AT 250kHz MODE OPERATION TO 500kHz C FEED FORWARD COMPENSATION NG PWM FOR CYCLE-BY-CYCLE CURRENT LIMITING NTERNALLY TRIMMED REFERENCE WITH UNDERVOLTAGE LOCKOUT GH CURRENT TOTEM POLE OUTPUT LOCKOUT WITH HYSTERESIS START-UP AND OPERATING CURRENT
Minidip
SO8
The UC384XT family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lockout featuring start-up current less than 0.5mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM
comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the offstate. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842T and UC3844T have UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applications The corresponding thresholds for the UC3843T and UC3845T are 8.5 V and 7.9 V. The UC3842T and UC3843T can operate to duty cycles approaching 100%. A range of zero to < 50 % is obtained by the UC3844T and UC3845T by the addition of an internal toggle flip flop which blanks the output off every other clock cycle.
BLOCK DIAGRAM (toggle flip flop used only in UC3844T and UC3845T)
Vi 7 34V GROUND 5 UVLO S/R 5V REF INTERNAL BIAS VREF GOOD LOGIC RT/CT 4 OSC ERROR AMP. 2R R 1V T
8
VREF 5V 50mA
2.50V
6
OUTPUT
VFB COMP CURRENT SENSE
2 1 3
+ -
S R CURRENT SENSE COMPARATOR
D95IN331
PWM LATCH
September 2001
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ABSOLUTE MAXIMUM RATINGS
Symbol Vi Vi IO EO Parameter Supply Voltage (low impedance source) Supply Voltage (Ii < 30mA) Output Current Output Energy (capacitive load) Analog Inputs (pins 2, 3) Error Amplifier Output Sink Current Ptot Ptot Tstg TL Power Dissipation at Tamb 25 C (Minidip) Power Dissipation at Tamb 25 C (SO8) Storage Temperature Range Lead Temperature (soldering 10s) Value 30 Self Limiting 1 5 - 0.3 to 5.5 10 1.25 800 - 65 to 150 300 A J V mA W mW C C Unit V
* All voltages are with respect to pin 5, all currents are positive into the specified terminal.
PIN CONNECTION (top view) Minidip/SO8
COMP VFB ISENSE RT/CT
1 2 3 4
D95IN332
8 7 6 5
VREF Vi OUTPUT GROUND
PIN FUNCTIONS
No 1 2 3 4 5 6 7 8 Function COMP VFB ISENSE RT/CT GROUND OUTPUT VCC Vref Description This pin is the Error Amplifier output and is made available for loop compensation. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible. This pin is the combined control circuitry and power ground. This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin. This pin is the positive supply of the control IC. This is the reference output. It provides charging current for capacitor C T through resistor RT.
ORDERING NUMBERS
SO8 UC3842TD UC3843TD UC3844TD UC3845TD Minidip UC3842TN UC3843TN UC3844TN UC3845TN
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THERMAL DATA
Symbol Rth j-amb Description Thermal Resistance Junction-ambient. max. Minidip 100 SO8 150 Unit C/W
ELECTRICAL CHARACTERISTICS ( [note 1] Unless otherwise stated, these specifications apply for 0 < Tamb < 105C; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
Symbol Parameter Test Conditions Min. Value Typ. 2 3 0.2 4.85 50 5 -30 Tj = 25C TA = Tlow to Thigh TJ = 25C (RT = 6.2k, CT = 1nF) VCC = 12V to 25V TA = Tlow to Thigh (peak to peak) TA = Tlow to Thigh VPIN1 = 2.5V VFB = 5V 2V Vo 4V TJ = 25C 12V Vi 25V VPIN2 = 2.7V VPIN1 = 1.1V VPIN2 = 2.3V VPIN1 = 5V VPIN2 = 2.3V; RL = 15K to Ground VPIN2 = 2.7V; RL = 15K to Pin 8 (note 3 & 4) VPIN1 = 5V (note 3) 12 Vi 25V (note 3) 2.85 0.9 65 0.7 60 2 -0.5 5 49 48 225 - - - 7.3 2.42 -100 52 - 250 0.2 1 1.6 - 2.50 -0.1 90 1 70 12 -1 6.2 0.8 1.1 25 -180 55 56 275 1 - - 8.8 2.58 -2 5.15 Max. 20 25 Unit
REFERENCE SECTION VREF VREF Line Regulation Load Regulation 12V Vi 25V 1 Io 20mA (Note 2) Line, Load, Temperature 10Hz f 10KHz Tj = 25C (note 2) Tamb = 125C, 1000Hrs (note 2) mV mV mV/C V V mV mA KHz KHz KHz % % V mA V A dB MHz dB mA mA V V
VREF/T Temperature Stability Total Output Variation eN Output Noise Voltage Long Term Stability ISC fOSC Output Short Circuit Frequency OSCILLATOR SECTION
fOSC/V fOSC/T VOSC Idischg V2 Ib
Frequency Change with Volt. Frequency Change with Temp. Oscillator Voltage Swing Discharge Current (VOSC =2V) Input Voltage Input Bias Current AVOL
ERROR AMP SECTION
BW PSRR Io Io
Unity Gain Bandwidth Power Supply Rejec. Ratio Output Sink Current Output Source Current VOUT High VOUT Low
CURRENT SENSE SECTION GV V3 SVR Ib Gain Maximum Input Signal Supply Voltage Rejection Input Bias Current Delay to Output 3 1 70 -2 100 -10 300 3.15 1.1 V/V V dB A ns
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ELECTRICAL CHARACTERISTICS (continued)
Symbol OUTPUT SECTION VOL VOH VOLS tr tf Output Low Level ISINK = 20mA ISINK = 200mA Output High Level ISOURCE = 20mA ISOURCE = 200mA UVLO Saturation Rise Time Fall Time Start Threshold VCC = 6V; ISINK = 1mA Tj = 25C CL = 1nF (2) Tj = 25C CL = 1nF (2) UC3842T/4T UC3843T/5T Min Operating Voltage After Turn-on PWM SECTION Maximum Duty Cycle UC3842T/3T UC3844T/5T Minimum Duty Cycle TOTAL STANDBY CURRENT Ist Ii Viz Start-up Current Vi = 6.5V for UC3843T/45T Vi = 14V for UC3842T/44T Operating Supply Current Zener Voltage VPIN2 = VPIN3 = 0V Ii = 25mA 30 0.3 0.3 12 36 0.5 0.5 17 mA mA mA V 94 47 96 48 100 50 0 % % % UC3842T/4T UC3843T/5T 15 7.8 9 7.0 13 12 0.1 1.6 13.5 13.5 0.1 50 50 16 8.4 10 7.6 1.1 150 150 17 9.0 11 8.2 0.4 2.2 V V V V V ns ns V V V V Parameter Test Conditions Min. Value Typ. Max. Unit
UNDER-VOLTAGE LOCKOUT SECTION
Notes : 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close to Tamb as possible. 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VPIN2 = 0. 4. Gain defined as : VPIN1 A= ; 0 VPIN3 0.8 V VPIN3 5. Adjust Vi above the start threshold before setting at 15 V.
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Figure 1: Open Loop Test Circuit.
VREF 4.7K 2N2222 100K ERROR AMP. ADJUST 4.7K COMP VFB 1K ISENSE ADJUST 5K ISENSE RT/CT RT VREF 1 2 3 4 8 7 Vi 0.1F 6 5 OUTPUT GROUND 1W 1K OUTPUT A 0.1F Vi
D.U.T.
CT
D95IN343
GROUND
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close
to pin 5 in a single point ground. The transistor and 5 K potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
Figure 2: Timing Resistor vs. Oscillator Frequency
RT (K) 50
C
T=
Figure 3: Output Dead-Time vs. Oscillator Frequency
D95IN334
D95IN333
%
20
0p
F
C
50
10 0p F
T=
C
20
T=
50
CT=5nF
C
0p
30 20 CT=1nF CT=500pF CT=200pF
CT=2nF CT=5nF CT=10nF
F
T=
1n
F
10
10
5
CT=2nF CT=10nF
5 3 2
CT=100pF
2
Vi=15V TA=25C
1 0.8 10K
Vi=15V TA=25C
20K 30K 50K 100K 200K 300K 500K fOSC(KHz)
1 10K 20K 30K 50K 100K 200K 300K 500K fOSC(KHz)
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Figure 4: Oscillator Discharge Current vs. Temperature.
Idischg (mA)
D95IN335
Figure 5: Maximum Output Duty Cycle vs. Timing Resistor.
D95IN336
Dmax (%) 90 Idischg=7.5mA 80 Idischg=8.8mA
Vi=15V VOSC=2V
8.5
8.0
70
60
7.5
50
Vi=15V CT=3.3nF TA=25C
7.0 -55 -25 0 25 50 75 100 TA(C)
40 0.8 1 2 3 5 RT(K)
Figure 6: Error Amp Open-Loop Gain and Phase vs. Frequency.
(dB) 80
D95IN337
Figure 7: Current Sense Input Threshold vs. Error Amp Output Voltage.
30 60 90 120 150 Vth (V) 1.0
D95IN338
Gain
60 40 20 0 -20 10
Vi=15V VO=2V to 4V RL=100K TA=25C
Vi=15V TA=25C
0.8
TA=125C Phase
0.6 0.4
TA=-40C
0.2 0.0
100
1K
10K
100K
1M
180 f(Hz)
0
2
4
6
VO(V)
Figure 8: Reference Voltage Change vs. Source Current.
60
D95IN339
Figure 9: Reference Short Circuit Current vs. Temperature.
ISC (mA) 100 Vi=15V RL0.1
D95IN340
Vi=15V
50 40
TA=-40C TA=125C
90 80
30 20 10 0 0 20 40 60 80 100 Iref(mA)
TA=25C
70 60 50 -55 -25 0 25 50 75 100 TA(C)
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Figure 10: Output Saturation Voltagevs. Load Current.
Vsat (V)
D95IN341
Figure 11: Supply Current vs. Supply Voltage.
Ii (mA) 20
D95IN342
Vi
-1 -2
Source Saturation (Load to Ground) TA=25C TA=-40C
Vi=15V 80s Pulsed Load 120Hz Rate
15
RT=10K CT=3.3nF VFB=0V ISense=0V TA=25C
UCX843/45
10
2 1 0 0
TA=-40C TA=25C
5
Sink Saturation (Load to Vi)
200 400 600
GND
0
IO(mA)
0
10
UCX842/44
3
20
30
Vi(V)
Figure 12: Output Waveform.
Figure 13: Output Cross Conduction
Vi =30V CL = 15pF TA = 25C VO 20V/DIV
90%
Vi =15V CL = 1.0nF TA = 25C
ICC 10% 50ns/DIV 100ns/DIV 100mA/DIV
Figure 14: Oscillator and Output Waveforms.
Vi 7 8 5V REG PWM RT CLOCK 4 OSCILLATOR ID CT 5 GND
D95IN344
CT
OUTPUT 6 OUTPUT LARGE RT/SMALL CT
CT
OUTPUT SMALL RT/LARGE CT
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Figure 15 : Error Amp Configuration.
2.5V
1mA + VFB COMP Zf
D95IN345
Zi
2 1
-
Figure 16 : Under Voltage Lockout.
Vi
7
ON/OFF COMMAND TO REST OF IC
ICC
UC3842T UC3844T VON VOFF 16V 10V
UC3843T UC3845T 8.4V 7.6V
<17mA
<0.5mA VOFF VON
VCC
D99IN1058
During UVLO, the Output is low
Figure 17 : Current Sense Circuit .
ERROR AMPL. IS COMP R RS C CURRENT SENSE 5 GND 1
2R R 1V
3
CURRENT SENSE COMPARATOR
D95IN347
Peak current (is) is determined by the formula 1.0 V IS max RS A small RC filter may be required to suppress switch transients.
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Figure 18 : Slope Compensation Techniques.
VREG RT IS RSLOPE R1 RS RT/CT CT ISENSE
8
VREG RT
8
4
IS
RT/CT RSLOPE R1 CT ISENSE
4
UC3842T
3 5 GND
UC3842T
3 5 GND
D99IN1059
RS
Figure 19 : Isolated MOSFET Drive and Current Transformer Sensing.
VCC Vin
7
5.0Vref
+ -
ISOLATION BOUNDARY VGS Waveforms
+ S R -
6
Q1
+ 0 -
50% DC
+ 0 -
25% DC
Q
Ipk =
V(pin 1) -1.4 3RS
()
NP
NS
+ COMP/LATCH 3 C
D95IN349
R RS NS NP
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Figure 20 : Latched Shutdown.
4
OSC
8 R BIAS R + 1mA + 2 EA 2R
R
1 5
2N 3905 2N 3903
D95IN350
SCR must be selected for a holding current of less than 0.5mA at TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.
Figure 21: Error Amplifier Compensation
From VO Ri 2 Rd Cf Rf 1
2.5V
+ 1mA + EA 2R
R
5
Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current.
+ 1mA RP Ri 2 CP Rd Cf Rf 1 5
D95IN351
From VO
2.5V
+ EA
2R
R
Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current.
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Figure 22: External Clock Synchronization.
VREF 8 R BIAS RT 4 CT EXTERNAL SYNC INPUT 0.01F 2 1 + EA + R
OSC
2R
47
R
5
The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300mV below ground
D95IN352
Figure 23: External Duty Cycle Clamp and Multi Unit Synchronization.
VREF RA 8 4
8 R BIAS R 3 4 + Q + 5K 1 7 + EA 2R
RB 6 5
5K
+ 5K
R
OSC
2 C
S
2
R
NE555
1 5 TO ADDITIONAL UC384XT
D99IN1060
f=
1.44 (RA + 2RB)C
Dmax =
RB RA + 2RB
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Figure 24: Soft-Start Circuit
8 R BIAS R 4 + 1mA 2 1M 1 C 5 + EA 2R
5Vref + -
OSC
S + R 1V Q R
D95IN354
Figure 25: Soft-Start and Error Amplifier Output Duty Cycle Clamp.
VCC
Vin
7 + -
8 R BIAS R 4 + 1mA 2 R2 + EA 2R R 1V + -
5Vref + -
7
OSC
6
Q1
VClamp
S Q R Comp/Latch 5
1 5
C
R1
BC109 VCLAMP = * R1 R1 + R 2 where 0 D95IN355
RS
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mm MIN. A a1 a2 a3 b b1 C c1 D (1) E e e3 F (1) L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.15 0.016 0.65 0.35 0.19 0.25 0.1 TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 0.026 0.014 0.007 0.010 0.004 MIN. inch TYP. MAX. 0.069 0.010 0.065 0.033 0.019 0.010 0.020
DIM.
OUTLINE AND MECHANICAL DATA
45 (typ.) 5.0 6.2 0.189 0.228 0.050 0.150 0.157 0.050 0.024 0.197 0.244
SO8
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
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mm MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 0.100 0.300 0.300 0.260 0.200 0.150 0.060 TYP. 3.32 0.020 0.045 0.014 0.008 0.065 0.022 0.012 0.430 0.384 MAX. MIN. inch TYP. 0.131 MAX.
DIM.
OUTLINE AND MECHANICAL DATA
Minidip
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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