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PIC16C55X Data Sheet
EPROM-Based 8-Bit CMOS Microcontrollers
2002 Microchip Technology Inc.
Preliminary
DS40143D
Note the following details of the code protection feature on PICmicro(R) MCUs. * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
* * *
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS40143D - page ii
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
EPROM-Based 8-Bit CMOS Microcontrollers
Devices Included in this Data Sheet:
Referred to collectively as PIC16C55X. * PIC16C554 * PIC16C557 * PIC16C558
Pin Diagram
PDIP, SOIC, Windowed CERDIP
RA2 RA3 RA4/T0CKI MCLR/Vpp VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PIC16C554/558
High Performance RISC CPU:
* Only 35 instructions to learn * All single-cycle instructions (200 ns), except for program branches which are two-cycle * Operating speed: - DC - 20 MHz clock input - DC - 20 ns instruction cycle Device PIC16C554 PIC16C557 PIC16C558 * * * * Program Memory 512 2K 2K Data Memory 80 128 128
SSOP
RA2 RA3 RA4/T0CKI MCLR/Vpp VSS VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4
PIC16C554/558
Interrupt capability 16-18 special function hardware registers 8-level deep hardware stack Direct, Indirect and Relative Addressing modes
PDIP, SOIC, Windowed CERDIP
RA4/T0CKI VDD VSS RA5 RA0 RA1 RA2 RA3 RB0/INT RB1 RB2 RB3 RB4 N/C *1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MCLR/VPP OSC1/CLKIN OSC2/CLKOUT RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5
PIC16C557
Peripheral Features:
* 13-22 I/O pins with individual direction control - Pull-up resistors on PORTB * High current sink/source for direct LED drive * Timer0: 8-bit timer/counter with 8-bit programmable prescaler
SSOP
VSS RA4/T0CKI VDD RA5 RA0 RA1 RA2 RA3 RB0/INT RB1 RB2 RB3 RB4 VSS *1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MCLR/VPP OSC1/CLKIN OSC2/CLKOUT RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5
PIC16C557
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 1
PIC16C55X
Special Microcontroller Features:
* Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code protection * Power saving SLEEP mode * Selectable oscillator options * Serial in-circuit programming (via two pins) * Four user programmable ID locations
Note:
For additional information on enhancements, see Appendix A
CMOS Technology:
* Low power, high speed CMOS EPROM technology * Fully static design * Wide operating voltage range - 2.5V to 5.5V * Commercial, Industrial and Extended temperature range * Low power consumption - < 2.0 mA @ 5.0V, 4.0 MHz - 15 A typical 3.0V, 32 kHz - < 1.0 A typical standby current @ 3.0V
Device Differences
Device PIC16C554 PIC16C557 PIC16C558 Voltage Range 2.5 - 5.5 2.5 - 5.5 2.5 - 5.5 Oscillator (Note 1) (Note 1) (Note 1)
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
DS40143D-page 2
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
Table of Contents
1.0 General Description...................................................................................................................................................................... 5 2.0 PIC16C55X Device Varieties ....................................................................................................................................................... 7 3.0 Architectural Overview ................................................................................................................................................................. 9 4.0 Memory Organization ................................................................................................................................................................. 13 5.0 I/O Ports ..................................................................................................................................................................................... 23 6.0 Special Features of the CPU...................................................................................................................................................... 31 7.0 Timer0 Module ........................................................................................................................................................................... 47 8.0 Instruction Set Summary ............................................................................................................................................................ 53 9.0 Development Support................................................................................................................................................................. 67 10.0 Electrical Specifications.............................................................................................................................................................. 73 11.0 Packaging Information................................................................................................................................................................ 87 Appendix A: Enhancements............................................................................................................................................................. 97 Appendix B: Compatibility ............................................................................................................................................................... 97 Index .................................................................................................................................................................................................... 99 On-Line Support................................................................................................................................................................................. 101 Systems Information and Upgrade Hot Line ...................................................................................................................................... 101 Reader Response .............................................................................................................................................................................. 102 Product Identification System ............................................................................................................................................................ 103
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Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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2002 Microchip Technology Inc.
Preliminary
DS40143D-page 3
PIC16C55X
NOTES:
DS40143D-page 4
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
1.0 GENERAL DESCRIPTION
The PIC16C55X are 18, 20 and 28-Pin EPROM-based members of the versatile PIC16CXX family of low cost, high performance, CMOS, fully-static, 8-bit microcontrollers. All PICmicro(R) microcontrollers employ an advanced RISC architecture. The PIC16C55X have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16C55X microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C554 has 80 bytes of RAM. The PIC16C557 and PIC16C558 have 128 bytes of RAM. The PIC16C554 and PIC16C558 have 13 I/O pins and an 8bit timer/counter with an 8-bit programmable prescaler. The PIC16C557 has 22 I/O pins and an 8-bit timer/ counter with an 8-bit programmable prescaler. PIC16C55X devices have special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for high speed crystals. The SLEEP (power-down) mode offers power saving. The user can wake-up the chip from SLEEP through several external and internal interrupts and RESET. A highly reliable Watchdog Timer, with its own on-chip RC oscillator, provides protection against software lock-up. A UV-erasable CERDIP packaged version is ideal for code development while the cost effective One-Time Programmable (OTP) version is suitable for production in any volume. Table 1-1 shows the features of the PIC16C55X midrange microcontroller families. A simplified block diagram of the PIC16C55X is shown in Figure 3-1. The PIC16C55X series fit perfectly in applications ranging from motor control to low power remote sensors. The EPROM technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C55X very versatile.
1.1
Family and Upward Compatibility
Users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for PIC16C5X can be easily ported to PIC16C55X family of devices (Appendix B). The PIC16C55X family fills the niche for users wanting to migrate up from the PIC16C5X family and not needing various peripheral features of other members of the PIC16XX mid-range microcontroller family.
1.2
Development Support
The PIC16C55X family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low cost development programmer and a full-featured programmer.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 5
PIC16C55X
TABLE 1-1:
Clock
PIC16C55X FAMILY OF DEVICES
PIC16C554 Maximum Frequency of Operation (MHz) EPROM Program Memory (x14 words) Data Memory (bytes) Timer Module(s) Interrupt Sources I/O Pins Voltage Range (Volts) Brown-out Reset Packages 20 512 80 TMR0 3 13 2.5-5.5 -- 18-pin DIP, SOIC; 20-pin SSOP PIC16C557 20 2K 128 TMR0 3 22 2.5-5.5 -- 28-pin DIP, SOIC; 28-pin SSOP PIC16C558 20 2K 128 TMR0 3 13 2.5-5.5 -- 18-pin DIP, SOIC, SSOP
Memory Peripherals
Features
All PICmicro(R) Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C55X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40143D-page 6
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
2.0 PIC16C55X DEVICE VARIETIES
2.3
A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C55X Product Identification System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number.
Quick-Turnaround Production (QTP) Devices
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package, is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes. and PROMATE Microchip's PICSTART programmers both support programming of the PIC16C55X.
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium-to-high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices, but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround Production (SQTPSM) Devices
2.2
One-Time Programmable (OTP) Devices
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry code, password or ID number.
The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. In addition to the program memory, the configuration bits must also be programmed.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 7
PIC16C55X
NOTES:
DS40143D-page 8
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16C55X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C55X uses a Harvard architecture in which program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently from 8-bit wide data words. Instruction opcodes are 14-bit wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a singlecycle (200 ns @ 20 MHz) except for program branches. The table below lists the memory (EPROM and RAM). Device PIC16C554 PIC16C557 PIC16C558 Program Memory (EPROM) 512 2K 2K Data Memor (RAM) 80 128 128 The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with a description of the device pins in Table 3-1.
The PIC16C554 addresses 512 x 14 on-chip program memory. The PIC16C557 and PIC16C558 addresses 2 K x 14 program memory. All program memory is internal. The PIC16C55X can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped into the data memory. The PIC16C55X has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any Addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16C55X simple yet efficient. In addition, the learning curve is reduced significantly. The PIC16C55X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 9
PIC16C55X
FIGURE 3-1: BLOCK DIAGRAM
Device PIC16C554 PIC16C557 PIC16C558
Program Memory 512 x 14 2 K x 14 2 K x 14
Data Memory 80 x 8 128 x 8 128 x 8
EPROM Program Memory 512 x 14 to 2K x 14 Program Bus 14 Instruction reg
13 Program Counter
Data Bus
8
PORTA RA0 RA1 RA2 RA3 RA4/T0CKI PORTB
8-Level Stack (13-bit)
RAM File Registers 80 x 8 to 128 x 8 RAM Addr(1) 8
Addr MUX Direct Addr 7 8 Indirect Addr RB0/INT RB7:RB1
FSR STATUS reg 8 3 PORTC(2)
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer
MUX RC7:RC0 ALU
8 W reg
Timer0 VPP VDD, VSS
Note
1: 2:
Higher order bits are from STATUS Register. PIC16C557 only.
DS40143D-page 10
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
TABLE 3-1:
Name PDIP OSC1/CLKIN OSC2/CLKOUT 16 15 SOIC 16 15 SSOP 18 17
PIC16C55X PINOUT DESCRIPTION
Pin Number Pin Type I O Buffer Type Description
ST/CMOS Oscillator crystal input/external clock source output. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (Reset) input/programming voltage input. This pin is an active low RESET to the device. Bi-directional I/O port Bi-directional I/O port Bi-directional I/O port Bi-directional I/O port Bi-directional I/O port or external clock input for TMR0. Output is open drain type. Bi-directional I/O port can be software programmed for internal weak pull-up. RB0/INT can also be selected as an external interrupt pin. Bi-directional I/O port can be software programmed for internal weak pull-up. Bi-directional I/O port can be software programmed for internal weak pull-up. Bi-directional I/O port can be software programmed for internal weak pull-up. Bi-directional I/O port can be software programmed for internal weak pull-up. Interrupt-on-change pin. Bi-directional I/O port can be software programmed for internal weak pull-up. Interrupt-on-change pin. Bi-directional I/O port can be software programmed for internal weak pull-up. Interrupt-on-change pin. Serial programming clock. Bi-directional I/O port can be software programmed for internal weak pull-up. Interrupt-on-change pin. Serial programming data. Bi-directional I/O port input buffer. Bi-directional I/O port input buffer. Bi-directional I/O port input buffer. Bi-directional I/O port input buffer. Bi-directional I/O port input buffer. Bi-directional I/O port input buffer. Bi-directional I/O port input buffer. Bi-directional I/O port input buffer. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RB0/INT
4 17 18 1 2 3 6
4 17 18 1 2 3 6
4 19 20 1 2 3 7
I/P I/O I/O I/O I/O I/O I/O
ST ST ST ST ST ST TTL/ST(1)
RB1 RB2 RB3 RB4 RB5 RB6
7 8 9 10 11 12
7 8 9 10 11 12
8 9 10 11 12 13
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL TTL TTL/ST(2)
RB7
13
13
14
I/O
TTL/ST(2)
RC0(3) RC1(3) RC2 RC3 RC4
(3) (3) (3)
18 19 20 21 22 23 24 25 5 14
18 19 20 21 22 23 24 25 5 14
18 19 20 21 22 23 24 25 5,6 15,16
I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL TTL TTL TTL TTL TTL TTL TTL -- --
RC5(3) RC6
(3)
RC7(3) VSS VDD Legend:
O = Output I/O = Input/output P = Power -- = Not used I = Input ST = Schmitt Trigger input TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: PIC16C557 only.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 11
PIC16C55X
3.1 Clocking Scheme/Instruction Cycle
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 3-2. while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register (IR)" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
3.2
Instruction Flow/Pipelining
An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC
PC PC+1 PC+2 Internal phase clocks
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC2/CLKOUT (RC mode)
Execute INST (PC-1)
Fetch INST (PC)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
1. MOVLW 55h 2. MOVWF PORTB 3. CALL 4. BSF SUB_1
INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
PORTA, BIT3
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
DS40143D-page 12
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 4-2:
The PIC16C55X has a 13-bit program counter capable of addressing an 8 K x 14 program memory space. Only the first 512 x 14 (0000h - 01FFh) for the PIC16C554 and 2K x 14 (0000h - 07FFh) for the PIC16C557 and PIC16C558 are physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 512 x 14 spaces in the PIC16C554, or 2K x 14 space of the PIC16C558 and PIC16C557. The RESET vector is at 0000h and the interrupt vector is at 0004h (Figure 4-1, Figure 4-2).
PROGRAM MEMORY MAP AND STACK FOR THE PIC16C557 AND PIC16C558
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2 Stack Level 8 RESET Vector 000h
FIGURE 4-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16C554
PC<12:0> Interrupt Vector
0004 0005
CALL, RETURN RETFIE, RETLW
13
On-chip Program Memory 07FFh 0800h
Stack Level 1 Stack Level 2
Stack Level 8 RESET Vector
1FFFh
000h
4.2
Data Memory Organization
Interrupt Vector
0004 0005
On-chip Program Memory 01FFh 0200h
The data memory (Figure 4-3 through Figure 4-5) is partitioned into two banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bank 0 is selected when the RP0 bit (STATUS <5>) is cleared. Bank 1 is selected when the RP0 bit is set. The Special Function Registers are located in the first 32 locations of each Bank. Register locations 20-6Fh (Bank 0) on the PIC16C554 and 207Fh (Bank 0) and A0-BFh (Bank 1) on the PIC16C558 and PIC16C557 are General Purpose Registers implemented as static RAM. Some special purpose registers are mapped in Bank 1.
4.2.1
1FFFh
GENERAL PURPOSE REGISTER FILE
The register file is organized as 80 x 8 in the PIC16C554 and 128 x 8 in the PIC16C557 and PIC16C558. Each can be accessed either directly or indirectly through the File Select Register, FSR (Section 4.4).
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 13
PIC16C55X
FIGURE 4-3:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB
DATA MEMORY MAP FOR THE PIC16C554
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
FIGURE 4-4:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
DATA MEMORY MAP FOR THE PIC16C557
File Address INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
PCLATH INTCON
PCLATH INTCON
PCLATH INTCON
PCLATH INTCON
PCON
PCON
6Fh 70h
General Purpose Register
General Purpose Register
General Purpose Register
BFh C0h
7Fh
FFh Bank 0 Bank 1
7Fh
FFh Bank 0 Bank 1
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
DS40143D-page 14
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
FIGURE 4-5:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB
DATA MEMORY MAP FOR THE PIC16C558
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (Table 4-1). These registers are static RAM. The Special Function Registers can be classified into two sets (core and peripheral). The special function registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
PCLATH INTCON
PCLATH INTCON
PCON
General Purpose Register
General Purpose Register
BFh C0h
7Fh
FFh Bank 0 Bank 1
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
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PIC16C55X
TABLE 4-1:
Address Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh-1Eh 1Fh Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh-9Eh 9Fh INDF OPTION PCL STATUS FSR TRISA TRISB TRISC(4) -- -- PCLATH INTCON -- -- PCON -- -- -- TRISB7 -- TRISB6 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 xxxx xxxx 1111 1111 0000 0000 Z DC C 0001 1xxx xxxx xxxx 21 18 21 17 21 23 25 27 -- -- 21 19 -- -- 20 -- -- INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC(4) -- -- PCLATH INTCON -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP
(2) (2)
SPECIAL REGISTERS FOR THE PIC16C55X
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Detail on POR Reset Page:
xxxx xxxx xxxx xxxx 0000 0000
21 47 21 17 21 23 25 27 -- -- 21 19 -- -- --
RP1
RP0 -- RB5 RC5
TO RA4 RB4 RC4
PD RA3 RB3 RC3
Z RA2 RB2 RC2
DC RA1 RB1 RC1
C RA0 RB0 RC0
0001 1xxx xxxx xxxx ---x xxxx xxxx xxxx xxxx xxxx -- --
Indirect data memory address pointer -- RB7 RC7 -- RB6 RC6
Unimplemented Unimplemented -- GIE -- (3) -- T0IE INTE RBIE T0IF INTF RBIF
Write buffer for upper 5 bits of program counter ---0 0000 0000 000x -- -- --
Unimplemented Unimplemented Unimplemented
Program Counter's (PC) Least Significant Byte -- -- RP0 -- TO PD
Indirect data memory address pointer
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 -- -- -- T0IE Write buffer for upper 5 bits of program counter ---0 0000 INTE RBIE T0IF INTF RBIF 0000 000x -- -- -- -- -- -- POR -- ---- --0-- --
TRISC7 TRISC6 Unimplemented Unimplemented -- GIE -- (3)
Unimplemented Unimplemented -- --
Unimplemented Unimplemented
Legend: -- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: IRP & RP1 bits are reserved, always maintain these bits clear. 3: Bit 6 of INTCON register is reserved for future use. Always maintain this bit as clear. 4: PIC16C557 only.
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PIC16C55X
4.2.2.1 STATUS Register
The STATUS register, shown in Figure 4-2, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as the destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000uu1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect any status bits. For other instructions, not affecting any status bits, see the "Instruction Set Summary". Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16C55X and should be programmed as '0'. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 4-1:
STATUS REGISTER (ADDRESS 03h OR 83h)
Reserved IRP bit7 Reserved RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
bit 7
IRP: Register Bank Select bit (used for Indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) The IRP bit is reserved on the PIC16C55X, always maintain this bit clear RP1:RP0: Register Bank Select bits (used for Direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C55X, always maintain this bit clear. TO: Timeout bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT timeout occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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Preliminary
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PIC16C55X
4.2.2.2 OPTION Register
Note 1: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2:
OPTION REGISTER (ADDRESS 81H)
R/W-1 RBPU bit7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
bit 7
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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PIC16C55X
4.2.2.3 INTCON Register
Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The INTCON register is a readable and writable register which contains the various enable and flag bits for all interrupt sources.
REGISTER 4-3:
INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0 GIE bit7 Reserved -- R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts Reserved: For future use. Always maintain this bit clear. T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6 bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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Preliminary
DS40143D-page 19
PIC16C55X
4.2.2.4 PCON Register
The PCON register contains a flag bit to differentiate between a Power-on Reset, an external MCLR Reset or WDT Reset. See Section 6.3 and Section 6.4 for detailed RESET operation.
REGISTER 4-4:
PCON REGISTER (ADDRESS 8Eh)
U-0 -- bit7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR U-0 -- bit0
bit 7-2 bit 1
Unimplemented: Read as '0' POR: Power-on Reset status bit 1 = No Power-on Reset occurred 0 = Power-on Reset occurred Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 0
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PIC16C55X
4.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high bits (PC<12:8>) are not directly readable or writable and come from PCLATH. On any RESET, the PC is cleared. Figure 4-6 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 4-6 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or vectoring to an interrupt address.
FIGURE 4-6:
LOADING OF PC IN DIFFERENT SITUATIONS
4.4
PCH 12 PC 5 PCLATH<4:0> 8 8 7 PCL 0 Instruction with PCL as Destination ALU result
Indirect Addressing, INDF and FSR Registers
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the file select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a nooperation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-7. However, IRP is not used in the PIC16C55X. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-1.
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
4.3.1
COMPUTED GOTO
EXAMPLE 4-1:
movlw movwf clrf incf btfss goto
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556).
NEXT
CONTINUE:
4.3.2
STACK
The PIC16C55X family has an 8-level deep x 13-bit wide hardware stack (Figure 4-1 and Figure 4-2). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.
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Preliminary
DS40143D-page 21
PIC16C55X
FIGURE 4-7: DIRECT/INDIRECT ADDRESSING PIC16C55X
Direct Addressing
(1)
Indirect Addressing
0 IRP(1) 7 FSR register 0
RP1 RP0
6
from opcode
bank select
location select 00 00h 01 10 11
bank select 00h
location select
not used Data Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-3 and Figure 4-5. Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
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PIC16C55X
5.0 I/O PORTS
FIGURE 5-2:
The PIC16C554 and PIC16C558 have two ports, PORTA and PORTB. The PIC16C557 has three ports, PORTA, PORTB and PORTC.
BLOCK DIAGRAM OF RA4 PIN
Data bus WR PORTA
D
Q Q
5.1
PORTA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open-drain output. Port RA4 is multiplexed with the T0CKI clock input. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as input or output. A '1' in the TRISA register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISA register puts the contents of the output latch on the selected pin(s). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. Note 1: On RESET, the TRISA register is set to all inputs.
CK
N Data Latch
D Q Q
I/O pin(1)
VSS Schmitt Trigger input buffer VSS
WR TRISA
CK
TRISA Latch
RD TRISA
Q D EN EN
RD PORTA TMR0 clock input
FIGURE 5-1:
BLOCK DIAGRAM OF PORT PINS RA<3:0>
Data Bus D WR PORTA Q VDD CK Data Latch D WR TRISA Q N I/O pin Q P VDD
CK
Q
VSS Schmitt Trigger input buffer
VSS
TRIS Latch
RD TRISA Q D
EN RD PORTA
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Preliminary
DS40143D-page 23
PIC16C55X
TABLE 5-1:
Name RA0 RA1 RA2 RA3 RA4/T0CKI
PORTA FUNCTIONS
Bit # Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Buffer Type ST ST ST ST ST Function Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port or external clock input for TMR0. Output is open drain type.
Legend: ST = Schmitt Trigger input
TABLE 5-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR ---x xxxx ---1 1111 Value on All Other RESETS ---u uuuu ---1 1111
Name
05h 85h
PORTA TRISA
-- --
-- --
-- --
RA4
RA3
RA2
RA1
RA0
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Legend: -- = Unimplemented locations, read as `0', x = unknown, u = unchanged Note 1: Shaded bits are not used by PORTA.
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PIC16C55X
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' in the TRISB register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected pin(s). Reading PORTB register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. Each of the PORTB pins has a weak internal pull-up (200 A typical). A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on Power-on Reset. Four of PORTB's pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RBIF interrupt (flag latched in INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: * Any read or write of PORTB (this will end the mismatch condition) * Clear flag bit RBIF A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. The interrupt on mismatch feature, together with software configurable pull-ups on these four pins, allows easy interface to a key pad and make it possible for wake-up on key-depression. (See AN552 in the Microchip Embedded Control Handbook.) Note 1: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature.
FIGURE 5-3:
BLOCK DIAGRAM OF RB7:RB4 PINS
RBPU(1) VDD weak P pull-up VDD
Data Latch Data Bus WR PORTB D CK TRIS Latch D WR TRISB CK Q Q Q
VDD P
N VSS VSS TTL ST Input Buffer Buffer Latch Q D EN
I/O pin
RD TRISB
RD PORTB Set RBIF
From other RB7:RB4 pins
Q
D EN
RB7:RB6 in Serial Programming mode Note 1:
RD PORTB
TRISB = 1 enables weak pull-up if RBPU = `0' (OPTION<7>).
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Preliminary
DS40143D-page 25
PIC16C55X
FIGURE 5-4: BLOCK DIAGRAM OF RB3:RB0 PINS
RBPU(1) VDD weak P pull-up VDD
Data Latch Data Bus WR PORTB D CK TRIS Latch D WR TRISB CK Q Q Q
VDD P
N VSS VSS TTL ST Input Buffer Buffer Latch Q D EN
I/O pin
RD TRISB
RD PORTB
RB0/INT ST Buffer RD PORTB Note 1: TRISB = 1 enables weak pull-up if RBPU = `0' (OPTION<7>).
TABLE 5-3:
Name RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7
PORTB FUNCTIONS
Bit # Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Buffer Type TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) Function Bi-directional I/O port. Internal software programmable weak pull-up. Bi-directional I/O port. Internal software programmable weak pull-up. Bi-directional I/O port. Internal software programmable weak pull-up. Bi-directional I/O port. Internal software programmable weak pull-up. Bi-directional I/O port (with interrupt-on-change). Internal software programmable weak pull-up. Bi-directional I/O port (with interrupt-on-change). Internal software programmable weak pull-up. Bi-directional I/O port (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock pin.
Bi-directional I/O port (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data pin. Legend: ST = Schmitt Trigger, TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 5-4:
Address Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB AND TRISB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR xxxx xxxx 1111 1111 1111 1111 0000 000x Value on All Other RESETS uuuu uuuu 1111 1111 1111 1111 0000 000x
06h 86h 81h 0BH, 8BH
PORTB TRISB OPTION INTCON
RB7 TRISB7 RBPU GIE
RB6 TRISB6 INTEDG Reserved
RB5 TRISB5 T0CS T0IE
RB4 TRISB4 T0SE INTE
RB3 TRISB3 PSA BRIE
RB2 TRISB2 PS2 T0IF
RB1 TRISB1 PS1 INTF
RB0 TRISB0 PS0 RBIF
Legend: x = unknown, u = unchanged Note 1: Shaded bits are not used by PORTB.
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PIC16C55X
5.3 PORTC and TRISC Registers(1)
FIGURE 5-5:
PORTC is a 8-bit wide latch. All pins have data direction bits (TRIS registers) which can configure these pins as input or output. A '1' in the TRISC register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISC register puts the contents of the output latch on the selected pin(s). Reading the PORTC register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch
BLOCK DIAGRAM OF PORT PINS RC<7:0>
Data Bus D WR PORTC Q VDD CK Data Latch D WR TRISC Q N I/O pin Q P VDD
CK
Q
VSS
VSS
TRIS Latch
TTL Input Buffer RD TRISC Q D
EN RD PORTC
TABLE 5-5:
Name RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 Legend:
PORTC FUNCTIONS
Bit # Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Buffer Type TTL TTL TTL TTL TTL TTL TTL TTL Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Function
ST = Schmitt Trigger, TTL = TTL input
TABLE 5-6:
Address Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC AND TRISC
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR xxxx xxxx 1111 1111 Value on All Other RESETS uuuu uuuu 1111 1111
07h 87h
PORTC TRISC
RC7 TRISC7
RC6 TRISC6
RC5 TRISC5
RC4 TRISC4
RC3 TRISC3
RC2 TRISC2
RC1 TRISC1
RC0 TRISC0
Legend: x = unknown, u = unchanged Note 1: PIC16C557 ONLY.
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Preliminary
DS40143D-page 27
PIC16C55X
5.4
5.4.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit 0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. However, if bit 0 is switched into Output mode later on, the content of the data latch may now be unknown.
Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 5-1 shows the effect of two sequential readmodify-write instructions (ex., BCF,BSF, etc.) on an I/O port. A pin actively outputting a low or high should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip.
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Preliminary
2002 Microchip Technology Inc.
PIC16C55X
EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT 5.4.2 SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle, as shown in Figure 5-6. Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with an NOP or another instruction not accessing this I/O port.
; Initial PORT settings: PORTB<7:4> Inputs ; ; PORTB<3:0> Outputs ; PORTB<7:6> have external pull-up and are ; not connected to other circuitry ; ; PORT latch PORT pins ; ---------- --------; BCF BCF BSF BCF BCF PORTB, 7 PORTB, 6 STATUS, RP0 TRISB, 7 TRISB, 6 ; ; ; ; ; 01pp pppp 10pp pppp 10pp pppp 10pp pppp 11pp pppp 11pp pppp 11pp pppp 10pp pppp
FIGURE 5-6:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC Instruction fetched
PC MOVWF PORTB Write to PORTB
PC + 1 MOVF PORTB, W Read PORTB
PC + 2 NOP
PC + 3 NOP
RB <7:0> Port pin sampled here T PD Execute MOVWF PORTB Execute MOVF PORTB, W Execute NOP
Note 1: This example shows write to PORTB followed by a read from PORTB. 2: Data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid. Therefore, at higher clock frequencies, a write followed by a read may be problematic.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 29
PIC16C55X
NOTES:
DS40143D-page 30
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
6.0 SPECIAL FEATURES OF THE CPU
6.1 Configuration Bits
The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h - 3FFFh), which can be accessed only during programming.
What sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. The PIC16C55X family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. OSC selection RESET Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-Up Timer (OST) Interrupts Watchdog Timer (WDT) SLEEP Code protection ID Locations In-circuit serial programmingTM
The PIC16C55X has a Watchdog Timer which is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), which is intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in RESET while the power supply stabilizes. With these two functions onchip, most applications need no external RESET circuitry. The SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 31
PIC16C55X
REGISTER 6-1:
CP1 bit 13 CP<1:0>: Code protection bits(1) 11 = Program Memory code protection off 10 = 0400h - 07FFh code protected 01 = 0200h - 07FFh code protected 11 = 0000h - 07FFh code protected Unimplemented: Read as '1' Reserved: Do not use PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. CP0
CONFIGURATION WORD
CP1 CP0 CP1 CP0 -- Reserved CP1 CP0 PWRTE WDTE F0SC1 F0SC0 bit 0
bit 13-8 bit 5-4
bit 7 bit 6 bit 3
bit 2
Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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Preliminary
2002 Microchip Technology Inc.
PIC16C55X
6.2
6.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 6-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS (PRELIMINARY)
The PIC16C55X can be operated in four different oscillator options. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor
Ranges Characterized: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC1(C1) 22 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF OSC2(C2) 22 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
HS
6.2.2
CRYSTAL OSCILLATOR / CERAMIC RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 6-1). The PIC16C55X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1 pin (Figure 6-2).
Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult with the resonator manufacturer for appropriate values of external components.
TABLE 6-2:
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR (PRELIMINARY)
Freq OSC1(C1) 68 - 100 pF 15 - 30 pF 68 - 150 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF OSC2(C2) 68 - 100 pF 15 - 30 pF 150 - 200 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF
FIGURE 6-1:
CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)
OSC1
Mode LP XT
32 kHz 200 kHz 100 kHz 2 MHz 4 MHz 8 MHz 10 MHz 20 MHz
C1 XTAL OSC2 C2 Note 1: 2: RS Note 1 RF
To internal logic SLEEP
HS
PIC16C55X
A series resistor may be required for AT strip cut crystals. See Table 6-1 and Table 6-2 for recommended values of C1 and C2.
FIGURE 6-2:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low-drive level specification. Since each crystal has its own characteristics, the user should consult with the crystal manufacturer for appropriate values of external components.
Clock from ext. system Open
OSC1 PIC16C55X OSC2
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 33
PIC16C55X
6.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 6.2.4 RC OSCILLATOR
Either a pre-packaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance. Figure 6-3 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180 phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This could be used for external oscillator designs. For timing insensitive applications the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 6-5 shows how the R/C combination is connected to the PIC16C55X. For REXT values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high REXT values (e.g., 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep REXT between 3 k and 100 k. Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (Figure 3-2 for waveform).
FIGURE 6-3:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
To other Devices
+5V 10k 4.7k 74AS04 74AS04 CLKIN PIC16C55X
10k XTAL 10k VDD 20 pF 20 pF REXT PIC16C55X OSC1 Internal Clock CEXT VSS Fosc/4 OSC2/CLKOUT
FIGURE 6-5:
RC OSCILLATOR MODE
Figure 6-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180 phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 6-4:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
330 74AS04 74AS04 CLKIN To other Devices PIC16C55X
330 74AS04 0.1 F
XTAL
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Preliminary
2002 Microchip Technology Inc.
PIC16C55X
6.3 RESET
The PIC16C55X differentiates between various kinds of RESET: * * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (normal operation) WDT wake-up (SLEEP) A simplified block diagram of the on-chip RESET circuit is shown in Figure 6-6. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Table 10-3 for pulse width specification.
Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a "RESET state" on Power-on Reset, on MCLR or WDT Reset and on MCLR Reset during SLEEP. They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different RESET situations as indicated in Table 6-4. These bits are used in software to determine the nature of the RESET. See Table 6-6 for a full description of RESET states of all registers.
FIGURE 6-6:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/ VPP Pin WDT Module VDD rise detect VDD
SLEEP WDT Timeout Reset Power-on Reset S
OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin On-chip(1) RC OSC R Q Chip_Reset
PWRT 10-bit Ripple-counter
Enable PWRT Enable OST
See Table 6-3 for timeout situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 35
PIC16C55X
6.4 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST)
POWER-ON RESET (POR) 6.4.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST timeout is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.
6.4.1
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.6V - 1.8V). To take advantage of the POR, just tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Electrical Specifications for details. The POR circuit does not produce internal RESET when VDD declines. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. For additional information, refer to Application Note AN607 "Power-up Trouble Shooting".
6.4.4
TIMEOUT SEQUENCE
On power-up, the timeout sequence is as follows: First PWRT timeout is invoked after POR has expired, then OST is activated. The total timeout will vary based on oscillator configuration and PWRTE bit status. For example, in RC mode with PWRTE bit erased (PWRT disabled), there will be no timeout at all. Figure 6-7, Figure 6-8 and Figure 6-9 depict timeout sequences. Since the timeouts occur from the POR pulse, if MCLR is kept low long enough, the timeouts will expire. Then bringing MCLR high will begin execution immediately (see Figure 6-8). This is useful for testing purposes or to synchronize more than one PIC16C55X device operating in parallel. Table 6-5 shows the RESET conditions for some special registers, while Table 6-6 shows the RESET conditions for all the registers.
6.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal) timeout on power-up only, from POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-Up Time delay will vary from chip to chip and due to VDD, temperature and process variation. See DC parameters for details.
DS40143D-page 36
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
6.4.5 POWER CONTROL/STATUS REGISTER (PCON)
Bit1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent RESET if POR is `0', it will indicate that a Poweron Reset must have occurred (VDD may have gone too low).
TABLE 6-3:
TIMEOUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 72 ms + 1024 TOSC 72 ms PWRTE = 1 1024 TOSC -- Wake-up from SLEEP 1024 TOSC --
Oscillator Configuration XT, HS, LP RC
TABLE 6-4:
POR 0 0 0 1 1 1 1
STATUS BITS AND THEIR SIGNIFICANCE
TO 1 0 X 0 0 u 1 PD 1 X 0 u 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 37
PIC16C55X
TABLE 6-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Interrupt Wake-up from SLEEP Program Counter 000h 000h 000h 000h PC + 1 PC + 1(1) STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu uuu1 0uuu PCON Register ---- --0---- --u---- --u---- --u---- --u---- --u-
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1.
TABLE 6-6:
INITIALIZATION CONDITION FOR REGISTERS
MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset uuuu uuuu -- uuuu uuuu 0000 0000 000q quuu(3) uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu ---0 0000 0000 000u 1111 1111 ---1 1111 1111 1111 1111 1111 ---- --uWake-up from SLEEP through interrupt Wake-up from SLEEP through WDT timeout uuuu uuuu -- uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu(1) uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu ---- --u-
Register
Address
Power-on Reset xxxx xxxx -- xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx ---x xxxx xxxx xxxx xxxx xxxx ---0 0000 0000 000x 1111 1111 ---1 1111 1111 1111 1111 1111 ---- --0-
W INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC
(4)
-- 00h 01h 02h 03h 04h 05h 06h 06h 0Ah 0Bh 81h 85h 86h
(4)
PCLATH INTCON OPTION TRISA TRISB TRISC PCON
86h 8Eh
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Note 1: One or more bits in INTCON will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 6-5 for RESET value for specific condition. 4: PIC16C557 only.
DS40143D-page 38
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
FIGURE 6-7: TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIMEOUT
TOST
OST TIMEOUT
INTERNAL RESET
FIGURE 6-8:
TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIMEOUT
TOST
OST TIMEOUT
INTERNAL RESET
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 39
PIC16C55X
FIGURE 6-9:
VDD MCLR INTERNAL POR TPWRT PWRT TIMEOUT
TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): CASE 3
TOST
OST TIMEOUT
INTERNAL RESET
FIGURE 6-10:
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD
VDD
D
R R1 MCLR C PIC16C55X
Note
1:
2: 3:
External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
DS40143D-page 40
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
6.5 Interrupts
The PIC16C55X has 3 sources of interrupt: * External interrupt RB0/INT * TMR0 overflow interrupt * PORTB change interrupts (pins RB7:RB4) The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. GIE is cleared on RESET. The "Return from Interrupt" instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables RB0/INT interrupts. The INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid RB0/INT recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 6-12). The latency is the same for one or two cycle instructions. Once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again.
FIGURE 6-11:
INTERRUPT LOGIC
T0IF T0IE INTF INTE RBIF RBIE Wake-up (If in SLEEP mode)
Interrupt to CPU
GIE
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 41
PIC16C55X
6.5.1 RB0/INT INTERRUPT 6.5.2 TMR0 INTERRUPT
An external interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION<6>) is set, or falling if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before reenabling this interrupt. The RB0/INT interrupt can wake-up the processor from SLEEP, if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. See Section 6.8 for details on SLEEP and Figure 6-14 for timing of wakeup from SLEEP through RB0/INT interrupt. An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 7.0.
6.5.3
PORTB INTERRUPT
An input change on PORTB <7:4> sets the RBIF (INTCON<0>) bit. The interrupt can be enabled/disabled by setting/clearing the RBIE (INTCON<4>) bit. For operation of PORTB (Section 5.2). Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may get set.
FIGURE 6-12:
INT PIN INTERRUPT TIMING
Q1 OSC1 CLKOUT 3
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
4 INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) PC+1 -- Dummy Cycle 0004h Inst (0004h) Dummy Cycle 0005h Inst (0005h) Inst (0004h) 1 5 1 Interrupt Latency 2
Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
DS40143D-page 42
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
6.6 Context Saving During Interrupts 6.7 Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W register and STATUS register). This will have to be implemented in software. Example 6-1 stores and restores the STATUS and W registers. The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x20 in Bank 0 and it must also be defined at 0xA0 in Bank 1). The user register, STATUS_TEMP, must be defined in Bank 0. The Example 6-1: * * * * Stores the W register Stores the STATUS register in Bank 0 Executes the ISR code Restores the STATUS (and bank select bit register) * Restores the W register The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the CLKIN pin. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT timeout generates a device RESET. If the device is in SLEEP mode, a WDT timeout causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the configuration bit WDTE as clear (Section 6.1).
6.7.1
WDT PERIOD
EXAMPLE 6-1:
SAVING THE STATUS AND W REGISTERS IN RAM
;copy W to TEMP ;register, could be in ;either bank ;swap STATUS to be ;saved into W ;change to bank0 ;regardless of ;current bank ;save STATUS to bank0 ;register
The WDT has a nominal timeout period of 18 ms, (with no prescaler). The timeout periods vary with temperature, VDD and process variations from part-to-part (see DC specs). If longer timeout periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, timeout periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET. The TO bit in the STATUS register will be cleared upon a Watchdog Timer timeout.
MOVWF W_TEMP
SWAPF STATUS,W BCF STATUS,RP0
6.7.2
MOVWF STATUS_TEMP
WDT PROGRAMMING CONSIDERATIONS
: : : SWAPF STATUS_TEMP,W;swap STATUS_TEMP ;register into W, sets ;bank to original state MOVWF STATUS ;move W into STATUS ;register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W
It should also be taken in account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a WDT timeout occurs.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 43
PIC16C55X
FIGURE 6-13: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 7-6)
0 Watchdog Timer 1
M U X
Postscaler 8 8 - to - 1 MUX PS<2:0>
PSA WDT Enable Bit To TMR0 (Figure 7-6) 0 MUX 1 PSA
WDT Timeout Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 6-7:
Address 2007h 81h
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7 -- RBPU Bit 6 Reserved INTEDG Bit 5 CP1 Bit 4 CP0 Bit 3 Bit 2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0 1111 1111 1111 1111 Value on POR Value on all other RESETS
Name Config. bits OPTION
PWRTE WDTE PSA PS2
T0CS T0SE
Legend: x = unknown, u = unchanged, q = value depends on condition, -- = unimplemented, read as `0'. Shaded cells are not used by the Watchdog Timer.
DS40143D-page 44
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
6.8 Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit in the STATUS register is cleared, the TO bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before SLEEP was executed (driving high, low, or hiimpedance). For lowest current consumption in this mode, all I/O pins should be either at VDD, or VSS, with no external circuitry drawing current from the I/O pin. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). Note: It should be noted that a RESET generated by a WDT timeout does not drive MCLR pin low. The first event will cause a device RESET. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device RESET. PD bit, which is set on power-up is cleared when SLEEP is invoked. TO bit is cleared if WDT Wake-up occurred. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have an NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from SLEEP. The SLEEP instruction is completely executed.
6.8.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin Watchdog Timer Wake-up (if WDT was enabled) Interrupt from RB0/INT pin or RB Port change
The WDT is cleared when the device wakes-up from SLEEP, regardless of the source of wake-up.
FIGURE 6-14:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2)
OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed Note 1: 2: 3: 4: PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency(2)
XT, HS or LP Oscillator mode assumed. TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
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Preliminary
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PIC16C55X
6.9 Code Protection
FIGURE 6-15:
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices.
External Connector Signals +5V
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections PIC16C55X VDD VSS MCLR/VPP RB6 RB7 VDD To Normal Connections
6.10
ID Locations
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify.
0V VPP CLK Data I/O
6.11
In-Circuit Serial ProgrammingTM
The PIC16C55X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RB6 and RB7 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After RESET, to place the device into Programming/ Verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X Programming Specifications (Literature #DS30228). A typical in-circuit serial programming connection is shown in Figure 6-15.
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2002 Microchip Technology Inc.
PIC16C55X
7.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. The prescaler is shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale value of 1:2, 1:4, ..., 1:256 are selectable. Section 7.3 details the operation of the prescaler.
Figure 7-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In Timer mode, the TMR0 will increment every instruction cycle (without prescaler). If Timer0 is written, the increment is inhibited for the following two cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to TMR0. Counter mode is selected by setting the T0CS bit. In this mode Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the source edge (T0SE) control
7.1
TIMER0 Interrupt
Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit. The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit (INTCON<2>) must be cleared in software by the Timer0 module interrupt service routine before reenabling this interrupt. The Timer0 interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP. See Figure 7-4 for Timer0 interrupt timing.
FIGURE 7-1:
RA4/T0CKI pin
TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 Programmable Prescaler 0 PSout Sync with Internal clocks (2 Tcy delay) Set Flag bit T0IF on Overflow TMR0 PSout 8
T0SE PSA
PS2:PS0 T0CS
Note 1: Bits, T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register. 2: The prescaler is shared with Watchdog Timer (Figure 7-6)
FIGURE 7-2:
PC (Program Counter) Instruction Fetch T0
TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC
MOVWF TMR0
PC+1
PC+2
PC+3
PC+4
MOVF TMR0,W
PC+5
MOVF TMR0,W
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
TMR0 Instruction Executed
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2
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Preliminary
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PIC16C55X
FIGURE 7-3:
PC (Program Counter) Instruction Fetch TMR0 Instruction Execute T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC
MOVWF TMR0
PC+1
PC+2
PC+3
PC+4
MOVF TMR0,W
PC+5
MOVF TMR0,W
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+1
NT0
NT0+1
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
FIGURE 7-4:
Q1 OSC1 CLKOUT(3) TMR0 timer T0IF bit (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed
TIMER0 INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
FEh 1
FFh 1
00h
01h
02h
Interrupt Latency Time
PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h)
Inst (PC)
Note
1: 2: 3:
T0IF interrupt flag is sampled here (every Q1). Interrupt latency = 4 TCY, where TCY = instruction cycle time. CLKOUT is available only in RC Oscillator mode.
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PIC16C55X
7.2 Using Timer0 with External Clock
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device.
7.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-5). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
7.2.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the TMR0 is actually incremented. Figure 7-5 shows the delay from the external clock edge to the timer incrementing.
FIGURE 7-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler output (2)
(1) (3)
External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = 4 TOSC max. 2: External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.
7.3
Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 7-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note: There is only one prescaler available which is mutually exclusive between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.
The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.
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Preliminary
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PIC16C55X
FIGURE 7-6:
CLKOUT (=Fosc/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Tcy TMR0 reg
0 T0CKI pin 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8-to-1MUX PS0 - PS2
Watchdog Timer
1
PSA 0 1 PSA
WDT Enable bit
MUX
WDT Timeout Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
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PIC16C55X
7.3.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 7-1) must be executed when changing the prescaler assignment from Timer0 to WDT. Lines 5-7 are required only if the desired postscaler rate is 1:1 (PS<2:0> = 000) or 1:2 (PS<2:0> = 001). To change prescaler from the WDT to the TMR0 module use the sequence shown in Example 7-2. This precaution must be taken even if the WDT is disabled.
EXAMPLE 7-2:
CLRWDT BSF MOVLW
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ;prescaler
STATUS, RP0 b'xxxx0xxx'
;Select TMR0, new ;prescale value and ;clock source
EXAMPLE 7-1:
BCF CLRF BSF MOVLW MOVWF
CHANGING PRESCALER (TIMER0WDT)
MOVWF BCF
OPTION STATUS, RP0
MOVLW MOVWF BCF
STATUS, RP0 ;Skip if already in ;Bank 0 CLRWDT Clear WDT TMR0 ;Clear TMR0 & Prescaler STATUS, RP0 ;Bank 1 '00101111'b ;These 3 lines (5, 6, 7) OPTION ;Are required only if ;Desired PS<2:0> are ;CLRWDT 000 or 001 '00101xxx'b ;Set Postscaler to OPTION ;Desired WDT rate STATUS, RP0 ;Return to Bank 0
TABLE 7-1:
Address 01h 0Bh/8Bh 81h 85h Name TMR0 INTCON OPTION TRISA
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR xxxx xxxx T0IE T0CS -- INTE T0SE TRISA4 RBIE PSA TRISA3 T0IF PS2 TRISA2 INTF PS1 TRISA1 RBIF PS0 TRISA0 0000 000x 1111 1111 ---1 1111 Value on All Other RESETS uuuu uuuu 0000 000x 1111 1111 ---1 1111
Timer0 module's register GIE RBPU -- Reserved INTEDG --
Legend: -- = Unimplemented locations, read as `0', Note 1: Shaded bits are not used by TMR0 module.
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PIC16C55X
NOTES:
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Preliminary
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PIC16C55X
8.0 INSTRUCTION SET SUMMARY
The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 8-1 lists the instructions recognized by the MPASMTM assembler. Figure 8-1 shows the three general formats that the instructions can have. Note: To maintain upward compatibility with future PICmicro(R) products, do not use the OPTION and TRIS instructions. Each PIC16C55X instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16C55X instruction set summary in Table 8-2 lists byte-oriented, bitoriented, and literal and control operations. Table 81 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value.
TABLE 8-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 Label name Top of Stack Program Counter Program Counter High Latch Global Interrupt Enable bit Watchdog Timer/Counter Timeout bit Power-down bit Destination either the W register or the specified register file location Options Contents Assigned to Register bit field
FIGURE 8-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
d
label TOS PC PCLATH GIE WDT TO PD dest [ ( ] )
0
0
<>
In the set of italics User defined term (font is courier)
0
k = 11-bit immediate value
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PIC16C55X
TABLE 8-2:
Mnemonic, Operands
PIC16C55X INSTRUCTION SET
14-Bit Opcode Description Cycles MSb LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1(2) 1(2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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PIC16C55X
8.1 Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register.
k
Words: Cycles: Example
1 1
ADDLW 0x15
Words: Cycles: Example
1 1
ANDLW 0x5F
Before Instruction W = 0x10 After Instruction W = 0x25
Before Instruction W = 0xA3 After Instruction W = 0x03
ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (dest) C, DC, Z
00 0111 dfff ffff Add the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
ANDWF f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (dest) Z
00 0101 dfff ffff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Words: Cycles: Example
1 1
ADDWF FSR, 0
Words: Cycles: Example
1 1
ANDWF FSR, 1
Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0xD9 FSR = 0xC2
Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0x17 FSR = 0x02
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PIC16C55X
BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None
01 00bb bfff ffff Bit 'b' in register 'f' is cleared.
BTFSC f,b Syntax: Operands: Operation: Status Affected: Encoding: Description:
Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None
01 10bb bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is skipped. If bit 'b' is '0' then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction.
1 1
BCF FLAG_REG, 7
Before Instruction FLAG_REG = After Instruction FLAG_REG =
Words: 0xC7 0x47 Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSC GOTO * * * FLAG,1 PROCESS_CODE
BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None
01 01bb bfff ffff Bit 'b' in register 'f' is set.
f,b
Before Instruction PC = address HERE After Instruction if FLAG<1> = 0, PC = address TRUE if FLAG<1> = 1, PC = address FALSE
BSF
FLAG_REG,
7
Before Instruction FLAG_REG = After Instruction FLAG_REG =
0x0A 0x8A
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PIC16C55X
BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None
01 11bb bfff ffff
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None
10 0kkk kkkk kkkk Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
Status Affected: Encoding: Description:
If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a twocycle instruction.
Words: Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSS GOTO * * * FLAG,1 PROCESS_CODE
Words: Cycles: Example
1 2
HERE CALL THERE
Before Instruction PC = address HERE After Instruction if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE
Before Instruction PC = Address HERE After Instruction PC = Address THERE TOS = Address HERE+1
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z
00 0001 1fff ffff The contents of register 'f' are cleared and the Z bit is set.
f
1 1
CLRF FLAG_REG
Before Instruction FLAG_REG=0x5A After Instruction FLAG_REG=0x00 Z =1
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PIC16C55X
CLRW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Clear W [ label ] CLRW None 00h (W) 1Z Z
00 0001 0000 0011 W register is cleared. Zero bit (Z) is set.
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (dest) Z
00 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
f,d
1 1
CLRW
Words: Cycles: Example
1 1
COMF REG1,0
Before Instruction W = 0x5A After Instruction W = 0x00 Z = 1
Before Instruction REG1 = 0x13 After Instruction REG1 = 0x13 W = 0xEC
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (dest) Z
00 0011 dfff ffff Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Status Affected: Encoding: Description:
Words: Cycles: Example
1 1
DECF CNT, 1
Words: Cycles: Example
1 1
CLRWDT
Before Instruction WDT counter After Instruction WDT counter WDT prescaler TO PD
=? = = = = 0x00 0 1 1
Before Instruction CNT = 0x01 Z =0 After Instruction CNT = 0x00 Z =1
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DECFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (dest); None
00 1011 dfff ffff The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction.
GOTO Syntax: Operands: Operation:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None
10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
skip if result = 0 Status Affected: Encoding: Description:
Words: Cycles: Example
1 2
GOTO THERE
Words: Cycles: Example
1 1(2)
HERE DECFSZ GOTO CONTINUE * * * CNT, 1 LOOP
After Instruction PC = Address THERE
INCF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (dest) Z
00 1010 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
Before Instruction PC = address HERE After Instruction CNT = CNT - 1 if CNT = 0, PC = address CONTINUE if CNT 0, PC = address HERE+1
Words: Cycles: Example
1 1
INCF CNT, 1
Before Instruction CNT = 0xFF Z = 0 After Instruction CNT = 0x00 Z = 1
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PIC16C55X
INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (dest), skip if result = 0 None
00 1111 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction.
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (dest) Z
00 0100 dfff ffff Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
Words: Cycles: Example
1 1
IORWF RESULT, 0
Words: Cycles: Example
1 1(2)
INCFSZ GOTO CONTINUE * * * HERE CNT, LOOP 1
Before Instruction PC = address HERE After Instruction CNT = CNT + 1 if CNT = 0, PC = address CONTINUE if CNT 0, PC = address HERE +1
Before Instruction RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93 Z =1
IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z
11 1000 kkkk kkkk The contents of the W register is OR'ed with the eight bit literal 'k'. The result is placed in the W register.
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to W [ label ] k (W) None
11 00xx kkkk kkkk The eight bit literal 'k' is loaded into W register. The don't cares will assemble as 0's.
MOVLW k
0 k 255
Words: Cycles: Example
1 1
IORLW 0x35
Words: Cycles: Example
1 1
MOVLW 0x5A
Before Instruction W = 0x9A After Instruction W = 0xBF Z = 1
After Instruction W = 0x5A
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MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
No Operation [ label ] None No operation None
00 0000 0xx0 0000 No operation.
NOP
The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. 1 1
MOVF FSR, 0
NOP
Words: Cycles: Example
After Instruction W = value in FSR register Z =1
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Move W to f [ label ] (W) (f) None
00 0000 1fff ffff Move data from W register to register 'f'.
OPTION f Syntax: Operands: Operation: Status Affected: Encoding: Description:
Load Option Register [ label ] None (W) OPTION None
00 0000 0110 0010 The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.
MOVWF
OPTION
0 f 127
1 1
MOVWF OPTION
Before Instruction OPTION = W = After Instruction OPTION = W =
Words: 0xFF 0x4F 0x4F 0x4F Cycles: Example
1 1
To maintain upward compatibility with future PICmicroTM products, do not use this instruction.
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PIC16C55X
RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Interrupt [ label ] None TOS PC, 1 GIE None
00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Subroutine [ label ] None TOS PC None
00 0000 0000 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction.
RETFIE
RETURN
Words: Cycles: Example
1 2
RETURN
Words: Cycles: Example
1 2
RETFIE
After Interrupt PC =
TOS
After Interrupt PC = GIE =
TOS 1
RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None
11 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Left f through Carry [ label ] RLF 0 f 127 d [0,1] See description below C
00 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. C Register f
f,d
Words: Cycles: Example
1 2
CALL TABLE;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset TABLE RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table
Words: Cycles: Example
1 1
RLF REG1,0
Before Instruction W = 0x07 After Instruction W = value of k8
Before Instruction REG1 = 1110 0110 C =0 After Instruction REG1 = 1110 0110 W = 1100 1100 C =1
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PIC16C55X
RRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. C Register f
SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) C, DC, Z
11 110x kkkk kkkk
The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Example 1:
1 1
SUBLW 0x02
Words: Cycles: Example
1 1
RRF REG1,0
Before Instruction W C W C Example 2: W C W C = = = = = = = = = = = = 1 ? 1 1; result is positive 2 ? 0 1; result is zero 3 ? 0xFF 0; result is nega-
Before Instruction REG1 = 1110 0110 C =0 After Instruction REG1 = 1110 0110 W = 0111 0011 C =0
After Instruction
Before Instruction
After Instruction
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD
00 0000 0110 0011 The power-down status bit, PD is cleared. Timeout status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 6.8 for more details.
SLEEP
Example 3:
Before Instruction W C W C tive
After Instruction
Status Affected: Encoding: Description:
Words: Cycles: Example:
1 1
SLEEP
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PIC16C55X
SUBWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (dest) C, DC, Z Status Affected:
00 0010 dfff ffff
SWAPF Syntax: Operands: Operation:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None
00 1110 dfff ffff The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.
Encoding: Description:
Subtract (2's complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Words: Cycles: Example 1:
1 1
SUBWF REG1,1
Words: Cycles: Example
1 1
SWAPF REG, 0
Before Instruction REG1 = W = C = After Instruction REG1 = W = C = Example 2: REG1 = W = C = After Instruction REG1 = W = C = Example 3: REG1 = W = C = After Instruction REG1 = W = C = 0xFF 2 0; result is negative 0 2 1; result is zero 1 2 ? 1 2 1; result is positive 2 2 ? 3 2 ?
Before Instruction REG1 REG1 W = 0xA5 = 0xA5 = 0x5A After Instruction
TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description:
Load TRIS Register [ label ] TRIS 5f7 (W) TRIS register f; None
00 0000 0110 0fff The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.
Before Instruction
f
Before Instruction Words: Cycles: Example
1 1
To maintain upward compatibility with future PICmicroTM products, do not use this instruction.
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PIC16C55X
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z
11 1010 kkkk kkkk The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Example:
1 1
XORLW 0xAF
Before Instruction W W = = 0xB5 0x1A After Instruction
XORWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (dest) Z
00 0110 dfff ffff Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Words: Cycles: Example
1 1
XORWF REG 1
Before Instruction REG = W = After Instruction REG = W = 0x1A 0xB5 0xAF 0xB5
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NOTES:
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PIC16C55X
9.0 DEVELOPMENT SUPPORT
The MPLAB IDE allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files - absolute listing file - machine code The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the costeffective simulator to a full-featured emulator with minimal retraining. The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPICTM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Entry-Level Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ(R) Demonstration Board
9.2
MPASM Assembler
The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCU's. The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects. * User-defined macros to streamline assembly code. * Conditional assembly for multi-purpose source files. * Directives that allow complete control over the assembly process.
9.1
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows(R)-based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor * A project manager * Customizable toolbar and key mapping * A status bar * On-line help
9.3
MPLAB C17 and MPLAB C18 C Compilers
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI `C' compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display.
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Preliminary
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PIC16C55X
9.4 MPLINK Object Linker/ MPLIB Object Librarian 9.6
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: * Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. * Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: * Easier linking because single libraries can be included instead of many smaller files. * Helps keep code maintainable by grouping related modules together. * Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted.
MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily re configured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows environment were chosen to best make these features available to you, the end user.
9.7
ICEPIC In-Circuit Emulator
9.5
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi-project software development tool.
The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present.
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PIC16C55X
9.8 MPLAB ICD In-Circuit Debugger 9.11
Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in realtime.
PICDEM 1 Low Cost PICmicro Demonstration Board
9.9
PRO MATE II Universal Device Programmer
The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in Stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In Stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode.
The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB.
9.12
PICDEM 2 Low Cost PIC16CXX Demonstration Board
9.10
PICSTART Plus Entry Level Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad.
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Preliminary
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9.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board 9.14 PICDEM 17 Demonstration Board
The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware.
9.15
KEELOQ Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchip's HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters.
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2002 Microchip Technology Inc.
24CXX/ 25CXX/ 93CXX
PIC14000
HCSXXX
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
PIC16F62X
PIC16C7XX
PIC16F8XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
PIC18FXXX
MCRFXXX
MCP2510
TABLE 9-1:
MPLAB(R) Integrated Development Environment
MPLAB(R) C17 C Compiler
Software Tools
MPLAB(R) C18 C Compiler
MPASMTM Assembler/ MPLINKTM Object Linker
Programmers Debugger Emulators
Demo Boards and Eval Kits
2002 Microchip Technology Inc. ** * ** **

MPLAB(R) ICE In-Circuit Emulator
ICEPICTM In-Circuit Emulator
MPLAB(R) ICD In-Circuit Debugger
*
PICSTART(R) Plus Entry Level Development Programmer
PRO MATE(R) II Universal Device Programmer
DEVELOPMENT TOOLS FROM MICROCHIP
Preliminary
PICDEMTM 1 Demonstration Board
PICDEMTM 2 Demonstration Board
PICDEMTM 3 Demonstration Board
PICDEMTM 14A Demonstration Board
PICDEMTM 17 Demonstration Board
KEELOQ(R) Evaluation Kit
KEELOQ(R) Transponder Kit
microIDTM Programmer's Kit
125 kHz microIDTM Developer's Kit
125 kHz Anticollision microIDTM Developer's Kit
13.56 MHz Anticollision microIDTM Developer's Kit
MCP2510 CAN Developer's Kit
PIC16C55X
DS40143D-page 71
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB(R) ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date.
PIC16C55X
NOTES:
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PIC16C55X
10.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Ambient Temperature under bias ...............................................................................................................-40 to +125C Storage Temperature ................................................................................................................................ -65 to +150C Voltage on any pin with respect to VSS (except VDD and MCLR) .......................................................-0.6V to VDD +0.6V Voltage on VDD with respect to VSS ................................................................................................................. 0 to +7.5V Voltage on MCLR with respect to VSS................................................................................................................0 to +14V Total power Dissipation (Note 1)...............................................................................................................................1.0W Maximum Current out of VSS pin ..........................................................................................................................300 mA Maximum Current into VDD pin .............................................................................................................................250 mA Input Clamp Current, IIK (VI < 0 or VI > VDD) ........................................................................................................ 20 mA Output Clamp Current, IOK (V0 < 0 or V0 > VDD).................................................................................................. 20 mA Maximum Output Current sunk by any I/O pin ........................................................................................................25 mA Maximum Output Current sourced by any I/O pin...................................................................................................25 mA Maximum Current sunk by PORTA, PORTB and PORTC ....................................................................................200 mA Maximum Current sourced by PORTA, PORTB and PORTC ...............................................................................200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 73
PIC16C55X
FIGURE 10-1: PIC16LC554/557/558 VOLTAGE-FREQUENCY GRAPH, 0C TA +70C (COMMERCIAL TEMPS)
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 0 4 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 20 25
FIGURE 10-2:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0
PIC16LC554/557/558 VOLTAGE-FREQUENCY GRAPH, -40C TA < 0C, +70C < TA +125C (OUTSIDE OF COMMERCIAL TEMPS)
4
10 Frequency (MHz)
20
25
Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
DS40143D-page 74
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
FIGURE 10-3:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 20 25
PIC16LC554/557/558 VOLTAGE-FREQUENCY GRAPH, 0C TA +85C
FIGURE 10-4:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.7 2.5 2.0 0
PIC16LC554/557/558 VOLTAGE-FREQUENCY GRAPH, -40C TA 0C
4
10 Frequency (MHz)
20
25
Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 75
PIC16C55X
10.1 DC Characteristics: PIC16C55X-04 (Commercial, Industrial, Extended) PIC16C55X-20 (Commercial, Industrial, Extended) PIC16LC55X-04(Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for extended Characteristic Supply Voltage 16LC55X 16C55X VDR VPOR SVDD IDD D010 RAM Data Retention Voltage(1) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(2) 16LC55X -- 1.4 2.5 mA XT and RC osc configuration Fosc = 2.0 MHz, VDD = 3.0V, WDT disabled(4) LP osc configuration Fosc = 32 kHz, VDD = 3.0V, WDT disabled XT and RC osc configuration FOSC = 4 MHz, VDD = 5.5V, WDT disabled(4) LP osc configuration, PIC16C55X-04 only FOSC = 32 kHz, VDD = 4.0V, WDT disabled HS osc configuration FOSC = 20 MHz, VDD = 5.5V, WDT disabled 3.0 2.5 3.0 4.5 -- -- 0.05* -- -- -- 1.5* VSS -- 5.5 5.5 5.5 5.5 -- -- -- V V V V V XT and RC osc configuration LP osc configuration XT, RC and LP osc configuration HS osc configuration Device in SLEEP mode See Section 6.4, Power-on Reset for details Min Typ Max Units Conditions
DC Characteristics
Param No. D001 D001 D001A D002 D003 D004
Sym VDD
V/ms See Section 6.4, Power-on Reset for details
D010A
--
26
53
A
D010
16C55X
--
1.8
3.3
mA
D010A
--
35
70
A
D013
--
9.0
20
mA
*
These parameters are characterized but not tested.
Data is "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins configured as input, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
DS40143D-page 76
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
10.1 DC Characteristics: PIC16C55X-04 (Commercial, Industrial, Extended) PIC16C55X-20 (Commercial, Industrial, Extended) PIC16LC55X-04(Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for extended Characteristic Power-Down Current(3) 16LC55X 16C55X IWDT WDT Current(5) 16LC55X 16C55X * -- -- 6.0 6.0 15 20 A A VDD = 3.0V VDD = 4.0V (+85C to +125C) -- -- 0.7 1.0 2 2.5 15 A A A VDD = 3.0V, WDT disabled VDD = 4.0V, WDT disabled (+85C to +125C) Min Typ Max Units Conditions
DC Characteristics
Param No. D020
Sym IPD
These parameters are characterized but not tested.
Data is "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins configured as input, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 77
PIC16C55X
10.2 DC Characteristics: PIC16C55X (Commercial, Industrial, Extended) PIC16LC55X(Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for automotive Operating voltage VDD range as described in DC spec Table 10-1
Characteristic Input Low Voltage I/O ports D030 D031 D032 D033 VIH D040 D041 D042 D043 D043A D070 IPURB IIL with TTL buffer with Schmitt Trigger input MCLR, RA4/T0CKI,OSC1 (in RC mode) OSC1 (in XT* and HS) OSC1 (in LP*) Input High Voltage I/O ports with TTL buffer with Schmitt Trigger input MCLR RA4/T0CKI OSC1 (XT*, HS and LP*) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current
(2)(3)
DC Characteristics
Param. No.
Sym VIL
Min
Typ
Max
Unit
Conditions
VSS VSS VSS VSS VSS
--
0.8V 0.15 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.6 VDD-1.0
V V V V V
VDD = 4.5V to 5.5V otherwise (Note1)
-- -- -- --
2.0V 0.8 + 0.25 VDD 0.8V 0.8 VDD 0.7 VDD 0.9 VDD 50
-- -- -- -- 200
VDD VDD VDD VDD VDD 400 1.0
V V V V
VDD = 4.5V to 5.5V otherwise
(Note1)
A A A A A
VDD = 5.0V, VPIN = VSS VSS VPIN VDD, pin at hiimpedance Vss VPIN VDD, pin at hiimpedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration IOL=8.5 mA, VDD=4.5V, -40 to +85C IOL=7.0 mA, VDD=4.5V, +125C IOL=1.6 mA, VDD=4.5V, -40 to +85C IOL=1.2 mA, VDD=4.5V, +125C
I/O ports (Except PORTA) D060 D061 D063 VOL D080 PORTA RA4/T0CKI OSC1, MCLR Output Low Voltage I/O ports -- -- D083 OSC2/CLKOUT (RC only) VOH D090 * Output High Voltage
(3)
-- -- --
-- -- --
0.5 1.0 5.0
-- -- -- --
0.6 0.6 0.6 0.6
V V V V
-- --
I/O ports (Except RA4)
VDD-0.7
--
--
V
IOH=-3.0 mA, VDD=4.5V, -40 to +85C
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin.
DS40143D-page 78
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
10.2 DC Characteristics: PIC16C55X (Commercial, Industrial, Extended) PIC16LC55X(Commercial, Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for automotive Operating voltage VDD range as described in DC spec Table 10-1
Characteristic Output High Voltage(3) I/O ports (Except RA4) VDD-0.7 VDD-0.7 D092 OSC2/CLKOUT (RC only) * D100 VOD Open-Drain High Voltage Capacitive Loading Specs on Output Pins COSC2 OSC2 pin 15 pF In XT, HS and LP modes when external clock used to drive OSC1. VDD-0.7 VDD-0.7 -- -- -- -- -- -- -- -- 10* V V V V V IOH=-3.0 mA, VDD=4.5V, -40 to +85C IOH=-2.5 mA, VDD=4.5V, +125C IOH=-1.3 mA, VDD=4.5V, -40 to +85C IOH=-1.0 mA, VDD=4.5V, +125C RA4 pin Min Typ Max Unit Conditions
DC Characteristics
Param. No.
Sym VOH
D090
D101 *
CIO
All I/O pins/OSC2 (in RC mode)
50
pF
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 79
PIC16C55X
10.3 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase subscripts (pp) and their meanings: pp ck CLKOUT io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
os t0
OSC1 T0CKI
P R V Z
Period Rise Valid Hi-impedance
FIGURE 10-5:
LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2 for OSC2 output
DS40143D-page 80
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
10.4 Timing Diagrams and Specifications
EXTERNAL CLOCK TIMING
Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
FIGURE 10-6:
TABLE 10-1:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency(1) Min DC DC DC Oscillator Frequency(1) DC 0.1 1 DC Typ -- -- -- -- -- -- - -- -- -- -- -- -- -- Fos/4 -- -- -- -- -- -- Max 4 20 200 4 4 20 200 -- -- -- -- 10,000 1,000 -- DC -- -- -- -- -- -- Units MHz MHz kHz MHz MHz MHz kHz ns ns Conditions XT and RC osc mode, VDD=5.0V HS osc mode LP osc mode RC osc mode, VDD=5.0V XT osc mode HS osc mode LP osc mode XT and RC osc mode HS osc mode LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode TCY=FOS/4 XT osc mode LP osc mode HS osc mode XT osc mode LP osc mode HS osc mode
Sym Fos
1
Tosc
External CLKIN Period(1)
250 50 5
s
ns ns ns
Oscillator Period(1)
250 250 50 5
s s
ns
2 3*
Tcy TosL, TosH
Instruction Cycle Time
(1)
1.0 100* 2* 20* 25* 50* 15*
External Clock in (OSC1) High or Low Time
s
ns ns ns ns
4*
TosR, External Clock in (OSC1) Rise or TosF Fall Time
*
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0 V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 81
PIC16C55X
FIGURE 10-7: CLKOUT AND I/O TIMING
Q4 OSC1 10 22 23 13 14 I/O Pin (input) 17 I/O Pin (output) old value 15 new value 19 18 12 16 11 Q1 Q2 Q3
CLKOUT
20, 21 Note 1: All tests must be done with specified capacitance loads (Figure 10-5) 50 pF on I/O pins and CLKOUT.
DS40143D-page 82
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
TABLE 10-2:
Parameter # 10* 11* 12* 13* 14* 15* 16* 17* 18* 19* 20* 21* 22* 23* *
CLKOUT AND I/O TIMING REQUIREMENTS
Sym TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp Characteristic OSC1 to CLKOUT
(1)
Min -- -- -- -- -- -- -- -- --
(1)
Typ 75 -- 75 -- 35 -- 35 -- -- -- -- -- 50 -- -- -- 10 -- 10 -- -- -- --
Max 200 400 200 400 100 200 100 200 20 -- -- -- 150 300 -- -- -- 40 80 40 80 -- -- --
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OSC1 to CLKOUT (1) CLKOUT rise time(1) CLKOUT fall time(1) CLKOUT to Port out valid(1) Port in valid before CLKOUT Port in hold after CLKOUT (1) OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time RB0/INT pin high or low time RB<7:4> change interrupt high or low time
Tosc +200 ns Tosc +400 ns 0 -- -- 100 200 0 -- -- -- -- 25 40 Tcy
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 83
PIC16C55X
FIGURE 10-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Timeout OSC Timeout Internal RESET Watchdog Timer RESET 34 I/O Pins 32 30
31 34
TABLE 10-3:
Param No. 30 31 32 33 34 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS
Characteristic MCLR Pulse Width (low) Watchdog Timer Timeout Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O hi-impedance from MCLR low Min 2000 7* -- 28* Typ -- 18 1024 TOSC 72 -- Max -- 33* -- 132* 2.0* Units ns ms -- ms s Conditions -40 to +85C VDD = 5.0V, -40 to +85C TOSC = OSC1 period VDD = 5.0V, -40 to +85C
Sym TmcL Twdt Tost Tpwrt TIOZ
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS40143D-page 84
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
FIGURE 10-9:
RA4/T0CKI
TIMER0 CLOCK TIMING
40 42
41
TMR0
TABLE 10-4:
Param No. 40 Sym Tt0H
TIMER0 CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width No Prescaler With Prescaler Min 0.5 TCY + 20* 10* 0.5 TCY + 20* 10* TCY + 40* N Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 2, 4, ..., 256) Conditions
41
Tt0L
T0CKI Low Pulse Width
No Prescaler With Prescaler
42 *
Tt0P
T0CKI Period
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 10-10:
LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2 for OSC2 output
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 85
PIC16C55X
NOTES:
DS40143D-page 86
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
11.0
11.1
PACKAGING INFORMATION
Package Marking Information
18-Lead PDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16C558 -04I / P456 9823 CBA
28-Lead PDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16C557 -04I / P456 9823 CBA
20-Lead SSOP
XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example
PIC16C558 -04/SS218 0020 CBP
28-Lead SSOP
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
PIC16C557 -04I / SS123 0025 CBA
Legend:
XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 87
PIC16C55X
Package Marking Information (Cont'd)
18-Lead SOIC (.300")
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
PIC16C558 -04I / S0218 9818 CDK
28-Lead SOIC (.300")
XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16C557 -04I / P456 9823 CBA
18-Lead CERDIP Windowed
XXXXXXXX XXXXXXXX YYWWNNN
Example
16C558 /JW 9801 CBA
28-Lead CERDIP Windowed
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
Example
16C557 /JW 9801 CBA
DS40143D-page 88
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
18-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D
2 n 1
E
A2 A L A1 B1
c
eB Units Dimension Limits n p
B
p
MIN
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width .240 .250 .260 E1 Overall Length D .890 .898 .905 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 eB Overall Row Spacing .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007
INCHES* NOM 18 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 22.99 3.43 0.38 1.78 0.56 10.92 15 15
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 89
PIC16C55X
28-Lead Skinny Plastic Dual In-line (SP) - 300 mil (PDIP)
E1
D
2 n 1
E
A2 A c L A1 B1 B p
eB
Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN
INCHES* NOM 28 .100 .140 .125 .015 .300 .275 1.345 .125 .008 .040 .016 .320 5 5 .310 .285 1.365 .130 .012 .053 .019 .350 10 10 .325 .295 1.385 .135 .015 .065 .022 .430 15 15 .150 .130 .160 .135 MAX MIN
MILLIMETERS NOM 28 2.54 3.56 3.18 0.38 7.62 6.99 34.16 3.18 0.20 1.02 0.41 8.13 5 5 7.87 7.24 34.67 3.30 0.29 1.33 0.48 8.89 10 10 8.26 7.49 35.18 3.43 0.38 1.65 0.56 10.92 15 15 3.81 3.30 4.06 3.43 MAX
* Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095
Drawing No. C04-070
DS40143D-page 90
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
18-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E p E1
D
2 B n 1
h
45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0
INCHES* NOM 18 .050 .099 .091 .008 .407 .295 .454 .020 .033 4 .011 .017 12 12
MAX
MIN
.104 .094 .012 .420 .299 .462 .029 .050 8 .012 .020 15 15
MILLIMETERS NOM 18 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 11.33 11.53 0.25 0.50 0.41 0.84 0 4 0.23 0.27 0.36 0.42 0 12 0 12
MAX
2.64 2.39 0.30 10.67 7.59 11.73 0.74 1.27 8 0.30 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 91
PIC16C55X
28-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E E1 p
D
B n h 45 c A Units Dimension Limits n p A A2 A1 E E1 D h L c B L A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 A2 2 1
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0
.104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15
2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052
DS40143D-page 92
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
18-Lead Ceramic Dual In-line with Window (JW) - 300 mil (CERDIP)
E1
W2
D
2 n W1 E 1
A c eB A1 B1 B Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB W1 W2 INCHES* NOM 18 .100 .183 .160 .023 .313 .290 .900 .138 .010 .055 .019 .385 .140 .200 p
A2
L
MIN
MAX
MIN
Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Window Width Window Length * Controlling Parameter Significant Characteristic JEDEC Equivalent: MO-036 Drawing No. C04-010
.170 .155 .015 .300 .285 .880 .125 .008 .050 .016 .345 .130 .190
.195 .165 .030 .325 .295 .920 .150 .012 .060 .021 .425 .150 .210
MILLIMETERS NOM 18 2.54 4.32 4.64 3.94 4.06 0.38 0.57 7.62 7.94 7.24 7.37 22.35 22.86 3.18 3.49 0.20 0.25 1.27 1.40 0.41 0.47 8.76 9.78 3.30 3.56 4.83 5.08
MAX
4.95 4.19 0.76 8.26 7.49 23.37 3.81 0.30 1.52 0.53 10.80 3.81 5.33
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 93
PIC16C55X
28-Lead Ceramic Dual In-line with Window (JW) - 300 mil (CERDIP)
E1
W2
D
2 n W1 E A c A1 Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB W1 W2 INCHES* NOM 28 .100 .183 .160 .023 .313 .290 1.458 .140 .010 .058 .019 .385 .140 .300 B1 B MIN MAX MIN A2 L eB 1
p MILLIMETERS NOM 28 2.54 4.32 4.64 3.94 4.06 0.38 0.57 7.62 7.94 7.24 7.37 36.32 37.02 3.43 3.56 0.20 0.25 1.27 1.46 0.41 0.47 8.76 9.78 3.30 3.56 7.37 7.62
MAX
Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Window Width Window Length * Controlling Parameter Significant Characteristic JEDEC Equivalent: MO-058 Drawing No. C04-080
.170 .155 .015 .300 .285 1.430 .135 .008 .050 .016 .345 .130 .290
.195 .165 .030 .325 .295 1.485 .145 .012 .065 .021 .425 .150 .310
4.95 4.19 0.76 8.26 7.49 37.72 3.68 0.30 1.65 0.53 10.80 3.81 7.87
DS40143D-page 94
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
E E1 p
D
B n
2 1
c A
A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
.068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0
INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .013 5 5
MAX
MIN
.078 .072 .010 .322 .212 .289 .037 .010 8 .015 10 10
MILLIMETERS NOM 20 0.65 1.73 1.85 1.63 1.73 0.05 0.15 7.59 7.85 5.11 5.25 7.06 7.20 0.56 0.75 0.10 0.18 0.00 101.60 0.25 0.32 0 5 0 5
MAX
1.98 1.83 0.25 8.18 5.38 7.34 0.94 0.25 203.20 0.38 10 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 95
PIC16C55X
28-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
E E1 p
D
B n 2 1
A c A2
L
A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
.068 .064 .002 .299 .201 .396 .022 .004 0 .010 0 0
INCHES NOM 28 .026 .073 .068 .006 .309 .207 .402 .030 .007 4 .013 5 5
MAX
MIN
.078 .072 .010 .319 .212 .407 .037 .010 8 .015 10 10
MILLIMETERS* NOM MAX 28 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.10 5.11 5.25 5.38 10.06 10.20 10.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0.38 0 5 10 0 5 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073
DS40143D-page 96
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
APPENDIX A: ENHANCEMENTS APPENDIX B: COMPATIBILITY
The following are the list of enhancements over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14 bits. This allows larger page sizes both in program memory (4K now as opposed to 512 before) and register file (up to 128 bytes now versus 32 bytes before). A PC high latch register (PCLATH) is added to handle program memory paging. PA2, PA1, PA0 bits are removed from STATUS register. Data memory paging is slightly redefined. STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. RESET vector is changed to 0000h. RESET of all registers is revised. Three different RESET (and wake-up) types are recognized. Registers are reset differently. Wake-up from SLEEP through interrupt is added. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt-onchange feature. Timer0 clock input, T0CKI pin is also a port pin (RA4/T0CKI) and has a TRIS bit. FSR is made a full 8-bit register. "In-circuit programming" is made possible. The user can program PIC16C55X devices using only five pins: VDD, VSS, VPP, RB6 (clock) and RB7 (data in/out). PCON status register is added with a Power-on Reset (POR) status bit. Code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. PORTA inputs are now Schmitt Trigger inputs. To convert code written for PIC16C5X to PIC16C55X, the user should take the following steps: 1. 2. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change RESET vector to 0000h.
2.
3. 4. 5.
3. 4.
5. 6. 7. 8. 9.
10. 11.
12. 13. 14. 15.
16. 17.
18.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 97
PIC16C55X
NOTES:
DS40143D-page 98
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
INDEX
A
ADDLW Instruction ............................................................. 55 ADDWF Instruction ............................................................. 55 ANDLW Instruction ............................................................. 55 ANDWF Instruction ............................................................. 55 Architectural Overview .......................................................... 9 Assembler MPASM Assembler ..................................................... 67 CLRW ......................................................................... 58 CLRWDT .................................................................... 58 COMF ......................................................................... 58 DECF.......................................................................... 58 DECFSZ ..................................................................... 59 GOTO ......................................................................... 59 INCF ........................................................................... 59 INCFSZ....................................................................... 60 IORLW ........................................................................ 60 IORWF........................................................................ 60 MOVF ......................................................................... 61 MOVLW ...................................................................... 60 MOVWF...................................................................... 61 NOP............................................................................ 61 OPTION...................................................................... 61 RETFIE....................................................................... 62 RETLW ....................................................................... 62 RETURN..................................................................... 62 RLF............................................................................. 62 RRF ............................................................................ 63 SLEEP ........................................................................ 63 SUBLW ....................................................................... 63 SUBWF....................................................................... 64 SWAPF ....................................................................... 64 TRIS ........................................................................... 64 XORLW....................................................................... 65 XORWF ...................................................................... 65 Instruction Set Summary .................................................... 53 INT Interrupt ....................................................................... 42 INTCON Register................................................................ 19 Interrupts ............................................................................ 41 IORLW Instruction .............................................................. 60 IORWF Instruction .............................................................. 60
B
BCF Instruction ................................................................... 56 Block Diagram TIMER0....................................................................... 47 TMR0/WDT PRESCALER .......................................... 50 BSF Instruction ................................................................... 56 BTFSC Instruction............................................................... 56 BTFSS Instruction ............................................................... 57
C
CALL Instruction ................................................................. 57 Clocking Scheme/Instruction Cycle .................................... 12 CLRF Instruction ................................................................. 57 CLRW Instruction ................................................................ 58 CLRWDT Instruction ........................................................... 58 Code Protection .................................................................. 46 COMF Instruction ................................................................ 58 Configuration Bits................................................................ 31
D
Data Memory Organization ................................................. 13 DECF Instruction................................................................. 58 DECFSZ Instruction ............................................................ 59 Development Support ......................................................... 67
K
KEELOQ Evaluation and Programming Tools...................... 70
E
Errata .................................................................................... 3 External Crystal Oscillator Circuit ....................................... 34
M
MOVF Instruction................................................................ 61 MOVLW Instruction............................................................. 60 MOVWF Instruction ............................................................ 61 MPLAB C17 and MPLAB C18 C Compilers ....................... 67 MPLAB ICD In-Circuit Debugger ........................................ 69 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ................................................................. 68 MPLAB Integrated Development Environment Software.... 67 MPLINK Object Linker/MPLIB Object Librarian .................. 68
G
General purpose Register File ............................................ 13 GOTO Instruction ................................................................ 59
I
I/O Ports .............................................................................. 23 I/O Programming Considerations........................................ 28 ICEPIC In-Circuit Emulator ................................................. 68 ID Locations ........................................................................ 46 INCF Instruction .................................................................. 59 INCFSZ Instruction ............................................................. 60 In-Circuit Serial Programming ............................................. 46 Indirect Addressing, INDF and FSR Registers ................... 21 Instruction Flow/Pipelining .................................................. 12 Instruction Set ADDLW ....................................................................... 55 ADDWF....................................................................... 55 ANDLW ....................................................................... 55 ANDWF....................................................................... 55 BCF............................................................................. 56 BSF ............................................................................. 56 BTFSC ........................................................................ 56 BTFSS ........................................................................ 57 CALL ........................................................................... 57 CLRF........................................................................... 57
N
NOP Instruction .................................................................. 61
O
One-Time-Programmable (OTP) Devices ............................ 7 OPTION Instruction ............................................................ 61 OPTION Register................................................................ 18 Oscillator Configurations..................................................... 33 Oscillator Start-up Timer (OST) .......................................... 36
P
PCL and PCLATH............................................................... 21 PCON Register ................................................................... 20 PICDEM 1 Low Cost PICmicro Demonstration Board ........ 69 PICDEM 17 Demonstration Board...................................... 70 PICDEM 2 Low Cost PIC16CXX Demonstration Board ..... 69 PICDEM 3 Low Cost PIC16CXXX Demonstration Board ... 70
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 99
PIC16C55X
PICSTART Plus Entry Level Development Programmer .... 69 Port RB Interrupt ................................................................. 42 PORTA................................................................................ 23 PORTB.......................................................................... 25, 27 Power Control/Status Register (PCON) .............................. 37 Power-Down Mode (SLEEP)............................................... 45 Power-On Reset (POR) ...................................................... 36 Power-up Timer (PWRT)..................................................... 36 Prescaler ............................................................................. 49 PRO MATE II Universal Device Programmer ..................... 69 Program Memory Organization ........................................... 13
Q
Quick-Turnaround-Production (QTP) Devices ...................... 7
R
RC Oscillator ....................................................................... 34 Reset................................................................................... 35 RETFIE Instruction.............................................................. 62 RETLW Instruction .............................................................. 62 RETURN Instruction............................................................ 62 RLF Instruction.................................................................... 62 RRF Instruction ................................................................... 63
S
Serialized Quick-Turnaround-Production (SQTP) Devices ... 7 SLEEP Instruction ............................................................... 63 Software Simulator (MPLAB SIM)....................................... 68 Special Features of the CPU............................................... 31 Special Function Registers ................................................. 15 Stack ................................................................................... 21 Status Register.................................................................... 17 SUBLW Instruction.............................................................. 63 SUBWF Instruction.............................................................. 64 SWAPF Instruction.............................................................. 64
T
Timer0 TIMER0 ....................................................................... 47 TIMER0 (TMR0) Interrupt ........................................... 47 TIMER0 (TMR0) Module ............................................. 47 TMR0 with External Clock........................................... 49 Timer1 Switching Prescaler Assignment................................. 51 Timing Diagrams and Specifications................................... 81 TMR0 Interrupt .................................................................... 42 TRIS Instruction .................................................................. 64 TRISA.................................................................................. 23 TRISB............................................................................ 25, 27
W
Watchdog Timer (WDT) ...................................................... 43 WWW, On-Line Support........................................................ 3
X
XORLW Instruction ............................................................. 65 XORWF Instruction ............................................................. 65
DS40143D-page 100
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site.
SYSTEMS INFORMATION AND UPGRADE HOT LINE
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet Web Site
The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
092002
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 101
PIC16C55X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C55X Questions: 1. What are the best features of this document? Y N Literature Number: DS40143D FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS40143D-page 102
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a)
PIC17C756-16L Commercial Temp., PLCC package, 16 MHz, normal VDD limits PIC17LC756-08/PT Commercial Temp., TQFP package, 8MHz, extended VDD limits PIC17C756-33I/PT Industrial Temp., TQFP package, 33 MHz, normal VDD limits
b)
Device PIC17C756: Standard VDD range PIC17C756T: (Tape and Reel) PIC17LC756: Extended VDD range
c)
Temperature Range
I
= =
0C to +70C -40C to +85C
Package
CL PT L
= = =
Windowed LCC TQFP PLCC
Pattern
QTP, SQTP, ROM Code (factory specified) or Special Requirements. Blank for OTP and Windowed devices.
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 103
PIC16C55X
NOTES:
DS40143D-page 104
Preliminary
2002 Microchip Technology Inc.
PIC16C55X
NOTES:
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 105
WORLDWIDE SALES AND SERVICE
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08/01/02
DS40143D-page 106
Preliminary
2002 Microchip Technology Inc.

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