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Preliminary Technical Data
FEATURES
Filterless Class-D amplifier with built-in output stage 2 W into 4 and 1.2 W into 8 at 5.0 V supply with less than 10% THD 85% efficiency at 5.0 V, 2W into 4 speaker Better than 95dB SNR (signal-to-noise ratio) Available in 16-lead 3 mm x 3 mm LFCSP Single-supply operation from 2.2 V to 5.0 V 20 nA ultralow shutdown current Short-circuit and thermal protection Pop-and-click suppression Built-in resistors reduce board component count Default fixed 18dB gain and user-adjustable
2 W Filterless Class-D Stereo Audio Amplifier SSM2304
The SSM2304 features a high efficiency, low noise modulation scheme. It operates with 85% efficiency at 2 W into 4 from a 5.0 V supply and has a signal-to-noise ratio (SNR) that is better than 95 dB. PDM modulation is used to provide lower EMIradiated emissions compared with other Class-D architectures. The SSM2304 has a micropower shutdown mode with a typical shutdown current of 20 nA. Shutdown is enabled by applying a logic low to the SD pin. The architecture of the device allows it to achieve a very low level of pop and click. This minimizes voltage glitches at the output during turn-on and turn-off, thus reducing audible noise on activation and deactivation. The fully differential input of the SSM2304 provides excellent rejection of common-mode noise on the input. Input coupling capacitors can be omitted if the dc input common-mode voltage is approximately VDD/2. The SSM2304 also has excellent rejection of power supply noise, including noise caused by GSM transmission bursts and RF rectification. PSRR is typically 70 dB at 217 Hz. The gain can be set to 6 dB or 18 dB utilizing the gain control select pin connected respectively to ground or VDD. Gain can also be adjusted externally by using an external resistor. The SSM2304 is specified over the commercial temperature range (-40C to +85C). It has built-in thermal shutdown and output short-circuit protection. It is available in a 16-lead, 3 mm x 3 mm lead-frame chip scale package (LFCSP).
APPLICATIONS
Notebooks and PCs Mobile phones MP3 players Portable gaming Portable electronics Educational toys
GENERAL DESCRIPTION
The SSM2304 is a fully integrated, high efficiency, Class-D stereo audio amplifier. It is designed to maximize performance for portable applications. The application circuit requires a minimum of external components and operates from a single 2.2 V to 5.0 V supply. It is capable of delivering 2 W of continuous output power with less than 10% THD + N driving a 4 load from a 5.0 V supply.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
SSM2304
FUNCTIONAL BLOCK DIAGRAM
10F 0.1F
Preliminary Technical Data
VBATT 2.5V TO 5.0V VDD OUTR+ GAIN CONTROL MODULATOR FET DRIVER OUTR-
SSM2304
0.01F1 RIGHT IN+ RIGHT IN- 0.01F1 SHUTDOWN GAIN SD GAIN BIAS INR+ INR-
VDD
INTERNAL OSCILLATOR
0.01F1 LEFT IN+ LEFT IN- 0.01F1
INL+ INL- GAIN CONTROL MODULATOR GND FET DRIVER GND
OUTL+ OUTL-
1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
Figure 1.
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06162-001
Preliminary Technical Data TABLE OF CONTENTS
Features...............................................................................................1 Applications .......................................................................................1 General Description..........................................................................1 Functional Block Diagram ...............................................................2 Revision History................................................................................3 Specifications .....................................................................................4 Absolute Maximum Ratings ............................................................5 Thermal Resistance.......................................................................5 ESD Caution ..................................................................................5 Pin Configuration and Function Descriptions .............................6 Typical Performance Characteristics ..............................................7 Typical Application Circuits ..........................................................11 Application Notes............................................................................12 Overview ......................................................................................12 Gain Selection..............................................................................12
SSM2304
Pop-and-Click Suppression .......................................................12 EMI Noise ....................................................................................12 Layout ...........................................................................................13 Input Capacitor Selection ..........................................................13 Proper Power Supply Decoupling.............................................13 Evaluation Board Information ......................................................14 Introduction.................................................................................14 Operation .....................................................................................14 SSM2304 Application Board Schematic ..................................15 SSM2304 Stereo Class-D Amplifier Evaluation Module Component List...........................................................................16 SSM2304 Application Board Layout ........................................17 Outline Dimensions........................................................................18 Ordering Guide ...........................................................................18
REVISION HISTORY
7/06--Revision 0: Initial Version
Rev. PrD | Page 3 of 19
SSM2304 SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 , Gain=6dB, unless otherwise noted Table 1.
Parameter DEVICE CHARACTERISTICS Output Power Symbol PO Conditions
Preliminary Technical Data
Min
Typ
Max
Unit W W W W W W W W W W W W % % % % V dB dB MHz mV V dB dB mA mA mA nA dB dB K K V V ms s K V dB
Efficiency Total Harmonic Distortion + Noise Input Common-Mode Voltage Range Common-Mode Rejection Ratio Channel Separation Average Switching Frequency Differential Output Offset Voltage POWER SUPPLY Supply Voltage Range Power Supply Rejection Ratio
THD + N VCM CMRRGSM XTALK fSW VOOS VDD PSRR PSRRGSM ISY
RL = 4 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 8 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 4 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 8 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V POUT = 2.5 W, 4 , VDD = 5.0 V POUT = 1.4 W, 8 , VDD = 5.0 V PO = 2 W into 4 each channel, f = 1 kHz, VDD = 5.0 V PO = 1 W into 8 each channel, f = 1 kHz, VDD = 3.6 V 1.0 VCM = 2.5 V 100 mV at 217 Hz PO = 100 mW , f = 1 kHz G = 6 dB Guaranteed from PSRR test VDD = 2.5 V to 5.0 V , 50 Hz, input floating/ground VRIPPLE = 100 mV rms at 217 Hz, inputs ac GND, CIN = 0.01 F, input referred VIN = 0 V, no load, VDD = 5.0 V VIN = 0 V, no load, VDD = 3.6 V VIN = 0 V, no load, VDD = 2.5 V SD = GND GAIN1 = 0 V GAIN2 = VDD SD = VDD, Av0 and Av1 modes SD = GND ISY 1 mA ISY 300 nA SD rising edge from GND to VDD SD falling edge from VDD to GND SD = GND VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are ac grounded, AV = 6 dB, A weighting POUT = 2.5 W, RL = 4 2.5 70
1.4 TBD 0.615 TBD 0.275 3.3 1.53 TBD 0.77 TBD 0.35 87 85 0.2 0.25 VDD - 1 60 78 1.8 2.0 5.0 85 70 7.0 6.5 5.2 20 6 12 37.5 210 1.2 0.5 30 5 >100 35 98
Supply Current
Shutdown Current GAIN CONTROL Closed-Loop Gain Differential Input Impedance SHUTDOWN CONTROL Input Voltage High Input Voltage Low Turn-On Time Turn-Off Time Output Impedance NOISE PERFORMANCE Output Voltage Noise Signal-to-Noise Ratio
ISD Av0 Av1 ZIN
VIH VIL tWU tSD ZOUT en SNR
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25C, unless otherwise noted. Table 2.
Parameter Supply Voltage Input Voltage Common-Mode Input Voltage ESD Susceptibility Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature Range (Soldering, 60 sec) Rating 6V VDD VDD 4 kV -65C to +150C -40C to +85C -65C to +165C 300C
SSM2304
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type 16-lead, 3 mm x 3 mm LFCSP JA 44 JC 31.5 Unit C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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SSM2304 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16 GND 15 VDD
PIN 1 INDICATOR
Preliminary Technical Data
14 VDD 13 GND
OUTL+ 1 OUTL- 2 SD 3 INL+ 4
12 OUTR+ 11 OUTR- 10 GAIN 9 INR+
SSM2304
TOP VIEW (Not to Scale)
INR- 8
INL- 5
NC 6
NC 7
NC = NO CONNECT
Figure 2. SSM2304 LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic OUTL+ OUTL- SD INL+ INL- NC NC INR- INR+ GAIN OUTR- OUTR+ GND VDD VDD GND Description Inverting Output for Left Channel. Noninverting Output for Left Channel. Shutdown Input. Active low digital input. Noninverting Input for Left Channel. Inverting Input for Left Channel. No Connect. No Connect. Inverting Input for Right Channel. Noninverting Input for Right Channel. Gain Selection. Digital input. Noninverting Output for Right Channel. Inverting Output for Right Channel. Ground for Output Amplifiers. Power Supply for Output Amplifiers. Power Supply for Output Amplifiers. Ground for Output Amplifiers.
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06162-002
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
100 RL = 8, 33H GAIN = 6dB VDD = 2.5V 10
SSM2304
THD + N (%)
1 VDD = 3.6V 0.1
VDD = 5V 0.01 0.1 10
06162-004 06162-006 06162-005
0.000001 0.0001 0.0000001 0.00001 0.001
0.01
1
OUTPUT POWER (W)
Figure 3. THD + N vs. Output Power into 4 , AV = 12 dB
Figure 6. THD + N vs. Output Power into 8 , AV = 6 dB
100
RL = 8, 33H GAIN = 12dB VDD = 2.5V
100
VDD = 5V RL = 8, 33H
10
10 1
THD + N (%)
1 VDD = 3.6V 0.1
THD + N (%)
0.1
1W
0.01
0.5W
0.25W
0.001 VDD = 5V 0.0001 0.001 0.01 0.1 1 10
06162-003
0.01 0.000001 0.00001
0.0001 10
100
1k FREQUENCY (Hz)
10k
100k
OUTPUT POWER (W)
Figure 4. THD + N vs. Output Power into 8 , AV = 12 dB
Figure 7. THD + N vs. Frequency, VDD = 5.0 V
100
VDD = 3.6V RL = 8, 33H
10
1
THD + N (%)
0.1
500mW
0.01
250mW
125mW
0.001
0.0001 10
100
1k FREQUENCY (Hz)
10k
100k
Figure 5. THD + N vs. Output Power into 4 , AV = 6 dB
Rev. PrD | Page 7 of 19
Figure 8. THD + N vs. Frequency, VDD = 3.6 V
SSM2304
100 VDD = 2.5V RL = 8, 33H 1.6 1.4 1.2 1 250mW
Preliminary Technical Data
f = 1kHz
GAIN = 2 RL = 8, 33H
10
OUTPUT POWER (W)
THD + N (%)
1.0 10% 0.8 1% 0.6 0.4
0.1 125mW 75mW
0.01
0.001
0.2 0 2.5
06162-007
100
1k FREQUENCY (Hz)
10k
100k
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
Figure 9. THD + N vs. Frequency, VDD = 2.5 V
Figure 12. Maximum Output Power vs. Supply Voltage
9 8 7
SUPPLY CURRENT (mA)
6 5 4 3 2 1
06162-008
0 2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
Figure 10. Supply Current vs. Supply Voltage, No Load Figure 13. Efficiency vs. Output Power into 4
12 100 10 90 80 8 70 VDD = 2.5V VDD = 3.6V RL = 8, 33H
SHUTDOWN CURRENT (A)
VDD = 5V
EFFICIENCY (%)
VDD = 5V 6 VDD = 2.5V VDD = 3.6V 2
60 50 40 30 20 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 OUTPUT POWER (W)
06162-011
4
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
06162-009
0
0
SHUTDOWN VOLTAGE (V)
Figure 11. Supply Current vs. Shutdown Voltage
Figure 14. Efficiency vs. Output Power into 8
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06162-010
0.0001 10
Preliminary Technical Data
1.0 0.9 0.8 VDD = 3.6V RL = 8, 33H
SSM2304
POWER DISSIPATION (W)
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
06162-012
0
OUTPUT POWER (W)
Figure 15. Power Dissipation vs. Output Power at VDD = 3.6 V
Figure 18. Output Power vs. Load Resistance, THD = 1%
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
VDD = 5V RL = 8, 33H
400 RL = 8, 33H 350 VDD = 5V 300 250 200 VDD = 2.5V 150 100 50 0 VDD = 3.6V
POWER DISSIPATION (W)
06162-013
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 OUTPUT POWER (W)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
OUTPUT POWER (W)
Figure 16. Power Dissipation vs. Output Power at VDD = 5.0 V
Figure 19. Output Power vs. Supply Current, One Channel
0 -10 -20 -30
PSRR (dB)
-40 -50 -60 -70 -80 -90 100 1k FREQUENCY (Hz) 10k 100k
06162-015
-100 10
Figure 17. Output Power vs. Load Resistance, THD = 10%
Figure 20. Power Supply Rejection Ratio vs. Frequency
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06162-014
0
SUPPLY CURRENT (mA)
SSM2304
0 -10 -20 -30 -40 -50 -60 -70 -80 10 RL = 8, 33H GAIN = 6dB 7 6 5 4
VOLTAGE
Preliminary Technical Data
OUTPUT
SD INPUT
CMRR (dB)
3 2 1 0 -1
06162-016
100
1k FREQUENCY (Hz)
10k
100k
0
20
40
60
80
100
120
140
160
180
TIME (ms)
Figure 21. Common-Mode Rejection Ratio vs. Frequency
Figure 24. Turn-Off Response
0 -20 -40
CROSSTALK (dB)
VDD = 3.6V VRIPPLE = 1V rms RL = 8, 33H
-60 -80 -100 -120 -140 10
100
1k FREQUENCY (Hz)
10k
100k
Figure 22. Crosstalk vs. Frequency
06162-017
Figure 25. Output Frequency Spectrum
7 6 5 4
VOLTAGE
SD INPUT 3 2 1 0 -1
06162-018
OUTPUT
-2 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 TIME (ms)
Figure 23. Turn-On Response
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06162-019
-2 -20
Preliminary Technical Data TYPICAL APPLICATION CIRCUITS
10F 0.1F VBATT 2.5V TO 5.0V VDD OUTR+ GAIN CONTROL MODULATOR FET DRIVER OUTR-
SSM2304
SSM2304
0.01F1 RIGHT IN+ RIGHT IN- 0.01F1 SHUTDOWN VDD GAIN SD GAIN BIAS INR+ INR-
VDD
INTERNAL OSCILLATOR
0.01F1 LEFT IN+ LEFT IN- 0.01F1
INL+ INL- GAIN CONTROL MODULATOR FET DRIVER
OUTL+ OUTL-
GND
GND
1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
Figure 26. Stereo Differential Input Configuration
10F
0.1F
VBATT 2.5V TO 5.0V VDD OUTR+
SSM2304
0.01F RIGHT IN INR+ INR- 0.01F SHUTDOWN GAIN SD GAIN BIAS GAIN CONTROL
VDD
MODULATOR
FET DRIVER
OUTR-
INTERNAL OSCILLATOR
0.01F LEFT IN
INL+ INL- GAIN CONTROL MODULATOR FET DRIVER
OUTL+ OUTL-
0.01F GND GND
06162-031
Figure 27. Stereo Single-Ended Input Configuration
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06162-030
SSM2304 APPLICATION NOTES
OVERVIEW
The SSM2304 stereo Class-D audio amplifier features a filterless modulation scheme that greatly reduces the external components count, conserving board space and thus reducing systems cost. The SSM2304 does not require an output filter, but instead relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square-wave output. While most Class-D amplifiers use some variation of pulse-width modulation (PWM), the SSM2304 uses a - modulation to determine the switching pattern of the output devices. This provides a number of important benefits. - modulators do not produces a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. - modulation provides the benefits of reducing the amplitude of spectral components at high frequencies; that is, reducing EMI emission that might otherwise be radiated by speakers and long cable traces. The SSM2304 also offers protection circuits for overcurrent and temperature protection.
Preliminary Technical Data
from 30 kHz to 2 GHz. These figures clearly describe the SSM2304 EMI behavior as being well below the FCC regulation values, starting from 100 kHz and passing beyond 1 GHz of frequency. Although the overall EMI noise floor is slightly higher, frequency spurs from the SSM2304 are greatly reduced.
70 60 50
LEVEL (dB(V/m))
= HORIZONTAL = VERTICAL = REGULATION VALUE
40 30 20 10 0 0.1
1
10 FREQUENCY (MHz)
100
GAIN SELECTION
The SSM2304 has a pair of internal resistors which set a 18dB of default gain of the amplifier. It is possible to adjust the SSM2304 gain by using external resistors at the input. To set a gain lower than 18 dB refer to Error! Reference source not found. for differential input configuration and Error! Reference source not found. for single-ended configuration. The external gain configuration is calculated as External Gain Settings = 300k/(37.5k+Rext) The gain pin is not connected internally, therefore its external connection is not required.
70 60 50
LEVEL (dB(V/m))
Figure 28. EMI Emissions from SSM2304
= HORIZONTAL = VERTICAL = REGULATION VALUE
40 30 20 10 0 10
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audio pop in the speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system, therefore as not coming from the system input signal. Such transients can be generated when the amplifier system changes its operating mode. For example, the following can be sources of audible transients: system power-up/ power-down, mute/unmute, input source change, and sample rate change. The SSM2304 has a pop-and-click suppression architecture that reduces this output transients, resulting in noiseless activation and deactivation.
100
1k
10k
FREQUENCY (MHz)
Figure 29. EMI Emissions from SSM2304
The measurements for Figure 28 and Figure 29 were taken with a 1 kHz input signal, producing 0.5 W output power into an 8 load from a 3.6 V supply. Cable length was approximately 5 cm. The EMI was detected using a magnetic probe touching the 2" output trace to the load.
EMI NOISE
The SSM2304 uses a proprietary modulation and spreadspectrum technology to minimize EMI emissions from the device. Figure 28 shows SSM2304 EMI emission starting from 100 kHz to 30 MHz. Figure 29 shows SSM2304 EMI emission
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06162-033
06162-032
Preliminary Technical Data
LAYOUT
As output power continues to increase, care needs to be taken to lay out PCB traces and wires properly between the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Make track widths at least 200 mil for every inch of track length for lowest DCR, and use 1 oz or 2 oz of copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding guidelines helps to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load and supply pins should be as wide as possible to maintain the minimum trace resistances. It is also recommended to use a large-area ground plane for minimum impedances. Good PCB layouts also isolate critical analog paths from sources of high interference. High frequency circuits (analog and digital) should be separated from low frequency ones. Properly designed multilayer printed circuit boards can reduce EMI emission and increase immunity to RF field by a factor of 10 or more compared with double-sided boards. A multilayer board allows a complete layer to be used for ground plane, whereas the ground plane side of a doubleside board is often disrupted with signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be underneath the analog power plane, and, similarly, the digital ground plane should be underneath the digital power plane. There should be no overlap between analog and digital ground planes nor analog and digital power planes.
SSM2304
INPUT CAPACITOR SELECTION
The SSM2304 will not require input coupling capacitors if the input signal is biased from 1.0 V to VDD - 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed (Figure 26), or if using a singleended source (Figure 27). If high-pass filtering is needed at the input, the input capacitor along with the input resistor of the SSM2304 will form a high-pass filter whose corner frequency is determined by the following equation: fC = 1/(2 x RIN x CIN) Input capacitor can have very important effects on the circuit performance. Not using input capacitors degrades the output offset of the amplifier as well as the PSRR performance.
PROPER POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. Although the actual switching frequency can range from 10 kHz to 100 kHz, these spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input needs to be decoupled with a good quality low ESL and low ESR capacitor--usually around 4.7 F. This capacitor bypasses low frequency noises to the ground plane. For high frequency transients noises, use a 0.1 F capacitor as close as possible to the VDD pin of the device. Placing the decoupling capacitor as close as possible to the SSM2304 helps maintain efficiency performance.
Rev. PrD | Page 13 of 19
SSM2304 EVALUATION BOARD INFORMATION
INTRODUCTION
The SSM2304 audio power amplifier is a complete low power, Class-D, stereo audio amplifier capable of delivering 2.8 W/channel into 4 load. In addition to the minimal parts required for the application circuit, measurement filters are provided on the evaluation board so that conventional audio measurements can be made without additional components. This section provides an overview of Analog Devices SSM2304 evaluation board. It includes a brief description of the board as well as a list of the board specifications. Table 5. SSM2304 Evaluation Board Specifications
Parameter Supply Voltage Range, VDD Power Supply Current Rating Continuous Output Power, PO (RL = 4 , f = 1 kHz, 22 kHz BW) Minimum Load Impedance Specification 2.5 V to 5.0 V 1.5 A 2W 4
Preliminary Technical Data
Inputs and Outputs
1. 2. 3. Ensure that the audio source is set to the minimum level. Connect the audio source to Inputs INL and INR. Connect the speakers to Outputs OUTL and OUTR.
External Gain Settings
It is possible to adjust the SSM2304 gain lower than 18 dB using external resistors at the input, refer to Error! Reference source not found.6 and Error! Reference source not found.7 on the product data sheet for proper circuit configuration. For external gain configuration, use the following formula: External Gain Settings = 300k/(37.5k+Rext)
Shutdown Control
The shutdown select header controls the shutdown function of the SSM2304. The shutdown pin on the SSM2304 is active low, meaning that a low voltage (GND) on this pin places the SSM2304 into shutdown mode. 1. 2. Select jumper to 1-2 position. Shutdown pulled to VDD. Select jumper to 2-3 position. Shutdown pulled to GND.
OPERATION
Use the following steps when operating the SSM2304 evaluation board.
Power and Ground
1. Set the power supply voltage between 2.5 V and 5.0 V. When connecting the power supply to the SSM2304 evaluation board, make sure to attach the ground connection to the GND header pin first and then connect the positive supply to the VDD header pin.
Input Configurations
1. 2. For differential input configuration with input capacitors do not place a jumper on JP8, JP9, JP10, and JP11. For differential input configuration without input capacitors place a jumper on JP8, JP9, JP10, and JP11.
Rev. PrD | Page 14 of 19
Preliminary Technical Data
SSM2304 APPLICATION BOARD SCHEMATIC
JP2 POWER JP8 HEADER 2 12 C8 JP1 3 2 1 LEFT IN LIN+ LIN- 0.01F C9 0.01F 4 3 2 21 JP9 HEADER 2 JP10 HEADER 2 12 C10 RIN+ 3 RIN- 2 1 RIGHT IN 0.01F C11 0.01F 21 JP11 HEADER 2 VDD R3 100k GAIN JP12 1 3 5 2 4 6 VDD SD
06162-034
SSM2304
VDD C7 0.1F INL+ C6 0.1F
12
C5 10F L1 FERRITE BEAD L2 FERRITE BEAD
C1 1nF JP3 1 2 C2 1nF
OUT LEFT
SD
OUTL+
OUTL-
INL+
SD
1
5 6 7 8
INL- NC NC
GND VDD VDD
16 15 14 13 VDD
OUTR+
GAIN
INR+
INR-
OUTR- 12
GND
U1 SSM2302
9
10
11
GAIN
L1 FERRITE BEAD L2 FERRITE BEAD
C3 1nF 1 2 C4 1nF OUT RIGHT
HEADER 13C
R4 100k
Figure 30. SSM2304 Application Board Schematic
Rev. PrD | Page 15 of 19
SSM2304
Table 6.
Reference C8, C9, C10, C11 C6, C7 C5 C1, C2, C3, C4 R3, R4 L1, L2, L3, L4 U1 EVAL BOARD Description Capacitors, 0.01 F Capacitor, 0.1 F Capacitor, 10 F Capacitor, 1 nF Resistor, 100 k Ferrite bead IC, SSM2304 PCB evaluation board Footprint 0402 0603 0805 0402 0603 0402 3.0 mm x 3.0 mm Quantity 4 2 1 4 2 4 1 1
Preliminary Technical Data
SSM2304 STEREO CLASS-D AMPLIFIER EVALUATION MODULE COMPONENT LIST
Manufacturer/Part Number Murata Manufacturing Co., Ltd./GRM15 Murata Manufacturing Co., Ltd./GRM18 Murata Manufacturing Co., Ltd./GRM21 Murata Manufacturing Co., Ltd./GRM15 Vishay/CRCW06031003F Murata Manufacturing Co., Ltd./BLM15EG121 SSM2304CSPZ
Rev. PrD | Page 16 of 19
Preliminary Technical Data
SSM2304 APPLICATION BOARD LAYOUT
SSM2304
Figure 31. SSM2304 Application Board Layout
Rev. PrD | Page 17 of 19
06162-035
SSM2304 OUTLINE DIMENSIONS
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 0.90 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 1.50 REF 0.60 MAX 0.50 0.40 0.30
Preliminary Technical Data
PIN 1 INDICATOR
*1.65 1.50 SQ 1.35
13 12
16
EXPOSED PAD
1
9 (BOTTOM VIEW) 4 8 5
0.25 MIN
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 32. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters
ORDERING GUIDE
Model SSM2304CPZ-REEL1 SSM2304CPZ-REEL71
1
Temperature Range -40C to +85C -40C to +85C
Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Package Option CP-16-3 CP-16-3
Branding A1F A1F
Z = Pb-free part.
Rev. PrD | Page 18 of 19
Preliminary Technical Data NOTES
SSM2304
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR06162-0-7/06(PrD)
Rev. PrD | Page 19 of 19

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