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1. Introduction
The development board for the ATA6621/22/24 (ATA6621-EK, ATA6622-EK, ATA6624-EK) is designed to give designers a quick start with the ICs and for prototyping and testing of new LIN designs. The ATA6621, ATA6622 and ATA6624 are system basis chips (SBCs) with fully integrated LIN transceiver according to the LIN specification 2.0, window watchdog with adjustable trigger times and low-drop voltage regulator providing 5V/50 mA (3.3V/50 mA for the ATA6622). The output current of the regulator can be boosted by using an external NPN transistor. The ATA6622 and the ATA6624 are totally pin- and function-compatible, the only difference between these circuits is the regulator's output voltage. The ATA6621 differs in a few more ways--an initial overview of these differences starts with the different pins listed in Table 1-1:
ATA6621/22/24 Development Board Application Note
Table 1-1.
Pin No. 2 6 8 10 16 17
Overview of Pin Differences
ATA6621 PTRIG Not connected Not connected Not connected GND TEMP ATA6622 GND GND GND INH KL_15 GND ATA6624 GND GND GND INH KL_15 GND
Figure 1-1.
ATA6621/22/24 Development Board
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Another difference is unequal watchdog timing (see Section 2.3 on page 4). The combination of the features included in the ATA6621/22/24 makes it possible to develop simple, but powerful and cheap, slave nodes in LIN-bus systems. The ICs are designed to handle the low-speed data communication in vehicles, for example, in convenience electronics. Improved slope control at the LIN driver ensures secure data communication up to 20 Kbaud. Sleep Mode and Silent Mode guarantee a very low current consumption. This document has been developed to give the user an easy start with the development board of the ATA6621/22/24. For more detailed information about the use of these devices themselves, refer to the corresponding datasheets.
1.1
Development Board Features
The development board for the ATA6621/22/24 supports the following features: * All necessary components to put the ATA6621/22/24 in operation are included * Placeholders for some optional components for extended functions included * All pins easily accessible * Easily adaptable watchdog times by replacing a resistor * Possibility to place an external NPN transistor for boosting up the output current of the voltage regulator (jumper J1) * Possibility of selecting between master or slave operation (mounting D3 and R4)
1.2
Quick Start
The development board for the ATA6621/22/24 is shipped with all necessary components and a default jumper setting to start with the development of a LIN slave node immediately. After connecting an external 12V DC power supply between the terminals VB and GND, the circuit is in the Pre-normal mode (Fail Safe mode) and a 5V (3.3V) DC voltage provided by the internal voltage regulator can be measured between VCC and GND. (The Pre-normal mode is called Fail Safe mode in the datasheets of the devices ATA6622 and ATA6624.) Furthermore, the following voltages or states can be measured at the pins WD_OSC, TEMP, INH, RXD and LIN:
Table 1-2.
Mode
ATA6621
VCC 5V 5V WD_OSC 2.5V 2.5V TEMP ~2V ~2V INH RXD 5V 5V LIN Recessive Recessive Transceiver Off On
Pre-normal mode Normal mode
Table 1-3.
Mode
ATA6622
VCC 3.3V 3.3V WD_OSC 1.23V 1.23V TEMP INH On On RXD 3.3V 3.3V LIN Recessive Recessive Transceiver Off On
Fail Safe mode Normal mode
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ATA6621/22/24 Development Board
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ATA6621/22/24 Development Board
Table 1-4.
Mode Fail Safe mode Normal mode
ATA6624
VCC 5V 5V WD_OSC 1.23V 1.23V TEMP INH On On RXD 5V 5V LIN Recessive Recessive Transceiver Off On
As the window watchdog of the ATA6621/22/24 is already active in the Pre-normal mode (Fail Safe mode), a periodic reset signal will be generated at the pin NRES as long as no trigger signal can be received at the watchdog trigger input. Normally the connected microcontroller will be monitored by the watchdog, so it has to generate the required trigger signal as described in Section 2.3 on page 4 and in more detail in the datasheet of the corresponding device. For the quick start it is sufficient to generate a square-wave signal with VPP = VCC and f = 75Hz at pin NTRIG or PTRIG for the ATA6621 or with f = 50Hz at pin NTRIG for the ATA6622 and ATA6624 (this is recommended only for testing purposes). In order to check that the watchdog is triggered in the expected way, the reset pin NRES can be monitored until a continuous high level is available. Please note that the communication is still inactive in Pre-normal mode (Fail Safe mode). In order to communicate via the LIN bus interface you have to switch to normal mode by applying the VCC voltage (5V or 3.3V, as appropriate) at pin EN.
2. Hardware Description
In the following sections only the normal operating conditions will be described. For further information concerning one of the mentioned features, refer to the corresponding datasheet.
2.1
Power Supply (VB and GND)
In order to get the development board running, an external 5.7V to 18V DC power supply is required between the terminals VB and GND. The input circuit is protected against inverse-polarity with the protection diode D1, so that there is normally a difference between the VB and VS level of approximately 0.7V.
2.2
Voltage Regulator (PVCC and VCC)
The internal 5V/3.3V voltage regulator is capable of driving loads with up to 50 mA current consumption so the SBCs are able to supply a microcontroller, sensors and/or other ICs. The voltage regulator is protected against overloads by means of current limitation and overtemperature shutdown. To boost the maximum load current, an external NPN transistor may be used, with its base being connected to the VCC pin and its emitter connected to PVCC. If this is done, the regulated output voltage of 5V or 3.3V is available at pin PVCC. For this reason, the pin PVCC and not the pin VCC is led to the connector available off the board. But in normal operation, the pins PVCC and VCC have to be connected directly. This is done by setting jumper J1.
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2.3
The Window Watchdog (PTRIG, NTRIG and NRES)
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG input (negative edge) within a defined time window. The ATA6621 has an additional PTRIG input, so it is also possible to trigger the watchdog with a positive edge. If no correct trigger signal is received, a reset signal will be generated at the NRES output. During Silent or Sleep Mode the watchdog is switched off to reduce current consumption. The minimum time for the first watchdog pulse is required after the undervoltage reset at the NRES pin disappears and is defined as lead time td. The timing basis of the watchdog is provided by the internal oscillator, whose time period tOSC is adjustable via the external resistor R3 at the pin WD_OSC. For the ATA6621, the voltage at this pin is 2.5V, for the ATA6622 and ATA6624 it is 1.23V (see Table 1-2 on page 2 through Table 1-4 on page 3). Due to these different voltages at the devices, the resulting timings are also different. There is a resistor R3 with a value of 51 k mounted on the development board, which results in the following timing sequence for the ATA6621:
Figure 2-1.
Timing Sequence with R3 = 51 k at the ATA6621
VCC = 5V Undervoltage Reset NRES treset = 10 ms Watchdog Reset tnres = 1.9 ms
td = 49 ms t1 = 10 ms twd t2 = 10.5 ms
t1
t2
NTRIG
PTRIG
ttrigg > 3 s
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ATA6621/22/24 Development Board
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ATA6621/22/24 Development Board
For the ATA6622 and ATA6624 the resistor R3 at pin WD_OSC with the same value of 51 k results in the different timing sequence shown in Figure 2-2: Figure 2-2. Timing Sequence with R3 = 51 k at the ATA6622 and ATA6624
VCC = 3.3V/5V Undervoltage Reset NRES treset = 4 ms Watchdog Reset tnres = 4 ms
td = 150 ms t1 = 20 ms twd t2 = 21 ms
t1
t2
NTRIG
ttrigg > 200 ns
If you want to change the watchdog times mentioned above it is only necessary to change the value of the external resistor R3 (refer to the corresponding datasheet).
2.4
2.4.1
LIN Interface (LIN, TXD and RXD)
Bus Pin (LIN) A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor in compliance with the LIN specification 2.0 is implemented. LIN receiver thresholds are compatible with the LIN protocol specification. At the LIN pin there is a 220-pF capacitor to ground on the board. Additionally, when using the development board for a LIN master application, there is the opportunity to mount the two necessary extra components diode D2 (LL4148) in series with resistor R1 (1k) on the board at their designated placeholders.
2.4.2
Input Pin (TXD) This pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to have the LIN bus low. If TXD is high, the LIN output transistor is turned off and the bus is in the recessive state, pulled up by the internal resistor. If TXD is low, the LIN output transistor is turned on and the bus is in the dominant state. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than tDOM > 20 ms, the LIN bus driver is switched to the recessive state.
2.4.3
Output Pin (RXD) This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD, LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up structure with typ. 5 k to VCC. The output is short-circuit protected.
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2.5
Temp Pin (TEMP) (ATA6621 Only)
Besides the internal temperature monitoring of the voltage regulator, an additional sensor measures the junction temperature and provides a linearized voltage at the TEMP pin. Together with the analog functions of the microcontroller (for example, the analog comparator and/or the analog-to-digital converter), this enables the application to detect overload conditions. Further actions in order to prevent the IC from damage can be implemented.
2.6
Mode and TM Input Pins (MODE and TM)
The TM input is only used for Atmel (R) internal-testing purposes and therefore connected directly to GND. The Mode input is pulled to GND by the 4.7-k resistor R1 and therefore the watchdog is active in the normal operation mode. Especially during the early development phase it can be helpful to have the possibility to deactivate the watchdog in order to debug the application program without disturbing RESETS caused by the watchdog. Therefore the watchdog can be switched off by connecting the MODE pin to VCC externally.
2.7
Reset Output (NRES)
After ramping up the battery voltage or after a wake-up from Sleep mode, the 5V regulator is switched on and the VCC voltage exceeds the undervoltage threshold. The implemented undervoltage delay keeps the NRES output at low level for approximately 10 ms after VCC reaches its nominal value. Then it switches to high and the watchdog waits for the trigger sequence from the microcontroller. The NRES pin switches to low if the watchdog is not triggered correctly (see Section 2.3 on page 4). In the ATA6621 the Reset output is a push-pull state supplied by the VCC voltage. In the ATA6622 and ATA6624, the Reset output is an open drain output implemented with a single MOS transistor which is switched on in case of a VCC undervoltage or if the watchdog is not triggered correctly. In order to pull up the NRES output of the ATA6622/24 an external resistor connected to VCC is necessary. This resistor (R9) is taken into account on the development board. If a reset occurs (NRES is Low), the circuit switches to Pre-normal mode (Fail Safe mode).
2.8
KL_15 Input (KL_15) (ATA6622/24 Only)
This pin is a high voltage input used to wake up the device from Sleep or Silent mode. It is an edge sensitive pin (rising edge). It is usually connected to the ignition in order to generate a local wake-up in the application if the ignition is switched on. To protect the pin against voltage transients, a series resistor R12 and a 100-nF ceramic capacitor C8 have to be used. If this pin is not needed, it must be connected to GND.
2.9
Inhibit Output (INH) (ATA6622/24 Only)
This pin is a high-side switch and it is normally used to switch on an external voltage regulator during Normal mode or Fail Safe mode. In Sleep mode or Silent mode the INH output is switched off. For master node applications it is possible to switch off the external master resistor (R4) by the INH pin.
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ATA6621/22/24 Development Board
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ATA6621/22/24 Development Board
3. Boosting the Voltage Regulator
For some applications there is a need for a higher current than the internal voltage regulator can deliver (50 mA). So it is possible to boost the maximum current by using an external NPN transistor. On the development board there is already a placeholder for this part, into which would fit, for example, the MJD31C in a D-PAK package. In addition to the transistor itself there are two more components to be placed on the development board, the resistor R7 (3.3) and the electrolytic capacitor C4 (2.2 F). The jumper J1 has to be removed in this case. Note that the output voltage is no longer short-circuit protected when boosting the output current with an external NPN transistor. The limiting parameter for the output current is the maximum power dissipation of the external NPN transistor. In the version at this stage the thermal resistance of the MJD31C soldered on the minimum pad size is 80 K/W, meaning the maximum possible output current in the case of VS = 12V is approximately 230 mA at room temperature. It is not recommended to exceed this limit, because the transistor could be damaged as a result of overtemperature. If a higher output current is required, additional cooling of the external transistor has to be ensured (see Figure 3-2, Figure 3-3 and Figure 3-4 on page 8). Figure 3-1. Boosting the Voltage Regulator
Place T1, R7 and C4 and remove jumper J1 when boosting the output current
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Figure 3-2, Figure 3-3 and Figure 3-4 show the maximum output current (Imax) of the voltage regulator as a function of the supply voltage (VS) at different coolings or thermal resistances (RthJA) of the external NPN transistor T1. Figure 3-2. Imax versus VS at RthJA = 80 K/W (No Additional Cooling)
3 50 300 2 50
Imax (mA)
Ta = 25C 200 150 Ta = 85C 10 0 50 Ta = 125C
0
10
12
14
16
18
20
VS (V)
Figure 3-3.
Imax versus VS at RthJA = 50 K/W (Additional Cooling)
600
50 0
400
Imax (mA)
Ta = 25C 300 Ta = 85C 200
10 0 Ta = 125C 10 12 14 16 18 20
0
VS (V)
Figure 3-4.
Imax versus VS at RthJA = 20 K/W (Additional Cooling)
14 0 0 12 0 0 10 0 0
Imax (mA)
Ta = 25C 800 600 Ta = 85C 400 200 Ta = 125C 0 10 12 14 16 18 20
VS (V)
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ATA6621/22/24 Development Board
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ATA6621/22/24 Development Board
Figure 3-5 to Figure 3-10 on page 11 show some typical operating characteristics measured at the ATA6621. The supply voltage VS is approximately a diode forward voltage lower than Vbat (reverse battery protection). The external circuitry is shown in Figure 4-1 on page 12. Figure 3-5. Output Voltage PVCC versus Battery Voltage Vbat at Startup
ATA6621 with External Boosttransistor MJD31C
6
5 IOUT = 0
PVCC (V)
4 IOUT = 20 mA 3 2
1
0 0 2 4 6 8 10 12
Vbat (V)
Figure 3-6.
Output Voltage PVCC versus Battery Voltage Vbat at Different Output Currents
ATA6621 with External Boosttransistor MJD31C
5.0 2 0 IOUT = 0 5.0 15
PVCC (V)
5.0 10 5.0 0 5 IOUT = 20 mA 5.0 0 0 IOUT = 100 mA
4.9 9 5
4.9 9 0 0 10 20 30 40 50
Vbat (V)
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Figure 3-7.
Load- transient Response Ch1: IOUT, Ch2: PVCC
Figure 3-8.
Startup Response Ch1: VS, Ch2: PVCC
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ATA6621/22/24 Development Board
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ATA6621/22/24 Development Board
Figure 3-9.
Switching from Silent to Normal Mode Ch1: NRES, Ch2: PVCC
Figure 3-10. Output Voltage PVCC versus Temperature at Different Load Currents
5,0 5 5,0 4 5,0 3
PVCC (V)
IOUT = 0 5,0 2 IOUT = 20 mA 5,0 1 IOUT = 100 mA 5,0 0 4 ,9 9 4 ,9 8 -4 0 -2 0 0 20 40 60 80 10 0 12 0
Temperature (C)
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4. Schematic and Layout of the Development Board for the ATA6621/22/24
Figure 4-1.
PVCC VBAT D1 LL4148 V1 R8 100/1W
+ C2
Schematic of the Development Board for the ATA6621/22/24
R8b 0 C1 100 nF
VS
R10 10/2W
R10b 0 T1 MJD31C KL_15 (ATA6622/24) C7 1 nF PVCC TEMP GND R12 47 k R4 C8 MODE MODE TM WD_OSC NRES TXD R3 51 k R9 10 k PVCC 100 nF R1 4.7 k 1 k D3 LL4148
GND
D2 BZG04-33
22 F/50V
J1 VCC
+
TEMP
C4 2.2 F
+ C3
C5 100 nF
TEMP
TEMP
VS
20
10 F
VCC
19
R6 10 k
R7 3.3
18
17
16
GND
EN PTRIG NTRIG WAKE 33 k S1 Wake R13 0 R5
PTRIG NTRIG WAKE GND
2 3
KL15 INH
10
EN
1
15 14 13 12 11
GND
GND
5
6
7
GND
8 9
4
ATA6621/ ATA6622/ ATA6624
RXD
NC
LIN
NC
NC
INH (ATA6622/24) LIN R11 C6 220 pF
LIN RXD TXD NRES MODE KL_15 X1 MODE KL_15 ATA6621-EK ATA6622-EK ATA6624-EK Revision 2.0 47 k
Notes:
1. D3 and R4 are only necessary for a master node. 2. R9 and R13 are only needed for ATA6622 and ATA6624. 3. Pin KL_15 and the corresponding external circuitry are only available at the ATA6622/24. 4. Pin INH and the corresponding external circuitry are only available at the ATA6622/24. 5. Pin 17 has to be connected to GND by replacing C7 with a 0 resistor at ATA6622 or ATA6624. 6. ATA6621: Pin 10 has to be connected to GND via R11 = 0. Pin 16 has to be connected to GND by replacing C8 by a 0 resistor.
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ATA6621/22/24 Development Board
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ATA6621/22/24 Development Board
Figure 4-2. ATA6621/22/24 Board Component Placement; Top Side, Top View
Figure 4-3.
ATA6621/22/24 Development Board; Top Side, Top View
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Figure 4-4.
ATA6621/22/24 Development Board; Bottom Side, Top View (as if PCB Were Transparent)
14
ATA6621/22/24 Development Board
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ATA6621/22/24 Development Board
5. The Development Board in a Simple Application
To show just how easy it is to develop a LIN-based application with the development board for the ATA6621/22/24, here is a little example for a complete LIN slave node consisting of the ATA6621 and the microcontroller ATmega88, a flasher controlled via the LIN bus. The LIN interface of the slave is implemented with the ATA6621 and the control of the flasher as well as the protocol handling is done by the ATmega88 microcontroller. In the schematic of this slave node it is obvious that there are almost no other external components needed to fulfill the requirements of this application, other than the development board of the ATA6621/22/24 and the ATmega88.
Figure 5-1.
Simple Application Using the Development Board for the ATA6621/22/24 (Schematic)
PVCC X4 VS
VS
X5
XL1 R1 330 D1 LED LIN R2 330 D2 LED XL2
+
C8 100 F
X6
C6 100 nF
C7 10 F
+
X7 LED1 LED2
Flasher
PB1
R5 1 k
T1 BC817-40
XISP1 PB4 PB5 NRES ISP PD2 PD1 PD0 PVCC PB3 TXD RXD NTRIG LED2 NRES LED1 EN PC6/NRST
PC5
PC4
PC3
26
PVCC VS TEMP EN NTRIG LIN RXD TXD NRES JP2 X1 S1 PVCC C1 100 nF JP1 PD3 PD4 GND (3) VCC (4) GND (5) VCC (6) PB6 PB7
1 2 3
32
31
30
29
28
27
PC2
25 24
PC1 PC0 ADC7 GND (21) AREF ADC6 AVCC PB5 GND (33) PB5 C4 100 nF PVCC C5 100 nF TEMP
U1 ATMEGA88
23 22 21
4 5 6 7 8 9 10 11 12 13 14 15 16 MLF 5 mm x 5 mm 0.5 mm pitch 32 lead
20 19 18 17
Development board ATA6621/6622/6624
PD5
PD6
PD7
PB0
PB1
PB2
PB3 PB3
PB1
PB4 PB4
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For testing purposes two jumpers (JP1 and JP2) have been added to the LIN part of this application in order to have the opportunity to easily change some parameters at the pins NRES and VCC/PVCC. Additionally, the switch S1 has been included to generate a wake pulse. For the microcontroller part of this slave node, only a few blocking capacitors are necessary. XISP1 is the programming interface and D1, D2, R1 and R2 report the internal status of the slave node. Because the flasher runs with 12V DC, the transistor T1 is needed to transfer the 5V from the microcontroller to the 12V level. Furthermore, the flasher produces some glitches, so that there are some capacitors needed in order to block the 12V power supply. Figure 5-2. A Simple Application Using the Development Board for the ATA6621 (Photograph)
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