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| Si 5 0 2 2 - EVB EVALUATION BOARD FOR Si5022 SiPHYTM MULTI-RATE S O N E T / S D H C L O C K A N D D A TA R E C O V E R Y I C Description The Si5022 evaluation board provides a platform for testing and characterizing Silicon Laboratories' Si5022 SiPHYTM multi-rate SONET/SDH clock and data recovery IC. The Si5022 CDR supports OC-48/12/3, STM-16/4/1, Gigabit Ethernet, and 2.7 Gbps FEC rates. All high-speed I/Os are ac coupled to ease interfacing to industry standard test equipment. Features Single 2.5 V power supply Differential I/Os ac coupled Simple jumper configuration Function Block Diagram VDD 49.9 Jitter Analyzer + REFCLK - + CLKOUT - Si5022 ZC = 50 ZC = 50 Scope ZC = 50 ZC = 50 Pattern Analyzer ZC = 50 ZC = 50 Test Points ZC = 50 ZC = 50 Pulse Generator ZC = 50 ZC = 50 348 Pattern Generator ZC = 50 ZC = 50 + DATAIN - + DATAOUT - ZC = 50 ZC = 50 RATESEL0 LOS + + RATESEL1 LOL REFCLK CLKOUT LTR BER_ALM- - DSQLCH RESET/CAL Si5023 CLKDSBL + DATAIN - + DATAOUT - ZC = 50 Jumpers ZC = 50 RATESEL0 LOS LOS_LVL RATESEL1 LOL REXT LTR SLICE_LVL BER_ALM DSQLCH RESET/CAL BER_LVL CLKDSBL SI5022-EVB Rev B 10 k Test Points Rev. 1.0 12/02 Copyright (c) 2002 by Silicon Laboratories SI5022-EVB-10 SI5022-EVB Functional Description The evaluation board simplifies characterization of the Si5022 Clock and Data Recovery (CDR) device by providing access to all of the Si5022 I/Os. Device performance can be evaluated by following the "Test Configuration" section. Specific performance metrics include input sensitivity, jitter tolerance, jitter generation, and jitter transfer. When applied, REFCLK is used to center the frequency of the DSPLLTM so that the device can lock to the data. Ideally, the REFCLK frequency should be 1/128th, 1/32nd, or 1/16th the VCO frequency and must have a frequency accuracy of 100 ppm. Internally, the CDR automatically recognizes the REFCLK frequency within one of these three frequency ranges. Typical REFCLK frequencies are given in Table 1. REFCLK is ac coupled to the SMA jacks located on the top side of the evaluation board. Power Supply The evaluation board requires one 2.5 V supply. Supply filtering is placed on the board to filter typical system noise components; however, initial performance testing should use a linear supply capable of supplying the nominal voltage 5% dc. CAUTION: The evaluation board is designed so that the body of the SMA jacks and GND are shorted. Care must be taken when powering the PCB at potentials other than GND at 0.0 V and VDD at 2.5 V relative to chassis GND. Table 1. Typical REFCLK Frequencies SONET/SDH 19.44 MHz 77.76 MHz 155.52 MHz Gigabit Ethernet 19.53 MHz 78.125 MHz 156.25 MHz SONET/SDH with 15/14 FEC 20.83 MHz 83.31 MHz 166.63 MHz Ratio of VCO to REFCLK 128 32 16 Device Powerdown The CDR can be powered down via the RESET/CAL signal. When asserted, the evaluation board will draw minimal current. RESET/CAL is controlled via one jumper located in the lower left-hand corner of the evaluation board. RESET/CAL is wired to the signal post adjacent to the VDD post. For a valid reset to occur when using external reference clock mode, a proper external reference clock frequency must be applied as specified in Table 1. CLKOUT, DATAOUT, DATAIN CLKOUT, DATAOUT, and DATAIN (all high-speed I/Os) are wired to the board perimeter on 30 mil (0.030 inch) 50 microstrip lines to the end-launch SMA jacks as labeled on the PCB. These I/Os are ac coupled to simplify direct connection to a wide array of standard test hardware. Because each of these signals are differential, both the positive (+) and negative (-) terminals must be terminated to 50 . Terminating only one side will adversely degrade the performance of the CDR. The inputs are terminated on the die with 50 resistors. Note: The 50 termination is for each terminal/side of a differential signal, thus the differential termination is actually 50 + 50 = 100 . RATESEL RATESEL is used to configure the CDR to recover clock and data at different data rates. RATESEL is a two bit binary input controlled via two jumpers located in the lower left-hand corner of the evaluation board. RATESEL0/1 are wired to the center posts (signal post) between VDD and GND. For example, the OC-48 data rate is selected by jumping RATESEL0 to 1 and RATESEL1 to 1. GND GND RATESEL1 RATESEL0 622 Mbps GND RATESEL1 RATESEL0 155 Mbps VDD RATESEL1 RATESEL0 1244 Mbps VDD VDD RATESEL1 RATESEL0 2488 Mbps GND VDD Figure 1. RATESEL Jumper Configurations REFCLK REFCLK is optional for clock and data recovery within the Si5022 device. If REFCLK is not used, jumper both JP15 and JP16. These jumpers pull the REFCLK+ input to VDD and REFCLK- input to GND, which configures the device to operate without an external reference. Loss-of-Lock (LOL) Loss-of-lock (LOL) is an indicator of the relative frequency between the data and the REFCLK. LOL will assert when the frequency difference is greater than 600 ppm. In order to prevent LOL from de-asserting 2 Rev. 1.0 SI5022-EVB prematurely, there is hysterisis in returning from the outof-lock condition. LOL will be de-asserted when the frequency difference is less than 300 ppm. LOL is wired to a test point which is located on the upper right-hand side of the evaluation board. "BER Detection" section of the Si5022/Si5023 data sheet for threshold level programming. The BER_MON signal (JP14) is reserved for factory testing purposes. Test Configuration The three critical jitter tests typically performed on a CDR device are jitter transfer, jitter tolerance, and jitter generation. By connecting the Si5022 Evaluation Board as shown in Figure 3, all three measurements can be easily made. When applied, REFCLK should be within 100 PM of the frequency selected from Table 1. RATESEL must be configured to match the desired data rate, and PWRDN/CAL must be unjumpered. Jitter Tolerance: Referring to Figure 3, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, a pattern analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test, the Jitter Analyzer directs the Modulation Source to apply prescribed amounts of jitter to the synthesizer source. This "jitters" the pattern generator timebase which drives the DATAIN ports of the CDR. The Bit-Error-Rate (BER) is monitored on the Pattern Analyzer. The modulation (jitter) frequency and amplitude is recorded when the BER approaches a specified threshold. The Si5022 limiting amplifier can also be examined during this test. Simply lower the amplitude of the incoming data to the minimum value typically expected at the limiting amplifier inputs (typically 10 mVPP for the Si5022 device). Jitter Generation: Referring to Figure 3, this test requires a pattern generator, a clock source (synthesizer signal source), a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test, there is no modulation of the Data Clock, so the data that is sent to the CDR is jitter free. The Jitter Analyzer measures the RMS and peak-to-peak jitter on the CDR CLKOUT. Thus, any jitter measured is jitter generated by the CDR. Jitter Transfer: Referring to Figure 3, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test, the Jitter Analyzer modulates the data pattern and data clock reference. The modulated data clock reference is compared with the CLKOUT of the CDR. Jitter on CLKOUT relative to the jitter on the data clock reference is plotted versus modulation frequency at predefined jitter amplitudes. Loss-of-Signal Alarm Threshold Control The loss-of-signal alarm (LOS) is used to signal low incoming data amplitude levels. The input signal to the threshold control is set by applying a dc voltage level to the LOS_LVL pin. LOS_LVL is controllable through the BNC jack J10. The mapping of the LOS_LVL voltage to input signal alarm threshold level is shown in Figure 2. If this function is not used, jumper JP1. 40 mV LOS Threshold (mVPP) 30 mV LOS Disabled 15 mV LOS Undefined 40 mV/V 0 mV 0V 1.00 V 1.50 V 1.875 V 2.25 V 2.5 V LOS_LVL (V) Figure 2. LOS_LVL Mapping Data Slicing Level The slicing level allows optimization of the input crossover point for systems where the slicing level is not at the amplitude average. The data slicing level can be adjusted from the nominal cross-over point of the data by applying a voltage to the SLICE_LVL pin. SLICE_LVL is controllable through the BNC jack J11. The SLICE_LVL to the data slicing level is mapped as follows: V SLICE_LVL - 1.5 V SLICE = ------------------------------------------50 If this function is not used, jumper JP6. Bit-Error-Rate Alarm Threshold The bit-error-rate of the incoming data can be monitored by the BER_ALM pin. When the bit-error-rate exceeds an externally set threshold level, BER_ALM is asserted. BER_ALM is brought to a test point located in the upper right-hand corner of the board. The BER_ALM threshold level is set by applying a dc voltage to the BER_LVL pin. BER_LVL is controllable through the BNC jack J12. Jumper JP7 to disable the BER alarm. Refer to the Rev. 1.0 3 SI5022-EVB Pulse Generator Scope 2.5 V +- DATAOUT- Pattern Analyzer GPIB REFCLK+ REFCLK- + REFCLK - (optional) DATAOUT + - DATAOUT+ DATAIN+ DATAIN- + DATAIN - CLKOUT + - CLKOUT+ CLKOUT- SI5022-EVB Pattern Generator GPIB Clock Data Clock+ Jitter Analyzer GPIB Synthesizer Signal Source FM Modulation Source GPIB Figure 3. Test Configuration for Jitter Tolerance, Transfer, and Generation 4 Rev. 1.0 2.5V J13 POS1 POS2 1 2 L1 VDD JP2 JP3 JP5 JP8 JP9 JP10 ------LOL JP11 C12 tantalum 10uF C17 0603 0.1uF CLKDSBL RESET/CAL DSQLCH ------LTR RATESEL1 RATESEL0 ------LOS JP12 MKDSN 2,5/3-5,08 J10 BNC C13 JP1 VDD 0603 100pF C18 0603 0.1uF C14 ---------------BER_ALM JP13 LOS_LVL J11 BNC 0603 100pF JP6 C15 SLICE_LVL C19 0603 0.1uF J12 BNC JP7 11 14 18 21 25 0603 100pF C16 JP14 0603 100pF U1 BER_LVL BER_MON C20 0603 0.1uF 1 2 8 10 19 24 3 4 26 RATESEL0 RATESEL1 LTR DSQLCH RESET/CAL CLKDSBL VDDA VDDB VDDC VDDD VDDE R7 0603 4.99K 7 9 27 J7 AMP 449692 C5 LOL LOS BER_ALM Rev. 1.0 5 DIN+ J8 AMP 449692 0603 0.1uF LOS_LVL SLICE_LVL BER_LVL BER_MON 28 C4 DOUTAMP 449692 C6 0603 0.1uF C3 DOUTDOUT+ 16 17 0603 0.1uF J3 DIN- 0603 0.1uF VDD JP15 R6 12 13 DIN+ DIN- Si5022 AMP 449692 REFCLK+ J1 AMP 449692 0603 0.1uF C8 0603 49.9 J4 5 6 REFCLK+ REFCLKTDI REXT CLKOUTCLKOUT+ 22 23 DOUT+ CLKOUTAMP 449692 C2 J2 AMP 449692 C7 Reference Less Operation (jumper both JP15 and JP16) JP16 VDD JP4 15 20 R8 0603 100 0603 0.1uF C1 Si5022 0603 0.1uF 0603 0.1uF J5 AMP 449692 REFCLKR5 0603 348 R1 0603 10k (1%) J6 TDI (Do Not Install) CLKOUT+ SI5022-EVB Figure 4. Si5022 Schematic SI5022-EVB Bill of Materials Reference C1,C2,C3,C4,C5,C6, C7,C8,C17,C18,C19, C20 C12 C13,C14,C15,C16 JP1,JP6,JP7,JP11, JP12,JP13,JP14, JP15,JP16 JP2,JP3,JP5,JP8, JP9,JP10 J1,J2,J3,J4,J5,J6, J7,J8 J10,J11,J12 J13 L1 R1 R5 R6 R7 R8 U1 PCB No Load JP4 Description Manufacturer's # Manufacturer CAP,SM,0.1UF,16V,20%,X7R,0603 CAP,SM,10UF,10V,10%,TANTALUM,3216 CAP,SM,100PF,50V,10%,C0G,0603 CONN,HEADER,2X1 C0603X7R160-104KNE TA010TCM106KAR C0603C0G500-101KNE 2340-6111TN or 2380-6121TN VENKEL VENKEL VENKEL 3M CONN,HEADER,3X1 CONN,SMA SIDE MOUNT CONN,BNC,VERT CONN,POWER,2 POSITION FERRITE,SM,600,1206 RES,SM,10K,1%,0603 RES,SM,348,1%,0603 RES,SM,49.9,1%,0603 RES,SM,4.99K,1%,0603 RES,SM,100,1%,0603 Si5022 PRINTED CIRCUIT BOARD 2340-6111TN or 2380-6121TN 3M 901-10003 161-9317 AMPHENOL MOUSER 1729018 PHOENIX CONTACT BLM31A601S MURATA CR0603-16W-1002FT VENKEL CR0603-16W-3480FT VENKEL CR0603-16W-49R9FT VENKEL CR0603-16W-4991FT VENKEL CR0603-16W-1000FT VENKEL Si5022-BM SILICON LABORATORIES SI5022-EVB PCB Rev B SILICON LABORATORIES CONN,HEADER,3X1 2340-6111TN or 2380-6121TN 3M 6 Rev. 1.0 SI5022-EVB Figure 5. Si5022 Silkscreen Rev. 1.0 7 SI5022-EVB Figure 6. Si5022 Component Side 8 Rev. 1.0 SI5022-EVB Figure 7. Si5022 Solder Side Rev. 1.0 9 SI5022-EVB Document Change List Revision 0.23 to Revision 1.0 Removed "Preliminary" language. Evaluation Board Assembly Revision History Assembly Level A-01 B-01 B-02 PCB A A B SI5022-EVB Device A B B Assembly Notes Assemble per BOM rev A-01. Assemble per BOM rev B-01. Assemble per BOM rev B-02. 10 Rev. 1.0 SI5022-EVB Notes: Rev. 1.0 11 SI5022-EVB Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and SiPHY are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 12 Rev. 1.0 |
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