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CXA1787N
2GHz-band PLL IC for Mobile Communications For the availability of this product, please contact the sales office.
Descriptions The CXA1787N is a frequency synthesizer PLL IC developed for use in mobile communication systems. This IC has low current consumption, small package and is suitable for portable sets of cellular telephone and others. Features * Low current consumption Icc = 8.0mA (typ.) 0.3mA (typ.) in power saving mode * Maximum operating frequency 1.8GHz guaranteed * Operating supply voltage range 2.7 to 5.5V * Ultra small 20-pin SSOP package * Two types of phase comparator output: For external charge pump R P Two internal charge pumps DO1 DO2 Applications 1.1GHz-band mobile communication equipment such as cellular telephones 20 pin SSOP (Plastic)
Structure Bipolar silicon monolithic IC Absolute Maximum Ratings * Supply voltage Vcc * Operating temperature Topr * Storage temperature Tstg * Allowable power dissipation PD Operating Condition Supply voltage
7 -35 to +85 -65 to +150 300
V C C mW
Vcc
2.7 to 5.5
V
Block Diagram and Pin Configuration
OSCI 1 20 R
NC
2
Phase Comparator
19
NC
OSCO
3
18
P
Vp
4
Reference Programmable Counter 14bits
17
TEST
VCC
5
16
DO2
DO1
6
Charge Pump 1
Charge Pump 2
15
FC
GND
7
14
LAT
LD
8 Pulse Swallow Counter 7bits Programmable Counter 11bits
13
DATA
NC
9 1-bit Latch 14-bit Latch 18-bit Shift Resister 1-bit Shift
Resister
12
PS
FIN
10
2-modulus prescaler 1 1 or 64/65 128/129 Pulse swallow programmable counter
11
CK
18-bit Latch
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E94Z22A8Y
CXA1787N
Pin Description Pin No. 1 Symbol Typical pin voltage (DC) Equivalent circuit
VCC
Description Reference frequency signal input.
OSCI 2.2V
1 10
10 2 9 19
FIN
GND
VCO signal input.
NC
--
--
No connected.
VCC
3
OSCO
High: 2.2V Low: 2.0V
3
500 GND
Reference frequency signal output. Oscillator is formed by connecting the crystal resonator between this pin and the OSCI pin; the oscillator signal is used as the reference frequency signal. Power supply for the charge pump outputs (Do1, Do2) and phase comparator outputs (R, P). Power supply.
4
VP
3V
--
5 6
VCC DO1
3V
--
Vp
Charge pump 1 output. Charge pump 2 output. Outputs only when the LAT pin is High; in high impedance when the LAT pin is Low. Ground.
-- 16 DO2
6 16 GND
7 8 18 20 11 13 14
GND LD P R CK DATA LAT
--
Vp (LD is VCC)
Lock detection signal output. Phase comparator output. Used for the external charge pump. Clock input. Data input.
High: 2.2V Low: 0.1V
8 18 20 GND VCC
Open Low
11 13 14 GND
Latch input.
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CXA1787N
Pin No. 12
Symbol
Typical pin voltage (DC)
Equivalent circuit
Description Power saving pin. Power saving mode when this pin is Low. Switching for the phases of phase comparator output and the output signals of counter (reference, programmable) output to the TEST pin.
PS
VCC
Open High 15 FC
12 15 GND
17
TEST
High: 2.2V Low: 2.0V
17
The signal output which is frequency-divided at the counter.
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CXA1787N
Electrical Characteristics (Vcc = Vp = 3V, Ta = 25C, refer to the Electrical Characteristics Measurement Circuit) Item Current consumption Current consumption (in power saving mode) FIN operating frequency FIN input level OSCI operating frequency OSCI input level DO1 High output current DO2 DO1 Low output current DO2 DO1 High impedance DO2 leak current (leak current DO2 off) R P LD R P LD CK DATA LAT PS PS High output voltage Symbol Icc Icc (PS) fin Pin fosc Vosc IOH IOL 1 Vcc = Vp = 2.7V to 5.5V Ta = -35C to +85C Vcc = Vp = 2.7V to 5.5V Ta = -35C to +85C Vcc = Vp = 2.7V to 5.5V Ta = -35C to +85C Vcc = Vp = 2.7V to 5.5V Ta = -35C to +85C 150 -10 5 0.5 Conditions Min. Typ. 8.11 300 Max. 12.5 500 1800 6 20 2 -1 Unit mA A MHz dBm MHz Vpp mA mA
IOZ
-1
1
A
VOH
IL = 0.1mA
2
2.1
V
Low output voltage High input voltage High input current Low input voltage Low input current Low input current
VOL VIH IOH VIL IIL IIL
IL = 0.1mA Vcc x 0.7 VIN = Vcc -1
80
500
mV V
1 Vcc x 0.3
A V A A
VIN = GND except for PS VIN = GND
-1 -30 -15.5
1
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CXA1787N
Item High input voltage FC High input current Low input voltage Low input current High input voltage CK DATA LAT PS High input current Low input voltage Low input current PS Low input current High input voltage High input current FC Low input voltage Low input current
Symbol VIH IIH VIL IIL VIH IIH VIL IIL IIL VIH IIH VIL IIL
Conditions
Min. Vcc - 0.05
Typ.
Max.
Unit V
VIN = Vcc
-1
1 0.05
A V A V
VIN = GND Vcc = VP = 5.5V Vcc = VP = 5.5V, VIN = Vcc Vcc = VP = 5.5V Vcc = VP = 5.5V, VIN = GND except for PS Vcc = VP = 5.5V, VIN = GND Vcc = VP = 5.5V Vcc = VP = 5.5V, VIN = Vcc Vcc = VP = 5.5V Vcc = VP = 5.5V, VIN = GND
-50 Vcc x 0.7 -1
-20
1
1 Vcc x 0.3
A V A A V
-20 -60 Vcc - 0.05 -1
0 -30
1
1 0.05
A V A
-60
-35
1
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CXA1787N
Electrical Characteristics Measurement Circuit
Frequency Counter OUT Oscilloscope
A
A
A
Controller
5.1k V 20 19 V 18 17
A
A A
16
15
14
13
12
11
CXA1787N
OSCI
OSCO
Vcc
DO1
GND
DATA
TEST
DO2
LAT
NC
NC
VP
1000p
1 S.G. 51 1000p 51
2
3 V
4
5
6
LD
NC
7
8 V
9
10 S.G. 51
1000p
1
1
A
+
+
1000p
A
A
51
Application Circuit
Power save LAT DATA CK 1k 1k 1k
20 19 18 17 16 15 14 13 12 11 CXA1787N
FIN
10
CK 1000p FIN
51
FC
PS
R
P
OSCI
OSCO
Vcc
DO1
GND
DATA
TEST
DO2
LAT
NC
NC
VP
1
2
3
4
5
6
LD
7
8
1000p TCXO
1000p
1
+
1000p
L.P.F.
V.C.O. Output
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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NC
9
CK
FC
PS
R
P
1k
Controller
CXA1787N
Description of Operation 1. Data Setting Method The data is set using three signals -- CK, DATA, and LAT in this IC. In that case, the serial data as described below is input. (1) Data input method The 15 bits of data should be input to the reference counter latch and the 18 bis of data to the pulse swallow programmable counter latch to set the all initializing state in this IC. Every one bit of data is retrieved into the shift resister at the rising edge of clock input to the CK pin when the data is input to the DATA pin. The input data is retrieved into the reference counter latch or the pulse swallow programmable counter latch according to the state of the final bit C. The data is latched when the latch pulse is input to the LAT pin after 16 bits of data or 19 bits of data, which were added with the bit C, are sent to the shift resister. For actual use, first input the 16 bits (including the frequency division setting bit SW for 2-modulus prescaler) of reference counter data from the controller as indicated above. In this time, set the final bit C High. Next, input the 19 bits of pulse swallow programmable counter data in the same way. In this time, set the final bit C Low. Then, all of the interior state has been set. Hereafter, when only the programmable counter data is to be changed, only the latter 19 bits of programmable counter data should be changed. (In this case, set the bit C Low.) (2) Control data construction The control data consists of 16 bits for the reference counter and 19 bits for the pulse swallow programmable counter. The final bit of them is the identification code and the contents of data are discriminated by identifying the code. The frequency division value is composed of the binary values whose head is MSB as described on the next page.
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CXA1787N
(a) Data structure of reference counter
Input direction SW RD RC RB RA R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 C
(First, input the SW bit and input the C bit last.) R0 to RD: Frequency division number of reference counter (Binary value with R0 as LSB) SW: Switching bit of frequency division numbers of 2-modulus pre-scaler block for programmable counter. SW Frequency division number C: 1 64/65-frequency division 0 128/129-frequency division
This code decides the latch direction of data; set to High.
(b) Data structure of pulse swallow programmable counter
Input direction MA M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S6 S5 S4 S3 S2 S1 S0 C
(First, input the MA bit and input the C bit last.) M0 to MA: Frequency division number of main counter (Binary value with M0 as LSB) S0 to S6: Frequency division number of swallow counter (Binary value with S0 as LSB) C: This code decides the latch direction of data; set to Low. The frequency division value of programmable counter can be obtained with the following equation; NxM+S N: Frequency division value of 2-modulus pre-scaler (64 or 128) (M > S) M: Main counter value S: Swallow counter value (1) Data input timing
t1 to t5 500ns
DATA
(SW bit or MA bit) CK t1 LAT Data is read at the rising edge of CK. t2 t3
(C bit)
t4 t5
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CXA1787N
2. Power Save Pin (PS) This pin is left High when it is open and in power saving mode at Low. All circuits except for reference counter latch and pulse swallow programmable counter latch are set to off in the power saving mode. At that mode, Do1 and Do2 are high impedance and the data cannot be set. The data of reference counter and programmable counter are hold in power saving mode. 3. Do1 and Do2 Pins These are the charge pump output pins. Do1 operates always. Do2 operates only when the LAT pin is High ; it is in high impedance state when the LAT pin is Low. 4. FC Pin This pin switches the charge pump outputs (Do1, Do2) and the phases of phase comparator outputs (P, R). (Refer to the Table 1.) 5. TEST Pin This pin is for monitoring the counter output signal. The reference counter output and the pulse swallow programmable counter output are switched according to the FC state as shown at Table 1. This pin is emitter follower output High level = Vcc - Vf and Low level = Vcc - Vf - 200mV (200mV amplitude). The DC bias current is decreased to save the power consumption so that the amplitude may not be monitored for monitoring the waveforms with oscilloscope. In that case, connect the TEST pin to ground with an approximately 5k resistor.
Table 1. Phase comparator and TEST Pin outputs FC: High or open Do1 (2) fr > fp fr = fp fr < fp H Z L R L L H P L H H TEST Do1 (2) fr fr fr L Z H FC: Low R H L L P H H L TEST fp fp fp
Z: High impedance H: High L: Low
fr: Output frequency of reference counter fp: Output frequency of programmable counter
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CXA1787N
6. Reference signal (the input signal of reference counter) The external oscillator signal can be used as the reference signal by inputting the signal of the external oscillator to the OSCI pin, and the reference signal can be also generated by connecting the crystal resonator to the OSCI and OSCO pins. (1) Generation of the reference signal by the external oscillator Input the signal to the OSCI pin via a capacitor as shown below when the external oscillator signal is use as the reference signal.
OSCI 1 NC 2 OSCO 3
(2) Generation of the reference signal by the built-in oscillator Connect the crystal resonator between OSCI and OSCO pins as shown below. Use the crystal resonator of several MHz and confirm the stability of the oscillation and others. The capacitance ratio of CI and Co should be 1 to 2:1, and their values should be selected so that the serial capacitance of CI and Co may be the load capacitance specified by the crystal vibrator.
OSCI 1
NC 2
OSCO 3
CI
CO
Notes on Operation * This is ESD sensitive device due to handling the higher frequency signal of 2GHz; therefore prevent electrostatic damage more than 400V in the EIAJ system. * Make the input route of the RF signal from the VCO as short as possible. * Connect the Vcc and Vp pins to the ground respectively via the by-pass capacitors as short as possible because the frequency of signal used in this IC is higher.
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CXA1787N
Example of Representative Characteristics
FIN input level vs. Fin input frequency
10 VCC = VP = 2.7V Ta = 25C
0
FIN input level [dBm]
-10
-20
-30
-40
10
100 Fin input frequency [MHz]
1000
FIN maximum operating frequency vs. Ta
2500
FIN maximum operating frequency [MHz]
VCC = VP = 2.7V PIN = -10dBm 2450
2400 -35 0 25 Ta [C] 50 85
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CXA1787N
OSCI input level vs. input fequency
10 VCC = VP = 2.7V 25C -35C 85C
0
OSCI input level [dBm]
-10
-20
-30
-40
1
10 OSCI input frequency [MHz]
100
Current consumption vs. Supply voltage
10
Current consumption vs. Ta
Current consumption [mA]
8 7 6 5 4 3 2 1 0 -35 0 Ta [C] 50 85 Supply voltage 2.7V
Current consumption [mA]
9 8 7 6 5 4 3 2 1 0 2.7 Ta = 25C
3
4 Supply voltage [V]
5
5.5
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CXA1787N
Package Outline
Unit: mm
20PIN SSOP (PLASTIC)
6.5 0.1 + 0.2 1.25 - 0.1 0.1 20 11 A
4.4 0.1
1
10 0.65 + 0.05 0.15 - 0.02
+ 0.1 0.22 - 0.05
0.13 M 0.1 0.1
0 to 10 DETAIL A NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-20P-L01 SSOP020-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.1g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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0.5 0.2
6.4 0.2

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