View HYB314171BJ-50-_356781.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
HYB 314171BJ-50/-60/-70 HYB 314171BJL-50/-60/-70
Preliminary Information
* * * *
262 144 words by 16-bit organization 0 to 70 C operating temperature Fast access and cycle time RAS access time: 50 ns (-50 version) 60 ns (-60 version) 70 ns (-70 version) CAS access time: 15ns (-50,-60 version) 20 ns (-70 version) Cycle time: 95 ns (-50 version) 110 ns (-60 version) 130 ns (-70 version) Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) 45 ns (-70 version) Single + 3.3 V ( 0.3 V) supply with a builtin VBB generator
*
*
*
* *
*
*
*
* * * * * *
Low Power dissipation max. 450 mW active (-50 version) max. 378 mW active (-60 version) max. 306 mW active (-70 version) Standby power dissipation 7.2 mW standby (TTL) 3.6 mW max. standby (CMOS) 0.72 mW max. standby (CMOS) for Low Power Version Output unlatched at cycle end allows twodimensional chip selection Read, write, read-modify write, CASbefore-RAS refresh, RAS-only refresh, hidden-refresh and fast page mode capability 2 CAS / 1 WE control Self Refresh (L-Version) All inputs and outputs TTL-compatible 512 refresh cycles / 16 ms 512 refresh cycles / 128 ms Low Power Version only Plastic Packages: P-SOJ-40-1 400mil width
The HYB 314171BJ/BJL is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The HYB 314171BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 314171BJ/BJL to be packed in a standard plastic 400mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include Self Refresh (LVersion), single + 3.3 V ( 0.3 V) power supply, direct interfacing with high performance logic device families.
Semiconductor Group
1
7.96
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Ordering Information Type HYB 314171BJ-50 HYB 314171BJ-60 HYB 314171BJ-70 HYB 314171BJL-50 HYB 314171BJL-60 HYB 314171BJL-70 Truth Table RAS H L L L L L L L L LCAS H H L H L L H L L UCAS H H H L L H L L L WE H H H H H L L L H OE H H L L L H H H H I/O1-I/O8 High-Z High-Z Dout High-Z Dout Din Don't care Din High-Z I/O9-I/O16 High-Z High-Z High-Z Dout Dout Don't care Din Din High-Z Operation Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write Ordering Code on request on request on request on request on request on request Package P-SOJ-40-1 P-SOJ-40-1 P-SOJ-40-1 P-SOJ-40-1 P-SOJ-40-1 P-SOJ-40-1 Description 3.3V 50ns 256 K x 16 DRAM 3.3V 60 ns 256 K x 16 DRAM 3.3V 70 ns 256 K x 16 DRAM 3.3V 50 ns 256 K x 16 DRAM 3.3V 60 ns 256 K x 16 DRAM 3.3V 70 ns 256 K x 16 DRAM
Pin Names A0-A8 RAS UCAS, LCAS WE OE I/O1 - I/O16 Address Inputs Row Address Strobe Column Address Strobe Read/Write Input Output Enable Data Input/Output Power Supply (+ 3.3 V) Ground (0 V) No Connection
VCC VSS
N.C.
Semiconductor Group
2
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Pin Configuration (top view)
P-SOJ-40-1
Semiconductor Group
3
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Block Diagram
Semiconductor Group
4
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Absolute Maximum Ratings Operating temperature range ........................................................................................ 0 to + 70 C Storage temperature range..................................................................................... - 55 to + 150 C Input/output voltage .................................................................................... - 1 to (VCC + 0.5, 4.6) V Power supply voltage.................................................................................................. - 1 to + 4.6 V Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 5 ns Parameter Input high voltage Input low voltage LVTTL Output high voltage (IOUT = - 2.0 mA) LVTTL Output low voltage (IOUT = 2 mA) LVCMOS Output high voltage (IOUT = - 100 A) LVCMOS Output low voltage (IOUT = 100 A) Input leakage current, any input (0 V < VIN < VCC + 0.3 V, all other inputs = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < VCC + 0.3 V ) Average VCC supply current: -50 version -60 version -70 version Symbol Limit Values min. max. 2.0 - 1.0 2.4 - 2.4 - - 10 - 10 - Unit Notes V V V V V V A A mA 1 1 1 1 1 1 1 1 2, 3, 4
VIH VIL VOH VOL VOH VOL II(L) IO(L) ICC1
VCC + 0.5
0.8 - 0.4 - 0.4 10 10 125 105 85 2
Standby VCC supply current (RAS = LCAS = UCAS = WE = VIH) Average VCC supply current during RAS-only refresh cycles: -50 version -60 version -70 version
ICC2
- -
mA 2, 4
ICC3
125 105 85
mA
Semiconductor Group
5
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
DC Characteristics (cont'd) Parameter Average VCC supply current during fast page mode operation: -50 version -60 version -70 version Standby VCC supply current (RAS = LCAS = UCAS = WE = VCC - 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode: -50 version -60 version -70 version Standby VCC current (L-version) (RAS = LCAS = UCAS = WE= VCC - 0.2 V) Self Refresh Current (L-version) (RAS, LCAS, UCAS = 0.2 V A0 - A8 = VCC - 0.2 V or 0.2 V) Symbol - Limit Values min. max. 2, 3, 4 70 65 60 - - 1 mA Unit Notes
ICC4
ICC5
mA
1 2, 4
ICC6
125 105 85 - - 200 250
mA
ICC5 ICCS
A A
Capacitance TA = 0 to 70 C; VCC = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (A0 to A8) Input capacitance (RAS, UCAS, LCAS, WE, OE) Output capacitance (l/O1 to l/O16) Symbol Limit Values min. max. 6 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
6
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
AC Characteristics 5)6) TA = 0 to 70 C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 5 ns Parameter
Symbol
Limit Values -50 min. - 60 - 70 max. max. min. max. min.
Unit Note
Common Parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period Refresh period (L-version)
tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF tREF
95 35 50 15 0 10 0 10 20 15 15 50 5 3 - -
- - 10k 10k - - - - 35 25 - - - 50 16 128
110 40 60 15 0 10 0 15 20 15 15 60 5 3 - -
- - 10k 10k - - - - 45 30 - - - 50 16 128
130 50 70 20 0 10 0 15 20 15 20 70 5 3 - -
- - 10k 10k - - - - 50 35 - - - 50 16 128
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7
Read Cycle
Access time from RAS Access time from CAS OE access time Read command setup time Read command hold time Read command hold time ref. to RAS CAS to output inlow-Z
tRAC tCAC tOEA tRCS tRCH tRRH tCLZ
- - - - 25 0 0 0 0
50 15 25 15 - - - - -
- - - - 30 0 0 0 0
60 15 30 15 - - - - -
- - - - 35 0 0 0 0
70 20 35 20 - - - - -
ns ns ns ns ns ns ns ns ns
8, 9 8, 9 8,10
Access time from column address tAA Column address to RAS lead time tRAL
11 11 8
Semiconductor Group
7
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Parameter
Symbol
Limit Values -50 min. - 60 0 0 0 20 20 20 20 - - - 0 0 0 20 20 - 70 max. 20 20 - - - max. min. 15 15 - - max. min.
Unit Note
Output buffer turn-off delay from CAS Output buffer turn-off delay from OE Data to OE low delay CAS high to datadelay OE high to data delay
tOFF tOEZ tDZO tCDD tODD
0 0 0 15 15
ns ns ns ns ns
12 12 13 14 14
Write Cycle
Write command hold time Write command pulse width Write command setup time
tWCH tWP tWCS
10 10 0 15 15 0 10 0
- - - - - - - -
10 10 0 15 15 0 15 0
- - - - - - - -
15 15 0 20 20 0 15 0
- - - - - - - -
ns ns ns ns ns ns ns ns 16 16 13 15
Write command to RAS lead time tRWL Write command to CAS lead time tCWL Data setup time Data hold time Data to CAS lowdelay
tDS tDH tDZC
Read-modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time
tRWC tRWD tCWD tAWD tOEH
140 75 40 50 15
- - - - -
160 90 45 60 20
- - - - -
185 100 50 65 20
- - - - -
ns ns ns ns ns 15 15 15
Fast Page Mode Cycle
Fast page mode cycle time CAS precharge time RAS pulse width RAS hold time from CAS precharge
tPC tCP tRASP tRHCP
35 10 - 50 30
- - 30 -
40 10 - 35
- - 35 -
45 10 - 40
- - 40 -
ns ns ns ns 7
Access time from CAS precharge tCPA
200k 60
200k 70
200k ns
Semiconductor Group
8
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Parameter
Symbol
Limit Values -50 min. - 60 - 70 max. max. min. max. min.
Unit Note
Fast Page Mode Read Modify Write Cycle
Fast page mode read/write cycle time CAS precharge to WE delay time
tPRWC tCPWD
80 55
- -
90 60
- -
100 65
- -
ns ns
CAS before RAS refresh Cycle
CAS setup time CAS hold tim RAS to CAS precharge time Write to RAS precharge time Write to RAS hold time
tCSR tCHR tRPC tWRP tWRH
5 10 0 10 10
- - - - -
5 10 0 10 10
- - - - -
5 10 0 10 10
- - - - -
ns ns ns ns ns
CAS-before RAS counter test cycle
CAS precharge time
tCPT
25
-
30
-
40
-
ns
Self Refresh Cycle (L-Version only)
RAS pulse width RAS precharge time CAS hold time Self Refresh
tRASS tRPS tCHS
100 95 35
- - -
100 110 40
- - -
100 130 50
- - -
s ns ns
Semiconductor Group
9
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a page mode cycle 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 100 pF and at Voh=2.0V (Ioh=-2mA), Vol=0.8V (Iol=2mA). 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. 13) Either tDZC or tDZO must be satisfied. 43) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles.
Semiconductor Group
10
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Read Cycle Semiconductor Group 11
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Write Cycle (Early Write)
Semiconductor Group
12
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Write Cycle (OE Controlled Write)
Semiconductor Group
13
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
14
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Fast Page Mode Read Cycle
Semiconductor Group
15
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Fast Page Mode Early Write Cycle
Semiconductor Group
16
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
17
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
RAS-Only Refresh Cycle
Semiconductor Group
18
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
CAS-Before-RAS Refresh Cycle
Semiconductor Group
19
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
CAS before RAS Self Refresh Cycle
Semiconductor Group
20
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Hidden Refresh Cycle (Read)
Semiconductor Group
21
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Hidden Refresh Cycle (Early Write)
Semiconductor Group
22
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
CAS/-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
23
HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM
Package Outline
Plastic Package, P-SOJ- 40-1 (SMD) (Plastic Small Outline J-leaded Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 24
Dimensions in mm
GPJ09018

▲Up To Search▲

Price & Availability of HYB314171BJ-50-

	To Download HYB314171BJ-50- Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .