 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 74C Family Characteristics 74C Family Characteristics Fairchild Semiconductor Application Note 90 August 1973 INTRODUCTION The purpose of this 54C/74C Family Characteristics application note is to set down, in one place, all those characteristics which are common to the devices in the MM54C/MM74C logic family. The characteristics which can be considered to apply are: 1. Output voltage-current characteristics 2. 3. 4. Noise characteristics Power consumption Propagation delay (speed) simple a manner as possible to facilitate its use. This coupled with the fact that 54C/74C has the same function and pin-out as standard series 54L/74L will make the application of CMOS to digital systems very straightforward. OUTPUT CHARACTERISTICS Figure 1 and Figure 2 show typical output drain characteristics for the basic inverter used in the 54C/74C family. For more detailed information on the operation of the basic inverter the reader is directed to Application Note AN-77, "CMOS, The Ideal Logic Family". Although more complex gates, and MSI devices, may be composed of combinations of parallel and series transistors the considerations that govern the output characteristics of the basic inverter apply to these more complex structures as well. 5. Temperature characteristics With a good understanding of the above characteristics the designer will have the necessary tools to optimize his system. An attempt will be made to present the information in as AN006021-1 (A) Typical Output Sink Characteristic (N-Channel) (B) Typical Output Source Characteristic (P-Channel) FIGURE 1. AN006021-2 AN006021-3 (A) Typical Output Sink Characteristic (N-Channel) (B) Typical Output Source Characteristic (P-Channel) FIGURE 2. AN006021-4 AN-90 www.fairchildsemi.com (c) 1998 Fairchild Semiconductor Corporation AN006021 The 54C/74C family is designed so that the output characteristics of all devices are matched as closely as possible. To ensure uniformity all devices are tested at four output conditions (see Figure 1 and Figure 2). These points are: VCC = 5.0V VIN = 5.0V IDS 1.75 mA VCC = 10V VDS 5.0V VIN = 10V IDS 8.0 mA VDS 10V VIN = 0V |IDS| 1.75 mA |VDS| 5.0V VIN = 0V |IDS| 8.0 mA |VDS| 10V NOISE CHARACTERISTICS Definition of Terms Noise Immunity: The noise immunity of a logic element is that voltage which applied to the input will cause the output to change its output state. Noise Margin: The noise margin of a logic element is the difference between the guaranteed logical "1" ("0") level output voltage and the guaranteed logical "1" ("0") level input voltage. The transfer characteristic of Figure 3 shows typical noise immunity and guaranteed noise margin for a 54C/74C device operating at VCC = 10V. The typical noise immunity does not change with voltage and is 45% of VCC. Note that each device data sheet guarantees these points in the table of electrical characteristics. The output characteristics can be used to determine the output voltage for any load condition. Figure 1 and Figure 2 show load lines for resistive loads to VCC for sink currents and to GND for source currents. The intersections of this load line with the drain characteristic in question gives the output voltage. For example at VCC = 5.0V, VOUT = 1.5V (typ) with a load of 500 to ground. These figures also show the guaranteed points for driving two 54L/74L standard loads. As can be seen there is typically ample margin at VCC = 5.0V. In the case where the 54C/74C device is driving another CMOS device the load line is coincident with the IDS = 0 axis and the output will then typically switch to either VCC or ground. AN006021-5 FIGURE 3. Typical Transfer Characteristics All 54C/74C devices are guaranteed to have a noise margin of 1.0V or greater over all operating conditions (see Figure 4). www.fairchildsemi.com 2 this guarantees that every node within a system can have 1.0V of noise, in logic "1" or logic "0" state, without malfunctioning. This could not be guaranteed without testing for both conditions in Figure 5. POWER CONSUMPTION There are four sources of power consumption in CMOS devices: (1) leakage current; (2) transient power due to load capacitance; (3) transient power due to internal capacitance and; (4) transient power due to current spiking during switching. The first, leakage current, is the easiest to calculate and is simply the leakage current times VCC. The data sheet for each specific device specifies this leakage current. The second, transient power due to load capacitance, can be derived from the fact that the energy stored on a capacitor is 1/2 CV2. Therefore every time the load capacitance is charged or discharged this amount of energy must be provided by the CMOS device. The energy per cycle is then 2[(1/2) CVCC2] = CVCC2. Energy per unit time, or power, is then CVCC2 f, where C is the load capacitance and f is the frequency. The third, transient power due to internal capacitance takes exactly the same form as the load capacitance. Every device has some internal nodal capacitance which must be charged and discharged. This then represents another power term which must be considered. The fourth, transient power due to switching current, is caused by the fact that whenever a CMOS device goes through a transition, with VCC 2 VT, there is a time when both N-channel and P-channel devices are both conducting. An expression for this current is derived in Application Note AN-77. The expression is: AN006021-6 FIGURE 4. Guaranteed Noise Margin over Temperature vs VCC Noise immunity is an important device characteristic. However, noise margin is of more use to the designer because it very simply defines the amount of noise a system can tolerate under any circumstances and still maintain the integrity of logic levels. Any noise specification to be complete must define how measurements are to be made. Figure 5 indicates two extreme cases; driving all inputs simultaneously and driving one input at a time. Both conditions must be included because each represents one worst case extreme. AN006021-7 (A) where: VT = threshold voltage ICC(MAX) = peak non-capacitive current during switching f = frequency Note that this expression, like the capacitive power term is directly proportional to frequency. If the PVI term is combined with the term arising from the internal capacitance, a capacitance CPD may be defined which closely approximates the no load power consumption for a CMOS device when used in the following expression: Power (no load) = CPD VCC2 f The total power consumption is then simplified to: Total Power = (CPD + CL) VCC2 f + ILEAK VCC(1) The procedure for obtaining CPD is to measure the no load power at VCC = 10V vs frequency and calculate the value of CPD which corresponds to the measured power consumption. This value of CPD is given on each 54C/74C data sheet and with equation (1) the computation of power consumption is straightforward. To simplify the task even further Figure 6 gives a graph of normalized power vs frequency for different power supply AN006021-8 *VOUT = VOUT (1) MIN, VOUT (0) MAX VN = Allowable Noise Voltage = 1.0V (B) FIGURE 5. Noise Margin Test Circuits To guarantee a noise margin of 1.0V, all 54C/74C devices are tested under both conditions. It is important to note that 3 www.fairchildsemi.com voltages. To obtain actual power consumption find the normalized power for a particular VCC and frequency, then multiply by CPD + CL. plex and has many nodes charging and discharging at various rates, all of the effects can be easily lumped into one easy to use term, CPD. Calculation of transient power due to load capacitance is a little more complex since each output is switched at one half the rate of the previous output: Taking this into account the complete expression for power consumption is: AN006021-9 FIGURE 6. Normalized Typical Power Consumption vs Frequency As an example let's find the total power consumption for an MM74C00 operating at f = 100 kHz, VCC = 10V and CL = 50 pF. From the curve, normalized power per gate equals 10 W/pF. From the data sheet CPD = 12 pF; therefore, actual power per gate is: This reduces to: PTOTAL = (CPD + CL) VCC2 f + IL VCC From the data sheet CPD = 90 pF and IL = 0.05 A. Using Figure 6 total power is then: Up to this point the discussion of power consumption has been limited to simple gate functions. Power consumption for an MSI function is more complex but the same technique just derived applies. To demonstrate the technique let's compute the total power consumption of a MM74C161, four bit binary counter, at VCC = 10V, f = 1 MHz and CL = 50 pF on each output. The no load power is still given by P (no load) = CPD VCC2 f. This demonstrates the usefulness of the concept of the internal capacitance, CPD. Even though the circuit is very com- This demonstrates that with more complex devices the concept of CPD greatly simplifies the calculation of total power consumption. It becomes an easy task to compute power for different voltages and frequencies by use of Figure 6 and the equations above. PROPAGATION DELAY Propagation delay for all 54C/74C devices is guaranteed with a load of 50 pF and input rise and fall times of 20 ns. A 50 pF load was chosen, instead of 15 pF as in the 4000 series, because it is representative of loads commonly seen in CMOS systems. A good rule of thumb, in designing with CMOS, is to assume 10 pF of interwiring capacitance. Operating at the specified propagation delay would allow 5 pF www.fairchildsemi.com 4 fanout for the 4000 series while 54C/74C has a fanout of 40 pF. A fanout of 5 pF (one gate input) is all but useless, and specified propagation delay would most probably not be realized in an actual system. The same formula and curves may be applied to more complex devices. For example the propagation delay from data to output for an MM74C157 operating at VCC = 10V and CL = 100 pF is: AN006021-10 FIGURE 7. Typical Propagation Delay per pF of Load Capacitance vs Power Supply Operating at loads other than 50 pF poses a problem since propagation is a function of load capacitance. To simplify the problem Figure 7 has been generated and gives the slope of the propagation delay vs load capacitance line (tpd/pF) as a function of power supply voltage. Because the propagation delay for zero load capacitance is not zero and depends on the internal structure of each device, an offset term must be added that is unique to a particular device type. Since each data sheet gives propagation delay for 50 pF the actual delay for different loads can be computed with the aid of the following equation: It is significant to note that this equation and Figure 7 apply to all 54C/74C devices. This is true because of the close match in drive characteristics of every device including MSI functions, i.e., the slope of the propagation delay vs load capacitance line at a given voltage is typically equal for all devices. The only exception is high fan-out buffers which have a smaller tpd/pF. Another point to consider in the design of a CMOS system is the effect of power supply voltage on propagation delay. Figure 8 shows propagation delay as a function of VCC and propagation delay times power consumption vs VCC for an MM74C00 operating with 50 pF load at f = 100 kHz. AN006021-11 FIGURE 8. Speed Power Product and Propagation Delay vs VCC Above VCC = 5.0V note the speed power product curve approaches a straight line. However the tpd curve starts to "flatten out". Going from VCC = 5.0V to VCC = 10V gives a 40% decrease in propagation delay and going from VCC = 10V to VCC = 15V only decreases propagation delay by 25%. Clearly for VCC > 10V a small increase in speed is gained by a disproportionate increase in power. Conversely, for small decreases in power below VCC = 5.0V large increases in propagation delay result. Obviously it is optimum to use the lowest voltage consistent with system speed requirements. However, in general it can be seen from Figure 8 that the best speed power performance will be obtained in the VCC = 5.0V to VCC = 10V range. As an example let's compute the propagation delay for an MM74C00 driving 15 pF load and operating with a VCC = 5.0V. The equation gives: 5 www.fairchildsemi.com TEMPERATURE CHARACTERISTICS Figure 9 and Figure 10 give temperature variations in drain characteristics for the N-channel and P-channel devices operating at VCC = 5.0V and VCC = 10V respectively. As can be seen from these curves the output sink and source current decreases as temperature increases. The effect is almost linear and can be closely approximated by a temperature coefficient of -0.3% per degree centigrade. Since the tpd can be entirely attributed to rise and fall time, the temperature dependence of tPD is a function of the rate at which the output load capacitance can be charged and discharged. This in turn is a function of the sink/source current which was shown above to vary as -0.3% per degree centigrade. Consequently we can say that tpd varies as -0.3% per degree centigrade. Actual measurements of tpd with temperature verifies this number. AN006021-12 AN006021-13 (A) Typical Output Drain Characteristic (N-Channel) FIGURE 9. (B) Typical Output Drain Characteristic (P-Channel) AN006021-14 AN006021-15 (A) Typical Output Drain Characteristic (N-Channel) (B) Typical Output Drain Characteristic (P-Channel) FIGURE 10. The drain characteristics of Figure 9 and Figure 10 show considerable variation with temperature. Examination of the transfer characteristics of Figure 11 indicates that they are almost independent of temperature. The transfer characteristic is not dependent on temperature because although both the N-channel and P-channel device characteristics change with temperature these changes track each other closely. The proof of this tracking is the temperature independence of the transfer characteristics. Noise margin and maximum/ minimum logic levels will then not be dependent on temperature. As discussed previously power consumption is a function of CPD, CL, VCC, f and ILEAKAGE. All of these terms are essentially constant with temperature except ILEAKAGE. However, the leakage current specified on each 54C/74C device applies across the entire temperature range and therefore represents a worst case limit. AN006021-16 FIGURE 11. Typical Gate Transfer Characteristics www.fairchildsemi.com 6 74C Family Characteristics LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Corporation Americas Customer Response Center Tel: 1-888-522-5372 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 8 141-35-0 English Tel: +44 (0) 1 793-85-68-56 Italy Tel: +39 (0) 2 57 5631 www.fairchildsemi.com Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: +852 2737-7200 Fax: +852 2314-0061 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 AN-90 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
Price & Availability of AN-90
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |