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PRELIMINARY
W127/W127-A
Spread Spectrum 3 DIMM System Frequency Synthesizer w/AGP
Features
* Maximized EMI suppression using Cypress's Spread Spectrum technology * I2C interface * Four copies of CPU Output * Six copies of PCI Output * Two copies of AGP Output * One copy of 48-MHz USB Output * One copy of 24-MHz SIO Output * Twelve copies of SDRAM Output * One buffered copy of 14.318-MHz reference input * Mode input pin selects optional power management input control pins (reconfigures pins 29, 30, 31, and 32) * Smooth frequency transition upon frequency reselection * Available in 48-pin SSOP (300 mils) * Standard W127 device supports up to 112-MHz operations. High-performance option W127-A supports up to 124-MHz. CPU Cycle to Cycle Jitter: ........................................... 250 ps CPU to AGP Skew:..................................................0500 ps AGP to PCI Skew: .................................. 1.5 ns (AGP Leads) CPU Output Edge Rate: ............................................ >1 V/ns SDRAM Output Edge Rate:.................................... >1.5 V/ns Note: All skews are optimized @VDDQ2 = VDDQ3 = 3.3V5%. Skews are not guaranteed for VDDQ2 = 2.5V. Table 1. Pin Selectable Frequency[1] Input Address FS2 0 0 0 0 1 1 1 1 Supply Voltages: .......... VDDQ3 = 3.3V, VDDQ2 = 3.3V or 2.5V
.
FS1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1
CPU (MHz) 68.5 112 95.25 100 83.3 75.0 124 66.6
AGP (MHz) 68.5 74.6 63.5 66.6 55.53 75 82.6 66.6
PCI (MHz) 34.25 37.3 31.75 33.3 27.77 37.5 41.3 33.3
Key Specifications
Block Diagram
SDATA SCLOCK Serial Port Device Control PLL Ref Freq X1 X2 XTAL OSC I/O PLL1 (CPU_STOP#) /1 /1.5 CPU STOP SDRAM STOP VDDQ3 REF/SD_SEL VDDQ2 CPU0:3 4 VDDQ3 SDRAM0:11 12
Pin Configuration [2]
VDDQ3 VDDQ3 REF/SD_SEL* GND X1 X2 VDDQ3 PCI_F/FS2* PCI0 GND PCI1 PCI2 PCI3 PCI4 GND GND AGP_F/MODE* AGP0 VDDQ3 SDRAM11 SDRAM10 VDDQ3 SDATA VDDQ3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48MHz/FS1* 24MHz/FS0* GND GND CPU0 CPU1 VDDQ2 CPU2 CPU3 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4(AGP_STOP#)* SDRAM5(PWR_DWN#)* SDRAM6(CPU_STOP#)* SDRAM7(PCI_STOP#)* GND SDRAM8 SDRAM9 SCLOCK
W127/W127-A
AGP_F/MODE /2 (AGP_STOP#) PCI STOP (PCI_STOP#) (PWR_DWN#) Power Down Control /1 PLL2 /2 I/O
I/O
AGP STOP
I/O AGP0 PCI_F/FS2 I/O / PCI0:4 5
VDDQ3 48MHZ/FS1 24MHZ/FS0
Notes: 1. Configuration "110" is supported by W127-A only (see shaded row of Table 1). 2. Signal names with "*" denote pins have internal 250K pull-up resistor, though not relied upon for pulling to VDDQ3 . Signal names with parenthesis denote function is selectable by MODE pin strapping.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 December 20, 1999, rev. 09.1
PRELIMINARY
Pin Definitions
Pin Name CPU0:3 Pin No. 44, 43, 41, 40 8 Pin Type O Pin Description
W127/W127-A
CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. Free-running PCI Clock Output and Frequency Selection Bit 2: As an output, this pin works in conjunction with PCI0:4. Output voltage swing is controlled by voltage applied to VDDQ3. When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per Table 1, "Pin Selectable Frequency" on page 1. PCI Clock Outputs 0 through 4: Output voltage swing is controlled by voltage applied to VDDQ3. Outputs are held LOW if PCI_STOP# is set LOW. SDRAM Clock Outputs: These eight SDRAM clock outputs run synchronous to the CPU clock outputs or AGP clock output as selected using SD_SEL per Table 2. SDRAM Clock Outputs: These four SDRAM clock outputs run synchronous to the CPU clock outputs or AGP clock output as selected using SD_SEL per Table 2. If programmed as inputs, (refer to MODE pin description), these pins are used for STOP_ CPU, AGP, PCI, and power-down control. 48-MHz Output and Frequency Selection Bit 1: Fixed clock output that defaults to 48 MHz following device power-up. When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per Table 1, "Pin Selectable Frequency" on page 1. 24-MHz Output and Frequency Selection Bit 0: Fixed clock output that defaults to 24 MHz following device power-up. When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per Table 1, "Pin Selectable Frequency" on page 1. Free-running AGP Output and Mode Control Input: As an output, this pin works in conjunction with AGP0 and is a free running clock. When an input, it determines the functions for pin 29, 30, 31, and 32. See Table 3. AGP Output: This output is controlled by the AGP_STOP# pin. Fixed 14.318-MHz and SDRAM Output Selection: As an output, this pin is used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. When an input, this pin selects the SDRAM to run synchronous to either CPU or AGP. See Table 2. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data Interface section that follows. Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data Interface section that follows. Power Connection: Connected to 3.3V supply. Power Connection: Power Supply for CPU0:3 clock outputs. (3.3V Supply) Ground Connection: Connect all ground pins to the common system ground plane.
PCI_F/FS2
I/O
PCI0:4 SDRAM0:3 SDRAM8:11 SDRAM4:7
9, 11, 12, 13, 14 38, 37, 35, 34, 27, 26, 21, 20 32, 31, 30, 29
O O I/O
48MHZ/FS1
48
I/O
24MHZ/FS0
47
I/O
AGP_F/MODE
17
I/O
AGP0 REF/SD_SEL
18 3
O I/O
X1
5
I
X2 SDATA SCLOCK VDDQ3 VDDQ2 GND
6 23 25 1, 2, 7, 19, 22, 24, 36 42 4, 10, 15, 16, 28, 33, 39, 45, 46
I I I P P G
2
PRELIMINARY
W127/W127-A Pin Selection Tables
Table 2. SD_SEL Function SD_SEL 1 0 Table 3. Mode Function Pin Function Mode 1 0 Pin 29 SDRAM7 PCI_STOP# Pin 30 SDRAM6 CPU_STOP# Pin 31 SDRAM5 PWR_DWN# SDRAM0:11 Running @ CPU Frequency Running @ AGP Frequency
W127/W127-A
Pin 32 SDRAM4 AGP_STOP#
Table 4. Power Management Pin Function SIGNAL CPU_STOP# PCI_STOP# AGP_STOP# PWR_DWN# =0 CPU0:3 & SDRAM0:11 = LOW PCI0:4 = LOW AGP0 = LOW All Clock Outputs LOW =1 Active Active Active Active
Overview
The W127/W127-A was designed specifically to provide all clock signals required for a motherboard designed with the Via MVP3 chipset using either a Pentium(R) or K6 microprocessor. Although it can be used with split voltages (3.3/2.5), the skew specifications are guaranteed only for single 3.3V supply. The primary distinguishing feature of the W127/W127-A is the 95.25-MHz CPU frequency option, which supports the K6 333MHz CPU. Twelve SDRAM outputs are provided for support of up to 3 SDRAM DIMM modules. Unused clock outputs can be disabled through the I2C interface to reduce system power consumption and more importantly reduce EMI emissions.
Upon W127/W127-A power-up, the first 2 ms of operation is used for input logic selection. During this period, the 24-MHz, 48-MHz, REF, PCI_F and AGP_F clock output buffers are three-stated, allowing the output strapping resistor on each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or logic LOW state. At the end of the 2-ms period, the established logic 0 or 1 condition of each l/O pin is latched. Next the output buffers are enabled, converting all l/O pins into operating clock outputs. The 2-ms timer starts when VDDQ3 reaches 2.0V. The input bits can only be reset by turning VDDQ3 off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock output is 40 (nominal), which is minimally affected by the 10-k strap to ground or VDDQ3. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDDQ3 should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, target (normal) output frequency is delivered, assuming that V DDQ3 has stabilized. If VDDQ3 has not yet reached full value, output frequency initially may be below target but will increase to target once VDDQ3 voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
Functional Description
I/O Pin Operation Pins 3, 8, 17, 47, and 48 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after powerup, the logic state of each pin is latched and the pins then become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between each l/O pin and ground or VDDQ3. Connection to ground sets a latch to "0," connection to VDDQ3 sets a latch to "1." Figure 1 and Figure 2 show two suggested methods for strapping resistor connection.
3
PRELIMINARY
VDDQ3
W127/W127-A
Output Strapping Resistor 10 k (Load Option 1) W127/W127-A Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
Series Termination Resistor R Clock Load
10 k (Load Option 0)
Q
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
VDD 10 k W127/W127-A Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
Output Strapping Resistor Series Termination Resistor R Clock Load
Q
Data Latch
Figure 2. Input Logic Selection Through Jumper Option CPU/PCI Frequency Selection CPU output frequency is selected with I/O pins 8, 47, and 48. Refer to Table 1 for CPU/PCI frequency programming information. Alternatively, frequency selections are available through the serial data interface. Refer to Table 8, "Additional Frequency Selections through Serial Data Interface Data Bytes," on page 9. Output Buffer Configuration Clock Outputs All clock outputs are designed to drive serially terminated clock lines. The W127/W127-A outputs are CMOS-type, which provide rail-to-rail output swing. Crystal Oscillator The W127/W127-A requires one input reference clock to synthesize all output frequencies. The reference clock can be either an externally generated clock signal or the clock generated by the internal crystal oscillator. When using an external clock signal, pin X1 is used as the clock input and pin X2 is left open. The input threshold voltage of pin X1 is (VDDQ3)/2. The internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins X1 and X2. This forms a parallel resonant crystal oscillator circuit. The W127/W127-A incorporates the necessary feedback resistor and crystal load capacitors. Including typical stray circuit capacitance, the total load presented to the crystal is approximately 20 pF. For optimum frequency accuracy without the addition of external capacitors, a parallel-resonant mode crystal specifying a load of 20 pF should be used. This will typically yield reference frequency accuracies within 100 ppm. To achieve similar accuracies with a crystal calling for a greater load, external capacitors must be added such that the total load (internal, external, and parasitic capacitors) equals that called for by the crystal.
4
PRELIMINARY
Spread Spectrum Generator
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured.
W127/W127-A
The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is 0.5% of the center frequency. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1-0 in data byte 0 of the I2C data stream. Refer to Table 7 for more details.
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (+.0.5%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN. (-0.5%)
Figure 4. Typical Modulation Profile
5
100%
PRELIMINARY
Serial Data Interface
The W127/W127-A features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W127/W127-A initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two Table 5. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description
W127/W127-A
logic outputs of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 5 summarizes the control functions of the serial data interface. Operation Data is written to the W127/W127-A in ten bytes of eight bits each. Bytes are written in the order shown in Table 6.
Common Application
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused SDRAM DIMM socket or PCI slot. Provides CPU/PCI frequency selections. Frequency is changed in a smooth and controlled fashion. For alternate CPU devices and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Production PCB testing.
CPU Clock Frequency Selection
Output Three-state (Reserved)
Puts all clock outputs into a high-impedance state.
Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0.
Table 6. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W127/W127-A to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W127/W127-A is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W127/W127-A, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W127/W127-A, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal W127/W127-A registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 7, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 7
6
PRELIMINARY
Writing Data Bytes Each bit in the data bytes controls a particular device function except for the "reserved" bits, which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit 7. Table 7 gives the bit formats for registers located in Data Bytes 0-6. Table 7. Data Bytes 0-6 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 2 1-0 --Pin No. ----8, 47, 48 Pin Name ----FS0:2 Control Function (Reserved) SEL_2 SEL_1 SEL_0 BYT0 /FS# (Reserved) Bit 1 0 0 1 1 Bit 0 0 1 0 1 0 -Refer to Table 8 Refer to Table 8 Refer to Table 8 Frequency Controlled by external pins FS0:2 -Data Byte 0 -Bit Control 1
W127/W127-A
Table 8 details additional frequency selections that are available through the serial data interface. Table 9 details the select functions for Byte 0, bits 1 and 0.
Default 0 0 0 0 0 0 00
Frequency Controlled by SEL_0:2, above --
Function (See Table 9 for function details) Normal Operation (Reserved) Spread Spectrum On All Outputs Three-stated ----Low Low Low Low -Low -Low Low Low Low Low ----Active Active Active Active -Active -Active Active Active Active Active
Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0 -8 -14 13 12 11 9 -PCI_F -PCI4 PCI3 PCI2 PCI1 PCI0 (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 0 1 0 1 1 1 1 1 ----40 41 43 44 ----CPU3 CPU2 CPU1 CPU0 (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 0 0 0 0 1 1 1 1
7
PRELIMINARY
Table 7. Data Bytes 0-6 Serial Configuration Map (continued) Affected Pin Bit(s) 7 6 5 4 3 2 1 0 Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 5 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0 ----------------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) -----------------------3 -------REF (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable -------Low -------Active --17 18 20 21 26 27 --AGP_F AGP0 SDRAM11 SDRAM10 SDRAM9 SDRAM8 (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable --Low Low Low Low Low Low --Active Active Active Active Active Active Pin No. 29 30 31 32 34 35 37 38 Pin Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Control Function Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 0 Low Low Low Low Low Low Low Low Data Byte 3 Active Active Active Active Active Active Active Active Bit Control 1
W127/W127-A
Default 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
8
PRELIMINARY
Table 8. Additional Frequency Selections through Serial Data Interface Data Bytes[3] Input Conditions Data Byte 0, Bit 3 = 1 Bit 6 SEL_2 0 0 0 0 1 1 1 1 Bit 5 SEL_1 0 0 1 1 0 0 1 1 Bit 4 SEL_0 0 1 0 1 0 1 0 1 CPU Clocks (MHz) 68.5 112 95.25 100 83.3 75.0 124 66.6 AGP 68.5 74.6 63.5 66.6 55.53 75 82.6 66.6
W127/W127-A
Output Frequency PCI Clocks (MHz) 34.25 37.3 31.75 33.3 27.77 37.5 41.3 33.3
Table 9. Select Function for Data Byte 0, Bits 0:1 Input Conditions Data Byte 0 Function Normal Operation Spread Spectrum Three-state Bit 1 0 1 1 Bit 0 0 0 1 CPU0:3, SRAM0:11 Note 4 0.5% Hi-Z Output Conditions PCI_F, PCI0:4 Note 4 0.5% Hi-Z REF 14.318 MHz 14.318 MHz Hi-Z 48/24MHZ 48/24 MHz 48/24 MHz Hi-Z
Notes: 3. Configuration "110" is supported by W127-A only (see shaded row of Table 8). 4. CPU, SDRAM, and PCI frequency selections are listed in Table 1 and Table 8.
9
PRELIMINARY
How To Use the Serial Data Interface
Electrical Requirements Figure 5 illustrates electrical characteristics for the serial interface bus used with the W127/W127-A. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resistors on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data.
VDD
W127/W127-A
Although the W127/W127-A is a receive-only device (no data write-back capability), it does transmit an "acknowledge" data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance.
VDD
~ 2k SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE
~ 2k
SDCLK CLOCK IN CLOCK OUT N DATA IN DATA OUT
SDATA CLOCK IN N
SCLOCK DATA IN DATA OUT
SDATA
N
CHIP SET (SERIAL BUS MASTER TRANSMITTER)
CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER)
Figure 5. Serial Interface Bus Electrical Characteristics
10
PRELIMINARY
Signaling Requirements As shown in Figure 6, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met).
W127/W127-A
A write sequence is initiated by a "start bit" as shown in Figure 7. A "stop bit" signifies that a transmission has ended. As stated previously, the W127/W127-A sends an "acknowledge" pulse after receiving eight data bits in each byte as shown in Figure 8.
SDATA
SCLOCK
Valid Data Bit
Change of Data Allowed
Figure 6. Serial Data Bus Valid Data Bit
SDATA
SCLOCK Start Bit Stop Bit
Figure 7. Serial Data Bus Start and Stop Bit
11
Figure 8. Serial Data Bus Write Sequence
Signaling from System Core Logic Start Condition Slave Address (First Byte)
SDATA MSB 1 1 0 1 0 0 LSB 1 0 MSB
Stop Condition Command Code (Second Byte)
LSB
Byte Count (Third Byte)
MSB MSB
Last Data Byte (Last Byte)
LSB
SCLOCK
1
2
3
4
5
6
7
8
A
1
2
3
4
5
6
7
8
A
1
2
3
4
1
2
3
4
5
6
7
8
A
PRELIMINARY
SDATA
Signaling by Clock Device
Acknowledgment Bit from Clock Device
12 Figure 9. Serial Data Bus Timing Diagram
SDATA tSPF tLOW SCLOCK tSTHD tR tHIGH tF tDSU tDHD tSP tSPSU tSTHD t SPSU
W127/W127-A
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
W127/W127-A
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min.) Unit V C C C kV
Parameter VDDQ3, VIN TSTG TB TA ESDPROT
Description Voltage on any Pin with Respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection
3.3V DC Electrical Characteristics TA = 0C to +70C, VDDQ3 = VDDQ2 = 3.3V5% (3.135-3.465V)
Parameter Supply Current IDD Logic Inputs VIL VIH IIL IIH VOL VOH IOL Input Low Voltage Input High Voltage Input Low Current
[6]
Description Combined 3.3V Supply Current
Test Condition CPU0:3 = 66.6 MHz Outputs Loaded[5]
Min.
Typ. 290
Max.
Unit mA
0.8 2.0 20 5 IOL = 1 mA IOH = -1 mA CPU0:3 SDRAM0:11, AGP_F, AGP0 PCI_F, PCI0:4 REF 48/24MHz VOL = 1.5V 3.1 55 80 55 60 55 VOH = 1.5V 55 80 55 60 55 75 110 75 75 75 85 120 85 85 85 1.65 20 Pin X2 unconnected 30 105 155 105 90 105 125 175 125 110 125 50
V V A A mV V mA
Input High Current Output Low Voltage Output High Voltage Output Low Current
Clock Outputs
IOH
Output High Current
CPU0:3 SDRAM0:11, AGP_F, AGP0 PCI_F, PCI0:4 REF 48/24MHz
mA
Crystal Oscillator VTH CLOAD CIN,X1 X1 Input Threshold Voltage[7] Load Capacitance, Imposed on External Crystal[8] X1 Input Capacitance[9] V pF pF
Notes: 5. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 6. W127/127-A logic inputs have internal pull-up devices (not full CMOS level). 7. X1 input threshold voltage (typical) is VDD/2. 8. The W127/W127-A contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 20 pF; this includes typical stray capacitance of short PCB traces to crystal. 9. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
13
PRELIMINARY
W127/W127-A
3.3V DC Electrical Characteristics (continued) TA = 0C to +70C, VDDQ3 = VDDQ2 = 3.3V5% (3.135-3.465V)
Parameter CIN COUT LIN VIL VIH IIL IIH IOL CIN CSDATA CSCLOCK Description Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Input Low Voltage Input High Voltage Input Low Current Input High Current Sink Current into SDATA or SCLOCK, Open Drain N-Channel Device On Input Capacitance of SDATA and SCLOCK Total Capacitance of SDATA Bus Total Capacitance of SCLOCK Bus IOL = 0.3(VDDQ3) 6 10 400 400 VDDQ3 = 3.3V VDDQ3 = 3.3V 0.7VDDQ3 10 10 Test Condition Except X1 and X2 Min. Typ. Max. 5 6 7 0.3VDDQ3 Unit pF pF nH V V A A mA pF pF pF Pin Capacitance/Inductance
Serial Input Port
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5% (3.35-3.465V), fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU AGP Clock Outputs, CPU0:3, AGP_F, AGP0 (Lump Capacitance Test Load = 20 pF) CPU = 66.6 MHz Parameter tP f tH tL tR tF tD tJC tSK fST Period Frequency, Actual High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew Description Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V 5.2 5 1 1 45 4 4 55 250 250 3 Min. 15 66.6 Typ. Max. Unit ns MHz ns ns V/ns V/ns % ps ps ms
Frequency Stabilization from Assumes full supply voltage reached within 1 ms Power-up (cold start) from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 10 15
Zo
20
14
PRELIMINARY
AC Electrical Characteristics (continued)
SDRAM Clock Outputs, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
W127/W127-A
CPU = 66.6 MHz Parameter tP f tR tF tD tJC tSK tSK fST Period Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew Description Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V 100 500 3 1 1 45 Min. 15 66.6 4 4 55 250 Typ. Max. Unit ns MHz V/ns V/ns % ps ps ps ms
CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on rising edge at 1.5V. Frequency Stabilization from Power-up (cold start) AC Output Impedance Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 10 15
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PCI Clock Outputs, PCI_F and PCI0:4 (Lump Capacitance Test Load = 30 pF) CPU = 66.6 MHz Parameter tP f tH tL tR tF tD tJC tSK tO fST Period Frequency, Actual High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew AGP to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Description Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 1 12 12 1 1 45 4 4 55 250 250 3 3 Min. 30 33.3 Typ. Max. Unit ns MHz ns ns V/ns V/ns % ps ps ns ms
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PRELIMINARY
AC Electrical Characteristics (continued)
REF Clock Output (Lump Capacitance Test Load = 45 pF)
W127/W127-A
CPU = 66.6 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V 0.5 0.5 40 Min. Typ. 14.31818 2 2 60 1.5 Max. Unit MHz V/ns V/ns % ms
Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 30
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48-/24-MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66.6 MHz Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V 0.5 0.5 45 Min. Typ. Max. Unit MHz ppm 2 2 55 3 V/ns V/ns % ms 48.008/24.004 +167 57/17, 54/34
Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 30
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Serial Input Port Parameter fSCLOCK tSTHD tLOW tHIGH tDSU tDHD tR tF tSTSU tSPF tSP Description SCLOCK Frequency Start Hold Time SCLOCK Low Time SCLOCK High Time Data Set-up Time Data Hold Time (Transmitter should provide a 300-ns hold time to ensure proper timing at the receiver.) From 0.7VDD to 0.3VDD 4.0 4.7 50 Normal Mode Test Condition Min. 0 4.0 4.7 4.0 250 0 1000 300 Typ. Max. 100 Unit kHz s s s ns ns ns ns s s ns
Rise Time, SDATA and SCLOCK From 0.3VDD to 0.7VDD Fall Time, SDATA and SCLOCK Stop Set-up Time Bus Free Time between Stop and Start Condition Allowable Noise Spike Pulse Width
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PRELIMINARY
Ordering Information
Ordering Code W127 W127-A Document #: 38-00893 Pentium is a registered trademark of Intel Corporation. Package Name H Package Type 48-pin SSOP (300 mils)
W127/W127-A
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PRELIMINARY
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
W127/W127-A
Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102
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PRELIMINARY
Addendum: W127/W127-A Replaces W48S87-27A
W127/W127-A
The W127/W127-A is a pin-compatible replacement for the W48S87-27A with the following output frequency modifications (Refer to Table 1): 1. The 90-MHz CPU operation is changed to 95.25-MHz to support the K6 333-MHz chipset. 2. The 60-MHz CPU operation is changed to 124-MHz to support new motherboard designs.
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PRELIMINARY
Revision History
Document Title: W127/W127-A Document Number: 38-00893 REV. 0.4 0.90 ** ECN NO. --ISSUE DATE --ORIG. OF CHANGE ? ? IKA
W127/W127-A
DESCRIPTION OF CHANGE 1. Revision Control established 1. Distinguished between standard W127 device and highperformance W127-A option (see Table 1) 1. Converted to Cypress template, entered into DCON system
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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