View CLC114AJ-MLS_376000.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MICROCIRCUIT DATA SHEET MNCLC114A-X REV 0A0
QUAD, LOW-POWER VIDEO BUFFER
General Description
The CLC114 is a high-performance, closed-loop quad buffer intended for power sensitive applications. Requiring only 30mW of quiescent power dissipation per channel (+5V supplies), the CLC114 offers a small signal bandwidth of 200MHz (0.5Vpp) and a slew rate of 450V/uS. Designed specifically for high density crosspoint switch and analog multiplexer applications, the CLC114 offers excellent linearity and wide channel isolation (62dB @ 10MHz). Driving a typical crosspoint switch load, the CLC114 offers differential gain and phase performance of 0.08% and 0.1%; gain flatness through 30MHz is typically 0.1dB. With its patented closed-loop topology, the CLC114 has significant performance advantages over conventional open-loop designs. Applications requiring low output impedance and true unity gain stability through very high frequencies (active filters, dynamic load buffering, etc.) will benefit from the CLC114's superior performance. Original Creation Date: 08/03/98 Last Update Date: 01/12/99 Last Major Revision Date: 08/03/98
Industry Part Number
CLC114A
NS Part Numbers
CLC114AE-QML * CLC114AJ-MLS CLC114AJ-QML **
Prime Die
UB1417A
Controlling Document
5962-9233901MCA**, M2A*
Processing
(blank)
Subgrp Description
1 2 3 4 5 6 7 8A 8B 9 10 11 Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at Switching tests at Switching tests at Switching tests at
Temp ( oC)
+25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55
Quality Conformance Inspection
(blank)
1
MNCLC114A-X REV 0A0
MICROCIRCUIT DATA SHEET
Features
Closed-loop, quad buffer 200MHz small-signal bandwidth 450V/uS slew rate Low power, 30mW per channel (+5V sup.) 62dB channel isolation (10MHz) Specified for crosspoint switch loads
Applications
Video crosspoint switch driver Video disribution buffers Video switching buffers Video signaling multiplexing Instrumentation amps Active filters
2
MNCLC114A-X REV 0A0
MICROCIRCUIT DATA SHEET
(Absolute Maximum Ratings)
(Note 1) Supply Voltage (Vs) +7V dc Output Current (Iout) 35 mA Power Dissipation (Pd) (Note 2) 1.2W Lead Temperature (soldering, 10 seconds) +300 C Junction Temperature (Tj) +175 C Storage Temperature Range -65 C to +150 C Thermal Resistance Junction-to-ambient (ThetaJA) Ceramic DIP (Still Air) (500 LFPM) LCC (Still Air) (500 LFPM) Junction-to-case (ThetaJC) Ceramic DIP LCC Package Weight (Typical) Ceramic DIP LCC ESD Tolerance (Note 3)
97 C/W 59 C/W TBD TBD 20 C/W TBD
2160 mg TBD
2200V Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. The maximum power dissipation must be derated at elevated temperatures and is dictated by Tjmax (maximum junction temperature), ThetaJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is Pdmax = (Tjmax - TA)/ThetaJA or the number given in the Absolute Maximum Ratings, whichever is lower. Human body model, 100pF discharged through 1.5K Ohms.
Note 2:
Note 3:
Recommended Operating Conditions
Supply Voltage (Vs) +5V dc Ambient Operating Temperature Range (Ta) -55 C to +125 C
3
MNCLC114A-X REV 0A0
MICROCIRCUIT DATA SHEET
Electrical Characteristics
PARAMETERS
(The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vs = +5V dc, Av = +1, and load resistance (Rl) = 100 Ohms. -55 C < Ta < +125 C SYMBOL Iin PARAMETER Input Bias Current CONDITIONS NOTES PINNAME MIN -5 -4 -10 Voo Output Offset Voltage Rs = 50 Ohms -5.0 -8.0 -8.2 Tc (Iin) Average Input Bias Current Drift Average Offset Voltage Drift Total Supply Current No Load 1 1 1 1 Is -25 -62 -30 -40 MAX +5 +4 +10 +5.0 +8.0 +8.2 +25 +62 +30 +40 16.5 16.0 17.0 +Rin Input Resistance 1 1 1 Iout Output Current 1 1 1 PSRR Power Supply Rejection Ratio Small Signal Bandwidth +Vs = +4.5V to +5.0V, -Vs = -4.5V to -5.0V -3dB bandwidth, Vout < 0.5Vpp 3 3 LSBW GFPL Large Signal Bandwidth Gain Flatness Peaking Low Gain Flatness Peaking High -3dB bandwidth, Vout < 2.0Vpp At 0.1MHz to 30MHz, Vout < 0.5Vpp 3 GFPH 30MHz to 200MHz, Vout < 0.5Vpp 3 3 1 1.0 2.0 0.3 25 20 12 48 46 SSBW 135 120 135 70 0.2 0.3 0.4 0.7 1.3 UNIT uA uA uA mV mV mV SUBGROUPS 1 2 3 1 2 3
nA/C 2 nA/C 3 uV/C 2 uV/C 3 mA mA mA 1 2 3
Tc (Vio)
MOhms 1 MOhms 2 MOhms 3 mA mA mA dB dB MHz MHz MHz MHz dB dB dB dB dB 1 2 3 1, 3 2 4 5 6 4, 5, 6 4 5, 6 4 5 6
4
MNCLC114A-X REV 0A0
MICROCIRCUIT DATA SHEET
Electrical Characteristics
PARAMETERS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vs = +5V dc, Av = +1, and load resistance (Rl) = 100 Ohms. -55 C < Ta < +125 C SYMBOL GFR PARAMETER Gain Flatness Rolloff CONDITIONS 0.1MHz to 60 MHz, Vout < 0.5Vpp 3 3 HD2 2nd Harmonic Distortion 2 Vpp at 20 MHz 3 3 HD3 3rd Harmonic Distortion 2 Vpp at 20 MHz 3 3 SNF GA Input Noise Floor Small Signal Gain At > 1 MHz Rl = 100Ohms 1 1 1 ILIN Integral Endpoint Linearity At +1V, full scale At +1V, full scale At +1V, full scale XT Crosstalk At 10MHz 1 1 1 1, 2 1, 2 +Vout Output Voltage Swing Output Voltage Swing Input Capacitance Rl = 100Ohms 1 1 -Vout Rl = 100Ohms 1 1 Cin 1 1 Ro Output Impedance dc 1 1 SR Slew Rate Measured +1V with +4V Step Measured +1V with +4V Step TRS Rise and Fall Time 0.5V Step 1 1 1 1 200 180 2.8 3.0 58 60 +1.8 +1.0 -1.8 -1.0 3.0 3.5 3.5 5.0 0.96 0.95 0.6 0.5 1.0 NOTES PINNAME MIN MAX 0.8 1.0 0.8 -38 -38 -36 -50 -45 -50 -153 UNIT dB dB dB dBc dBc dBc dBc dBc dBc dBm 1Hz V/V V/V % % % dB dB V V V V pF pF SUBGROUPS 4 5 6 4 5 6 4 5 6 4, 5, 6 4, 5 6 4 5 6 4, 6 5 4, 5 6 4, 5 6 4 5, 6
Ohms 1, 2 Ohms 3 V/uS 9 V/uS 10, 11 nS nS 9, 11 10
5
MNCLC114A-X REV 0A0
MICROCIRCUIT DATA SHEET
Electrical Characteristics
PARAMETERS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vs = +5V dc, Av = +1, and load resistance (Rl) = 100 Ohms. -55 C < Ta < +125 C SYMBOL TRL PARAMETER Rise and Fall Time Settling Time 2V Step CONDITIONS NOTES 1 1 Ts 2V Step at 0.1% of the fixed value 1 1 2V Step at 0.01% of the fixed value 1 1 OS Overshoot 0.5V Step 1 1 PINNAME MIN MAX 7.0 8.0 15 20 30 40 10 15 UNIT nS nS nS nS nS nS % % SUBGROUPS 9, 11 10 9, 11 10 9, 11 10 9 10, 11
DC: PARAMETERS: DRIFT LIMITS
(The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vs = +5V dc, Av = +1. "Deltas not required on B-level product. Deltas required for S-level (-MLS) product as specified on Internal Processing Instructions (IPI)." (Note 4) Iin Is Voo Input Bias Current Total Supply Current Output Offset Voltage Note 1: Note 2: Note 3: Note 4: No Load Rs = 50 Ohms -0.5 -0.5 -0.25 +0.5 +0.5 +0.25 uA mA mV 1 1 1
If not tested, shall be guaranteed to the limits specified in table I herein. Three channels are driven simultaneously while observing the output of the undriven fourth channel. Group A sample tested only. The algebraic convention, whereby the most negative value is a minimum and most positive is a maximum, is used in this table. Negative current shall be defined as convential current flow out of a device terminal.
6
MNCLC114A-X REV 0A0
MICROCIRCUIT DATA SHEET
Graphics and Diagrams
GRAPHICS# 06375HRA1 07084HRA2 E20ARE J14ARH P000402A P000447A DESCRIPTION LCC (E), TYPE C, 20 TERMINAL (B/I CKT) CERDIP (J), 14 LEAD (B/I CKT) LCC (E), TYPE C, 20 TERMINAL(P/P DWG) CERDIP (J), 14 LEAD (P/P DWG) CERDIP (J),14 LEAD (PINOUT) LCC (E), TYPE C, 20 TERMINAL (PINOUT)
See attached graphics following this page.
7
IN1 N/C IN2 N/C IN3 N/C IN4
1 2 3 4 5 6 7
14 13 12 11 10 9 8
OUT1 +VCC OUT2 N/C OUT3 -VCC OUT4
CLC114J 14 - LEAD DIP CONNECTION DIAGRAM TOP VIEW P000402A
N
MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050
Out 1 1 20
3 4 In 2 5 6 In 3 7 8 9
2
19 18 17 16 15 14 Out 3 Out 2
10 In 4
11
12 Out 4
13 -Vcc
CLC114E 20 - LEAD LCC CONNECTION DIAGRAM TOP VIEW P000447A
MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050
N
+Vcc
In 1
MNCLC114A-X REV 0A0
MICROCIRCUIT DATA SHEET
Revision History
Rev
0A0
ECN #
Rel Date
Originator
Shaw Mead
Changes
Initial MDS Release
M0003193 01/12/99
8

▲Up To Search▲

Price & Availability of CLC114AJ-MLS

	To Download CLC114AJ-MLS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .