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CS5550
Two Channel, Low Cost A/D Converter
Features
Power Consumption <12 mW
Description
The CS5550 combines two ADCs and a serial interface on a single chip. The CS5550 has - with VD+ = 3.3 V on-chip functionality to facilitate offset and gain Adjustable Input Range on AIN1 GND-Referenced Signals with Single Supply calibration. The CS5550 features a bi-directional serial interface for communication with a On-chip 2.5 V Reference (25 ppm/C typ) microcontroller.
Simple Three-Wire Digital Serial Interface Power Supply Configurations
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V
ORDERING INFORMATION: CS5550-IS -40C to +85C
24-pin SSOP
VA+
RESET
VD+
AIN1+ AIN1-
+
10x,50x
-
4th Order Modulator
Digital Filter
Calibration Registers Config Register Serial Interface
CS SDI SDO SCLK INT
AIN2+ AIN2-
+ -
10x
2nd Order Modulator
Digital Filter
Output Registers
VREFIN
x1
VREFOUT
Voltage Reference
Clock Generator
AGND
XIN XOUT CPUCLK
DGND
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2004 (All Rights Reserved)
AUG 04 DS630PP2 1
(c)
CS5550
TABLE OF CONTENTS
1. PIN DESCRIPTION 4 2. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 5 ANALOG CHARACTERISTICS ................................................................................................ 5 VOLTAGE REFERENCE.......................................................................................................... 6 5 V DIGITAL CHARACTERISTICS........................................................................................... 7 3 V DIGITAL CHARACTERISTICS........................................................................................... 7 RECOMMENDED OPERATING CONDITIONS ....................................................................... 7 SWITCHING CHARACTERISTICS .......................................................................................... 8 2.1 Theory of Operation ......................................................................................................... 10 2.1.1 High-Rate Digital Low-Pass Filters ..................................................................... 10 2.1.2 Digital Compensation Filters ............................................................................... 10 2.1.3 Gain and Offset Adjustment ................................................................................ 10 2.2 Performing Measurements ............................................................................................... 10 2.3 CS5550 Linearity Performance ........................................................................................ 11 3. FUNCTIONAL DESCRIPTION ............................................................................................... 11 3.1 Analog Inputs ................................................................................................................... 11 3.2 Voltage Reference ........................................................................................................... 11 3.3 Oscillator Characteristics ................................................................................................. 11 3.4 Calibration ........................................................................................................................ 12 3.4.1 Overview of Calibration Process ......................................................................... 12 3.4.2 Calibration Sequence .......................................................................................... 12 3.4.3 Calibration Signal Input Level ............................................................................. 12 3.4.4 Input Configurations for Calibrations ................................................................... 12 3.4.5 Description of Calibration Algorithms .................................................................. 13 3.4.5.1 Offset Calibration Sequence ............................................................... 13 3.4.5.2 Gain Calibration Sequence ................................................................. 13 3.4.6 Duration of Calibration Sequence ....................................................................... 13 3.5 Interrupt ........................................................................................................................... 13 3.5.1 Typical use of the INT pin ................................................................................... 14 3.5.2 INT Active State .................................................................................................. 14 3.6 PCB Layout ...................................................................................................................... 14 4. SERIAL PORT OVERVIEW .................................................................................................... 15 4.1 Commands ....................................................................................................................... 15 4.2 Serial Port Interface ......................................................................................................... 18 4.3 Serial Read and Write ...................................................................................................... 18 4.3.1 Register Write ..................................................................................................... 18 4.3.2 Register Read ..................................................................................................... 18 4.4 System Initialization ......................................................................................................... 18 4.5 Serial Port Initialization .................................................................................................... 19 4.6 CS5550 Power States ...................................................................................................... 19 5. REGISTER DESCRIPTION .................................................................................................... 20 5.1 Configuration Register ...................................................................................................... 20 5.2 Offset Registers ................................................................................................................ 21 5.3 Gain Registers .................................................................................................................. 21 5.4 Cycle Count Register ........................................................................................................ 21 5.5 OUT1 and OUT2 Output Registers................................................................................... 22 5.6 FILT1, FILT2 Unsigned Output Register........................................................................... 22 5.7 Status Register and Mask Register .................................................................................. 22 5.8 Control Register ................................................................................................................ 23 6. PACKAGE DIMENSIONS ....................................................................................................... 24
2
DS630PP2
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LIST OF FIGURES
Figure 1. CS5550 Read and Write Timing Diagrams...................................................................... 9 Figure 2. Oscillator Connection..................................................................................................... 12 Figure 3. System Calibration of Gain. ........................................................................................... 12 Figure 4. System Calibration of Offset. ......................................................................................... 13 Figure 5. Example of Gain Calibration .......................................................................................... 13
Table 1. Change History Revision 1 2 Date 10 October 2003 19 August 2004 Initial release Update THD on AIN1. Update Noise on AIN2. Update PSRR on AIN2. Delete AC Calibration references. Changes
Contacting Cirrus Logic Support
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IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Microwire is a trademark of National Semiconductor Corporation.
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CS5550
1. PIN DESCRIPTION
Crystal Out CPU Clock Output Positive Power Supply Digital Ground Serial Clock Serial Data Ouput Chip Select Test Output Differential Analog Input Differential Analog Input Voltage Reference Output Voltage Reference Input XOUT CPUCLK VD+ DGND SCLK SDO CS TSTO AIN2+ AIN2VREFOUT VREFIN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 XIN SDI TSTO TSTO INT RESET TSTO TSTO AIN1+ AIN1VA+ AGND Crystal In Serial Data Input Test Output Test Output Interrupt Reset Test Output Test Output Differential Analog Input Differential Analog Input Positive Analog Supply Analog Ground
Clock Generator
Crystal Out Crystal In CPU Clock Output
1,24
XOUT, XIN - A gate inside the chip is connected to these pins and can be used with a crystal to provide the system clock for the device. Alternatively, an external (CMOS compatible) clock can be supplied into XIN pin to provide the system clock for the device. CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
2
Control Pins and Serial Data I/O
Serial Clock Input Serial Data Output Chip Select Reset Interrupt Serial Data Input
5 6 7 19 20 23
SCLK - A clock signal on this pin determines the input and output rate of the data for the SDI and SDO pins respectively. The SCLK pin will recognize clocks only when CS is low. SDO -The serial data port output pin. Its output is in a high impedance state when CS is high. CS - When low, the port will recognize SCLK. An active high on this pin forces the SDO pin to a high impedance state. CS should be changed when SCLK is low. RESET - When reset is taken low, all internal registers are set to their default states. INT - When INT goes low it signals that an enabled event has occurred. SDI - The serial data port input pin. Data will be input at a rate determined by SCLK.
Measurement and Reference Input
Differential Analog Inputs Voltage Reference Output Voltage Reference Input
9,10,15,16 11 12
AIN1+, AIN1-, AIN2+, AIN2- - Differential analog input pins. VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magnitude of 2.5 V and is referenced to the AGND pin on the converter. VREFIN - The input establishes the voltage reference for the on-chip modulator.
Power Supply Connections
Positive Digital Supply Digital Ground Positive Analog Supply Analog Ground Test Output 4
3 4,9,10 14
VD+ - The positive digital supply relative to DGND. DGND - The common-mode potential of digital ground must be equal to or above the common-mode potential of AGND. VA+ - The positive analog supply relative to AGND. AGND - The analog ground pin must be at the lowest potential.
13
8,17,18,21,22 TSTO - These pins are used for factory testing and must be left floating.
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2. CHARACTERISTICS/SPECIFICATIONS
* * * Min / Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25C. DGND = 0 V. All voltages with respect to 0 V.
ANALOG CHARACTERISTICS
Parameter Symbol (DC, 50, 60 Hz) CMRR Min 80 (Gain = 10) (Gain = 50) Both Gain Ranges (50, 60 Hz) (Gain = 10) (Gain = 50) (Gain = 10) (Gain = 50) (Gain = 10) (Gain = 50) (Note 1) (Note 1) {(AIN2+) - (AIN2-)} IC1 EII1 N1 AIN1 THD1 0 0 80 -0.25 30 30 0 65 -0.25 (50, 60 Hz) (Gain = 10) (Gain = 10) (Gain = 10) (Note 1) (Note 1) IC2 EII2 N2 VOS FSE 5 Typ 5 25 25 0.2 Max 500 100 VA+ -115 22.5 4.5 0.001 0.001 500 VA+ -70 150 0.01 0.01 Unit dB nV/C
mVP-P mVP-P
Accuracy (Both Channels)
Common Mode Rejection Offset Drift
Analog Inputs (AIN1)
Differential Input Voltage Range {(AIN1+) - (AIN1-)} Total Harmonic Distortion Common Mode + Signal Crosstalk with AIN2 at Full Scale Input Capacitance Effective Input Impedance (Note 2) Noise (Referred to Input)
dB V dB pF pF k k
Vrms Vrms
Accuracy Bipolar Offset Error
Full-Scale Error
VOS FSE AIN2 THD2
%F.S. %F.S.
mVP-P
Analog Inputs (AIN2)
Differential Input Voltage Range Total Harmonic Distortion Common Mode + Signal Crosstalk with AIN1 at Full Scale Input Capacitance Effective Input Impedance (Note 2) Noise (Referred to Input) dB V dB pF M
Vrms
Accuracy
Bipolar Offset Error Full-Scale Error Notes: 1. Applies after system calibration 2. Effective Input Impedance (EII) is determined by clock frequency (DCLK) and Input Capacitance (IC). EII = 1/(IC*DCLK/4). Note that DCLK = MCLK / K. %F.S. %F.S.
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ANALOG CHARACTERISTICS (Continued)
Parameter Dynamic Characteristics High Rate Filter Output Word Rate Input Sampling Rate Full Scale Calibration Range High Pass Filter Pole Frequency DCLK = MCLK/K (Note 3) -3 dB IA+ ID+ (VD+ = 5 V) ID+ (VD+ = 3.3 V) PSCA PSCD PSCD PC FSCR Symbol OWR Min 25 56 70 Typ DCLK/1024 DCLK/8 0.5 1.3 2.9 1.7 21 11.6 6.75 10 55 Max 100 30 Unit Hz Hz %F.S. Hz mA mA mA mW mW mW W dB dB dB
Power Supplies Power Supply Currents (Active State)
Power Consumption (Note 4)
Active State (VD+ = 5 V) Active State (VD+ = 3.3 V) Stand-by State Sleep State (Gain = 10) (Gain = 50) (Gain = 50)
Power Supply Rejection Ratio (AIN1) (50, 60 Hz)(Note 5) Power Supply Rejection Ratio (AIN2) (50, 60 Hz)(Note 5)
PSRR1 PSRR1 PSRR2
Notes: 3. The minimum FSCR is limited by the maximum allowed gain register value. 4. All outputs unloaded. All inputs CMOS level. 5. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply
voltage at VA+ and VD+ pins. The "+" and "-" input pins of both input channels are shorted to AGND. Then the CS5550 is commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel's inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB):
VOLTAGE REFERENCE
Parameter Symbol REFOUT (Note 6) TC VR VREFIN (Output Current 1 A Source or Sink) Min 2.4 Typ 25 6 Max 2.6 60 10 Unit V ppm/C mV
Reference Output
Output Voltage Temperature Coefficient Load Regulation
Reference Input
Input Voltage Range Input Capacitance Input CVF Current 2.4 2.5 4 25 2.6 V pF nA
Notes: 6. The voltage at VREFOUT is measured across the temperature range. From these measurements the following formula is used to calculate the VREFOUT Temperature Coefficient:.
TCVREF =
AMAX
1 - TAMIN
6
6
(
(
( (VREFOUTMAX - VREFOUTMIN) ( T VREFOUTAVG (

150 PSRR = 20 log -------V eq

( 1.0 x 10
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5 V DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage All Pins Except XIN and SCLK and RESET XIN SCLK and RESET Low-Level Input Voltage All Pins Except XIN and SCLK and RESET XIN SCLK and RESET High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance Iout = +5 mA Iout = -5 mA Symbol VIH 0.6 VD+ (VD+) - 0.5 0.8 VD+ VIL VOH VOL Iin IOZ Cout (VD+) - 1.0 1 5 0.8 1.5 0.2 VD+ 0.4 10 10 V V V V V A A pF V V V Min Typ Max Unit
3 V DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage All Pins Except XIN and SCLK and RESET XIN SCLK and RESET Low-Level Input Voltage All Pins Except XIN and SCLK and RESET XIN SCLK and RESET High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance Iout = +5 mA Iout = -5 mA Symbol VIH 0.6 VD+ (VD+) - 0.5 0.8 VD+ VIL VOH VOL Iin IOZ Cout (VD+) - 1.0 1 5 0.48 0.3 0.2 VD+ 0.4 10 10 V V V V V A A pF V V V Min Typ Max Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Positive Digital Power Supply Positive Analog Power Supply Negative Analog Power Supply Voltage Reference Specified Temperature Range Symbol VD+ VA+ AGND VREF TA Min 3.135 4.75 -0.25 -40 Typ 3.3 5 0 2.5 Max 5.25 5.25 0.25 +85 Unit V V V V C
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CS5550
SWITCHING CHARACTERISTICS
Master Clock Frequency Master Clock Duty Cycle CPUCLK Duty Cycle Rise Times (Note 9) Fall Times (Note 9) Parameter Internal Gate Oscillator (Note 7) (Note 8) Any Digital Input Except SCLK SCLK Any Digital Output Any Digital Input Except SCLK SCLK Any Digital Output XTAL = 4.096 MHz (Note 10) Symbol MCLK Min 2.5 40 40 200 200 50 50 100 100 Typ 4.096 50 50 60 20 20 20 Max 5 60 60 1.0 100 1.0 100 2 50 50 50 Unit MHz % % s s ns s s ns ms MHz ns ns ns ns ns ns ns ns ns
trise
tfall
Start-up Oscillator Start-Up Time Serial Port Timing Serial Clock Frequency Serial Clock SDI Timing CS Falling to SCLK Rising
tost SCLK t1 t2 t3 t4 t5 t6 t7 t8 t9
Pulse Width High Pulse Width Low
Data Set-up Time Prior to SCLK Rising Data Hold Time After SCLK Rising SCLK Falling Prior to CS Disable
SDO Timing CS Falling to SDI Driving
SCLK Falling to New Data Bit (hold time) CS Rising to SDO Hi-Z
Notes: 7. Device parameters are specified with a 4.096 MHz clock. If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. 8. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec. 9. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF. 10. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.
8
DS630PP2
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t6 t 4
LSB MSB LSB MSB - 1 MSB MSB - 1
CS
t3
t1
t2
SCLK t 5
LSB
SDI
LSB
MSB
MSB - 1
MSB
MSB - 1
Command Time 8 SCLKs High Byte Mid Byte
Low Byte
SDI Write Timing (Not to Scale)
CS
t7
MSB LSB MSB - 1 MSB MSB - 1
High Byte
Mid Byte
Low Byte
t
MSB LSB MSB - 1 LSB
9
SDO
t1 t 8
t2
SCLK
Figure 1. CS5550 Read and Write Timing Diagrams
LSB
SDI
MSB
MSB - 1
Command Time 8 SCLKs
Must strobe "SYNC0" command on SDI when reading each byte of data from SDO.
SDO Read Timing (Not to Scale)
CS5550
9
CS5550
2.1 Theory of Operation
The analog signals at the analog inputs are subject to the gains of the input PGAs. These signals are then sampled by the delta-sigma modulators at a rate of (MCLK/K) / 8. resent a normalized value between -1 and +1. The unsigned data in the CS5550 output registers represent normalized values between 0 and 1. A register value of 1 represents the maximum possible value. Note that a value of 1.0 is never actually obtained, the true maximum register value is [(2^23 - 1) / (2^23)] = 0.999999880791. After each A/D conversion, the CRDY bit will be asserted in the Status Register, and the INT pin will also become active if the CRDY bit is unmasked (in the Mask Register). The assertion of the CRDY bit indicates that new instantaneous samples have been collected. The unsigned FILT1 and FILT2 calculations are updated every N conversions (which is known as 1 "computation cycle") where N is the value in the Cycle Count Register. At the end of each computation cycle, the DRDY bit in the Mask Register will be set, and the INT pin will become active if the DRDY bit is unmasked. DRDY is set only after each computation cycle has completed, whereas the CRDY bit is asserted after each individual A/D conversion. When these bits are asserted, they must be cleared before they can be asserted again. If the Cycle Count Register value (N) is set to 1, all output calculations are instantaneous, and DRDY will indicate when instantaneous calculations are finished, just like the CRDY bit. For the FILT results to be valid, the Cycle-Count Register must be set to a value greater than 10. A computation cycle is derived from the master clock and its frequency is (MCLK/K)/(1024*N). Under default conditions with a 4.096 MHz clock at XIN, instantaneous A/D conversions are performed at a 4000 Hz rate, whereas FILT calculations are performed at a 1 Hz rate.
2.1.1 High-Rate Digital Low-Pass Filters
The data is then low-pass filtered, to remove high-frequency noise from the modulator output. The high rate filters on both channels are implemented as fixed Sinc3 filters.
2.1.2 Digital Compensation Filters
The data from both channels is then passed through two 4th-order IIR "compensation" filters, whose purpose is to correct (compensate) for the magnitude roll-off of the low-pass filtering operation. These filters "re-flatten" the magnitude response of the AIN1 and AIN2 channels over the relevant frequency range, by correcting for the magnitude roll-off effects that are induced by the Sinc3 low-pass filter stages.
2.1.3 Gain and Offset Adjustment
After the filtering, the digital codes are subjected to value adjustments, based on the values in the DC Offset Registers (additive) and the Gain Registers (multiplicative). These registers are used for calibration of the device (see Section 3.4, Calibration). After offset and gain, the data is available to the user by reading the appropriate registers.
2.2 Performing Measurements
The CS5550 performs measurements at an output word rate (sampling rate) of (MCLK/K) / 1024. From these instantaneous samples, FILT1 and FILT2 are computed, using the most recent N instantaneous samples that were acquired. All of the measurements/results are available as a percentage of full scale. The signed output format is a two's complement format, and the output data words rep-
10
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2.3 CS5550 Linearity Performance
FILT1 FILT2
1% - 100%
voltage signal that can be placed across the inputs, with no saturation is:
500mV P-P 2 2 = ~176.78mV RMS
Range (% of FS) Linearity
0.2% - 100%
0.1% of reading
0.1% of reading
Table 2. Available range of 0.1% output linearity, with default settings in the gain/offset registers.
which is ~70.7% of full-scale. So for sinusoidal inputs at the full scale peak-to-peak level the full scale registration is ~.707.
Table 2 lists the range of input levels (as a percentage of full-scale registration in the FILT Registers) over which the output linearity of the FILT Register measurements are guaranteed to be within 0.1%. This linearity is guaranteed for all available full-scale input voltage ranges. Note that until the CS5550 is calibrated (see Calibration) the accuracy of the CS5550 is not guaranteed to within 0.1%. But the linearity of any given sample of CS5550, before calibration, will be within 0.1% of reading over the ranges specified, with respect to the input voltage levels required to cause full-scale readings in the FILT Registers. Table 2 describes linearity + variation specs after the completion of each successive computation cycle.
3.2 Voltage Reference
The CS5550 is specified for operation with a +2.5 V reference between the VREFIN and AGND pins. The converter includes an internal 2.5 V reference (25 ppm/C drift) that can be used by connecting the VREFOUT pin to the VREFIN pin of the device. If higher accuracy/stability is required, an external reference can be used.
3.3 Oscillator Characteristics
XIN and XOUT are the input and output of an inverting amplifier to provide oscillation and can be configured as an on-chip oscillator, as shown in Figure 2. The oscillator circuit is designed to work with a quartz crystal or a ceramic resonator. To reduce circuit cost, two load capacitors C1 and C2 are integrated in the device. With these load capacitors, the oscillator circuit is capable of oscillation up to 20 MHz. To drive the device from an external clock source, XOUT should be left unconnected while XIN is driven by the external circuitry. There is an amplifier between XIN and the digital section which provides CMOS level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times. The CS5550 can be driven by an external oscillator ranging from 2.5 to 20 MHz, but the K divider value must be set such that the internal DCLK will run somewhere between 2.5 MHz and 5 MHz. The K divider value is set with the K[3:0] bits in the Configuration Register. As an example, if XIN = MCLK = 15 MHz, and K is set to 5, then DCLK is 3 MHz, which is a valid value for DCLK.
3. FUNCTIONAL DESCRIPTION 3.1 Analog Inputs
The CS5550 has two available full-scale differential input voltage ranges for AIN1. The input ranges are the maximum sinusoidal signals that can be applied to the analog inputs, yet theses values will not result in full scale registration. If the analog inputs are set to 500 mVP-P, only a 250 mVRMS signal will register full scale. Yet it would not be practical to inject a sinusoidal signal with a value of 250 mVRMS. When such a sine wave enters the higher levels of its positive crest region (over each cycle), the voltage level of this signal exceeds the maximum differential input voltage range of the input channels. The largest sine wave
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CS5550
quence is complete. The results of the calibration are now available in the appropriate gain/offset registers.
C1 Oscillator Circuit
XOUT
3.4.3 Calibration Signal Input Level
For gain calibrations, there is an absolute limit on the voltage levels that are selected for the gain calibration input signals. The maximum value that the gain register can attain is 4. Therefore, for either channel, if the voltage level of a gain calibration input signal is low enough that it causes the CS5550 to attempt to set either gain register higher than 4, the gain calibration result will be invalid and all CS5550 results obtained while performing A/D conversions will be invalid.
XIN C2
DGND
C1 = C2 = 22 pF
Figure 2. Oscillator Connection
3.4 Calibration 3.4.1 Overview of Calibration Process
The CS5550 offers digital calibration for offset and gain. Since both channels have separate offset and gain registers associated with them, system offset or system gain can be performed on either channel without the calibration results from one channel affecting the other.
3.4.4 Input Configurations for Calibrations
Figure 3 shows the basic setup for gain calibration. When performing a gain calibration a positive DC voltage level must be applied at the inputs of the AIN1 and/or AIN2 channels. This voltage should be set to the level that represents the absolute maximum instantaneous voltage level that needs to be measured across the inputs (including the maximum over-range level that must be accurately measured). For offset calibrations, the "+" and "-' pins of the AIN channels should be connected to their ground reference level. (See Figure 4.) Calibrating both offset and gain at the same time will cause undesirable calibration results.
External Con nections + F ull + Scale A IN+ XG AIN CM
3.4.2 Calibration Sequence
1. Before Calibration the CS5550 must be operating in its active state, and ready to accept valid commands. The `DRDY' bit in the Status Register should also be cleared. 2. Apply appropriate calibration signals to the inputs of the AIN1 and AIN2 channels (discussed next in Sections 3.4.3 and 3.4.4.) 3. Send the 8-bit calibration command to the CS5550 serial interface. Various bits within this command specify the exact type of calibration. The calibration command should not be sent to the device while performing A/D conversions. 4. After the CS5550 finishes the desired internal calibration sequence, the DRDY bit is set in the Status Register to indicate that the calibration se-
+
-
+ -
AIN-
Figure 3. System Calibration of Gain.
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Before Gain Calibration (Vgain Register = 1)
External Connections + AIN+ 0V + CM + AINXGAIN -250 mV -1.0000... 250 mV 230 mV
DC Signal
0.9999... 0.92 Output Register Values
+
INPUT 0 V SIGNAL
FILT Register = 230/250 = 0.92
Figure 4. System Calibration of Offset.
3.4.5 Description of Calibration Algorithms
Note: For proper calibration, the value of the AIN1/AIN2 Gain Registers must be set to default (1.0) before running the gain calibration(s), and the value in the Offset Registers must be set to default (0) before running offset calibrations. This can be accomplished by a software or hardware reset of the device. The values in the calibration registers do affect the results of the calibration sequences.
After Gain Calibration (Vgain Register changed to 1.0870)
230 mV
DC Signal
0.9999... Ouptut Register Values
INPUT 0 V SIGNAL FILT Register = 0.9999...
Figure 5. Example of Gain Calibration
3.4.5.1 Offset Calibration Sequence
The Offset Registers hold the negative of the simple average of N samples taken while the offset calibration was executed. The inputs should be grounded during offset calibration. The offset value is added to the signal path to nullify the DC offset in the system.
CS5550 during a given calibration sequence. For offset/gain calibrations, the calibration sequence takes at least N + 30 conversion cycles to complete. As N is increased, the accuracy of calibration results will increase.
3.5 Interrupt
The INT pin is used to indicate that an event has taken place in the converter that needs attention. These events inform the system about operation conditions and internal error conditions. The INT signal is created by combining the Status Register with the Mask Register. Whenever a bit in the Status Register becomes active, and the corresponding bit in the Mask Register is a logic 1, the INT signal becomes active. The interrupt condition is cleared when the bits of the Status Register are returned to their inactive state.
3.4.5.2 Gain Calibration Sequence
Based on the level of the positive DC calibration voltage applied across the "+' and "-" inputs, the CS5550 determines the Gain Register value by averaging the Digital Output Register's output signal values over one computation cycle (N samples) and then dividing this average into 1. Therefore, after the gain calibration, the Instantaneous Register will read at full-scale whenever the DC level of the input signal is equal to the level of the calibration signal applied to the inputs during the gain calibration (see Figure 5).
3.4.6 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines the number of conversions performed by the
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CS5550
3.5.1 Typical use of the INT pin
The steps below show how interrupts can be handled. * Initialization: Step I0 - All Status bits are cleared by writing FFFFFF (Hex) into the Status Register. Step I1 - The conditional bits which will be used to generate interrupts are then set to logic 1 in the Mask Register. Step I3 - Enable interrupts. * Interrupt Handler Routine: Step H0 - Read the Status Register. Step H1 - Disable all interrupts. Step H2 - Branch to the proper interrupt service routine. Step H3 - Clear the Status Register by writing back the read value in step H0. Step H4 - Re-enable interrupts. Step H5 - Return from interrupt service routine. This handshaking procedure insures that any new interrupts activated between steps H0 and H3 are not lost (cleared) by step H3.
3.5.2 INT Active State
The behavior of the INT pin is controlled by the IMODE and IINV bits of the Configuration Register. The pin can be active low (default), active high, active on a return to logic 0 (pulse-low), or active on a return to logic 1 (pulse-high). If the interrupt output signal format is set for either pulse-high or pulse-low, the duration of the INT pulse will be at least one DCLK cycle (DCLK = MCLK / K).
3.6 PCB Layout
The CS5550 should be placed entirely over an analog ground plane with both the AGND and DGND pins of the device connected to the analog plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip.
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4. SERIAL PORT OVERVIEW
The CS5550's serial port incorporates a state machine with transmit/receive buffers. The state machine interprets 8-bit command words on the rising edge of SCLK. Upon decoding of the command word, the state machine performs the requested command or prepares for a data transfer of the addressed register. Request for a read requires an internal register transfer to the transmit buffer, while a write waits until the completion of 24 SCLKs before performing a transfer. The internal registers are used to control the ADC's functions. All registers are 24-bits in length. The CS5550 is initialized and fully operational in its active state upon power-on. After a power-on, the device will wait to receive a valid command (the first 8-bits clocked into the serial port). Upon receiving and decoding a valid command word, the state machine instructs the converter to either perform a system operation, or transfer data to or from an internal register. The user should refer to the "Commands" section to decode all valid commands.
4.1 Commands
All command words are 1 byte in length. Any 8-bit word that is not listed in this section should be considered an illegal command word, and issuing any such illegal command word to the serial interface can result in unpredictable operation of the CS5550. Commands that write to a register must be followed by 3 bytes of register data. Commands that read data can be chained with other commands (e.g., while reading data, a new command can be sent to SDI which can execute before the original read is completed). This allows for "chaining" commands.
4.1.1 Start Conversions
B7 1 B6 1 B5 1 B4 0 B3 C B2 0 B1 0 B0 0
This command indicates to the state machine to begin acquiring measurements and calculating results. The device has two modes of acquisition. C= Modes of acquisition/measurement 0 = Perform a single computation cycle 1 = Perform continuous computation cycles
4.1.2 SYNC0 Command
B7 1 B6 1 B5 1 B4 1 B3 1 B2 1 B1 1 B0 0
This command is the end of the serial port re-initialization sequence. The command can also be used as a NOP command. The serial port is resynchronized to byte boundaries by sending three or more consecutive SYNC1 commands followed by a SYNC0 command.
4.1.3 SYNC1 Command
B7 1 B6 1 B5 1 B4 1 B3 1 B2 1 B1 1 B0 1
This command is part of the serial port re-initialization sequence. The command also serves as a NOP command.
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4.1.4 Power-Up/Halt
B7 1 B6 0 B5 1 B4 0 B3 0 B2 0 B1 0 B0 0
If the device is powered-down, this command will power-up the device. When powered-on, no computations will be running. If the part is already powered-on, all computations will be halted.
4.1.5 Power-Down and Software Reset
B7 1 B6 0 B5 0 B4 S1 B3 S0 B2 0 B1 0 B0 0
The device has two power-down states to conserve power. If the chip is put in stand-by state, all circuitry except the analog/digital clock generators is turned off. In the sleep state, all circuitry except the digital clock generator and the instruction decoder is turned off. Waking up the CS5550 out of sleep state requires more time than out of stand-by state, because of the extra time needed to re-start and re-stabilize the analog clock signal. S1,S0 Power-down state 00 = Software Reset 01 = Halt and enter stand-by power saving state. This state allows quick power-on time 10 = Halt and enter sleep power saving state. This state requires a slow power-on time 11 = Reserved
4.1.6 Calibration
B7 1 B6 1 B5 0 B4 A2 B3 A1 B2 0 B1 G B0 O
The device has the capability of performing a system offset calibration and gain calibration. Offset and gain calibrations should NOT be performed at the same time (must do one after the other). Proper inputs must be supplied to the device before initiating calibration. A2,A1 Designates calibration channel 00 = Not allowed 01 = Calibrate the AIN1 channel 10 = Calibrate the AIN2 channel 11 = Calibrate AIN1 channel and AIN2 channel simultaneously Designates gain calibration 0 = Normal operation 1 = Perform gain calibration Designates offset calibration 0 = Normal operation 1 = Perform offset calibration
G
O
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4.1.7 Register Read/Write
B7 0 B6 W/R B5 RA4 B4 RA3 B3 RA2 B2 RA1 B1 RA0 B0 0
The Read/Write command informs the state machine that a register access is required. During a read operation, the addressed register is loaded into the device's output buffer and clocked out by SCLK. During a write operation, the data is clocked into the input buffer and, and all 24 bits are transferred to the addressed register on the 24th SCLK. W/R Write/Read control 0 = Read register 1 = Write register Register address bits (bits 1 through 5) of the read/write command. RA[4-0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Abbreviation Config AIN1DCoff AIN1gn AIN2DCoff AIN2gn Cycle Count Res OUT1 OUT2 Res Res FILT1 FILT2 Res Res Status Res Res Res Res Res Res Res Res Res Res Mask Res Ctrl Res Res Res Name/Description Configuration Register AIN1 Offset Register AIN1 Gain Register AIN2 Offset Register AIN2 Gain Register Number of A/D conversions used in one computation cycle (N)). Reserved AIN1 Output Register AIN2 Output Register Reserved Reserved Computed Filtered value for AIN1 Computed Filtered value for AIN2 Reserved Reserved Status Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Mask Register Reserved Control Register Reserved Reserved Reserved
RA[4:0] Address 0 1 2 3 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
These registers are for internal use only. For proper device operation, the user must not attempt to write to these registers.
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4.2 Serial Port Interface
The CS5550's serial interface consists of four control lines, which have the following pin-names: CS, SDI, SDO, and SCLK. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied to logic 0, the port can function as a three wire interface. SDI, Serial Data In, is the data signal used to transfer data to the converters. SDO, Serial Data Out, is the data signal used to transfer output data from the converters. The SDO output will be held at high impedance any time CS is at logic 1. SCLK, Serial Clock, is the serial bit-clock which controls the shifting of data to or from the ADC's serial port. The CS pin must be held at logic 0 before SCLK transitions can be recognized by the port logic. To accommodate opto-isolators SCLK is designed with a Schmitt-trigger input to allow an opto-isolator with slower rise and fall times to directly drive the pin. Additionally, SDO is capable of sinking or sourcing up to 5 mA to directly drive an opto-isolator LED. SDO will have less than a 400 mV loss in the drive voltage when sinking or sourcing 5 mA. must be followed by 24 bits of data. To write the Configuration Register, the user would transmit the command (0x40) to initiate a write to the Configuration Register. The CS5550 will then acquire the serial data input from the (SDI) pin when the user pulses the serial clock (SCLK) 24 times. Once the data is received, the state machine writes the data to the Configuration Register and then waits to receive another valid command.
4.3.2 Register Read
When a read command is initiated, the serial port will start transferring register content bits serial (MSB first) on the SDO pin for the next 8, 16, or 24 SCLK cycles. Command words instructing a register read may be terminated at 8-bit boundaries (e.g., read transfers may be 8, 16, or 24 bits in length). Also data register reads allow "command chaining". This means that the micro-controller is allowed to send a new command while reading register data. The new command will be acted upon immediately and could possibly terminate the first register read. For example, if the user is only interested in acquiring the 16 most significant bits of data from the first read, then the user can begin to strobe a second read command on SDI after the first 8 data bits have been read from SDO. During the read cycle, the SYNC0 command (NOP) should be strobed on the SDI port while clocking the data from the SDO port.
4.3 Serial Read and Write
The state machine decodes the command word as it is received. Data is written to and read from the CS5550 by using the Register Read/Write command. Figure 1 illustrates the serial sequence necessary to write to, or read from the serial port's buffers. As shown in Figure 1, a transfer of data is always initiated by sending the appropriate 8-bit command (MSB first) to the serial port (SDI pin).
4.4 System Initialization
A software or hardware reset can be initiated at any time. The software reset is initiated by sending the command 0x80. A hardware reset is initiated when the RESET pin is forced low with a minimum pulse width of 50 ns. The RESET signal is asynchronous, requiring no MCLKs for the part to detect and store a reset event. The RESET pin is a Schmitt Trigger input, which allows it to accept slow rise times and/or noisy control signals. Once the RESET pin is inacDS630PP2
4.3.1 Register Write
When a command involves a write operation, the serial port will continue to clock in the data bits (MSB first) on the SDI pin for the next 24 SCLK cycles. Command words instructing a register write
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tive, the internal reset circuitry remains active for 5 MCLK cycles to insure resetting the synchronous circuitry in the device. The modulators are held in reset for 12 MCLK cycles after RESET becomes inactive. After a hardware or software reset, the internal registers (some of which drive output pins) will be reset to their default values on the first MCLK received after detecting a reset event. The internal register values are also set to their default values after initial power-on of the device. The CS5550 will then assume its active state. (The term active state, as well as the other defined power states of the CS5550, are described in Section 4.6). Refer to Section 5 of the data sheet to see the default register values for any particular device register. 2) Hardware Reset (drive RESET pin low, for at least 10 s, then drive back to high). 3) Issue the Serial Port Initialization Sequence, which is performed by clocking 3 (or more) SYNC1 command bytes (0xFF) followed by one SYNC0 command byte (0xFE).
4.6 CS5550 Power States
Active state denotes the operation of CS5550 when the device is fully powered on (not in sleep state or stand-by state). Performing either of the following actions will insure that the CS5550 is operating in the active state: 1) Power on the CS5550. (Or if the device is already powered on, recycle the power.) 2) Software Reset 3) Hardware Reset In addition to the actions listed above, note that if the device is in sleep state or in stand-by state, the action of waking up the device out of sleep state or stand-by state (by issuing the Power-Up/Halt command) will also insure that the device is set into active state. In order to send the Power-Up/Halt command to the device, the serial port must be initialized. Therefore, after applying power to the CS5550, a hardware reset should always be performed.
4.5 Serial Port Initialization
It is possible for the serial interface to become unsynchronized, with respect to the SCLK input. If this occurs, any attempt to clock valid CS5550 commands into the serial interface will result in either no operation or unexpected operation, because the CS5550 will not interpret the input command bits correctly. The CS5550's serial port must then be re-initialized. To initialize the serial port, any of the following actions can be performed: 1) Drive (assert) the CS pin low [or if CS pin is already low, drive the pin high, then back to low].
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5. REGISTER DESCRIPTION
1. "Default**" => bit status after power-on or reset 2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
5.1 Configuration Register
Address: 0
23 15 7 22 14 6 2HPF 21 13 5 1HPF 20 12 IMODE 4 iCPU 19 11 IINV 3 K3 18 10 2 K2 17 9 1 K1 16
gain
8 0 K0
Default** = 0x000001 gain Sets the gain of the AIN1 PGA 0 = gain is 10 1 = gain is 50
[IMODE IINV] Soft interrupt configuration bits. Select the desired pin behavior for indication of an interrupt. 00 = active low level (default) 01 = active high level 10 = falling edge (INT is normally high) 11 = rising edge (INT is normally low) 1HPF Control the use of the High Pass Filter on AIN1 Channel. 0 = HPF disabled 1 = HPF enabled Control the use of the High Pass Filter on AIN2 Channel. 0 = HPF disabled 1 = HPF enabled Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPUCLK should not be active during the sample edge. 0 = normal operation (default) 1 = minimize noise when CPUCLK is driving rising edge logic Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range between 1 and 16. Note that a value of "0000" will set K to 16 (not zero).
2HPF
iCPU
K[3:0]
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5.2 Offset Registers
Address: 1 (Offset Register - AIN1) 3 (Offset Register - AIN2)
LSB
MSB
-(2 )
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2-23
Default** = 0.000 The Offset Registers are initialized to zero on reset, allowing the device to function and perform measurements. The register is loaded after one computation cycle with the offset when the proper input is applied and the Calibration Command is received. DRDY will be asserted at the end of the calibration. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range full scale. The numeric format of this register is two's complement notation.
5.3 Gain Registers
Address: 2 (Gain Register - AIN1) 4 (Gain Register - AIN2)
LSB
MSB
21
20
2-1
2-2
2-3
2-4
2-5
2-6
.....
2-16
2-17
2-18
2-19
2-20
2-21
2-22
Default** = 1.000 The Gain registers are initialized to 1.0 on reset, allowing the device to function and perform measurements. The Gain registers hold the result of the gain calibrations. If a calibration is performed, the register is loaded after one computation cycle with the system gain when the proper DC input is applied and the Calibration Command is received. DRDY will be asserted at the end of the calibration. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range 0.0 Gain < 3.9999.
5.4 Cycle Count Register
Address: 5
MSB LSB
223
222
221
220
219
218
217
216
.....
26
25
24
23
22
21
20
Default** = 4000 The Cycle Count Register value (denoted as `N') determines the length of one computation cycle. During continuous conversions, the computation cycle frequency is (MCLK/K)/(1024N) where MCLK is master clock input frequency (into XIN/XOUT pins), K is clock divider value (as specified in the Configuration Register), and N is Cycle Count Register Value.
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5.5 OUT1 and OUT2 Output Registers
Address:
7 (AIN1 Output Register) 8 (AIN2 Output Register)
LSB
MSB
-(2 )
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2-23
These signed registers contain the last value of the measured results of AIN1 and AIN2. The results will be within the range of -1.0 AIN1,AIN2 < 1.0. The value is represented in two's complement notation, with the binary point place to the right of the MSB (MSB has a negative weighting). These values are 22 bits in length. The two least significant bits, (located at the far right-side) have no meaning, and will always have a value of "0".
5.6 FILT1, FILT2 Unsigned Output Register
Address:
11 (AIN1 Filtered Output Register) 12 (AIN2 Filtered Output Register)
LSB
MSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
.....
2-18
2-19
2-20
2-21
2-22
2-23
2-24
These unsigned registers contain the last values of FILT1 and FILT2. The results are in the range of 0.0 FILT1,FILT2 < 1.0. The value is represented in (unsigned) binary notation, with the binary point place to the left of the MSB. These results are updated after each computation cycle.
5.7 Status Register and Mask Register
Address: Address:
23 DRDY 15 7
15 (Status [Clear] Register) 26 (Mask Register)
22 14 FOR1 6 21 13 FOR2 5 20 CRDY 12 4 OD2 19 11 3 OD1 18 10 2 17 OR1 9 1 16 OR2 8 0 IC
Default** = 0x000000 (Status [Clear] Register 0x000000 (Mask Register) The Status [Clear] Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause the bit to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature the user can simply write back to the Status [Clear] Register to clear the bits that have been seen, without concern of clearing any newly set bits. Even if a status bit is masked to prevent the interrupt (at the time that the status bit is asserted), the status bit will still be set in (both of) the Status Registers so the user can poll the status. The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will allow the corresponding bit in the Status Register to activate the INT pin when the status bit becomes active. DRDY Data Ready. When running in single or continuous conversion acquisition mode, this bit will indicate the end of computation cycles. When running calibrations, this bit indicates that the calibration sequence has completed, and the results have been stored in the offset or gain AIN Output Out of Range. Set when the magnitude of the calibrated output is too large or too
OR1, OR2
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small to fit in the AIN Output Register. CRDY OD1, OD2 Conversion Ready. Indicates a new conversion is ready. Modulator oscillation detect. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the Input Voltage Range. FILT out of range. Set when the calibrated voltage value is too large for the FILT register. Invalid Command. Normally logic 1. Set to logic 0 if the host interface is strobed with an 8-bit word that is not recognized as one of the valid commands (see Section 4.1, Commands).
FOR1, FOR2 IC
5.8 Control Register
Register Address: 28
23 15 7 22 14 6 21 13 5 20 12 4 INTOD 19 11 3 18 10 2 NOCPU 17 9 1 NOOSC 16 8 0
Default** = 0x000000 INTOD NOCPU NOOSC 1 = Converts INT output to open drain configuration. 1 = saves power by disabling the CPUCLK external drive pin. 1 = saves power by disabling the crystal oscillator circuit.
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6. PACKAGE DIMENSIONS
24L SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E
L
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025 0
INCHES NOM -0.006 0.068 -0.323 0.307 0.209 0.026 0.03 4
MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041 8
MIN -0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.13 1.73 -8.20 7.80 5.30 0.65 0.75 4
NOTE MAX 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03 8
2,3 1 1
JEDEC #: MO-150
Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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