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Industrial Temperature K4F661612D, K4F641612D
4M x 16bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low pow er) are optional features of this family. All of this family have CAS -before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-width, low power consumption and high reliability.
CMOS DRAM
FEATURES
* Part Identification - K4F661612D-TI/P(3.3V, 8K Ref.) - K4F641612D-TI/P(3.3V, 4K Ref.) * Fast Page Mode operation * 2CAS Byte/Word Read/Write operation * CAS-before-RAS refresh capability * RAS-only and Hidden refresh capability * Self-refresh capability (L-ver only) * Fast parallel test mode capability * Active Power Dissipation Unit : mW Speed -45 -50 -60 8K 324 288 252 4K 468 432 396 * LVTTL(3.3V) compatible inputs and outputs * Early Write or output enable controlled write * JEDEC Standard pinout * Available in Plastic TSOP(II) packages * +3.3V 0.3V power supply * Industrial Temperature operating ( -40~85C )
* Refresh Cycles Part NO. K4F661612D* K4F641612D Refresh cycle 8K 4K Refresh time Normal 64ms L-ver 128ms
RAS UCAS LCAS W Control Clocks Vcc Vss
FUNCTIONAL BLOCK DIAGRAM
VBB Generator
Refresh Control Refresh Counter Memory Array 4,194,304 x 16 Cells
Sens e Am ps & I/O
* Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS -before-RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Refresh Timer
Row Decoder
Lower Data in Buffer Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer
DQ0 to DQ7
OE D Q8 to DQ15
* Performance Range Speed -45 -50 -60
tRAC
45ns 50ns 60ns
tCAC
12ns 13ns 15ns
tRC
80ns 90ns 110ns
tPC
31ns 35ns 40ns
A0~A12 (A0~A11)*1 A0~A8 (A0~A9)*1
Row Address Buffer Col. Address Buffer Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Industrial Temperature K4F661612D, K4F641612D CMOS DRAM
PIN CONFIGURATION (Top Views)
* K4F661612D-T * K4F641612D-T VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC W RAS N.C N.C N.C N.C A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C VSS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
(400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product
Pin Name A0 - A12 A0 - A11 DQ0 - 15 VSS RAS UCAS LCAS W OE VCC N.C
Pin function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Data Output Enable Power(+3.3V) No Connection
Industrial Temperature K4F661612D, K4F641612D
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VC C supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg PD IOS Address Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +150 1 50 Units V V C W mA
CMOS DRAM
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VC C VSS VIH VIL Min 3.0 0 2.0 -0.3 *2
(Voltage referenced to Vss, T A= -40 to 85C)
Typ 3.3 0 Max 3.6 0 Vcc+0.3 0.8
*1
Units V V V V
*1 : Vcc+1.3V at pulse width 15ns which is measured at VCC *2 : -1.3 at pulse width 15ns which is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVCC+0.3V, all other pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VVOUTVCC ) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL =2mA) Symbol II(L) Min -5 Max 5 Units uA
IO(L) VOH VOL
-5 2.4 -
5 0.4
uA V V
Industrial Temperature K4F661612D, K4F641612D
DC AND OPERATING CHARACTERISTICS
Symbol Power Speed -45 -50 -60 Dont care -45 -50 -60 -45 -50 -60 Dont care -45 -50 -60 Dont care Dont care
CMOS DRAM
(Continued)
Max K4F661612D 90 80 70 1 1 90 80 70 70 60 50 0.5 200 130 120 110 350 350 K4F641612D 130 120 110 1 1 130 120 110 70 60 50 0.5 200 130 120 110 350 350 Units mA mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA uA uA
ICC1
Dont care
ICC2
Normal L
ICC3
Dont care
ICC4
Dont care
ICC5
Normal L
ICC6 ICC7 ICCS
Dont care L L
ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tR C=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC =min.) ICC4* : Fast Page Mode Current (RAS=VIL , UCAS or LCAS, Address cycling @ tPC=min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC -0.2V) ICC6* : CAS-Before- RAS Refresh Current (RAS and UCAS or LCAS cycling @tR C=min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VC C-0.2V, Input low voltage(VIL )=0.2V, UCAS , LCAS=CAS -before-RAS cycling or 0.2V, W, OE=V IH , Address=Dont care, DQ=Open, TRC=31.25us ICCS : Self Refresh Current RAS=UCAS =LCAS=0.2V, W=OE=A0 ~ A12(A11)=VC C-0.2V or 0.2V, DQ0 ~ DQ15=V CC-0.2V, 0.2V or Open
*Note :
ICC1 , ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS =VIL. In I CC4, address can be changed maximum once within one fast page mode cycle time, tPC.
Industrial Temperature K4F661612D, K4F641612D
CAPACITANCE
(TA=25C, VCC=3.3V, f=1MHz)
Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, UCAS, LCAS, W, OE ] Output capacitance [DQ0 - DQ15] Symbol CIN1 CIN2 CDQ Min Max 5 7 7 Units pF pF pF
CMOS DRAM
AC CHARACTERISTICS
Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS
(-40CTA85C, See note 2)
-45 Min Max Min 90 133 45 12 23 0 0 1 25 45 12 45 12 18 13 5 0 8 0 8 23 0 0 0 8 8 13 12 0 10 10K 33 22 10K 13 50 0 0 1 30 50 13 50 13 20 15 5 0 10 0 10 25 0 0 0 10 10 15 13 0 10 10K 37 25 10K 13 50 50 13 25 0 0 1 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 0 10 10K 45 30 10K 13 50 -50 Max Min 110 153 60 15 30 -60 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 16 9,19 9,19 8 8 13 13 4 10 3,4,10 3,4,5 3,10 3 6 2
Test condition : VCC =3.3V0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Symbol Units Note
tR C tRWC tRAC tCAC tAA tCLZ tOFF tT tR P tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tW P tRWL tCWL tD S tD H
80 115
Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time
Industrial Temperature K4F661612D, K4F641612D
AC CHARACTERISTICS
Parameter Refresh period (Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Fast Page mode cycle time Fast Page mode read-modify-write cycle time CAS precharge time (Fast page cycle) RAS pulse width (Fast page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh)
CMOS DRAM
-45 Min Max 64 128 0 32 67 43 48 5 10 5 26 31 70 9 45 28 12 12 0 12 10 15 10 10 100 80 -50 13 13 0 13 10 15 10 10 100 90 -50 13 200K 35 76 10 50 30 13 13 0 15 10 15 10 10 100 110 -50 13 200 0 36 73 48 53 5 10 5 30 40 85 10 60 35 15 200 Min -50 Max 64 128 0 38 83 53 60 5 10 5 35 Min -60 Max 64 128 ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ns ns 20,21,22 20,21,22 20,21,22 11 11 6 3 14 3 17 18 7 7,15 7 7
(Continued)
Symbol Units Note
tREF tREF tWCS tCWD tRWD tAWD tCPWD
t CSR
tCHR tRPC tCPA tPC tPRWC tC P tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tRASS tRPS tCHS
Industrial Temperature K4F661612D, K4F641612D
TEST MODE CYCLE
Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column Address to RAS lead time CAS to W delay time RAS to W delay time Column Address to W delay time Fast Page mode cycle time Fast Page mode read-modify-write cycle time RAS pulse width (Fast page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -45 Max Min 95 138 50 17 28 50 17 17 50 28 37 72 48 36 75 50 200K 31 17 17 17 18 18 10K 10K 55 18 18 55 30 41 78 53 40 81 55 200K 35 18 18 20 55 18 30 10K 10K 65 20 20 65 35 43 88 58 45 90 65 200K 40 20 -50 Max Min 115 160 65 20 35 10K 10K -60 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 7 7 7 3,4,10,12 3,4,5,12 3,10,12 Units
CMOS DRAM
( Note 11 )
Note
tR C tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tPC tPRWC tRASP tCPA tOEA tOED tOEH
85 120
Industrial Temperature K4F661612D, K4F641612D
NOTES
1. An initial pause of 200A is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is achieved. 2. VIH(min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and V IL (max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL load and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC . 5. Assumes that tRCDtRCD(max). 6. tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCStWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD tCWD (min), tRWDtRWD(min) and tAWD tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in read-modifywrite cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
CMOS DRAM
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
K4F64(6)1612D Truth Table
RAS H L L L L L L L L LCAS X H L H L L H L L UCAS X H H L L H L L L W X X H H H L L L H OE X X L L L H H H H DQ0 - DQ7 Hi-Z Hi-Z DQ-OUT Hi-Z DQ-OUT DQ-IN DQ-IN Hi-Z DQ8-DQ15 Hi-Z Hi-Z Hi-Z DQ-OUT DQ-OUT DQ-IN DQ-IN Hi-Z STATE Standby Refresh Byte Read Byte Read Word Read Byte Write Byte Write Word Write -
Industrial Temperature K4F661612D, K4F641612D
13. tASC , tCAH are referenced to the earlier CAS falling edge. 14. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. 15. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle. 16. tCWL is specified from W falling edge to the earlier CAS rising edge. 17. tCSR is referenced to earlier CAS falling before RAS transition low. 18. tCHR is referenced to the later CAS rising high after RAS transition low.
CMOS DRAM
RAS
LCAS
UCAS
tCSR
tCHR
19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge.
LCAS UCAS
tD S
DQ0 ~ DQ15 Din
tDH
20. If tRASS 100us, then RAS precharge time must use tRPS instead of tR P. 21. For RAS -only-Refresh and Burst CAS -before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 22. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
Industrial Temperature K4F661612D, K4F641612D
WORD READ CYCLE
CMOS DRAM
tR C tR A S
V IH RAS V IL -
tR P
tCRP tRCD
V IH UCAS V IL -
tC S H tR S H tCAS tC S H tCRP
tCRP
V IH LCAS V IL -
tR C D
tR S H tC A S
tC R P
tR A D tASR
V IH A V IL -
tRAH
tA S C
tR A L tCAH
COLUMN ADDRESS
ROW ADDRESS
tR C S
V IH W V IL -
tRCH tRRH
tA A
V IH OE V IL -
tOEA t CAC tC L Z tOFF tOEZ
DATA-OUT
DQ0 ~ DQ7 V OH -
tR A C OPEN
V OL -
t CAC
DQ8 ~ DQ15 V OH -
tO F F tO E Z
DATA-OUT
tR A C OPEN
tC L Z
V OL -
D o n t c a r e
Undefined
Industrial Temperature K4F661612D, K4F641612D
LOWER BYTE READ CYCLE
N O T E : D IN = O P E N
CMOS DRAM
tR C tRAS
V IH RAS V IL -
t RP
tC R P
V IH UCAS V IL -
t RPC
t CSH tCRP tRCD
V IH LCAS V IL -
tR S H tCAS
tR A D tASR
V IH A V IL -
tRAH
tASC
tR A L tC A H
COLUMN ADDRESS
ROW ADDRESS
tRCS
V IH W V IL -
tRCH tR R H
t OFF tA A
V IH OE V IL -
tOEZ tOEA
t CAC
DQ0 ~ DQ7 V OH -
tC L Z tR A C OPEN
DATA-OUT
V OL -
DQ8 ~ DQ15 V OH V OL -
OPEN
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
UPPER BYTE READ CYCLE
N O T E : D IN = O P E N
CMOS DRAM
tR C tR A S
V IH RAS V IL -
tR P
tC S H tC R P
V IH UCAS V IL -
tR C D
tR S H tC A S
tC R P
tC R P
V IH LCAS V IL -
tR P C
tR A D tRAL tA S R t RAH tA S C tCAH
COLUMN ADDRESS
V IH A V IL -
ROW ADDRESS
tRCS
V IH W V IL -
tRCH tRRH
t OFF tAA
V IH OE V IL -
tOEZ tO E A
DQ0 ~ DQ7 V OH -
OPEN
V OL -
tC A C
DQ8 ~ DQ15 V OH -
tC L Z tR A C OPEN
DATA-OUT
V OL -
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
WORD WRITE CYCLE ( EARLY WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
tRC tR A S
V IH RAS V IL -
t RP
tCRP tR C D
V IH UCAS V IL -
t CSH tR S H tCAS tCRP
tCRP tR C D
V IH LCAS V IL -
tC S H tR S H tC A S tR A D tC R P
tASR
V IH A V IL -
tRAH
tA S C tCAH
COLUMN ADDRESS
tR A L
ROW ADDRESS
tWCS
V IH W V IL -
tWCH tW P
V IH OE V IL -
DQ0 ~ DQ7 V IH -
tD S
tDH
DATA-IN
V IL -
tD S
DQ8 ~ DQ15 V IH -
tDH
DATA-IN
V IL -
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
tR C t RAS
V IH RAS V IL -
t RP
tCRP
V IH UCAS V IL -
t RPC
tCRP tR C D
V IH LCAS V IL -
tC S H tR S H tC A S tC R P
t RAD tASR
V IH A V IL -
tRAH
tASC tCAH
COLUMN ADDRESS
tR A L
ROW ADDRESS
tWCS
V IH W V IL -
tWCH tW P
V IH OE V IL -
tD S
DQ0 ~ DQ7 V IH DATA-IN V IL -
tDH
DQ8 ~ DQ15 V IH V IL -
D o n t c a r e
Undefined
Industrial Temperature K4F661612D, K4F641612D
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
t RC tRAS
V IH RAS V IL -
tR P
tCRP
V IH UCAS V IL -
tC S H tRCD t RSH tC A S tCRP
tCRP
V IH LCAS V IL -
t RPC
tRAD tASR
V IH A V IL -
tR A H
tASC t CAH
COLUMN ADDRESS
t RAL
ROW ADDRESS
tWCS
V IH W V IL -
tW C H tW P
V IH OE V IL -
DQ0 ~ DQ7 V IH V IL -
tD S
DQ8 ~ DQ15 V IH DATA-IN V IL -
tD H
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
tR C tRAS
V IH RAS V IL -
t RP
tCRP tR C D
V IH UCAS V IL -
t CSH t RSH tCAS tCRP
tCRP tR C D
V IH LCAS V IL -
tC S H t RSH tC A S tR A D tC R P
tASR
V IH A V IL -
tRAH
tA S C tC A H
COLUMN ADDRESS
tR A L
ROW ADDRESS
tC W L tRWL
V IH W V IL -
tW P
V IH OE V IL -
tOED tD S
tOEH
DQ0 ~ DQ7 V IH -
t DH
DATA-IN
V IL -
tD S
DQ8 ~ DQ15 V IH -
t DH
DATA-IN
V IL -
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
LOWER BYTE WRITE CYCLE ( O E CONTROLLED WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
tRC tR A S
V IH RAS V IL -
tR P
tCRP
V IH UCAS V IL -
t RPC
tCRP
V IH LCAS V IL -
t CSH tRCD t RSH tCAS tCRP
tRAD tASR
V IH A V IL -
tR A H
tA S C tC A H
COLUMN ADDRESS
t RAL
ROW ADDRESS
tCWL tRWL
V IH W V IL -
tWP
V IH OE V IL -
tOED
tO E H
DQ0 ~ DQ7 V IH -
tD S
tD H
DATA-IN
V IL -
DQ8 ~ DQ15 V IH V IL -
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
UPPER BYTE WRITE CYCLE ( O E CONTROLLED WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
t RC tR A S
V IH RAS V IL -
tR P
tCRP tR C D
V IH UCAS V IL -
tC S H tRSH tC A S tCRP
tCRP
V IH LCAS V IL -
t RPC
tRAD tASR
V IH A V IL -
tR A H
tA S C t CAH
COLUMN ADDRESS
t RAL
ROW ADDRESS
tCWL
V IH W V IL -
tRWL tW P
V IH OE V IL -
tOED
tOEH
DQ0 ~ DQ7 V IH V IL -
DQ8 ~ DQ15 V IH -
tD S
tD H
DATA-IN
V IL -
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
WORD READ - MODIFY - WRITE CYCLE
CMOS DRAM
tR W C tR A S
V IH RAS V IL -
tR P
tC R P
V IH UCAS V IL -
tRCD
tR S H tCAS
tC R P
V IH LCAS V IL -
tRCD
tR S H tCAS
tRAD t CSH tASR t RAH tASC tC A H
V IH A V IL -
ROW ADDR
COLUMN ADDRESS
tR W L tA W D tC W D
V IH W V IL -
tCWL tW P
tR W D tO E A
V IH OE V IL -
tCLZ tC A C tAA
DQ0 ~ DQ7 V I/OH V I/OL -
tO E D t DS tO E Z
VALID DATA-OUT VALID DATA-IN
t DH
t RAC
t CLZ tC A C tAA
DQ8 ~ DQ15 V I/OH V I/OL -
tO E D tD S tO E Z
VALID DATA-OUT VALID DATA-IN
t DH
t RAC
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
LOWER-BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tR W C tR A S
V IH RAS V IL -
tR P
tCRP
V IH UCAS V IL -
t RPC
tC R P
V IH LCAS V IL -
tRCD
tR S H t CAS
tR A D t CSH tA S R t RAH tASC t CAH
V IH A V IL -
ROW ADDR
COLUMN ADDRESS
tAWD tCWD
V IH W V IL -
tRWL tC W L tW P
tR W D tO E A
V IH OE V IL -
tCLZ tC A C tAA
DQ0 ~ DQ7 V I/OH V I/OL -
tO E D tD S tO E Z
VALID DATA-OUT VALID DATA-IN
tDH
t RAC
DQ8 ~ DQ15 V I/OH -
OPEN
V I/OL -
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
UPPER-BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tR W C tRAS
V IH RAS V IL -
tR P
tCRP
V IH UCAS V IL -
tRCD
tR S H tC A S
tCRP
V IH LCAS V IL -
tR P C
t RAD tC S H tASR tRAH tASC tCAH
V IH A V IL -
ROW ADDR
COLUMN ADDRESS
tR W L tA W D tCWD
V IH W V IL -
tC W L tW P
tR W D tOEA
V IH OE V IL -
DQ0 ~ DQ7 V I/OH V I/OL -
OPEN
t CLZ t CAC tAA
DQ8 ~ DQ15 V I/OH V I/OL -
tOED t DS tOEZ
VALID DATA-OUT VALID DATA-IN
tDH
tR A C
D o n t c a r e
Undefined
Industrial Temperature K4F661612D, K4F641612D
FAST PAGE MODE WORD READ CYCLE
CMOS DRAM
tRASP
V IH RAS V IL o
tR P
tC S H tC R P tRCD
V IH UCAS V IL -
tR H C P tP C tC P tC A S tCAS tP C tC P tC A S t PC tC P tC A S t RPC
t RAL tC R P tRCD
V IH LCAS V IL -
tC P tC A S t CAS
t CP tC A S
tC P tC A S
tR P C
tASR
V IH A V IL -
t RAD t RAH tASC
ROW ADDR
t CAH
tASC
tC A H
tASC
tC A H
COLUMN ADDR
tASC
tC A H
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRCS tRCS
V IH W V IL -
tR C S tRCH
tRCS tRCH
tR R H
tRCH
tR C H
t CAC tA A tAA
V IH OE V IL -
t CAC tAA tCPA tAA t CPA tO E A
tC A C
tCPA tO E A
tOEA
tOEA
tCAC
DQ0 ~ DQ7 V OH VALID
tOFF tOEZ
DATA-OUT VALID DATA-OUT
tOFF tOEZ
VALID DATA-OUT
tO F F tOEZ
VALID DATA-OUT
tO F F tO E Z
tR A C
V OL -
tCLZ tC A C
DQ8 ~ DQ15 V OH VOL VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT
tOFF tOEZ
tOFF tOEZ
tO F F tOEZ
tO F F tO E Z
tR A C
t CLZ
D o n t c a r e
Undefined
Industrial Temperature K4F661612D, K4F641612D
FAST PAGE MODE LOWER BYTE READ CYCLE
CMOS DRAM
tR A S P
V IH RAS V IL o
tR P
tR H C P tCRP t RPC
V IH UCAS V IL -
t CSH tC R P tR C D t PC tC P tC A S tC A S t PC tC P tC A S tPC tC P
t RAL
tRPC tC A S
V IH LCAS V IL -
tR A D tASR
V IH A V IL -
t RAH
ROW
tASC
t CAH
tASC
t CAH
tA S C
tC A H
COLUMN ADDR
tA S C
tC A H
COLUMN
COLUMN ADDRESS
COLUMN ADDRESS
ADDR
ADDRESS
tR C S
V IH W V IL -
tR C S tRCH tRCH
tRCS tRCH
tRCS tR C H
tRRH
tC A C tAA tAA
V IH OE V IL -
tC A C tA A tC P A tO E A tA A tC P A tO E A
tCAC
tC P A tOEA
tO E A
t CAC
DQ0 ~ DQ7 VOH VOL -
tO F F tOEZ
VALID DATA-OUT VALID DATA-OUT
tO F F tO E Z
VALID DATA-OUT
t OFF tOEZ
VALID DATA-OUT
t OFF tOEZ
t RAC
tC L Z
DQ8 ~ DQ15 V OH -
OPEN
V OL -
D o n t c a r e
Undefined
Industrial Temperature K4F661612D, K4F641612D
FAST PAGE MODE UPPER BYTE READ CYCLE
CMOS DRAM
tR A S P
V IH RAS V IL o
tR P
t CSH tCRP tR C D
V IH UCAS V IL -
tR H C P t PC tC P tC A S tC A S t PC tC P tC A S tPC tC P tC A S t RPC
tC R P t RPC
V IH LCAS V IL -
t RAL tRAD tASR tR A H
ROW ADDR
tASC
tC A H
tASC
t CAH
tASC
tCAH
COLUMN ADDR
tASC
tC A H
COLUMN
V IH A V IL -
COLUMN ADDRESS
COLUMN ADDRESS
ADDRESS
tRCS
V IH W V IL -
tRCS tR C H tR C H
tRCS tR C H
tRCS tR C H
tRRH
tC A C tAA tAA
V IH OE V IL -
tC A C tA A tCPA tO E A tA A tC P A tO E A
tCAC
tC P A tOEA
tO E A
DQ0 ~ DQ7 V OH -
OPEN
V OL -
tC A C
DQ8 ~ DQ15 V OH VOL -
tO F F tO E Z
VALID DATA-OUT VALID DATA-OUT
tO F F tO E Z
VALID DATA-OUT
t OFF tOEZ
VALID DATA-OUT
tO F F tO E Z
t RAC
tCLZ
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
tRASP
V IH RAS V IL o
tR P tRHCP
tC R P tRCD
V IH UCAS V IL -
tP C tC P tCAS tC A S
o
t PC t CP
t RSH tC R P tCAS
tCRP tRCD
V IH LCAS V IL -
tP C tC P tCAS t RAD tCSH tC A S
o
t PC tC P
tRSH
tC A S
t RAL t CAH tASC t CAH
o
COLUMN ADDRESS
tA S R
V IH A V IL -
tR A H
ROW ADDR
tASC
tASC
t CAH
COLUMN ADDRESS
COLUMN ADDRESS
o
tW C S
V IH W V IL -
tWCH
tWCS
tWCH tW P
o
tWCS
tWCH tWP
tW P
V IH OE V IL -
o
o
DQ0 ~ DQ7 V IH V IL -
tD S
t DH
VALID DATA-IN
tD S
tD H
o
VALID DATA-IN
tD S
tD H
VALID DATA-IN
o
tD S
DQ8 ~ DQ15 V IH V IL -
t DH
VALID DATA-IN
tD S
tD H
o
VALID DATA-IN
tD S
VALID
tD H
DATA-IN
o
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
tRASP
V IH RAS V IL o
t RP tR H C P
t RPC tC R P
V IH UCAS V IL o
tC R P tRCD
V IH LCAS V IL -
tPC t CP tC A S t RAD tC S H tC A S
o
tPC tC P
t RSH
tCAS
tR A L tC A H tA S C tCAH
o
COLUMN ADDRESS
tASR
V IH A V IL -
tR A H
ROW ADDR
tASC
tA S C
t CAH
COLUMN ADDRESS
COLUMN ADDRESS
o
tWCS
V IH W V IL -
tWCH
tWCS
tW C H tW P
o
tW C S
tW C H tW P
tWP
V IH OE V IL -
o
o
DQ0 ~ DQ7 V IH V IL -
t DS
tD H
VALID DATA-IN
t DS
t DH
o
VALID DATA-IN
t DS
tDH
VALID DATA-IN
o
DQ8 ~ DQ15 V IH V IL -
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
t RASP
V IH RAS V IL o
t RP tRHCP
tCRP tR C D
V IH UCAS V IL -
tP C t CP tC A S tCAS
o
tP C t CP
t RSH
t CAS
tR P C tC R P
V IH LCAS V IL -
tR A D tC S H tA S R
V IH A V IL -
t RAL t CAH tASC tCAH
o
COLUMN ADDRESS
t RAH
ROW
tASC
tA S C
tCAH
COLUMN ADDRESS
COLUMN ADDRESS
ADDR.
o
tWCS
V IH W V IL -
tWCH
tWCS
tW C H tW P
o
tWCS
tW C H tW P
tW P
V IH OE V IL -
o
o
DQ0 ~ DQ7 V IH V IL o o
DQ8 ~ DQ15 V IH V IL -
tD S
t DH
VALID DATA-IN
t DS
tDH
o
VALID DATA-IN
t DS
tD H
VALID DATA-IN
o
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE
CMOS DRAM
tR P tR A S P
V IH RAS V IL -
tC S H
tC R P tR C D
V IH UCAS V IL -
tP R W C tC P tCAS
tR S H tCRP tC A S
tC R P tR C D
V IH LCAS V IL -
tC P tC A S tC A S
tCRP
t RAD t RAH tASR tASC
V IH A V IL ROW ADDR COL. ADDR
t RAL t CAH tASC
COL. ADDR
t CAH
tRCS tC W L
V IH W V IL -
tRCS tWP
tR W L tC W L tW P tCWD tAWD tCPWD
tCWD tAWD tRWD tOEA tOED tC A C tAA tO E Z tDH tD S tO E A
V IH OE V IL -
tCAC tAA
tOED t DH tD S tOEZ
DQ0 ~ DQ7 V I/OH V I/OL -
t RAC
tC L Z
VALID DATA-OUT
t CLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
tOED tC A C tA A
DQ8 ~ DQ15 V I/OH V I/OL -
t CAC tD H tD S tA A
tOED tDH t DS tO E Z
tOEZ
tR A C
tCLZ
VALID DATA-OUT
t CLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
D o n t c a r e
Undefined
Industrial Temperature K4F661612D, K4F641612D
FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRASP
V IH RAS V IL -
tR P
t CSH
tCRP
V IH UCAS V IL -
tR P C
tCRP tRCD
V IH LCAS V IL -
tPRWC t CP tC A S tR A D tR A H tC A H tASC
COL. ADDR
t RSH tC R P tC A S
tR A L tASC
COL. ADDR
tASR
V IH A V IL ROW ADDR
t CAH
tR W L tRCS
V IH W V IL -
tCWL tW P tCWD tAWD tRWD tOEA tO E D tC A C tAA tOEZ tD H tD S
tRCS
tC W L tW P tC W D tA W D tC P W D
V IH OE V IL -
tOEA tOED tDH t DS tOEZ
tC A C tA A
DQ0 ~ DQ7 V I/OH V I/OL -
tRAC
tCLZ
VALID DATA-OUT
t CLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
DQ8 ~ DQ15 V I/OH -
OPEN
V I/OL -
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tR A S P
V IH RAS V IL -
t RP
tC S H
tC R P tR C D
V IH UCAS V IL -
tP R W C tC P t CAS
tRSH t CAS
tCRP
tC R P
V IH LCAS V IL -
tRPC
t RAD t RAH tASR tASC
V IH A V IL ROW ADDR COL. ADDR
tC A H tASC
COL. ADDR
t RAL t CAH
tRCS tCWL
V IH W V IL -
tR W L tRCS tWP tCWD tAWD tRWD tO E A tO E A tCWD tAWD tCPWD tC W L tWP
V IH OE V IL -
DQ0 ~ DQ7 V I/OH V I/OL -
OPEN
tOED tCAC tA A
DQ8 ~ DQ15 V I/OH V I/OL -
tOED t CAC t DH tA A tD H tOEZ tD S
tOEZ
tD S
t RAC
t CLZ
VALID DATA-OUT
t CLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
D o n t c a r e
Undefined
Industrial Temperature K4F661612D, K4F641612D
RAS - ONLY REFRESH CYCLE
N O T E : W , O E , D I N = D o n t c a r e D OUT = O P E N t RC
V IH RAS V IL -
CMOS DRAM
tR P
tRAS t RPC tCRP
V IH UCAS V IL -
tCRP
V IH LCAS V IL -
tA S R
V IH A V IL -
tRAH
ROW ADDR
CAS - BEFORE - RAS REFRESH CYCLE
N O T E : O E , A = D o n t c a r e
tR C tR P
V IH RAS V IL -
tRAS
tR P
tC R P tC P
V IH UCAS V IL -
tR P C
t CSR
tC H R
tC P
V IH LCAS V IL -
t CSR
tC H R
DQ0 ~ DQ7 V OH -
t OFF OPEN
V OL DQ8 ~ DQ15 V OH -
OPEN
V OL -
tW R P
tWRH
V IH W V IL -
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
HIDDEN REFRESH CYCLE ( READ )
CMOS DRAM
t RC
V IH RAS V IL -
t RC tR P tRAS t RP
tRAS
tC R P
V IH UCAS V IL -
tRCD
t RSH
tCHR
tCRP
V IH LCAS V IL -
tRCD
t RSH
tC H R
tR A D tR A L tASR
V IH A V IL -
tRAH
tA S C
tC A H
COLUMN ADDRESS
ROW ADDRESS
tR C S
V IH W V IL -
tW R H
tA A
V IH OE V IL -
tO E A
tO F F t CAC tC L Z
DQ0 ~ DQ7 V OH -
tR A C OPEN
tOEZ
DATA-OUT
V OL -
DQ8 ~ DQ15 V OH -
OPEN
V OL -
D A T ADIA T A - O U T -N
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
HIDDEN REFRESH CYCLE ( WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
t RC
V IH RAS V IL -
tR P
tRC tRAS
tR P
tRAS
tC R P
V IH UCAS V IL -
tR C D
t RSH
tCHR
tC R P
V IH LCAS V IL -
tR C D
tR S H
tCHR
tR A D tR A L tASR
V IH A V IL -
t RAH
tASC
tC A H
COLUMN ADDRESS
ROW ADDRESS
tW R H tW R P tWCS
V IH W V IL -
tWCH tW P
V IH OE V IL -
t DS
DQ0 ~ DQ7 V IH DATA-IN V IL -
t DH
tD S
DQ8 ~ DQ15 V IH DATA-IN V IL -
tD H
D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
CAS - BEFORE - RAS SELF REFRESH CYCLE
N O T E : O E , A = D o n t c a r e
CMOS DRAM
tR P
V IH RAS V IL -
tRASS
tR P S
t RPC tC P
V IH UCAS V IL -
tR P C t CSR tC H S
tC P
V IH LCAS V IL -
t CSR
tC H S
DQ0 ~ DQ7 VOH -
tO F F OPEN
VOL DQ8 ~ DQ15 V OH -
OPEN
VOL -
tW R P
tWRH
V IH W V IL -
TEST MODE IN CYCLE
N O T E : O E , A = D o n t c a r e
tRC tR P
V IH RAS V IL -
tR P tRAS
tCRP tC P
V IH UCAS V IL -
t RPC tC S R tCHR
tC P
V IH LCAS V IL -
tC S R tCHR
V IH W V IL DQ0 ~ DQ15 V OH -
tWTS
tWTH
t OFF OPEN
VOL D o n t c a r e Undefined
Industrial Temperature K4F661612D, K4F641612D
PACKAGE DIMENSION
50 TSOP(II) 400mil
Units : Inches (millimeters)
CMOS DRAM
0 . 45 5 (1 1 .5 6 )
0 . 47 1 (1 1 .9 6 )
0 .4 0 0 (1 0 . 1 6)
0.004 (0.10) 0.010 (0.25)
0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.047 (1.20) MAX 0.010 (0.25) TYP 0~8 0.034 (0.875) 0.0315 (0.80) 0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45) 0.018 (0.45) 0.030 (0.75)
O

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