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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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Features
* Supports AT&T TR62411 Stratum 4 and Stratum 4 Enhanced for DS1 interfaces and for ETSI ETS 300 011, TBR 4, TBR 12, and TBR 13 for E1 interfaces * Supports ITU-T G.812 Type IV clocks for 1.544kbit/s interfaces and 2.048kbit/s interface
*
Introduction
PT7A4408/4408L employs a digital phase-locked loop (DPLL) to provide timing and synchronizing signals for multitrunk T1 and E1 primary rate transmission links, and for STS-3/OC3 links. The STBUS clock and framing signals are phase-locked to input reference signals of either 2.048 MHz, 1.544MHz or 8 kHz. The PT7A4408/4408L meets the requirements for AT&T TR62411 Stratum 4 and Stratum 4 Enhanced, and ETSI ETS 300 011 in jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range, phase slope, etc. The PT7A4408/4408L operates in Normal or Free-
Provides C1.5, C3, C2, C4, C8, C6, C16 and C19 output clock signals Provides five kinds of 8kHz ST-BUS framing signals Input reference frequency 1.544MHz, 2.048MHz or 8kHz selectable Normal or Free-Run operating modes available Power supply: 5V (4408) and 3.3V(4408L)
*
*
* *
Applications
* Synchronization and timing control for multitrunk T1 and E1 systems, STS-3/OC3 systems
* *
run Mode.
Ordering Information
Pa r t Nu m b er PT7A4408J PT7A4408LJ Pa ck a ge 44-Pin PLCC 44-Pin PLCC
ST-BUS clock and frame pulse sources Primary Trunk Rate Converters
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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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Contents
Features ....................................................................................................................................................... 1 Applications ................................................................................................................................................ 1 Introduction ................................................................................................................................................. 1 Ordering Information .................................................................................................................................. 1 Block Diagram ............................................................................................................................................ 3 Pin Information ........................................................................................................................................... 4 Pin Assignment ..................................................................................................................................... 4 Pin Configuration ................................................................................................................................. 4 Pin Description ..................................................................................................................................... 5 Functional Description ................................................................................................................................ 7 Overall Operation ................................................................................................................................. 7 Modes of Operation .............................................................................................................................. 9 Applications Information ...................................................................................................................... 9 Detailed Specifications .............................................................................................................................. 10 Definitions of Critical Performance Specifictions ............................................................................... 10 Absolute Maximum Ratings ............................................................................................................... 11 Recommended Operating Conditions ................................................................................................. 11 DC Electrical and Power Supply Characteristics ................................................................................ 12 AC Electrical Characteristics .............................................................................................................. 13 Mechanical Specifications ......................................................................................................................... 26 Note .......................................................................................................................................................... 27
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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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Block Diagram
Figure 1. Block Diagram
RST
VCC
GND
OSCi OSCo TCK TDI TMS TRST TDO
Master Clock
Loop Filter
APLL
DPLL
IEEE 1149.1a
Output Interface Circuit
REF
Phase Detector
ACKi ACKo C1.5 C2 C3 C4 C6 C8 C16 C19 F0 F8 F16 RSP TSP
Mode Control
Feedback Frequency Select MUX
MS
FS1
FS2
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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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Pin Information
Pin Assignment
Table 1. Pin Assignment
G r ou p Chip Clock Power & Ground Clock and Framing Outputs Control Signals Reference Inputs IEEE 1149.1a Symb ol OSCi, OSCo, ACKi, ACKo VCC, AVDD, GND, AGND C1.5, C3, C2, C4, C6, C8, C16, C19, F0, F8, F16, RSP, TSP MS, FS1, FS2, RST REF TCK, TDI, TMS, TRST, TDO F u n ct ion Clock Power Clock and Framing Signals Control Reference Clock IEEE 1149.1a Interface
Pin Configuration
Figure 2. Pin Configuration
6
4
3
2
1
44
43
42
41
VCC OSCo OSCi AGND F16 RSP F0 TSP F8 C1.5 AVDD
40
5
REF NC TRST NC TCK GND TMS RST TDI FS1 FS2
7 8 9 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 18 19 28
39 38 37 36
44-Pin PLCC
35 34 33 32 31 30 29
TEST NC NC MS TDO NC NC NC GND GND NC
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C3 C2 C4 C19 ACKi GND ACKo C8 C16 C6 VCC
Top View
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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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Pin Description
Table 2. Pin Description
P in 1, 23, 30, 31 2 3, 5, 29, 3234, 37, 38 4 6 7, 28 8 9 10 Na m e GND TCK NC TRST REF VCC OSCo OSCi AGND Typ e Ground Digit a l G r ou n d I I I Power O I Test C lock (T T L I n p u t ): Provides the clock to the JTAG test logic. This pin is internally pulled up to VCC. No con n ect ion Test R eset (T T L I n p u t ): Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is internally pulled down to GND. R efer en ce (T T L ): The reference signal, internally pulled down to GND. Power su p p ly 5V for PT7A4408J. 3.3V for PT7A4408LJ O scilla t or m a st er clock ou t p u t (C MO S): Output of 20MHz master clock O scilla t or m a st er clock in p u t (C MO S): Input of 20MHz master clock (can be connected directly to a clock source) Descr ip t ion
Ground An a log G r ou n d F r a m e p u lse ST-BUS 16.384Mb /s (C MO S): 8kHz frame signal with 61ns low level pulse that marks the beginning of a ST-BUS frame, typically used for ST-BUS opetation at 8.192Mb/s. See figure 10. R eceive Syn c P u lse (C MO S O u t p u t ). This is an 8kHz 488ns active high framing pulse, which marks the end of an ST-BUS frame. See Figure 11. F r a m e p u lse ST-BUS 2.048 Mb /s (C MO S): 8kHz frame signal with 244ns low level pulse that marks the beginning of a ST-BUS frame e, typically used for ST-BUS opetation at 2.048Mb/s. See figure 10. Tr a n sm it Syn c P u lse (C MO S O u t p u t ). This is an 8kHz 488ns active high framing pulse, which marks the beginning of an ST-BUS frame. See Figure 11. F r a m e p u lse ST-BUS 8.192 Mb /s (C MO S): 8kHz frame signal with 122ns high level pulse that marks the beginning of a ST-BUS frame 1.544 MH z clock (C MO S): This output is used in T1 applications. An a log Power Su p p ly: 5V for PT7A4408J and 3.3V for PT7A4408LJ 3.088 MH z clock (C MO S): This output is used in T1 applications. 2.048 MH z clock (C MO S): This output is used for ST-BUS operation at 2.048Mb/s. 4.096 MH z clock (C MO S): This output is used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. C lock 19.44MH z (C MO S O u t p u t ). This output is used in OC3/STS-3 applications. An a log P L L C lock I n p u t (C MO S I n p u t ). This input clock is a reference for an internal analog PLL. This pin is internally pulled down to GND. An a log P L L C lock O u t p u t (C MO S O u t p u t ). This output clock is generated by the internal analog PLL.
11
F16
O
12
RSP
O
13
F0
O
14 15 16 17 18 19 20 21 22 24
TSP F8 C1.5 AVDD C3 C2 C4 C19 ACKi ACKo
O O O Power O O O O I O
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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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Table 2. Pin Description (continued)
P in 25 26 27 35 36 39 Na me C8 C16 C6 TDO MS TEST Typ e O O O O I I Descr ip t ion 8.192 MH z clock (C MO S): This output is used for ST-BUS operation at 8.192Mb/s. 1 6 . 3 8 4 M H z c l o c k ( C M O S ) : T h i s o u t p u t i s u s e d f o r S T- BUS o p e r a t i o n wi t h a 16.384MHz clock. C lock 6.312 MH z (C MO S O u t p u t ). This output is used for DS2 applications. Test Ser ia l Da t a O u t (T T L O u t p u t ). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enable. Mod e/C on t r ol Select (T T L ): determines the operating states, Normal or Free-Run. Test (T T L I n p u t ). This input is normally tied low. When pulled high, it enables internal test modes. This pin is internally pulled down to GND. F r eq u en cy Select 2 (T T L ):Together with FS1, selects one of the three DPLL feedback frequencies to match the desired Input Reference Frequency (8 kHz, 1.544 MHz or 2.048 MHz). F r eq u en cy Select 1 (T T L ): Refer to the pin description of FS2. Test Ser ia l Da t a I n (T T L I n p u t ). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VCC.. R eset (Sch mit t ): Resets the device when at low logic level. Reset is needed whenever the operating mode is changed, or the reference signal frequency is switched or when powerup; so as to ensure proper operation of the device. Following Reset, the output clocks and frame signals are phase-aligned with the input reference source. Test Mod e Select (T T L I n p u t ). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VCC..
40 41 42
FS2 FS1 TDI
I I I
43
RST
I
44
TMS
I
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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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Functional Description
Overall Operation
The PT7A4408/4408L is a multitrunk synchronizer that provides the clock and frame signals for T1 and E1 primary rate digital transmission links, and STS-3/OC3 links. It basically consists of the Clock Generator, Mode Control, Digital Phase- Locked Loop (DPLL), Analog Phase- Locked Loop (APLL) and Output Interface Circuit. The DPLL circuit provides synchronization of the output signals with any given input reference signal. Master Clock The PT7A4408/4408L uses either an external clock source or an external crystal and a few discrete components with its internal oscillator as the master clock. Feedback Frequency Select MUX The feedback frequency is selected by FS1 and FS2 (as shown in Table 3) to match the particular incoming reference frequency (1.544MHz, 2.048MHz or 8kHz). A reset (RST) must be performed after every frequency select input change.
Table 3. Feedback Frequency Selection
F S2 0 0 1 1 F S1 0 1 0 1 I n p u t F r eq u en cy Reserved 8kHz 1.544MHz 2.048MHz
Digital Phase-Locked Loop (DPLL) The DPLL consists of the Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator (DCO) and Control Circuit. See Figure 3 for the block diagram of DPLL. The Reference is sent to Phase Detector for comparison with the Feedback Signal from the Feedback Frequency Select MUX. An error signal corresponding to their instantaneous phase difference is produced and sent to the Limiter. The Limiter amplifies this error signal to ensure the DPLL responds to all input transient conditions with a maximum output phase slope of 5ns per 125s. This performance easily meets the maximum phase slope of 7.6ns per 125s or 81ns per 1.326ms specified by AT&T TR62411. The Loop Filter is a 1.9Hz low pass filter for all three reference frequency selections: 8kHz, 1.544MHz and 2.048MHz. The filter ensures that the jitter transfer requirements in ETS 300011 and AT&T TR62411 are met.
Figure 3. Block Diagram of DPLL
Reference
Phase Detector
Limiter
Loop Filter DCO DPLL Reference to Output Interface Circuit
Control Circuit
Feedback Signal From Frequency Select MUX
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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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The Control Circuit decides Normal or Freerun state. The Error Signal, after limited and filtered, is sent to Digitally Controlled Oscillator. Based on the processed error value, the DCO will generate the corresponding digital output signals for the Tapped Delay Line in the Output Interface Circuit to produce 12.352MHz, 12.624MHz, 19.44MHz and 16.384MHz signals. The DCO synchronization method depends upon the PT7A4408/4408L operating state, as follows: In Normal state, the DCO generates four output signals which are frequency and phase locked to the selected input reference signal. In Free-Run state, the DCO is free running with an accuracy equal to that of the OSCi 20MHz source. Output Interface Circuit The Output Interface Circuit consists of the Tapped Delay Line and E1/T1 Dividers as shown in Figure 4. Signals from the DCO are sent to Tapped Delay Line to generate four clock signals, 16.384MHz, 12.624MHz, 19.44MHz and 12.352MHz, which are divided in the T1 and E1 Dividers respectively to provide needed clock and frame signals.
The T1 Divider uses the 12.352MHz signal to generate two clock signals, C1.5 and C3. They have a nominal 50% duty cycle. The DS2 Divider uses 12.624MHz signal to generate clock signal C6. Clock signal C19 is generated from 19.44MHz by tapped Delay Line. The E1 Divider uses the 16.384MHz signal to generate four clock signals and three frame signals, i.e., C2, C4, C8, C16, F0, F8 and F16. The frame signals are generated directly from the C16 signal. The C2, C4, C8 and C16 signals have nominal 50% duty cycle. All the frame and clock outputs are locked to each other for all operating states. They have limited driving capability and should be buffered when driving high capacitance (e.g., 30pF) loads.
Figure 4. Block Diagram of Output Interface Circuit
12.352MHz
T1 Divider
C1.5 C3
16.384MHz
Signal From DCO
Tapped Delay Line
E1 Divider
C2 C4 C8 C16 F0 F8 F16 RSP TSP C6
OSCi
12.624MHz
DS2 Divider
19.44MHz
C19
ACKi
APLL
ACKo
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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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Mode Controller The Mode Controller determines whether the PT7A4408/ 4408L operates in Normal or Free-Run state. All state changes are synchronous with the rising edge of F8. See the Modes of Operation section for complete details. APLL The analog PLL is intended to be used to achieve a 50% Duty cycle output clock. Connecting C19 to ACKi will generate a phase locked 19.44 MHz ACKo output with a nominal 50% duty cycle and a maximum peak-to-peak unfiltered jitter of 0.174 U.I. . The analog PLL has an intrinsic jitter of less than 0.01 U.I. In order to achieve this low jitter level separate pins are provided to power (AVDD, AGND) the APLL.
Applications Information
Master Clock The PT7A4408/4408L uses either an external clock source or an external crystal as the master timing source. In Free-Run State, the frequency tolerance of the PT7A4408/ 4408L output clocks are equal to the frequency tolerance of the timing source. In an application, if an accurate Free-Run State is not required, the tolerance of the master timing source may be 100ppm. If required, the tolerance must be no greater than 32ppm. The capture range of PT7A4408/4408L will also be considered when deciding the accuracy of the master timing source. The sum of the accuracy of the master timing source and the capture range of the PT7A4408/4408L will always equal 230ppm. For example, if the master timing source is 100ppm, the capture range will be 130ppm. * Clock Oscillator If using an external clock source, its output pin should be connected directly (not AC coupled) to the OSCi pin of the PT7A4408/4408L and the OSCo pin of PT7A4408/4408L can be left open as shown in Figure 5 or connected as an output pin. Figure 5. Clock Oscillator Connection
PT7A4408/4408L +5V OSCi
Modes of Operation
The PT7A4408/4408L operates in Normal or Free-Run controlled by pin MS. MS = 0: Normal MS = 1: Freerun Normal State In Normal State, the PT7A4408/4408L output signals are synchronized with input reference. In this state, the input reference signal is used as reference for the DPLL phase detector. Free-Run State Typically the Free-Run State is used when a master clock is required or immediately following system power-up before network synchronization is achieved. In Free-Run State, the outputs of the PT7A4408/4408L are uncorrelated with the input reference signal and the stored information of output reference. Instead, these output signals are based solely on the master clock frequency (OSCi). The accuracy of the output clock is equal to the accuracy of the master clock (OSCi).
+5V 20MHz OUT GND
0.1F
OSCo No Connection
When selecting the clock oscillator, following specifications should be considered. They are - absolute frequency - frequency change over temperature - output rise and fall time - output level - duty cycle Refer to AC Electrical Characteristics.
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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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* Crystal Oscillator If a crystal oscillator is selected as the master timing source, it should be connected to the PT7A4408/4408L as shown in Figure 6. Figure 6. Crystal Oscillator Connection
Detailed Specifications
Definitions of Critical Performance Specifictions
Intrinsic Jitter: Intrinsic jitter is the jitter produced by the synchronizing circuit. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode - such as free running or holdover - by measuring the output jitter of the device. Intrinsic jitter is usually measured with various band limiting filters depending on the applicable standards.
3-50pF
PT7A4408/4408L 20MHz OSCi
1M
56pF
39pF
Jitter Tolerance: Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is present on its reference. The applicable standard specifies how much jitter to apply to the reference when testing for jitter tolerance. Jitter Transfer: Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device with respect to a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. Its 3 possible input frequencies and 9 outputs give the PT7A4408/4408L 27 possible jitter transfer combinations. However, only three cases of the jitter transfer specifications are given in the AC Electrical Characteristics; as the remaining combinations can be derived from them. For the PT7A4408/4408L, two internal elements determine the jitter attenuation. They are internal 1.9Hz low pass loop filter and phase slope limiter. The phase slope limiter limits the output phase slope to 5ns/125s. Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated) to 5ns/125s. It should be noted that 1UI at 1.544MHz (644ns) is not equal to 1UI at 2.048MHz (488ns). A transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. Example : When the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is 18dB, The T1 and E1 output jitter can be calculated as follows:
OSCo
100
The crystal specification is as follows: - Frequency: - Tolerance: - Oscillation Mode: - Resonance Mode: - Load Capacitance: - Maximum Series Resistance: - pproximate Drive Level: Reset Circuit A simple power up reset circuit with about a 50s reset active (low) time is shown in Figure 7. Resistor RP is for protection only. The reset low time is not critical but should be greater than 300ns. Figure 7. Power-up Reset Circuit
PT7A4408/4408L
20MHz as required Fundamental Parallel 32pF 35 1mW
+5V
R 10k RST RP 1k C 10nF
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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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JT1o = JT1i x 10
( -A ) 20
= 20 x 10
( -18 ) 20
= 2.5UI
JE1o = JT1o x ( 1UIT1) = JT1o x ( 644ns ) = 3.3UI 488ns 1UIE1 Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the three jitter transfer functions provided. Note that the resulting jitter transfer functions for all combinations of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs (8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz, 6.312MHz, 19.44MHz) for a given input signal (jitter frequency and jitter amplitude) are the same. Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). Frequency Accuracy: Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the PT7A4408/4408L, the Free-Run accuracy is equal to the Master Clock (OSCi) accuracy.
Lock Range: If the PT7A4408/4408L DPLL is already in a state of synchronization ("lock") with the incoming reference signal, it is able to track this signal to maintain lock as its frequency varies over a certain range, called the Lock Range. The size of Lock Range is related to the range of the Digitally Controlled Oscillators and is equal to 230ppm minus the accuracy of the master clock (OSCi). For example, a 32ppm master clock results in a Lock Range of 198ppm. Capture Range: The PT7A4408/4408L DPLL is not at present in a state of synchronization (lock) with the incoming reference signal, it is able to initiate (acquire) lock only if the signal's frequency is within a certain range, called the Capture Range. For any PLL, no portion of the Capture Range can fall outside the Lock Range, and, in general, the Capture Range is more narrow than the Lock Range. However, owing to the design of its Phase Detector, the PT7A4408/4408L's Capture Range is equal to its Lock Range. Phase Slope: Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal of constant frequency. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal.
Absolute Maximum Ratings
Storage Temperature ...................................................... -65oC to +150oC Ambient Temperature with Power Applied ...................... -40oC to +85oC Supply Voltage to Ground Potential (Inputs & VCC Only) ...... -0.3 to 7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) .. -0.3 to 7.0V DC Input Voltage .................................................................. -0.3 to 7.0V DC Output Current ...................................................................... 120mA Power Dissipation ....................................................................... 900mW Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Table 4. Recommended Operating Conditions
Sym Descr ip t ion Supply Voltage for 4408 VCC Supply Voltage for 4408L TA Operating Temperature Over Recommended Operating Conditions Test C on d it ion s Min 4.5 3.0 -40 Typ 5.0 3.3 25 Ma x 5.5 3.6 85 Un it s V V
o
C
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Data Sheet PT7A4408/4408L T1/E1/OC3 System Synchronizer
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DC Electrical and Power Supply Characteristics
Table 5. DC Electrical and Power Supply Characteristics
Sym ICCQ Descr ip t ion Quiescent Power Supply Current 4408L 4408 OSCi = Clock, Note 2 4408L ICC Supply Current 4408 OSCi = Crystal, Note 2 4408L VIH VIL VCIH VCIL VSIH TTL HIGH Input Voltage-All pins except OSCi, RST TTL LOW Input Voltage-All pins except OSCi, RST CMOS HIGH Input VoltageOSCi pin CMOS LOW Input VoltageOSCi pin Schmitt HIGH Input VoltageRST pins Schmitt LOW Input VoltageRST pins Schmitt Hysteresis VoltageRST pins Input Leakage Current - Pins: TCK, REF, TDI, TMS IIL Input Leakage Current - Pins: TRST, ACKi, MS, TEST Input Leakage Current - other pins 4408 VOH VOL HIGH Output Voltage 4408L LOW Output Voltage IOH = -4mA IOL = 4mA 4408 4408L 4408 4408L -10 2.4 2.0 0.8 VI = VCC or 0V 4408 4408L 4408 4408L 0.4 -140 -100 140 100 10 3.6 2.6 1.8 1.1 0.7VCC 0.3VCC 2.0 0.8 40 mA V V V V V V V V V A A A A A V V V 70 mA 35 mA Device 4408 OSCi = 0V, Note 2 10 60 mA mA Test C on d it ion s Min Typ Ma x 20 Un it s mA
VSIL VHYS
Note: 1. Supply voltages and operating temperature are as per Recommended Operating Conditions. 2. MS = VCC, FS1 = VCC , FS2= GND, other inputs connected to GND. 3. All outputs are unloaded except for VOH and VOL measurement.
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AC Electrical Characteristics
Performance Table 6. Performance
Sym Descr ip t ion 0ppm Free-Run State Accuracy with OSCi at: 32ppm 100ppm 0ppm DPLL Capture Range With OSCi at: 32ppm 100ppm APLL Capture Range Phase Lock Time Output Phase Slope 8kHz Reference Input for Auto-Holdover with:1.544MHz 2.048MHz 43 3, 6-14 3-14, 27 3, 6, 9-11 3, 7, 9-11 3, 8-11 <-30k <-30k <-30k or or or 3, 6-8 5-8 Test C on d it ion s* Min 0 -32 -100 -190 -158 -90 10 Typ Ma x 0 +32 +100 +230 +198 +130 30 23 45 >+30k >+30k >+30k Un it s ppm ppm ppm ppm ppm ppm MHz s s/s ppm ppm ppm
* Refer to the Test Conditions on Page 25 for details.
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Voltage Levels for Timing Parameter Measurement Table 7. Voltage Levels for Timing Parameter Measurement
Sym VT VHM VLM Descr ip t ion Threshold Voltage Rising and Falling Threshold Voltage High Rising and Falling Threshold Voltage Low Sch mit t 0.5VCC 0.7VCC 0.3VCC TTL 1.5 2.0 0.8 CMOS 0.5VCC 0.7VCC 0.3VCC Un it s V V V
Figure 8. Voltage Levels for Timing Parameter Measurement
Timing Reference Points Signal VHM VT VLM
tIF.tOF
tIR.tOR
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Input and Output Timing Table 8. Input and Output Timing of 4408
Sym tRW tIRF tR8D tR15D tR2D tF0D tF16D tC15D tC6D tC3D tC2D tC4D tC8D tC16D tTSPD tRSPD tC19D tC15W tC3W tC6W tC2W tC4W tC8W
Descr ip t ion Reference Input pulse Width High or Low
Test C on d it ion s*
Min 100
Typ
Ma x
Un it s ns
3, 6-11, 39 Reference Input Rising or Falling Time 8kHz Reference Input to F8 Delay 1.544kHz Reference Input to F8 Delay 2.048kHz Reference Input to F8 Delay F8 to F0 Delay F8 to F16 Delay F8 to C1.5 Delay F8 to C6 Delay F8 to C3 Delay F8 to C2 Delay F8 to C4 Delay F8 to C8 Delay F8 to C16 Delay F8 to TSP Delay 3-14, 21, 39 F8 to RSP Delay F8 to C19 Delay C1.5 Pulse Width High or Low C3 Pulse Width High or Low C6 Pulse Width High or Low C2 Pulse Width High or Low C4 Pulse Width High or Low C8 Pulse Width High or Low -10 0 309 149 72 230 111 52 10 52 339 175 86 258 133 70 ns ns ns ns ns ns ns ns 3-14, 21, 39 3-14, 21 3, 6-14, 21, 23, 38 -28 337 217 110 19 -45 -8 -46 -10 -10 -10 -10 -10 10 -1 363 238 134 44 -31 9 -31 5 5 5 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* Refer to the Test Conditions on Page 25 for details.
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Table 9. Input and Output Timing of 4408L
Sym tRW tIRF tR8D tR15D tR2D tF0D tF16D tC15D tC6D1) tC3D tC2D tC4D tC8D tC16D tTSPD1) tRSPD1) tC19D1) tC15W tC3W tC6W1) tC2W tC4W tC8W Descr ip t ion Reference Input pulse Width High or Low 3, 6-11, 39 Reference Input Rising or Falling Time 8kHz Reference Input to F8 Delay 1.544kHz Reference Input to F8 Delay 2.048kHz Reference Input to F8 Delay F8 to F0 Delay F8 to F16 Delay F8 to C1.5 Delay F8 to C6 Delay F8 to C3 Delay F8 to C2 Delay F8 to C4 Delay F8 to C8 Delay F8 to C16 Delay F8 to TSP Delay 3-14, 21, 39 F8 to RSP Delay F8 to C19 Delay C1.5 Pulse Width High or Low C3 Pulse Width High or Low C6 Pulse Width High or Low C2 Pulse Width High or Low C4 Pulse Width High or Low C8 Pulse Width High or Low -10 0 309 149 72 230 111 52 10 52 339 175 86 258 133 70 ns ns ns ns ns ns ns ns 3-14, 21, 39 3-14, 21 3, 6-14, 21, 23, 38 -21 345 232 112 19 -47 -9 -49 -11 -11 -11 -11 -10 10 6 371 248 138 44 -31 9 -32 4 4 4 4 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test C on d it ion s* Min 100 Typ Ma x Un it s ns
* Refer to the Test Conditions on Page 25 for details.
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Table 10. Input and Output Timing (Continued)
Sym tC16WL tTSPW tRSPW tC19W tF0WL tF8WH tF16WL tORF tS tH Descr ip t ion C16 Pulse Width Low TSP Pulse Width High 3-14, 21 RSP Pulse Width High C19 Pulse Width High or Low F0 Pulse Width Low F8 Pulse Width High F16 Pulse Width Low Output Clock and Frame Pulse Rising or Falling Time Input Controls Setup Time Input Controls Hold Time 3-14, 21, 39 9 100 100 ns ns ns 478 16 230 111 52 495 36 258 133 70 ns ns ns ns ns Test C on d it ion s* Min 26 478 Typ Ma x 37 494 Un it s ns ns
* Refer to the Test Conditions on Page 25 for details. Figure 9. Input to Output Timing (Normal State, after RST)
t R8D
REF 8kH z VT
tR W t R15D tR W
VT
REF 1.544M H z
t R2D
REF 2.048M H z F8
tR W
VT VT
Note: Input to output delay values are valid after a RST with no further state changes.
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Figure 10. Output Timing
tF8WH
F8 VT
tF0D tF0WL
F0 VT
tF16D
F16
tF16WL tC16WL tC16D
VT
C16
VT
tC8W
C8
tC8W
tC8D
VT
tC4W
C4
tC4D tC4W tC2D
VT
C2
tC2W
VT
tC3D tC3W
C3
tC3W
VT
tC15W
C1.5
tC15D
VT
tC6W
C6
tC6W
tC6D
VT
tC19W
C19
tC19D
VT
tC19W
Figure 11. Output Timing
F8 C2 tRSPD RSP TSP
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tTSPW tTSPD
tRSPW
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Figure 12. Setup and Hold Timing of Input Controls
F8
VT
tS
MS
tH
VT
Intrinsic Jitter Unfiltered Table 11. Intrinsic Jitter Unfiltered
Sym
Descr ip t ion Instrinsic Jitter at F8 (8kHz) Instrinsic Jitter at F0 (8kHz) Instrinsic Jitter at F16 (8kHz) Instrinsic Jitter at C1.5 (1.544MHz) Instrinsic Jitter at C2 (2.048MHz) Instrinsic Jitter at C3 (3.088MHz) Instrinsic Jitter at C4 (4.096MHz) Instrinsic Jitter at C6 (6.312MHz) Instrinsic Jitter at C8 (8.192MHz) Instrinsic Jitter at C16 (16.384MHz) Instrinsic Jitter at C19 (19.44MHz) Instrinsic Jitter at TSP (8kHz) Instrinsic Jitter at RSP (8kHz)
Test C on d it ion s*
Min
Typ
Ma x 0.0002
Un it s UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
3-14, 21-24, 28
0.0002 0.0002
3-14, 21-24, 29 3-14, 21-24, 30 3-14, 21-24, 31 3-14, 21-24, 32 3-14, 21-24, 41 3-14, 21-24, 33 3-14, 21-24, 34 3-14, 21-24, 42 3-14, 21-24, 28 3-14, 21-24, 28
0.030 0.040 0.060 0.080 0.120 0.160 0.320 0.230 0.0002 0.0002
* Refer to the Test Conditions on Page 25 for details.
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C1.5 (1.544MHz) Instrinsic Jitter Filtered Table 12. C1.5 (1.544MHz) Instrinsic Jitter Filtered
Sym
Descr ip t ion Instrinsic Jitter (4Hz to 100kHz Filter) Instrinsic Jitter (10Hz to 40kHz Filter)
Test C on d it ion s*
Min
Typ
Ma x 0.015 0.010
Un it s UIpp UIpp UIpp UIpp
3-14, 21-24, 29 Instrinsic Jitter (8kHz to 40kHz Filter) Instrinsic Jitter (10Hz to 8kHz Filter)
* Refer to the Test Conditions on Page 25 for details.
0.010 0.005
C2 (2.048MHz) Instrinsic Jitter Filtered Table 13. C2 (2.048MHz) Instrinsic Jitter Filtered
Sym
Descr ip t ion Instrinsic Jitter (4Hz to 100kHz Filter) Instrinsic Jitter (10Hz to 40kHz Filter)
Test C on d it ion s*
Min
Typ
Ma x 0.015 0.010
Un it s UIpp UIpp UIpp UIpp
3-14, 21-24, 30 Instrinsic Jitter (8kHz to 40kHz Filter) Instrinsic Jitter (10Hz to 8kHz Filter)
* Refer to the Test Conditions on Page 25 for details.
0.010 0.005
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8kHz Input to 8kHz Output Jitter Transfer Table 14. 8kHz Input to 8kHz Output Jitter Transfer
Sym Descr ip t ion Jitter Attenuation for 1Hz with 0.01UIpp Input Jitter Attenuation for 1Hz with 0.54UIpp Input Jitter Attenuation for 10Hz with 0.10UIpp Input Jitter Attenuation for 60Hz with 0.10UIpp Input Jitter Attenuation for 300Hz with 0.10UIpp Input Jitter Attenuation for 3600Hz with 0.005UIpp Input Test C on d it ion s* Min 0 6 12 3, 6, 9-14, 21, 22, 24, 28, 35 28 42 45 38 dB dB dB Typ Ma x 6 16 22 Un it s dB dB dB
* Refer to the Test Conditions on Page 25 for details.
1.544MHz Input to 1.544MHz Output Jitter Transfer Table 15. 1.544MHz Input to 1.544MHz Output Jitter Transfer
Sym Descr ip t ion Jitter Attenuation for 1Hz with 20UIpp Input Jitter Attenuation for 1Hz with 104UIpp Input Jitter Attenuation for 10Hz with 20UIpp Input Jitter Attenuation for 60Hz with 20UIpp Input Jitter Attenuation for 300Hz with 20UIpp Input Jitter Attenuation for 10kHz with 0.3UIpp Input Jitter Attenuation for 100kHz with 0.3UIpp Input 3, 7, 9-14, 21, 22, 24, 29, 35 Test C on d it ion s* Min 0 6 12 28 42 45 45 Typ Ma x 6 16 22 38 Un it s dB dB dB dB dB dB dB
* Refer to the Test Conditions on Page 25 for details.
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2.048MHz Input to 2.048MHz Output Jitter Transfer Table 16. 2.048MHz Input to 2.048MHz Output Jitter Transfer
Sym Descr ip t ion Test C on d it ion s* 3,8,9-14,21,22,24,30,35 Jitter at Output for 1Hz 3.00UIpp Input 3,8,9-14,21,22,24,30,36 3,8,9-14,21,22,24,30,35 Jitter at Output for 3Hz 2.33UIpp Input 3,8,9-14,21,22,24,30,36 3,8,9-14,21,22,24,30,35 Jitter at Output for 5Hz 2.07UIpp Input 3,8,9-14,21,22,24,30,36 3,8,9-14,21,22,24,30,35 Jitter at Output for 10Hz 1.76UIpp Input 3,8,9-14,21,22,24,30,36 Jitter at Output for 100Hz 1.50UIpp Input 3,8,9-14,21,22,24,30,35 3,8,9-14,21,22,24,30,36 3,8,9-14,21,22,24,30,35 3,8,9-14,21,22,24,30,36 3,8,9-14,21,22,24,30,35 3,8,9-14,21,22,24,30,36 0.10 0.06 0.05 0.04 0.03 0.04 0.02 UIpp UIpp UIpp UIpp UIpp UIpp UIpp 0.10 0.40 UIpp UIpp 0.10 0.80 UIpp UIpp 0.09 1.3 UIpp UIpp Min Typ Ma x 2.9 Un it s UIpp
Jitter at Output for 2400Hz 1.50UIpp Input
Jitter at Output for 100kHz 0.20UIpp Input
* Refer to the Test Conditions on Page 25 for details.
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8kHz Input Jitter Tolerance Table 17. 8kHz Input Jitter Tolerance
Sym Descr ip t ion Jitter Tolerance for 1Hz Input Jitter Tolerance for 5Hz Input Jitter Tolerance for 20Hz Input Jitter Tolerance for 300Hz Input 3,6,9-14,21,22,24-26,28 Jitter Tolerance for 400Hz Input Jitter Tolerance for 700Hz Input Jitter Tolerance for 2400Hz Input Jitter Tolerance for 3600Hz Input 0.15 0.08 0.02 0.01 UIpp UIpp UIpp UIpp Test C on d it ion s* Min 0.80 0.70 0.60 0.20 Typ Ma x Un it s UIpp UIpp UIpp UIpp
* Refer to the Test Conditions on Page 25 for details.
1.544MHz Input Jitter Tolerance Table 18. 1.544MHz Input Jitter Tolerance
Sym Descr ip t ion Jitter Tolerance for 1Hz Input Jitter Tolerance for 5Hz Input Jitter Tolerance for 20Hz Input Jitter Tolerance for 300Hz Input Jitter Tolerance for 400Hz Input Jitter Tolerance for 700Hz Input Jitter Tolerance for 2400Hz Input Jitter Tolerance for 10kHz Input Jitter Tolerance for 100kHz Input 3,7,9-14,21,22,24-26,29 Test C on d it ion s* Min 150 140 130 35 25 15 4 1 0.5 Typ Ma x Un it s UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
* Refer to the Test Conditions on Page 25 for details.
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2.048MHz Input Jitter Tolerance Table 19. 2.048MHz Input Jitter Tolerance
Sym
Descr ip t ion Jitter Tolerance for 1Hz Input Jitter Tolerance for 5Hz Input Jitter Tolerance for 20Hz Input Jitter Tolerance for 300Hz Input Jitter Tolerance for 400Hz Input Jitter Tolerance for 700Hz Input Jitter Tolerance for 2400Hz Input Jitter Tolerance for 10kHz Input Jitter Tolerance for 100kHz Input
Test C on d it ion s*
Min 150 140 130 50
Typ
Ma x
Un it s UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
3,8,9-14,21,22,24-26,30
40 20 5 1 1
* Refer to the Test Conditions on Page 25 for details.
OSCi 20MHz Master Clock Input Table 20. OSCi 20MHz Master Clock Input
Sym Descr ip t ion Test C on d it ion s* 15, 18 Tolerance 16, 19 17, 20 Duty Cycle Rising Time Falling Time Min 0 -32 -100 40 Typ Ma x 0 +32 +100 60 10 10 Un it s ppm ppm ppm % ns ns
* Refer to the Test Conditions on Page 25 for details.
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Notes: 1. Voltages are with respect to ground (GND) unless otherwise stated. 2. Supply voltage and operation temperature are as per Recommended Operating Conditions. 3. Timing parameters are as per AC Electrical Characteristics - Voltage Levels for Timing Parameter Measurement.
Test Conditions: 1. 2. 3. Normal State selected. 4. 5. Free-Run State selected. 6. 8kHz frequency source selected. 7. 1.544MHz frequency source selected. 8. 2.048MHz frequency source selected. 9. Master clock input OSCi at 20MHz 0ppm. 10. Master clock input OSCi at 20MHz 32ppm. 11. Master clock input OSCi at 20MHz 100ppm. 12. Selected reference input at 0ppm. 13. Selected reference input at 32ppm. 14. Selected reference input at 100ppm. 15. For Free-Run State of 0ppm. 16. For Free-Run State of 32ppm. 17. For Free-Run State of 100ppm. 18. For capture range of 230ppm. 19. For capture range of 198ppm. 20. For capture range of 130ppm. 21. 25pF capacitive load.
22. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI p-p where 1UI p-p = 1/20MHz. 23. Jitter on reference input is less than 7ns p-p. 24. Applied jitter is sinusoidal. 25. Minimum applied input jitter magnitude to regain synchronization. 26. Loss of synchronization is obtained at slightly higher input jitter amplitudes. 27. Within 10ms of the state, reference or input change. 28. 1UIpp = 125s for 8kHz signals. 29. 1UIpp = 648ns for 1.544MHz signals. 30. 1UIpp = 488ns for 2.048MHz signals. 31. 1UIpp = 324ns for 3.088MHz signals. 32. 1UIpp = 244ns for 4.096MHz signals. 33. 1UIpp = 122ns for 8.192MHz signals. 34. 1UIpp = 61ns for 16.384MHz signals. 35. No filter. 36. 40Hz to 100kHz bandpass filter. 37. With respect to reference input signal frequency. 38. After a RST 39. Master clock duty cycle 40% to 60%. 40. In Normal State and phase locked. 41. 1UIpp = 162ns for 6.312MHz signals. 42. 1UIpp = 51ns for 19.44MHz signals.
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Mechanical Specifications
Figure 13. 44-pin PLCC
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Note
Pericom Technology Inc.
Email: support@pti.com.cn China: Asia Pacific: U.S.A.: Web-Site: www.pti.com.cn, www.pti-ic.com No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 2380 Bering Drive, San Jose, California 95131, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.
PT0106(09/02)
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