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Description
The SE9174C is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 2A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the REFEN pin voltage. The SE9174C also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The SE9174C are available in the PSOP-8 (Exposed Pad) surface mount packages.
Features
Ideal for DDR-I, DDR-II and DDR-III VTT Applications Sink and Source 2A Continuous Current Integrated Power MOSFETs Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces. High Accuracy Output Voltage at Full-Load Output Adjustment by Two External Resistors Low External Component Count Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output Current Limiting Protection On-Chip Thermal Protection Available in PSOP-8 (Exposed Pad) Packages VIN and VCNTL No Power Sequence Issue 100% Lead (Pb)-Free
Application
Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR-I, DDR-II and DDR-III Memory Systems
Pin Configuration
Block Diagram
Pin Description
Pin Name VIN GND VCNTL REFEN VOUT Power Input Ground Gate Drive Voltage Reference Voltage input and Chip Enable Output Voltage Pin function
Revision 12/4/2008 All contents are subject to change without prior notice (c) Seaward Electronics Inc., 2007. * www.seawardinc.com.cn * Page 1
Absolute Maximum Rating (1)
Parameter Input Voltage Control Voltage Power Dissipation ESD Rating Storage Temperature Range Lead Temperature (Soldering, 5 sec.) Package Thermal Resistance Symbol VIN VCNTL PD -TS TLEAD JC Value 6 6 Internally Limited 3 -65 to 150 260 28 Unit V V -KV C C C/W
Operating Rating(2)
Parameter Input Voltage Control Voltage Ambient Temperature Junction Temperature Symbol VIN VCNTL TA TJ Value 2.5 to 1.5 3% 5.0 or 3.3 5% -40 to +85 -40 to +125 Units V V
Electrical Characteristics
VIN=2.5V/1.8V/1.5V, VCNTL=3.3V, VREFEN=1.25V/0.9V/0.75V, COUT=10F (Ceramic)), TA=25C, unless otherwise specified
Parameter Input VCNTL Operation Current Standby Current Output (DDR / DDR II / DDR III) Output Offset Voltage(3) Load Regulation
(4)
Symbol
Test Conditions
Min
Typ
Max
Units
ICNTL ISTBY VOS VLOAD
IOUT=0A
VREFEN < 0.2V (Shutdown),RLOAD = 180
---20 -20
1 50 ---
2.5 90 +20 +20
mA A mV
IOUT= 0A IOUT= +2A IOUT= -2A
Protection Current limit Thermal Shutdown Temperature Thermal Shutdown Hysteresis REFEN Shutdown Shutdown Threshold
ILIM TSD TSD VIH VIL
3.3V VCNTL 5V 3.3V VCNTL 5V
2.2 --0.6 --
-170 35 ---
----0.2
A
Enable Shutdown
V
Note 1: Exceeding the absolute maximum rating may damage the device. Note 2: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN Note 3: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note 4: Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A.
Revision 12/4/2008 All contents are subject to change without prior notice (c) Seaward Electronics Inc., 2007. * www.seawardinc.com.cn * Page 2
Typical Operating Characteristics
Revision 12/4/2008 All contents are subject to change without prior notice (c) Seaward Electronics Inc., 2007. * www.seawardinc.com.cn * Page 3
Application Information
Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the SE9174C. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance converter. Consideration while designs the resistance of voltage divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. and cause undesired oscillation
Thermal Consideration SE9174C regulators have internal thermal limiting circuitry designed to protect the device during overload conditions.For continued operation, do not exceed maximum operation junction temperature 125. The power dissipation definition in device is: PD = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) -TA ) /JA Where TJ(MAX) is the maximum operation junction temperature 125, TA is the ambient temperature and the JA is the junction to ambient thermal resistance. The junction to ambient thermal resistance (JA is layout dependent) for PSOP-8 package (Exposed Pad) is 75/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25 can be calculated by following formula: PD(MAX) = (125 - 25) / 75/W = 1.33W The thermal resistanceJA of PSOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of PSOP-8 package. We have to consider the copper couldn't stretch infinitely and avoid the tin overflow.
between SE9174C and the preceding power
Revision 12/4/2008 All contents are subject to change without prior notice (c) Seaward Electronics Inc., 2007. * www.seawardinc.com.cn * Page 4
Application Diagram
VCNTL=3.3V VIN=2.5V/1.8V/1.5V R1 2N7002 EN R2 P3 CSS P1 P6
VIN
VCNTL
P4
CIN
CCNTL
RTT
REFEN VOUT GND
P2
COUT
RDUMMY
R1 = R2 = 100K, RTT = 50/33/25 COUT, min = 10F (Ceramic) + 1000F under the worst case testing condition RDUMMY = 1k as for VOUT discharge when VIN is not present but VCNTL is present CSS = 1F, CIN = 470F(Low ESR), CCNTL = 47F
Revision 12/4/2008 All contents are subject to change without prior notice (c) Seaward Electronics Inc., 2007. * www.seawardinc.com.cn * Page 5
Outline Drawing PSOP-8
Contact Information
Seaward Electronics Incorporated - China Room 1605, Building 1, International Pioneering Park, #1 Shangdi Xinxi Rd. Haidian District, Beijing 100085, China Tel: 86-10-8289-5700/01/05 Fax: 86-10-8289-5706 Email: sales@seawardinc.com.cn Seaward Electronics Corporation - Taiwan 2F, #181, Sec. 3, Min Quan East Rd. Taipei, Taiwan R.O.C Tel: 886-2-2712-0307 Fax: 886-2-2712-0191 Email: sales@seawardinc.com.tw Seaward Electronics Incorporated - North America 1512 Centre Pointe Dr. Milpitas, CA95035, USA Tel: 1-408-821-6600 Last Updated - 12/4/2008
Revision 12/4/2008 All contents are subject to change without prior notice (c) Seaward Electronics Inc., 2007. * www.seawardinc.com.cn * Page 6

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