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| 8-Bit, 165 MSPS TxDAC D/A Converter AD9748* (R) FEATURES High Performance Member of Pin Compatible TxDAC Product Family Linearity: 0.1 LSB DNL 0.1 LSB INL Twos Complement or Straight Binary Data Format Differential Current Outputs: 2 mA to 20 mA SINAD @ 5 MHz Output: 50 dB Power Dissipation: 135 mW @ 3.3 V Power-Down Mode: 15 mW @ 3.3 V On-Chip 1.20 V Reference CMOS Compatible Digital Interface 32-Lead LFCSP Edge-Triggered Latches Fast Settling: 11 ns to 0.1% Full Scale APPLICATIONS Communications Direct Digital Synthesis (DDS) Instrumentation FUNCTIONAL BLOCK DIAGRAM 3.3V 150pF 0.1 F +1.20V REF REFIO FS ADJ RSET 3.3V DVDD DCOM CLK CLK 3.3V CLKVDD CLKCOM SLEEP DIGITAL DATA INPUTS (DB7-DB0) SEGMENTED SWITCHES LSB SWITCHES CURRENT SOURCE ARRAY AVDD ACOM AD9748 IOUTA IOUTB MODE CMODE LATCHES GENERAL DESCRIPTION The AD9748 is an 8-bit resolution, wideband, third generation member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9748 offers exceptional ac and dc performance while supporting update rates up to 165 MSPS. The AD9748's low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 60 mW with a slight degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature compensated band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families. PRODUCT HIGHLIGHTS 1. 32-lead LFCSP package. 2. The AD9748 is the 8-bit member of the pin compatible TxDAC family, which offers excellent INL and DNL performance. 3. Differential or single-ended clock input (LVPECL or CMOS), supports 165 MSPS conversion rate. 4. Data input supports twos complement or straight binary data coding. 5. Low power: Complete CMOS DAC function operates on 135 mW from a 2.7 V to 3.6 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 6. On-chip voltage reference: The AD9748 includes a 1.2 V temperature-compensated band gap voltage reference. *Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD9748-SPECIFICATIONS DC SPECIFICATIONS Parameter RESOLUTION DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current 3 REFERENCE INPUT Input Compliance Range Reference Input Resistance (External Reference) Small Signal Bandwidth TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD CLKVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD)4 Clock Supply Current (ICLKDVDD) Supply Current Sleep Mode (IAVDD) Power Dissipation4 Power Dissipation5 Power Supply Rejection Ratio--AVDD6 Power Supply Rejection Ratio--DVDD6 OPERATING RANGE 1 (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.) Min 8 0.25 0.25 -0.02 -0.5 -0.5 2.0 -1.0 0.1 0.1 0.25 0.25 +0.02 +0.5 +0.5 20.0 +1.25 Typ Max Unit Bits LSB LSB % of FSR % of FSR % of FSR mA V kW pF V nA V MW MHz ppm of FSR/C ppm of FSR/C ppm of FSR/C ppm/C 0.1 0.1 100 5 1.14 1.20 100 1.26 0.1 1 0.5 0 50 100 50 1.25 2.7 2.7 2.7 3.3 3.3 3.3 33 8 5 5 135 145 3.6 3.6 3.6 36 9 7 6 145 +1 +0.04 +85 -1 -0.04 -40 V V V mA mA mA mA mW mW % of FSR/V % of FSR/V C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32 times the I REF current. 3 An external buffer amplifier with an input bias current <100 nA should be used to drive any external load. 4 Measured at fCLOCK = 100 MSPS and f OUT = 1 MHz. 5 Measured as unbuffered voltage output with I OUTFS = 20 mA and 50 W RLOAD at IOUTA and IOUTB, f CLOCK = 100 MSPS and f OUT = 40 MHz. 6 5% power supply variation. Specifications subject to change without notice. -2- REV. 0 AD9748 DYNAMIC SPECIFICATIONS Single-Ended Output, 50 Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA)2 Output Noise (IOUTFS = 2 mA)2 AC LINEARITY Signal-to-Noise and Distortion Ratio fCLOCK = 50 MSPS; fOUT = 5 MHz fCLOCK = 50 MSPS; fOUT = 19 MHz fCLOCK = 100 MSPS; fOUT = 5 MHz fCLOCK = 100 MSPS; fOUT = 39 MHz fCLOCK = 165 MSPS; fOUT = 5 MHz fCLOCK = 165 MSPS; fOUT = 49 MHz Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1 MHz fCLOCK = 50 MSPS; fOUT = 12.5 MHz fCLOCK = 100 MSPS; fOUT = 25 MHz fCLOCK = 165 MSPS; fOUT = 41.3 MHz Spurious-Free Dynamic Range to Nyquist fCLOCK = 25 MSPS; fOUT = 1 MHz 0 dBFS Output fCLOCK = 65 MSPS; fOUT = 5 MHz fCLOCK = 65 MSPS; fOUT = 19 MHz fCLOCK = 100 MSPS; fOUT = 5 MHz fCLOCK = 100 MSPS; fOUT = 39 MHz fCLOCK = 165 MSPS; fOUT = 5 MHz fCLOCK = 165 MSPS; fOUT = 49 MHz (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, Differential Doubly Terminated, unless otherwise noted.) Min 165 11 1 5 2.5 2.5 50 30 Typ Max Unit MSPS ns ns pV-s ns ns pA//Hz pA//Hz 50 47 50 46 50 47 -72 -65 -60 -58 -61 dB dB dB dB dB dB dBc dBc dBc dBc 61 72 69 65 68 62 68 54 dBc dBc dBc dBc dBc dBc dBc NOTES 1 Measured single-ended into 50 W load. 2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. Specifications subject to change without notice. DIGITAL SPECIFICATIONS Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW) CLK INPUTS* Input Voltage Range Common-Mode Voltage Differential Voltage (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.) Min 2.1 -10 -10 5 2.0 1.5 1.5 0 0.75 0.5 3 2.25 Typ 3 0 Max Unit V V mA mA pF ns ns ns V V V 0.9 +10 +10 1.5 1.5 *Applicable to CLK+ and CLK- inputs when configured for differential or PECL clock input mode. Specifications subject to change without notice. REV. 0 -3- AD9748 ABSOLUTE MAXIMUM RATINGS* Parameter AVDD DVDD CLKVDD ACOM ACOM DCOM AVDD AVDD DVDD CLOCK, SLEEP Digital Inputs, MODE IOUTA, IOUTB REFIO, REFLO, FSADJ CLK+, CLK-, CMODE Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to Min Max ACOM DCOM CLKCOM DCOM CLKCOM CLKCOM DVDD CLKVDD CLKVDD DCOM DCOM ACOM ACOM CLKCOM +3.9 +3.9 +3.9 +0.3 +0.3 +0.3 +3.9 +3.9 +3.9 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 CLKVDD + 0.3 150 -65 +150 300 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -3.9 -3.9 -3.9 -0.3 -0.3 -1.0 -0.3 -0.3 Unit V V V V V V V V V V V V V V C C C DB0-DB11 tS CLOCK tH tLPW tPD tST 0.1% 0.1% IOUTA OR IOUTB Figure 1. Timing Diagram ORDERING GUIDE Model Temperature Range Package Description Package Options* AD9748ACP -40C to +85C 32-Lead LFCSP CP-32 AD9748ACP-PCB Evaluation Board *CP = Lead Frame Chip Scale Package *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 32-Lead LFCSP JA= 32.5C/W Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9748 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- REV. 0 AD9748 PIN CONFIGURATION 32 DB2 31 DB3 30 DB4 29 DB5 28 DB6 27 DB7 (MSB) 26 DCOM 25 SLEEP DB1 1 (LSB) DB0 2 DVDD 3 NC 4 NC 5 NC 6 NC 7 NC 8 PIN 1 INDICATOR AD9748 TOP VIEW 24 FSADJ 23 REFIO 22 ACOM 21 IOUTA 20 IOUTB 19 ACOM 18 AVDD 17 AVDD NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. 27 28-32, 1 2 3 4-9 10, 26 11 12 13 14 15 16 17, 18 19, 22 20 21 23 24 25 Mnemonic DB7 DB6-DB1 DB0 DVDD NC DCOM CLKVDD CLK+ CLK- CLKCOM CMODE MODE AVDD ACOM IOUTB IOUTA REFIO FSADJ SLEEP Description Most Significant Data Bit (MSB) Data Bits 6-1 Least Significant Data Bit (LSB) Digital Supply Voltage (3.3 V) No Internal Connection Digital Common Clock Supply Voltage (3.3 V) Differential Clock Input Differential Clock Input Clock Common Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK-). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip). Selects Input Data Format. Connect to CLKCOM for straight binary, CLKVDD for twos complement. Analog Supply Voltage (3.3 V) Analog Common Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Reference Input/Output. Requires 0.1 mF capacitor to ACOM. Full-Scale Current Output Adjust Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not used. REV. 0 NC 9 DCOM 10 CLKVDD 11 CLK 12 CLK 13 CLKCOM 14 CMODE 15 MODE 16 -5- AD9748 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (or DNL) offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per C. For reference drift, the drift is reported in ppm per C. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero is called the offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion (THD) The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Output Compliance Range THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Multitone Power Ratio The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift The spurious free dynamic range containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. Temperature drift is specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For 3.3V 150pF 0.1 F +1.20V REF REFIO FS ADJ *AWG2021 CLOCK RETIMED SO THAT THE DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. DVDD DCOM RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR RSET 3.3V DVDD DCOM CLK 50 CLK 3.3V CLKVDD CLKCOM SLEEP DIGITAL DATA INPUTS (DB7-DB0) DIGITAL DATA TEKTRONIX AWG-2021 WITH OPTION 4 LATCHES SEGMENTED SWITCHES LSB SWITCHES CURRENT SOURCE ARRAY AVDD ACOM AD9748 MINI-CIRCUITS T1-1T IOUTA IOUTB MODE 50 CMODE 50 20pF 20pF 100 ROHDE & SCHWARZ FSEA30 SPECTRUM ANALYZER CLOCK OUTPUT Figure 2. Basic AC Characterization Test Setup -6- REV. 0 Typical Performance Characteristics-AD9748 55 5mA 55 10mA 80 20mA 75 THD@50MSPS 70 50 10mA 45 2.5mA 50 5mA 45 2.5mA 40 SINAD - dB 20mA SINAD/THD - dB THD@100MSPS 65 60 THD@165MSPS 55 SINAD@50MSPS 50 45 SINAD@165MSPS SINAD@100MSPS 100 40 35 SINAD - dB 35 30 1 10 fOUT - MHz 100 30 1 10 fOUT - MHz 100 40 1 10 fOUT - MHz TPC 1. SINAD vs. IOUTFS @ 100 MSPS (Single-Ended Output) TPC 2. SINAD vs. IOUTFS @ 165 MSPS (Single-Ended Output) TPC 3. SINAD/THD vs. fOUT (SingleEnded Output) 80 75 70 THD@165MSPS 0 -10 -20 0 fCLOCK = 25MSPS fOUT = 7.81MHz MAGNITUDE - dBm SFDR = 65.0dBc AMPLITUDE = 0dBFS -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 fCLOCK = 125MSPS fOUT = 27MHz SFDR = 56.2dBc AMPLITUDE = 0dBFS MAGNITUDE - dBm SINAD/THD - dB -30 -40 -50 -60 -70 -80 65 THD@50MSPS 60 55 50 45 40 1 SINAD@50MSPS SINAD@100MSPS 10 100 THD@100MSPS SINAD@165MSPS -90 -100 0 2 4 6 8 10 12 FREQUENCY - MHz 0 10 20 30 40 50 60 fOUT - MHz FREQUENCY - MHz TPC 4. SINAD/THD vs. fOUT (Differential Output) TPC 5. Single-Tone Spectral Plot @ 25 MSPS (Single-Ended Output) TPC 6. Single-Tone Spectral Plot@ 125 MSPS (Single-Ended Output) 0 -10 -20 fCLOCK = 165MSPS fOUT = 49MHz SFDR = 50.1dBc AMPLITUDE = 0dBFS MAGNITUDE - dBm -30 -40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 60 FREQUENCY - MHz 70 80 5ns/DIV TPC 7. Single-Tone Spectral Plot @ 165 MSPS (Single-Ended Output) TPC 8. Step Response (Single-Ended Output) REV. 0 50mV/DIV -7- AD9748 3.3V 150pF 0.1 F +1.20V REF REFIO FS ADJ RSET 3.3V DVDD DCOM CLK CLK 3.3V CLKVDD CLKCOM SLEEP DIGITAL DATA INPUTS (DB7-DB0) SEGMENTED SWITCHES LSB SWITCHES CURRENT SOURCE ARRAY AVDD ACOM AD9748 VDIFF = VOUTA - VOUTB IOUTA IOUTB MODE CMODE RLOAD 50 RLOAD 50 LATCHES Figure 3. Simplified Block Diagram FUNCTIONAL DESCRIPTION REFERENCE OPERATION Figure 3 shows a simplified block diagram of the AD9748. The AD9748 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing up to 20 mA of full-scale current (IOUTFS). The array is divided into 31 equal currents that make up the 5 most significant bits (MSBs). The next 3 bits consist of 7 equal current sources whose value is 1/8th of an MSB current source. Implementing the lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DAC's high output impedance (i.e., >100 kW). All of these current sources are switched to one or the other of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on the architecture that was pioneered in the AD9764 family, with further refinements to reduce distortion contributed by the switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. The analog and digital sections of the AD9748 have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently over a 2.7 V to 3.6 V range. The digital section, which is capable of operating at a rate of up to 165 MSPS, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.2 V band gap voltage reference, and a reference control amplifier. The DAC full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET, connected to the full-scale adjust (FSADJ) pin. The external resistor, in combination with both the reference control amplifier and voltage reference, VREFIO, sets the reference current IREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is 32 times IREF. The AD9748 contains an internal 1.2 V band gap reference, which can be easily overridden by an external reference with no effect on performance. When using the internal reference, simply decouple the REFIO pin to ACOM with a 0.1 mF capacitor. The internal reference voltage will be present at REFIO. If the voltage at REFIO is to be used anywhere else in the circuit, an external buffer amplifier with an input bias current of less than 100 nA should be used. An example of the use of the internal reference is given in Figure 4. 3.3V OPTIONAL EXTERNAL REF BUFFER +1.2V REF REFIO ADDITIONAL LOAD 0.1 F 2k FS ADJ CURRENT SOURCE ARRAY 150pF AVDD AD9748 Figure 4. Internal Reference Configuration An external reference can be applied to REFIO as shown in Figure 5. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 mF compensation capacitor is not required since the internal reference is overridden, and the relatively high input impedance of REFIO minimizes any loading of the external reference. 3.3V AVDD +1.2V REF EXTERNAL REF RSET VREFIO REFIO FS ADJ IREF = VREFIO/R SET 150pF AVDD CURRENT SOURCE ARRAY REFERENCE CONTROL AMPLIFIER AD9748 Figure 5. External Reference Configuration -8- REV. 0 AD9748 REFERENCE CONTROL AMPLIFIER The AD9748 contains a control amplifier that is used to regulate the full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 4, so that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied to the segmented current sources with the proper scale factor to set IOUTFS as stated in Equation 3. The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 mA and 625 mA. The wide adjustment span of IOUTFS provides several benefits. The first relates directly to the power dissipation of the AD9748, which is proportional to IOUTFS (refer to the Power Dissipation section). The second relates to the 20 dB adjustment, which is useful for system gain control purposes. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency small signal multiplying applications. DAC TRANSFER FUNCTION These last two equations highlight some of the advantages of operating the AD9748 differentially. First, the differential operation will help cancel common-mode error sources associated with IOUTA and IOUTB, such as noise, distortion, and dc offsets. Second, the differential code dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (i.e., VOUTA or VOUTB), thus providing twice the signal power to the load. Note that the gain drift temperature performance for a singleended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9748 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship as shown in Equation 8. ANALOG OUTPUTS Both DACs in the AD9748 provide complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 255) while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as: The complementary current outputs in each DAC, IOUTA, and IOUTB, may be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equations 5 through 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB, can also be converted to a singleended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9748 is optimum and specified using a differential transformer coupled output in which the voltage swing at IOUTA and IOUTB is limited to 0.5 V. The distortion and noise performance of the AD9748 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude decreases. This is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Since the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer will allow the AD9748 to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kW in parallel with 5 pF. It is also slightly dependent on the output voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration will result in the optimum dc linearity. Note that the INL/DNL specifications for the AD9748 are measured with IOUTA maintained at a virtual ground via an op amp. IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of -1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9748. -9- IOUTA = ( DAC CODE / 256 ) I OUTFS IOUTB = (255 - DAC CODE ) / 256 I OUTFS (1) (2) where DAC CODE = 0 to 255 (i.e., decimal representation). As mentioned previously, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage, VREFIO, and external resistor, RSET. It can be expressed as: IOUTFS = 32 IREF where IREF = VREFIO / RSET (3) (4) The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, that are tied to analog common, ACOM. Note, RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 W or 75 W cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply: VOUTA = IOUTA RLOAD VOUTB = IOUTB RLOAD (5) (6) Note that the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. VDIFF = ( IOUTA - IOUTB ) RLOAD (7) Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be expressed as: VDIFF = {(2 DAC CODE - 255) / 256} (32 R LOAD /R SET ) VREFIO REV. 0 (8) AD9748 The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.2 V for an IOUTFS = 20 mA to 1.0 V for an IOUTFS = 2 mA. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. DIGITAL INPUTS output. Optimal performance will be achieved if the CLOCK input has a sharp rising edge, since the DAC latches are positive edge triggered. In the differential input mode, the clock input functions as a high impedance differential pair. The common-mode level of the CLK+ and CLK- inputs can vary from 0.75 V to 2.25 V, and the differential voltage can be as low as 0.5 V p-p. This mode can be used to drive the clock with a differential sine wave, since the high gain-bandwidth of the differential inputs will convert the sine wave into a single-ended square wave internally. The final clock mode allows for a reduced external component count when the DAC clock is distributed on the board using PECL logic. The internal termination configuration is shown in Figure 7. These termination resistors are untrimmed and the absolute resistance can vary up to 20%. However, matching between the resistors should be generally better than 1%. AD9748 The AD9748 digital section consists of 8 input bit channels and a clock input. The 8-bit parallel data inputs follow standard positive binary coding, where DB7 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a fullscale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. DVDD DIGITAL INPUT CLK+ CLK- 50 50 CLOCK RECEIVER TO DAC CORE Figure 6. Equivalent Digital Input VTT = 1.3V NOM The digital interface is implemented using an edge-triggered master/slave latch. The DAC output updates on the rising edge of the clock and is designed to support a clock rate as high as 165 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulsewidth. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. CLOCK INPUT Figure 7. Clock Termination in PECL Mode DAC TIMING Input Clock and Data Timing Relationship SFDR - dB A configurable clock input allows for one single-ended and two differential modes. The mode selection is controlled by the CMODE input, as summarized in Table I. Connecting CMODE to CLKCOM selects the single-ended clock input. In this mode, the CLK+ input is driven with rail-to-rail swings and the CLK- input is left floating. If CMODE is connected to CLKVDD, the differential receiver mode is selected. In this mode both inputs are high impedance. The final mode is selected by floating CMODE. This mode is also differential, but internal terminations for positive emitter-coupled logic (PECL) are activated. There is no significant performance difference between any of the three clock input modes. Table I. Clock Mode Selection Dynamic performance in a DAC is dependent on the relationship between the position of the clock edges and the time at which the input data changes. The AD9748 is rising edge triggered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9748 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 8 shows the relationship of SFDR to clock placement with different sample rates. Note that at the lower sample rates, more tolerance is allowed in clock placement, while at higher rates, more care must be taken. 80 75 70 65 60 55 50MHz SFDR 50 45 40 35 30 0 2 4 6 8 10 12 20MHz SFDR CMODE Pin CLKCOM CLKVDD Float Clock Input Mode Single-Ended Differential PECL In the single-ended clock input mode, the CLK+ pin must be driven to rail-to-rail CMOS levels. The quality of the DAC output is directly related to the clock quality, and jitter is a key concern. Any noise or jitter in the clock will translate directly into the DAC -10- CLOCK PLACEMENT - ns Figure 8. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz (fCLOCK = 165 MSPS) REV. 0 AD9748 Sleep Mode Operation 10 DIFF 9 8 7 ICLKVDD - mA 6 5 4 3 2 1 0 0 30 60 90 120 150 180 The AD9748 has a power-down function that turns off the output current and reduces the supply current to less than 6 mA over the specified supply range of 2.7 V to 3.6 V and temperature range. This mode can be activated by applying a logic level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 AVDD. This digital input also contains an active pull-down circuit that ensures that the AD9748 remains enabled if this input is left disconnected. The AD9748 takes less than 50 ns to power down and approximately 5 ms to power back up. POWER DISSIPATION PECL SE The power dissipation, PD, of the AD9748 is dependent on several factors that include the: Power supply voltages (AVDD, CLKVDD, and DVDD) Full-scale current output IOUTFS Update rate fCLOCK Reconstructed digital input waveform fCLK Figure 11. ICLKVDD vs. fCLOCK and Clock Mode APPLYING THE AD9748 Output Configurations The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, as shown in Figure 9, and is insensitive to fCLOCK. Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figure 10 shows IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 3.3 V. 35 30 The following sections illustrate some typical output configurations for the AD9748. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting within the bandwidth of the chosen op amp. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground. 25 IAVDD - mA 20 15 10 5 2 4 6 8 10 12 IOUTFS - mA 14 16 18 20 Figure 9. IAVDD vs. IOUTFS 16 14 12 10 8 6 65MSPS 4 2 0 0.01 125MSPS 165MSPS IDVDD - mA 0.1 RATIO - fOUT /f C LOCK 1.0 Figure 10. IDVDD vs. Ratio @ DVDD = 3.3 V REV. 0 -11- AD9748 DIFFERENTIAL COUPLING USING A TRANSFORMER An RF transformer can be used to perform a differential-to-singleended signal conversion, as shown in Figure 12. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer's pass band. An RF transformer, such as the Mini-Circuits T1-1T, provides excellent rejection of commonmode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only. MINI-CIRCUITS T1-1T IOUTA AD9748 while meeting other system level objectives (e.g., cost, or power) should be selected. The op amp's differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. The differential circuit shown in Figure 14 provides the necessary level shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9748 and the op amp, is also used to level shift the differential output of the AD9748 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. 500 AD9748 IOUTA 225 225 AD8041 1k AVDD AD9748 IOUTB OPTIONAL RDIFF RLOAD IOUTB COPT 25 25 1k Figure 12. Differential Output Using a Transformer The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9748. A differential resistor, RDIFF, may be inserted in applications where the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer's impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF. DIFFERENTIAL COUPLING USING AN OP AMP Figure 14. Single-Supply DC Differential Coupled Circuit SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT An op amp can also be used to perform a differential-to-singleended conversion as shown in Figure 13. The AD9748 is configured with two equal load resistors, R LOAD, of 25 W. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp's distortion performance by preventing the DACs high slewing output from overloading the op amp's input. 500 Figure 15 shows the AD9748 configured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated 50 W cable, since the nominal full-scale current, IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 W. In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL), discussed in the Analog Output section of this data sheet. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested. AD9748 IOUTA 50 IOUTB 25 50 IOUTFS = 20mA VOUTA = 0V TO 0.5V Figure 15. 0 V to 0.5 V Unbuffered Voltage Output SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION AD9748 225 IOUTA 225 IOUTB COPT 500 25 25 AD8047 Figure 13. DC Differential Coupling Using an Op Amp The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide some additional signal gain. The op amp must operate off a dual supply since its output is approximately 1.0 V. A high speed amplifier capable of preserving the differential performance of the Figure 16 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9748 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, minimizing the nonlinear output impedance effect on the DAC's INL performance, as discussed in the Analog Output section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by U1's slew rate capabilities. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be set within U1's voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may result with a reduced IOUTFS since U1 will be required to sink less signal current. REV. 0 -12- AD9748 COPT RFB 200 AD9748 IOUTA 22 IOUTFS = 10mA noise to higher frequencies. Worst-case PSRR for either one of the differential DAC outputs will occur when the full-scale current is directed toward that output. As a result, the PSRR measurement in Figure 17 represents a worst-case condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured. VOUT = IOUTFS R FB U1 IOUTB 21 200 Figure 16. Unipolar Buffered Voltage Output POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION Many applications seek high speed and high performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the printed circuit board is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing as well as power supply bypassing and grounding to ensure optimum performance. Figures 22 to 25 illustrate the recommended printed circuit board ground, power, and signal plane layouts implemented on the AD9748 evaluation board. One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. This is referred to as the power supply rejection ratio. For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC's full-scale current, IOUTFS. AC noise on the dc supplies is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise will occur over the spectrum from tens of kHz to several MHz. The PSRR versus frequency of the AD9748 AVDD supply over this frequency range is shown in Figure 17. 85 80 75 70 PSRR - dB 65 60 55 50 45 40 An example serves to illustrate the effect of supply noise on the analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV of noise and, for simplicity sake (i.e., ignore harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired noise will appear as current noise superimposed on the DAC's full-scale current, IOUTFS, one must determine the PSRR in dB using Figure 17 at 250 kHz. To calculate the PSRR for a given RLOAD, such that the units of PSRR are converted from A/V to V/V, adjust the curve in Figure 17 by the scaling factor 20 log(RLOAD). For instance, if RLOAD is 50 W, the PSRR is reduced by 34 dB (i.e., PSRR of the DAC at 250 kHz which is 85 dB in Figure 17 becomes 51 dB VOUT/VIN). Proper grounding and decoupling should be a primary objective in any high-speed, high resolution system. The AD9748 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be decoupled to DCOM as close to the chip as physically possible. For those applications that require a single 3.3 V supply for both the analog and digital supplies, a clean analog supply may be generated using the circuit shown in Figure 18. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors. FERRITE BEADS TTL/CMOS LOGIC CIRCUITS AVDD 100 F ELECT. 10 F-22 F TANT. 0.1 F CER. ACOM 3.3V POWER SUPPLY Figure 18. Differential LC Filter for Single 3.3 V Applications EVALUATION BOARD General Description 0 2 6 4 8 FREQUENCY - MHz 10 12 Figure 17. Power Supply Rejection Ratio The AD9748 evaluation board allows for easy set up and testing of the product in the 32-lead LFCSP package. Careful attention to layout and circuit design, combined with a prototyping area, allows the user to evaluate the AD9748 easily and effectively in any application that requires high resolution, high speed conversion. This board allows the user the flexibility to operate the AD9748 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. The digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to exercise the power-down feature of the AD9748 and select the clock and data modes. -13- Note that ratio in Figure 17 is calculated amps out/volts in. Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. The voltage noise on AVDD, therefore, will be added in a nonlinear manner to the desired IOUT. Due to the relative size of these switches, PSRR is very code dependent. This can produce a mixing effect that can modulate low-frequency power supply REV. 0 AD9748 L1 BEAD TB1 1 C3 0.1 F TB1 2 BLK TP2 C2 10 F 6.3V C10 0.1 F RED TP12 CVDD 2 4 6 8 HEADER STRAIGHT UP MALE NO SHROUD 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J1 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X 10 12 L2 BEAD RED TP13 DVDD C7 0.1 F BLK TP4 C4 10 F 6.3V C6 0.1 F 14 16 18 20 22 24 26 28 L3 BEAD RED TP5 AVDD C9 0.1 F BLK TP6 C5 10 F 6.3V C8 0.1 F 30 32 34 36 38 40 TB3 1 TB3 2 TB4 1 JP3 CKEXTX TB4 2 R3 100 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X R4 100 R15 100 R16 100 R17 100 R18 100 R19 100 R20 100 1 RP3 2 RP3 3 RP3 4 RP3 5 RP3 6 RP3 7 RP3 8 RP3 1 RP4 2 RP4 3 RP4 4 RP4 5 RP4 6 RP4 7 RP4 8 RP4 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CKEXT CKEXTX R21 100 R24 100 R25 100 R26 100 R27 100 R28 100 Figure 19. Evaluation Board Schematic: Power Supply and Digital Inputs -14- REV. 0 AD9748 AVDD SLEEP TP11 WHT C17 0.1 F DVDD C19 0.1 F CVDD C32 0.1 F R29 10k DB7 DB6 DVDD DB5 DB4 DB3 DB2 DB1 DB0 CVDD CLK CLKB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CMODE 16 DB7 DB6 DVDD DB5 DB4 DB3 DB2 DB1 DB0 DCOM U1 CVDD CLK CLKB CCOM CMODE MODE DB8 DB9 DB10 DB11 DB12 DB13 DCOM1 SLEEP FSADJ REFIO ACOM IA IB ACOM1 AVDD AVDD1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DB8 DB9 DB10 DB11 DB12 DB13 TP3 WHT TP1 WHT 3 2 1 AVDD C11 0.1 F T1-1T JP9 T1 4 5 6 S3 AGND: 3, 4, 5 R11 50 DNP C13 JP8 IOUT AD9744LFCSP TP7 WHT R30 10k JP1 MODE CVDD DNP C12 R1 2k 0.1% R10 50 Figure 20. Evaluation Board Schematic: Output Signal Conditioning 1 7 U4 2 AGND: 5 CVDD: 8 CVDD CVDD C20 10 F 16V C35 0.1 F R5 120 CLKB JP2 CKEXT CLK 3 U4 4 AGND: 5 CVDD: 8 C34 0.1 F 6 S5 AGND: 3, 4, 5 R6 50 R2 120 Figure 21. Evaluation Board Schematic: Clock Input REV. 0 -15- AD9748 Figure 22. Evaluation Board Layout: Primary Side Figure 23. Evaluation Board Layout: Secondary Side -16- REV. 0 AD9748 Figure 24. Evaluation Board Layout: Ground Plane Figure 25. Evaluation Board Layout: Power Plane REV. 0 -17- AD9748 Figure 26. Evaluation Board Layout: Assembly--Primary Side Figure 27. Evaluation Board Layout: Assembly--Secondary Side -18- REV. 0 AD9748 OUTLINE DIMENSIONS 32-Lead, Lead Frame Chip Scale Package (LFCSP) (CP-32) Dimensions shown in millimeters 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC BOTTOM VIEW 3.25 3.10 SQ 2.95 8 0.50 0.40 0.30 12 MAX 0.70 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 REF COPLANARITY 0.08 17 16 9 3.50 REF 1.00 0.90 0.80 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 REV. 0 -19- -20- C03211-0-2/03(0) PRINTED IN U.S.A. |
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